XC878CLM XC878 XC800 52K/64K PG-LQFP-64 LQFP-64 XC878M XC878CM XC878LM - Datasheet Archive

 

XC878CLM 8-Bit Single-Chip Microcontroller Data Sheet V1.2 2009-11 Micr o co n t ro l l e rs Edition 2009-11 Published by

 

8-Bit XC878CLM XC878CLM 8-Bit Single-Chip Microcontroller Data Sheet V1.2 2009-11 Micr o co n t ro l l e rs Edition 2009-11 Published by Infineon Technologies AG 81726 Munich, Germany © 2009 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. 8-Bit XC878CLM XC878CLM 8-Bit Single-Chip Microcontroller Data Sheet V1.2 2009-11 Micr o co n t ro l l e rs XC878CLM XC878CLM XC878 XC878 Revision History: 2009-11 Previous Version: V1.1 Page V1.2 Subjects (major changes since last revision) Changes from V1.1 2009-08 to V1.2 2009-10 3 Table 1 and Table 2 has been updated to include the variants for the Automotive profile. 57 Table 21 has been added to show the Flash data retention and endurance for Automotive profile. 106 Table 37 has been updated to show the Chip Identification number for the new Automotive variants. We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: mcdocu.comments@infineon.com Data Sheet V1.2, 2009-11 XC878CLM XC878CLM Data Sheet V1.2, 2009-11 XC878CLM XC878CLM Table of Contents Table of Contents 1 Summary of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 2.1 2.2 2.3 2.4 General Device Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5 6 7 8 3 3.1 3.2 3.2.1 3.2.1.1 3.2.2 3.2.2.1 3.2.2.2 3.2.3 3.2.3.1 3.2.4 3.2.4.1 3.2.4.2 3.2.4.3 3.2.4.4 3.2.4.5 3.2.4.6 3.2.4.7 3.2.4.8 3.2.4.9 3.2.4.10 3.2.4.11 3.2.4.12 3.2.4.13 3.2.4.14 3.2.4.15 3.3 3.3.1 3.4 3.4.1 3.4.2 3.4.3 3.5 3.6 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Processor Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory Protection Strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Memory Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Special Function Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Address Extension by Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Address Extension by Paging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bit Protection Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Password Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC878 XC878 Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MDU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CORDIC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . System Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . WDT Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer 2 Compare/Capture Unit Registers . . . . . . . . . . . . . . . . . . . . . Timer 21 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CCU6 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UART1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SSC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MultiCAN Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OCDS Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Bank Pagination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Source and Vector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Supply System with Embedded Voltage Regulator . . . . . . . . . . . . 19 19 20 22 22 24 24 26 30 31 32 32 33 34 35 38 38 41 45 47 48 52 52 53 53 55 56 58 59 59 65 67 68 70 Data Sheet I-1 V1.2, 2009-11 XC878CLM XC878CLM Table of Contents 3.7 3.7.1 3.7.2 3.8 3.8.1 3.8.2 3.9 3.10 3.11 3.12 3.13 3.13.1 3.13.2 3.14 3.15 3.15.1 3.16 3.17 3.18 3.19 3.20 3.21 3.22 3.22.1 3.22.2 3.23 3.23.1 3.24 Reset Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Module Reset Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Booting Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Clock Generation Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Recommended External Oscillator Circuits . . . . . . . . . . . . . . . . . . . . . . 75 Clock Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Power Saving Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Multiplication/Division Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 CORDIC Coprocessor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 UART and UART1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Baud-Rate Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Baud Rate Generation using Timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Normal Divider Mode (8-bit Auto-reload Timer) . . . . . . . . . . . . . . . . . . . . . 89 LIN Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 LIN Header Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 High-Speed Synchronous Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . 92 Timer 0 and Timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Timer 2 and Timer 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Timer 2 Capture/Compare Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Capture/Compare Unit 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Controller Area Network (MultiCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Analog-to-Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 ADC Clocking Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 ADC Conversion Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 On-Chip Debug Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 JTAG ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Chip Identification Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 4 4.1 4.1.1 4.1.2 4.1.3 4.2 4.2.1 4.2.2 4.2.3 4.2.3.1 4.2.4 4.3 4.3.1 4.3.2 Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parameter Interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input/Output Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Supply Threshold Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC Conversion Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Testing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Rise/Fall Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Sheet I-2 108 108 108 109 110 111 111 114 115 118 119 123 123 124 V1.2, 2009-11 XC878CLM XC878CLM Table of Contents 4.3.3 4.3.4 4.3.5 4.3.6 4.3.7 4.3.8 5 5.1 5.2 5.3 Data Sheet Power-on Reset and PLL Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . On-Chip Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Data Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . External Clock Drive XTAL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . JTAG Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SSC Master Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 126 127 129 130 132 Package and Quality Declaration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Quality Declaration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 133 134 135 I-3 V1.2, 2009-11 XC878CLM XC878CLM Table of Contents Data Sheet I-4 V1.2, 2009-11 8-Bit Single-Chip Microcontroller 1 XC878CLM XC878CLM Summary of Features The XC878 XC878 has the following features: · High-performance XC800 XC800 Core ­ compatible with standard 8051 processor ­ two clocks per machine cycle architecture (for memory access without wait state) ­ two data pointers · On-chip memory ­ 8 Kbytes of Boot ROM ­ 256 bytes of RAM ­ 3 Kbytes of XRAM ­ 64/52 Kbytes of Flash; (includes memory protection strategy) · I/O port supply at 3.3 V or 5.0 V and core logic supply at 2.5 V (generated by embedded voltage regulator) (more features on next page) Flash 52K/64K 52K/64K x 8 On-Chip Debug Support Port 0 8-bit Digital I/O Capture/Compare Unit 16-bit Port 1 8-bit Digital I/O Compare Unit 16-bit Boot ROM 8K x 8 UART SSC Port 3 8-bit Digital I/O Timer 2 Capture/ Compare Unit 16-bit Port 4 8-bit Digital I/O Port 5 8-bit Digital I/O XC800 XC800 Core XRAM 3K x 8 RAM 256 x 8 Timer 0 16-bit Timer 1 16-bit Timer 21 16-bit MDU CORDIC MultiCAN Watchdog Timer UART1 ADC 10-bit 8-channel . 8-bit Analog Input Figure 1 Data Sheet XC878 XC878 Functional Units 1 V1.2, 2009-11 XC878CLM XC878CLM Summary of Features Features: (continued) · · · · · · · · · · · · · · · · · Power-on reset generation Brownout detection for core logic supply On-chip OSC and PLL for clock generation ­ Loss-of-Clock detection Power saving modes ­ slow-down mode ­ idle mode ­ power-down mode with wake-up capability via RXD or EXINT0 ­ clock gating control to each peripheral Programmable 16-bit Watchdog Timer (WDT) Five ports ­ Up to 40 pins as digital I/O ­ 8 dedicated analog inputs used as A/D converter input 8-channel, 10-bit ADC Four 16-bit timers ­ Timer 0 and Timer 1 (T0 and T1) ­ Timer 2 and Timer 21 (T2 and T21) Multiplication/Division Unit for arithmetic operations (MDU) CORDIC Coprocessor for computation of trigonometric, hyperbolic and linear functions MultiCAN with 2 nodes, 32 message objects Two Capture/compare units ­ Capture/compare unit 6 for PWM signal generation (CCU6) ­ Timer 2 Capture/compare unit for vaious digital signal generation (T2CCU) Two full-duplex serial interfaces (UART and UART1) Synchronous serial channel (SSC) On-chip debug support ­ 1 Kbyte of monitor ROM (part of the 8-Kbyte Boot ROM) ­ 64 bytes of monitor RAM PG-LQFP-64 PG-LQFP-64 pin package Temperature range TA: ­ SAF (-40 to 85 °C) ­ SAX (-40 to 105 °C) Data Sheet 2 V1.2, 2009-11 XC878CLM XC878CLM Summary of Features XC878 XC878 Variant Devices The XC878 XC878 product family features devices with different configurations, program memory sizes, power supply voltage, temperature and quality profiles (Automotive or Industrial), to offer cost-effective solutions for different application requirements. The list of XC878 XC878 device configurations are summarized in Table 1. The type of package available is the LQFP-64 LQFP-64. Table 1 Device Configuration Device Name CAN Module LIN BSL Support MDU Module XC878 XC878 No No No XC878M XC878M No No Yes XC878CM XC878CM Yes No Yes XC878LM XC878LM No Yes Yes XC878CLM XC878CLM Yes Yes Yes From these 5 different combinations of configuration, each are further made available in many sales types, which are grouped according to device type, program memory sizes, power supply voltage, temperature and quality profiles (Automotive or Industrial), as shown in Table 2. Table 2 Device Profile Sales Type Device Program Type Memory (Kbytes) Power TempSupply erature (V) (°C) Quality Profile SAF-XC878-13FFI SAF-XC878-13FFI 5V Flash 52 5.0 -40 to 85 Industrial SAF-XC878M-13FFI SAF-XC878M-13FFI 5V Flash 52 5.0 -40 to 85 Industrial SAF-XC878CM-13FFI SAF-XC878CM-13FFI 5V Flash 52 5.0 -40 to 85 Industrial SAF-XC878-16FFI SAF-XC878-16FFI 5V Flash 64 5.0 -40 to 85 Industrial SAF-XC878M-16FFI SAF-XC878M-16FFI 5V Flash 64 5.0 -40 to 85 Industrial SAF-XC878CM-16FFI SAF-XC878CM-16FFI 5V Flash 64 5.0 -40 to 85 Industrial SAF-XC878-13FFI SAF-XC878-13FFI 3V3 Flash 52 3.3 -40 to 85 Industrial SAF-XC878M-13FFI SAF-XC878M-13FFI 3V3 Flash 52 3.3 -40 to 85 Industrial SAF-XC878CM-13FFI SAF-XC878CM-13FFI 3V3 Flash 52 3.3 -40 to 85 Industrial SAF-XC878-16FFI SAF-XC878-16FFI 3V3 Flash 64 3.3 -40 to 85 Industrial SAF-XC878M-16FFI SAF-XC878M-16FFI 3V3 Flash 64 3.3 -40 to 85 Industrial Data Sheet 3 V1.2, 2009-11 XC878CLM XC878CLM Summary of Features Table 2 Device Profile (cont'd) Sales Type Device Program Type Memory (Kbytes) Power TempSupply erature (V) (°C) Quality Profile SAF-XC878CM-16FFI SAF-XC878CM-16FFI 3V3 Flash 64 3.3 -40 to 85 Industrial SAX-XC878-13FFA SAX-XC878-13FFA 5V Flash 52 5.0 -40 to 105 Automotive SAX-XC878CM-13FFA SAX-XC878CM-13FFA 5V Flash 52 5.0 -40 to 105 Automotive SAX-XC878LM-13FFA SAX-XC878LM-13FFA 5V Flash 52 5.0 -40 to 105 Automotive SAX-XC878CLM-13FFA SAX-XC878CLM-13FFA 5V Flash 52 5.0 -40 to 105 Automotive SAX-XC878-16FFA SAX-XC878-16FFA 5V Flash 64 5.0 -40 to 105 Automotive SAX-XC878CM-16FFA SAX-XC878CM-16FFA 5V Flash 64 5.0 -40 to 105 Automotive SAX-XC878LM-16FFA SAX-XC878LM-16FFA 5V Flash 64 5.0 -40 to 105 Automotive SAX-XC878CLM-16FFA SAX-XC878CLM-16FFA 5V Flash 64 5.0 -40 to 105 Automotive As this document refers to all the derivatives, some description may not apply to a specific product. For simplicity, all versions are referred to by the term XC878 XC878 throughout this document. Ordering Information The ordering code for Infineon Technologies microcontrollers provides an exact reference to the required product. This ordering code identifies: · · The derivative itself, i.e. its function set, the temperature range, and the supply voltage The package and the type of delivery For the available ordering codes for the XC878 XC878, please refer to your responsible sales representative or your local distributor. Data Sheet 4 V1.2, 2009-11 XC878CLM XC878CLM General Device Information 2 General Device Information Chapter 2 contains the block diagram, pin configurations, definitions and functions of the XC878 XC878. 2.1 Block Diagram The block diagram of the XC878 XC878 is shown in Figure 2. XC878 XC878 CORDIC SSC WDT OCDS MultiCAN 52/64-Kbyte Flash 4 MHz On-chip OSC P3.0 - P3.7 P4.0 - P4.7 P5.0 - P5.7 CCU6 3-Kbyte XRAM Clock Generator P1.0 - P1.7 UART1 MDU P ort 0 UART P ort 1 XTAL1 XTAL2 T0 & T1 P ort 3 TMS MBC TM RESET VDDP VSSP VDDC VSSC 256-byte RAM + 64-byte monitor RAM P ort 4 XC800 XC800 Core P0.0 - P0.7 P ort 5 Internal Bus 8-Kbyte Boot ROM 1) PLL Timer 2 Capture/ Compare Unit AD C Timer 21 AN0 ­ AN7 VAREF VAGND 1) Includes 1-Kbyte monitor ROM Figure 2 Data Sheet XC878 XC878 Block Diagram 5 V1.2, 2009-11 XC878CLM XC878CLM General Device Information 2.2 Logic Symbol The logic symbol of the XC878 XC878 is shown in Figure 3. VSSP VDDP Port 0 8-Bit VAREF Port 1 8-Bit VAGND RESET MBC Port 3 8-Bit XC878 XC878 TMS Port 4 8-Bit TM Port 5 8-Bit XTAL1 XTAL2 AN0 ­ AN7 VDDC Figure 3 Data Sheet VSSC XC878 XC878 Logic Symbol 6 V1.2, 2009-11 XC878CLM XC878CLM General Device Information 2.3 Pin Configuration AN7 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P4.3 P3.6 P3.7 P3.0 P3.1 P4.4 P4.5 P4.6 P4.7 The pin configuration of the XC878 XC878 in Figure 4. 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P3.2 49 32 VAREF P3.3 50 31 V AGND P3.4 51 30 AN6 P3.5 52 29 AN5 RESET 53 28 AN4 VSSP 54 27 AN3 V DDP 55 26 VSSP N.C. 56 25 V DDP TM 57 24 AN2 MBC 58 23 AN1 P4.0 59 22 AN0 P4.1 60 21 P0.1 P4.2 61 20 P5.7 P0.7 62 19 P5.6 P0.3 63 18 P0.2 P0.4 64 17 P0.0 XC878 XC878 TMS P5.5 P5.4 P5.3 P5.0 P5.2 VDDP 9 10 11 12 13 14 15 16 P1.7 8 P1.6 7 P5.1 6 VDDC XTAL2 4 5 VSSC P0.6 Data Sheet 3 P0.5 Figure 4 2 XTAL1 1 XC878 XC878 Pin Configuration, PG-LQFP-64 PG-LQFP-64 Package (top view) 7 V1.2, 2009-11 XC878CLM XC878CLM General Device Information 2.4 Pin Definitions and Functions The functions and default states of the XC878 XC878 external pins are provided in Table 3. Table 3 Pin Definitions and Functions Symbol Pin Number (LQFP-64 LQFP-64) Type Reset Function State P0 I/O Port 0 Port 0 is an 8-bit bidirectional general purpose I/O port. It can be used as alternate functions for the JTAG, CCU6, UART, UART1, T2CCU, Timer 21, MultiCAN, SSC and External Interface. P0.0 17 Hi-Z TCK_0 T12HR T12HR_1 JTAG Clock Input CCU6 Timer 12 Hardware Run Input CC61_1 Input/Output of Capture/Compare channel 1 CLKOUT_0 Clock Output RXDO_1 UART Transmit Data Output P0.1 21 Hi-Z TDI_0 T13HR T13HR_1 RXD_1 RXDC1_0 COUT61 COUT61_1 EXF2_1 P0.2 18 PU CTRAP_2 TDO_0 TXD_1 TXDC1_0 P0.3 63 Hi-Z SCK_1 COUT63 COUT63_1 RXDO1_0 A17 Data Sheet 8 JTAG Serial Data Input CCU6 Timer 13 Hardware Run Input UART Receive Data Input MultiCAN Node 1 Receiver Input Output of Capture/Compare channel 1 Timer 2 External Flag Output CCU6 Trap Input JTAG Serial Data Output UART Transmit Data Output/Clock Output MultiCAN Node 1 Transmitter Output SSC Clock Input/Output Output of Capture/Compare channel 3 UART1 Transmit Data Output Address Line 17 Output V1.2, 2009-11 XC878CLM XC878CLM General Device Information Table 3 Pin Definitions and Functions (cont'd) Symbol Pin Number (LQFP-64 LQFP-64) P0.4 64 Type Reset Function State Hi-Z MTSR_1 CC62_1 TXD1_0 A18 P0.5 1 Hi-Z MRST_1 EXINT0_0 T2EX1_1 RXD1_0 COUT62 COUT62_1 A19 SSC Master Transmit Output/ Slave Receive Input Input/Output of Capture/Compare channel 2 UART1 Transmit Data Output/Clock Output Address Line 18 Output SSC Master Receive Input/Slave Transmit Output External Interrupt Input 0 Timer 21 External Trigger Input UART1 Receive Data Input Output of Capture/Compare channel 2 Address Line 19 Output P0.6 2 PU T2CC4_1 WR P0.7 62 PU CLKOUT_1 Clock Output T2CC5_1 Compare Output Channel 5 RD External Data Read Control Output Data Sheet 9 Compare Output Channel 4 External Data Write Control Output V1.2, 2009-11 XC878CLM XC878CLM General Device Information Table 3 Pin Definitions and Functions (cont'd) Symbol Pin Number (LQFP-64 LQFP-64) Type Reset Function State P1 I/O Port 1 Port 1 is an 8-bit bidirectional general purpose I/O port. It can be used as alternate functions for the JTAG, CCU6, UART, Timer 0, Timer 1, T2CCU, Timer 21, MultiCAN, SSC and External Interface. P1.0 34 PU RXD_0 T2EX_0 RXDC0_0 A8 UART Receive Data Input Timer 2 External Trigger Input MultiCAN Node 0 Receiver Input Address Line 8 Output P1.1 35 PU EXINT3_0 T0_1 TXD_0 A9 External Interrupt Input 3 Timer 0 Input UART Transmit Data Output/Clock Output MultiCAN Node 0 Transmitter Output Address Line 9 Output TXDC0_0 P1.2 36 PU SCK_0 A10 SSC Clock Input/Output Address Line 10 Output P1.3 37 PU MTSR_0 SSC Master Transmit Output/Slave Receive Input SSC Clock Input/Output MultiCAN Node 1 Transmitter Output Address Line 11 Output SCK_2 TXDC1_3 A11 P1.4 38 PU MRST_0 EXINT0_1 RXDC1_3 MTSR_2 A12 Data Sheet 10 SSC Master Receive Input/ Slave Transmit Output External Interrupt Input 0 MultiCAN Node 1 Receiver Input SSC Master Transmit Output/Slave Receive Input Address Line 12 Output V1.2, 2009-11 XC878CLM XC878CLM General Device Information Table 3 Pin Definitions and Functions (cont'd) Symbol Pin Number (LQFP-64 LQFP-64) P1.5 39 Type Reset Function State PU CCPOS0_1 EXINT5_0 T1_1 MRST_2 EXF2_0 RXDO_0 CCU6 Hall Input 0 External Interrupt Input 5 Timer 1 Input SSC Master Receive Input/ Slave Transmit Output Timer 2 External Flag Output UART Transmit Data Output P1.6 10 PU CCPOS1_1 CCU6 Hall Input 1 T12HR T12HR_0 CCU6 Timer 12 Hardware Run Input EXINT6_0 External Interrupt Input 6 RXDC0_2 MultiCAN Node 0 Receiver Input T21_1 Timer 21 Input P1.7 11 PU CCPOS2_1 CCU6 Hall Input 2 T13HR T13HR_0 CCU6 Timer 13 Hardware Run Input T2_1 Timer 2 Input TXDC0_2 MultiCAN Node 0 Transmitter Output P1.5 and P1.6 can be used as a software chip select output for the SSC. Data Sheet 11 V1.2, 2009-11 XC878CLM XC878CLM General Device Information Table 3 Pin Definitions and Functions (cont'd) Symbol Pin Number (LQFP-64 LQFP-64) Type Reset Function State P3 I/O Port 3 Port 3 is an 8-bit bidirectional general purpose I/O port. It can be used as alternate functions for CCU6, UART1, T2CCU, Timer 21, MultiCAN and External Interface. P3.0 43 Hi-Z CCPOS1_2 CCU6 Hall Input 1 CC60_0 Input/Output of Capture/Compare channel 0 RXDO1_1 UART1 Transmit Data Output T2CC0_1/ External Interrupt Input 3/T2CCU EXINT3_2 Capture/Compare Channel 0 P3.1 44 Hi-Z CCPOS0_2 CCU6 Hall Input 0 CC61_2 Input/Output of Capture/Compare channel 1 COUT60 COUT60_0 Output of Capture/Compare channel 0 TXD1_1 UART1 Transmit Data Output/Clock Output P3.2 49 Hi-Z CCPOS2_2 RXDC1_1 RXD1_1 CC61_0 T2CC1_1/ EXINT4_2 P3.3 50 Hi-Z COUT61 COUT61_0 TXDC1_1 T2CC2_1/ EXINT5_2 A13 Data Sheet 12 CCU6 Hall Input 2 MultiCAN Node 1 Receiver Input UART1 Receive Data Input Input/Output of Capture/Compare channel 1 External Interrupt Input 4/T2CCU Capture/Compare Channel 1 Output of Capture/Compare channel 1 MultiCAN Node 1 Transmitter Output External Interrupt Input 5/T2CCU Capture/Compare Channel 2 Address Line 13 Output V1.2, 2009-11 XC878CLM XC878CLM General Device Information Table 3 Pin Definitions and Functions (cont'd) Symbol Pin Number (LQFP-64 LQFP-64) P3.4 51 Type Reset Function State Hi-Z CC62_0 RXDC0_1 T2EX1_0 T2CC3_1/ EXINT6_3 A14 P3.5 52 Hi-Z COUT62 COUT62_0 Input/Output of Capture/Compare channel 2 MultiCAN Node 0 Receiver Input Timer 21 External Trigger Input External Interrupt Input 6/T2CCU Capture/Compare Channel 3 Address Line 14 Output A15 Output of Capture/Compare channel 2 Timer 21 External Flag Output MultiCAN Node 0 Transmitter Output Address Line 15 Output EXF21 EXF21_0 TXDC0_1 P3.6 41 PU CTRAP_0 CCU6 Trap Input P3.7 42 Hi-Z EXINT4_0 COUT63 COUT63_0 External Interrupt Input 4 Output of Capture/Compare channel 3 Address Line 16 Output A16 Data Sheet 13 V1.2, 2009-11 XC878CLM XC878CLM General Device Information Table 3 Pin Definitions and Functions (cont'd) Symbol Pin Number (LQFP-64 LQFP-64) Type Reset Function State P4 I/O P4.0 59 Port 4 Port 4 is an 8-bit bidirectional general purpose I/O port. It can be used as alternate functions for CCU6, Timer 0, Timer 1, T2CCU, Timer 21, MultiCAN and External Interface. Hi-Z RXDC0_3 CC60_1 T2CC0_0/ EXINT3_1 D0 P4.1 60 Hi-Z TXDC0_3 MultiCAN Node 0 Receiver Input Output of Capture/Compare channel 0 External Interrupt Input 3/T2CCU Capture/Compare Channel 0 Data Line 0 Input/Output T2CC1_0/ EXINT4_1 D1 MultiCAN Node 0 Transmitter Output Output of Capture/Compare channel 0 External Interrupt Input 4/T2CCU Capture/Compare Channel 1 Data Line 1 Input/Output COUT60 COUT60_1 P4.2 61 PU EXINT6_1 T21_0 D2 External Interrupt Input 6 Timer 21 Input Data Line 2 Input/Output P4.3 40 Hi-Z T2EX_1 EXF21 EXF21_1 COUT63 COUT63_2 Timer 2 External Trigger Input Timer 21 External Flag Output Output of Capture/Compare channel 3 Data Line 3 Input/Output D3 P4.4 45 Data Sheet Hi-Z CCPOS0_3 CCU6 Hall Input 0 T0_0 Timer 0 Input CC61_4 Output of Capture/Compare channel 1 T2CC2_0/ External Interrupt Input 5/T2CCU EXINT5_1 Capture/Compare Channel 2 D4 Data Line 4 Input/Output 14 V1.2, 2009-11 XC878CLM XC878CLM General Device Information Table 3 Pin Definitions and Functions (cont'd) Symbol Pin Number (LQFP-64 LQFP-64) Type Reset Function State P4.5 46 Hi-Z CCPOS1_3 CCU6 Hall Input 1 T1_0 Timer 1 Input COUT61 COUT61_2 Output of Capture/Compare channel 1 T2CC3_0/ External Interrupt Input 6/T2CCU EXINT6_2 Capture/Compare Channel 3 D5 Data Line 5 Input/Output P4.6 47 Hi-Z CCPOS2_3 CCU6 Hall Input 2 T2_0 Timer 2 Input CC62_2 Output of Capture/Compare channel 2 T2CC4_0 Compare Output Channel 4 D6 Data Line 6 Input/Output P4.7 48 Hi-Z CTRAP_3 COUT62 COUT62_2 T2CC5_0 D7 Data Sheet 15 CCU6 Trap Input Output of Capture/Compare channel 2 Compare Output Channel 5 Data Line 7 Input/Output V1.2, 2009-11 XC878CLM XC878CLM General Device Information Table 3 Pin Definitions and Functions (cont'd) Symbol Pin Number (LQFP-64 LQFP-64) Type Reset Function State P5 I/O Port 5 Port 5 is an 8-bit bidirectional general purpose I/O port. It can be used as alternate functions for UART, UART1, T2CCU, JTAG and External Interface. P5.0 8 PU EXINT1_1 A0 External Interrupt Input 1 Address Line 0 Output P5.1 9 PU EXINT2_1 A1 External Interrupt Input 2 Address Line 1 Output P5.2 12 PU RXD_2 T2CC2_2/ EXINT5_3 A2 UART Receive Data Input External Interrupt Input 5/T2CCU Capture/Compare Channel 2 Address Line 2 Output P5.3 13 PU CCPOS0_0 CCU6 Hall Input 0 EXINT1_0 External Interrupt Input 1 T12HR T12HR_2 CCU6 Timer 12 Hardware Run Input CC61_3 Input of Capture/Compare channel 1 TXD_2 UART Transmit Data Output/Clock Output T2CC5_2 Compare Output Channel 5 A3 Address Line 3 Output P5.4 14 PU CCPOS1_0 CCU6 Hall Input 1 EXINT2_0 External Interrupt Input 2 T13HR T13HR_2 CCU6 Timer 13 Hardware Run Input CC62_3 Input of Capture/Compare channel 2 RXDO_2 UART Transmit Data Output T2CC4_2 Compare Output Channel 4 A4 Address Line 4 Output Data Sheet 16 V1.2, 2009-11 XC878CLM XC878CLM General Device Information Table 3 Pin Definitions and Functions (cont'd) Symbol Pin Number (LQFP-64 LQFP-64) Type Reset Function State P5.5 15 PU CCPOS2_0 CCU6 Hall Input 2 CTRAP_1 CCU6 Trap Input CC60_3 Input of Capture/Compare channel 0 TDO_1 JTAG Serial Data Output TXD1_2 UART1 Transmit Data Output/ Clock Output T2CC0_2/ External Interrupt Input 3/T2CCU EXINT3_3 Capture/Compare Channel 0 A5 Address Line 5 Output P5.6 19 PU TCK_1 RXDO1_2 T2CC1_2/ EXINT4_3 A6 JTAG Clock Input UART1 Transmit Data Output External Interrupt Input 4/T2CCU Capture/Compare Channel 1 Address Line 6 Output P5.7 20 PU TDI_1 RXD1_2 T2CC3_2/ EXINT6_4 A7 JTAG Serial Data Input UART1 Receive Data Input External Interrupt Input 6/T2CCU Capture/Compare Channel 3 Address Line 7 Output Data Sheet 17 V1.2, 2009-11 XC878CLM XC878CLM General Device Information Table 3 Pin Definitions and Functions (cont'd) Symbol Pin Number (LQFP-64 LQFP-64) Type Reset Function State VDDP 7, 25, 55 ­ ­ I/O Port Supply (3.3 or 5.0 V) Also used by EVR and analog modules. All pins must be connected. VSSP 26, 54 ­ ­ I/O Ground All pins must be connected. VDDC VSSC VAREF VAGND 6 ­ ­ Core Supply Monitor (2.5 V) 5 ­ ­ Core Supply Ground 32 ­ ­ ADC Reference Voltage 31 ­ ­ ADC Reference Ground AN0 22 I Hi-Z Analog Input 0 AN1 23 I Hi-Z Analog Input 1 AN2 24 I Hi-Z Analog Input 2 AN3 27 I Hi-Z Analog Input 3 AN4 28 I Hi-Z Analog Input 4 AN5 29 I Hi-Z Analog Input 5 AN6 30 I Hi-Z Analog Input 6 AN7 33 I Hi-Z Analog Input 7 XTAL1 4 I Hi-Z External Oscillator Input (Feedback resistor required, normally NC) XTAL2 3 O Hi-Z External Oscillator Output (Feedback resistor required, normally NC) TMS 16 I PD JTAG Test Mode Select RESET 53 I PU Reset Input MBC 58 I PU Monitor & BootStrap Loader Control TM 57 ­ ­ Test Mode (External pull down device required) NC 56 ­ ­ No Connection Data Sheet 18 V1.2, 2009-11 XC878CLM XC878CLM Functional Description 3 Functional Description Chapter 3 provides an overview of the XC878 XC878 functional description. 3.1 Processor Architecture The XC878 XC878 is based on a high-performance 8-bit Central Processing Unit (CPU) that is compatible with the standard 8051 processor. While the standard 8051 processor is designed around a 12-clock machine cycle, the XC878 XC878 CPU uses a 2-clock machine cycle. This allows fast access to ROM or RAM memories without wait state. The instruction set consists of 45% one-byte, 41% two-byte and 14% three-byte instructions. The XC878 XC878 CPU provides a range of debugging features, including basic stop/start, single-step execution, breakpoint support and read/write access to the data memory, program memory and Special Function Registers (SFRs). Figure 5 shows the CPU functional blocks. Internal Data Memory Core SFRs Register Interface External Data Memory External SFRs 16-bit Registers & Memory Interface fCCLK Memory Wait Reset Legacy External Interrupts (IEN0, IEN1) External Interrupts Non-Maskable Interrupt Figure 5 Data Sheet Opcode & Immediate Registers Multiplier / Divider Opcode Decoder Program Memory ALU Timer 0 / Timer 1 State Machine & Power Saving UART Interrupt Controller CPU Block Diagram 19 V1.2, 2009-11 XC878CLM XC878CLM Functional Description 3.2 Memory Organization The XC878 XC878 CPU operates in the following address spaces: · · · 8 Kbytes of Boot ROM program memory 256 bytes of internal RAM data memory 3 Kbytes of XRAM memory (XRAM can be read/written as program memory or external data memory) A 128-byte Special Function Register area 64/52 Kbytes of Flash program memory (Flash devices) · · Figure 6 and Figure 7 illustrate the memory address spaces of the XC878 XC878 with 64Kbytes and 52Kbytes embedded Flash respectively. Bank F F' FFFF H Reserved Bank E Bank D Bank C Bank B Bank A Reserved Bank 9 Bank 8 Bank 7 Bank 6 Bank 5 Bank 4 Bank 3 External Reserved Bank 2 External XRAM 3 KByte Reserved Boot ROM 8 KByte Reserved Bank 1 Bank 0 D-Flash 4 KByte F' 0000H 0000H E' FFFFH E' 0000H 0000H D' FFFFH D' 0000H 0000H C' FFFFH C' 0000H 0000H B' FFFFH B' 0000H 0000H A' FFFFH A' 0000H 0000H 9' FFFFH 9' 0000H 0000H 8' FFFFH 8' 0000H 0000H 7' FFFFH 7' 0000H 0000H 6' FFFFH 6' 0000H 0000H 5' FFFFH 5' 0000H 0000H 4' FFFFH 4' 0000H 0000H 3' FFFFH 3' 0000H 0000H 2' FFFFH 2' FEC0H 2' FE00H FE00H 2' FC00H FC00H 2' F000H F000H 2' E000H E000H 2' C000H C000H 2' 0000H 0000H 1' FFFFH External XRAM 3 KByte External Reserved External F' FFFF H F' FC00H FC00H F' F000H F000H F' 0000H 0000H E' FFFFH E' 0000H 0000H D' FFFFH D' 0000H 0000H C' FFFFH C' 0000H 0000H B' FFFFH B' 0000H 0000H A' FFFFH A' 0000H 0000H 9' FFFFH 9' 0000H 0000H 8' FFFFH 8' 0000H 0000H 7' FFFFH 7' 0000H 0000H 6' FFFFH 6' 0000H 0000H 5' FFFFH 5' 0000H 0000H 4' FFFFH 4' 0000H 0000H 3' FFFFH 3' 0000H 0000H 2' FFFFH 2' FEC0H 2' FE00H FE00H 2' FC00H FC00H Reserved External Reserved External 1' 0000H 0000H 0' FFFFH 2' F000H F000H 2' E000H E000H Memory Extension Stack Pointer (MEXSP) 2' C000H C000H 2' 0000H 0000H 1' FFFFH 1' 0000H 0000H 0' FFFFH Direct Address Internal RAM Special Function Registers FFH Extension Stack RAM 80H 0' F000H F000H Reserved 7FH P-Flash 60 KByte Internal RAM 0' 0000H 0000H Code Space Indirect Address 0' 0000H 0000H 00H Data Space Internal Data Space Memory Map User Mode Figure 6 Data Sheet Memory Map of XC878 XC878 with 64K Flash Memory in user mode 20 V1.2, 2009-11 XC878CLM XC878CLM Functional Description F'FFFF H Reserved External 1'0000H 0000H FFFF H FEC0H XRAM 2 KByte D-Flash 4 KByte External 1'0000H 0000H FFFF H FEC0H Reserved Reserved External F'FFFF H External FE00H FE00H FC00H FC00H F000 H External XRAM 2 KByte FE00H FE00H FC00 H F000 H E000H E000H Reserved Boot ROM 8 KByte C000H C000H P-Flash 48 KByte / Reserved C000H C000H Reserved / External 8000H 8000H 8000H 8000H Memory Extension Stack Pointer (MEXSP) P-Flash 32 KByte Indirect Address Direct Address Internal RAM Special Function Registers FF H Reserved Extension Stack RAM 80H 7FH Internal RAM 0000H 0000H Code Space Figure 7 Data Sheet 0000H 0000H 00 H Data Space Internal Data Space Memory Map User Mode Memory Map of XC878 XC878 with 52K Flash Memory in user mode 21 V1.2, 2009-11 XC878CLM XC878CLM Functional Description 3.2.1 Memory Protection Strategy The XC878 XC878 memory protection strategy includes: · · · Basic protection: The user is able to block any external access via the boot option to any memory Read-out protection: The user is able to protect the contents in the Flash Flash program and erase protection These protection strategies are enabled by programming a valid password (16-bit nonone value) via Bootstrap Loader (BSL) mode 6. 3.2.1.1 Flash Memory Protection As long as a valid password is available, all external access to the device, including the Flash, will be blocked. For additional security, the Flash hardware protection can be enabled to implement a second layer of read-out protection, as well as to enable program and erase protection. Flash hardware protection is available only for Flash devices and comes in two modes: · · Mode 0: Only the P-Flash is protected; the D-Flash is unprotected Mode 1: Both the P-Flash and D-Flash are protected The selection of each protection mode and the restrictions imposed are summarized in Table 4. Table 4 Flash Protection Modes Flash Protection Without hardware protection With hardware protection Hardware Protection Mode - 0 Activation Program a valid password via BSL mode 6 Selection Bit 13 of password = 0 Bit 13 of password = 1 Bit 13 of password = 1 MSB of password = 0 MSB of password = 1 P-Flash contents can be read by Read instructions in any program memory Read instructions in the P-Flash Read instructions in the P-Flash or DFlash Not possible Not possible External Not possible access to PFlash Data Sheet 1 22 V1.2, 2009-11 XC878CLM XC878CLM Functional Description Table 4 Flash Protection Modes (cont'd) Flash Protection Without hardware protection With hardware protection P-Flash program and erase Possible Possible only on the Possible only on the condition that MSB - 1 condition that MSB - 1 of password is set to 1 of password is set to 1 D-Flash contents can be read by Read instructions in any program memory Read instructions in any program memory Read instructions in the P-Flash or DFlash External Not possible access to DFlash Not possible Not possible D-Flash program Possible Possible Possible, on the condition that MSB - 1 of password is set to 1 D-Flash erase Possible Possible, on these Possible, on the conditions: condition that MSB - 1 · MISC_CON.DFLASH of password is set to 1 EN bit is set to 1 prior to each erase operation; or · the MSB - 1 of password is set to 1 BSL mode 6, which is used for enabling Flash protection, can also be used for disabling Flash protection. Here, the programmed password must be provided by the user. To disable the flash protection, a password match is required. A password match triggers an automatic erase of the protected P-Flash and D-Flash contents, including the programmed password. With a valid password, the Flash hardware protection is then enabled or disabled upon next reset. For the other protection strategies, no reset is necessary. Although no protection scheme can be considered infallible, the XC878 XC878 memory protection strategy provides a very high level of protection for a general purpose microcontroller. Note: If ROM read-out protection is enabled, only read instructions in the ROM memory can target the ROM contents. Data Sheet 23 V1.2, 2009-11 XC878CLM XC878CLM Functional Description 3.2.2 Special Function Register The Special Function Registers (SFRs) occupy direct internal data memory space in the range 80H to FFH. All registers, except the program counter, reside in the SFR area. The SFRs include pointers and registers that provide an interface between the CPU and the on-chip peripherals. As the 128-SFR 128-SFR range is less than the total number of registers required, address extension mechanisms are required to increase the number of addressable SFRs. The address extension mechanisms include: · · Mapping Paging 3.2.2.1 Address Extension by Mapping Address extension is performed at the system level by mapping. The SFR area is extended into two portions: the standard (non-mapped) SFR area and the mapped SFR area. Each portion supports the same address range 80H to FFH, bringing the number of addressable SFRs to 256. The extended address range is not directly controlled by the CPU instruction itself, but is derived from bit RMAP in the system control register SYSCON0 at address 8FH. To access SFRs in the mapped area, bit RMAP in SFR SYSCON0 must be set. Alternatively, the SFRs in the standard area can be accessed by clearing bit RMAP. The SFR area can be selected as shown in Figure 8. As long as bit RMAP is set, the mapped SFR area can be accessed. This bit is not cleared automatically by hardware. Thus, before standard/mapped registers are accessed, bit RMAP must be cleared/set, respectively, by software. Data Sheet 24 V1.2, 2009-11 XC878CLM XC878CLM Functional Description Standard Area (RMAP = 0) FF H Module 1 SFRs SYSCON0.RMAP Module 2 SFRs rw . Module n SFRs 80 H SFR Data (to/from CPU) Mapped Area (RMAP = 1) FF H Module (n+1) SFRs Module (n+2) SFRs . Module m SFRs 80 H Direct Internal Data Memory Address Figure 8 Data Sheet Address Extension by Mapping 25 V1.2, 2009-11 XC878CLM XC878CLM Functional Description SYSCON0 System Control Register 0 7 6 5 Reset Value: 04H 4 3 2 1 0 0 IMODE 0 1 0 RMAP r rw r r r rw Field Bits Type Description RMAP 0 rw Interrupt Node XINTR0 Enable 0 The access to the standard SFR area is enabled 1 The access to the mapped SFR area is enabled 1 2 r Reserved Returns 1 if read; should be written with 1. 0 [7:5], 3,1 r Reserved Returns 0 if read; should be written with 0. Note: The RMAP bit should be cleared/set by ANL or ORL instructions.The rest bits of SYSCON0 should not be modified. 3.2.2.2 Address Extension by Paging Address extension is further performed at the module level by paging. With the address extension by mapping, the XC878 XC878 has a 256-SFR 256-SFR address range. However, this is still less than the total number of SFRs needed by the on-chip peripherals. To meet this requirement, some peripherals have a built-in local address extension mechanism for increasing the number of addressable SFRs. The extended address range is not directly controlled by the CPU instruction itself, but is derived from bit field PAGE in the module page register MOD_PAGE. Hence, the bit field PAGE must be programmed before accessing the SFR of the target module. Each module may contain a different number of pages and a different number of SFRs per page, depending on the specific requirement. Besides setting the correct RMAP bit value to select the SFR area, the user must also ensure that a valid PAGE is selected to target the desired SFR. A page inside the extended address range can be selected as shown in Figure 9. Data Sheet 26 V1.2, 2009-11 XC878CLM XC878CLM Functional Description SFR Address (from CPU) PAGE 0 MOD_PAGE.PAGE SFR0 rw SFR1 . SFRx PAGE 1 SFR0 SFR Data (to/from CPU) SFR1 . SFRy . PAGE q SFR0 SFR1 . SFRz Module Figure 9 Address Extension by Paging In order to access a register located in a page different from the actual one, the current page must be exited. This is done by reprogramming the bit field PAGE in the page register. Only then can the desired access be performed. If an interrupt routine is initiated between the page register access and the module register access, and the interrupt needs to access a register located in another page, the current page setting can be saved, the new one programmed and the old page setting restored. This is possible with the storage fields STx (x = 0 - 3) for the save and restore action of the current page setting. By indicating which storage bit field should be used in parallel with the new page value, a single write operation can: · Save the contents of PAGE in STx before overwriting with the new value (this is done in the beginning of the interrupt routine to save the current page setting and program the new page number); or Data Sheet 27 V1.2, 2009-11 XC878CLM XC878CLM Functional Description · Overwrite the contents of PAGE with the contents of STx, ignoring the value written to the bit positions of PAGE (this is done at the end of the interrupt routine to restore the previous page setting before the interrupt occurred) ST3 ST2 ST1 ST0 STNR PAGE value update from CPU Figure 10 Storage Elements for Paging With this mechanism, a certain number of interrupt routines (or other routines) can perform page changes without reading and storing the previously used page information. The use of only write operations makes the system simpler and faster. Consequently, this mechanism significantly improves the performance of short interrupt routines. The XC878 XC878 supports local address extension for: · · · · Parallel Ports Analog-to-Digital Converter (ADC) Capture/Compare Unit 6 (CCU6) System Control Registers Data Sheet 28 V1.2, 2009-11 XC878CLM XC878CLM Functional Description The page register has the following definition: MOD_PAGE Page Register for module MOD 7 6 Reset Value: 00H 5 4 3 2 1 OP STNR 0 PAGE w w r 0 rw Field Bits Type Description PAGE [2:0] rw Page Bits When written, the value indicates the new page. When read, the value indicates the currently active page. STNR [5:4] w Storage Number This number indicates which storage bit field is the target of the operation defined by bit field OP. If OP = 10B, the contents of PAGE are saved in STx before being overwritten with the new value. If OP = 11B, the contents of PAGE are overwritten by the contents of STx. The value written to the bit positions of PAGE is ignored. 00 01 10 11 Data Sheet ST0 is selected. ST1 is selected. ST2 is selected. ST3 is selected. 29 V1.2, 2009-11 XC878CLM XC878CLM Functional Description Field Bits Type Description OP [7:6] w Operation 0X Manual page mode. The value of STNR is ignored and PAGE is directly written. 10 New page programming with automatic page saving. The value written to the bit positions of PAGE is stored. In parallel, the previous contents of PAGE are saved in the storage bit field STx indicated by STNR. 11 Automatic restore page action. The value written to the bit positions PAGE is ignored and instead, PAGE is overwritten by the contents of the storage bit field STx indicated by STNR. 0 3 r Reserved Returns 0 if read; should be written with 0. 3.2.3 Bit Protection Scheme The bit protection scheme prevents direct software writing of selected bits (i.e., protected bits) using the PASSWD register. When the bit field MODE is 11B, writing 10011B 10011B to the bit field PASS opens access to writing of all protected bits, and writing 10101B 10101B to the bit field PASS closes access to writing of all protected bits. In both cases, the value of the bit field MODE is not changed even if PASSWD register is written with 98H or A8H. It can only be changed when bit field PASS is written with 11000B 11000B, for example, writing D0H to PASSWD register disables the bit protection scheme. Note that access is opened for maximum 32 CCLKs if the "close access" password is not written. If "open access" password is written again before the end of 32 CCLK cycles, there will be a recount of 32 CCLK cycles. The protected bits include the N- and KDivider bits, NDIV and KDIV; the Watchdog Timer enable bit, WDTEN; and the powerdown and slow-down enable bits, PD and SD. Data Sheet 30 V1.2, 2009-11 XC878CLM XC878CLM Functional Description 3.2.3.1 Password Register PASSWD Password Register 7 6 Reset Value: 07H 5 4 3 2 1 0 PASS PROTECT _S MODE w rh rw Field Bits Type Description MODE [1:0] rw Bit Protection Scheme Control Bits 00 Scheme disabled - direct access to the protected bits is allowed. 11 Scheme enabled - the bit field PASS has to be written with the passwords to open and close the access to protected bits. (default) Others:Scheme Enabled. These two bits cannot be written directly. To change the value between 11B and 00B, the bit field PASS must be written with 11000B 11000B; only then, will the MODE[1:0] be registered. PROTECT_S 2 rh Bit Protection Signal Status Bit This bit shows the status of the protection. 0 Software is able to write to all protected bits. 1 Software is unable to write to any protected bits. PASS [7:3] w Password Bits The Bit Protection Scheme only recognizes three patterns. 11000B 11000B Enables writing of the bit field MODE. 10011B 10011B Opens access to writing of all protected bits. 10101B 10101B Closes access to writing of all protected bits Data Sheet 31 V1.2, 2009-11 XC878CLM XC878CLM Functional Description 3.2.4 XC878 XC878 Register Overview The SFRs of the XC878 XC878 are organized into groups according to their functional units. The contents (bits) of the SFRs are summarized in Chapter 3.2.4.1 to Chapter 3.2.4.15. Note: The addresses of the bitaddressable SFRs appear in bold typeface. 3.2.4.1 CPU Registers The CPU SFRs can be accessed in both the standard and mapped memory areas (RMAP = 0 or 1). Table 5 CPU Register Overview Addr Register Name Bit 7 6 5 4 3 2 1 0 RMAP = 0 or 1 81H SP Reset: 07H Stack Pointer Register Bit Field 82H DPL Reset: 00H Data Pointer Register Low Bit Field DPH Reset: 00H Data Pointer Register High Bit Field PCON Reset: 00H Power Control Register Bit Field TCON Reset: 00H Timer Control Register Bit Field TF1 TR1 TF0 Type rwh rw rwh TMOD Reset: 00H Timer Mode Register Bit Field GATE 1 T1S rw rw 83H 87H 88H 89H Type Type Type Type Type 8AH 8BH 8CH 8DH 94H 95H 96H SP rw DPL7 DPL6 DPL5 DPL4 DPL3 DPL2 DPL1 DPL0 rw rw rw rw rw rw rw rw DPH7 DPH6 DPH5 DPH4 DPH3 DPH2 DPH1 DPH0 rw rw rw rw rw rw rw rw SMOD 0 GF1 GF0 0 IDLE rw r rw rw r rw TR0 IE1 IT1 IE0 IT0 rw rwh rw rwh rw T1M GATE 0 T0S T0M rw rw rw rw TL0 Reset: 00H Timer 0 Register Low Bit Field VAL Type rwh TL1 Reset: 00H Timer 1 Register Low Bit Field VAL Type rwh TH0 Reset: 00H Timer 0 Register High Bit Field VAL Type rwh TH1 Reset: 00H Timer 1 Register High Bit Field VAL Type rwh MEX1 Reset: 00H Memory Extension Register 1 Bit Field MEX2 Reset: 00H Memory Extension Register 2 Bit Field MEX3 Reset: 00H Memory Extension Register 3 Bit Field Type NB r Type Type Data Sheet CB rw MCM MCB IB rw rw rw MCB1 9 0 MXB1 9 MXM MXB rw r rw rw rw 32 V1.2, 2009-11 XC878CLM XC878CLM Functional Description Table 5 CPU Register Overview (cont'd) Addr Register Name Bit 7 97H MEXSP Reset: 7FH Memory Extension Stack Pointer Register Bit Field 0 MXSP Type r rwh SCON Reset: 00H Serial Channel Control Register Bit Field SBUF Reset: 00H Serial Data Buffer Register Bit Field VAL Type rwh EO Reset: 00H Extended Operation Register Bit Field 0 TRAP_ EN 0 DPSE L0 Type r rw r rw 98H 99H A2H A8H B8H B9H Type 6 5 4 3 2 1 0 SM0 SM1 SM2 REN TB8 RB8 TI RI rw rw rw rw rw rwh rwh rwh IEN0 Reset: 00H Interrupt Enable Register 0 Bit Field EA 0 ET2 ES ET1 EX1 ET0 EX0 Type rw r rw rw rw rw rw rw IP Reset: 00H Interrupt Priority Register Bit Field 0 PT2 PS PT1 PX1 PT0 PX0 Type r rw rw rw rw rw rw IPH Reset: 00H Interrupt Priority High Register Bit Field 0 PT2H PSH PT1H PX1H PT0H PX0H Type r rw rw rw rw rw rw E0H E8H F0H PSW Reset: 00H Program Status Word Register Bit Field CY AC F0 RS1 RS0 OV F1 P Type rwh rwh rw rw rw rwh rw rh ACC Reset: 00H Accumulator Register Bit Field ACC7 ACC6 ACC5 ACC4 ACC3 ACC2 ACC1 ACC0 rw rw rw rw rw rw rw rw IEN1 Reset: 00H Interrupt Enable Register 1 Bit Field ECCIP 3 ECCIP 2 ECCIP 1 ECCIP 0 EXM EX2 ESSC EADC Type D0H rw rw rw rw rw rw rw rw Bit Field B7 B6 B5 B4 B3 B2 B1 B0 Type rw rw rw rw rw rw rw rw PCCIP 3 PCCIP 2 PCCIP 1 PCCIP 0 PXM PX2 PSSC PADC B B Register Reset: 00H Type F8H IP1 Reset: 00H Interrupt Priority 1 Register F9H IPH1 Reset: 00H Bit Field Interrupt Priority 1 High Register Bit Field Type Type 3.2.4.2 rw rw rw rw rw rw rw rw PCCIP 3H PCCIP 2H PCCIP 1H PCCIP 0H PXMH PX2H PSSC H PADC H rw rw rw rw rw rw rw rw 2 1 0 MDU Registers The MDU SFRs can be accessed in the mapped memory area (RMAP = 1). Table 6 MDU Register Overview Addr Register Name Bit 7 6 5 4 3 RMAP = 1 B0H MDUSTAT Reset: 00H MDU Status Register Data Sheet Bit Field 0 BSY IERR IRDY Type r rh rwh rwh 33 V1.2, 2009-11 XC878CLM XC878CLM Functional Description Table 6 MDU Register Overview (cont'd) Addr Register Name Bit 7 6 5 4 B1H Bit Field IE IR RSEL STAR T OPCODE Type rw rw rw rwh rw MDUCON Reset: 00H MDU Control Register MD0 Reset: 00H MDU Operand Register 0 Bit Field B2H MR0 Reset: 00H MDU Result Register 0 Bit Field B3H MD1 Reset: 00H MDU Operand Register 1 Bit Field MR1 Reset: 00H MDU Result Register 1 Bit Field MD2 Reset: 00H MDU Operand Register 2 Bit Field MR2 Reset: 00H MDU Result Register 2 Bit Field MD3 Reset: 00H MDU Operand Register 3 Bit Field MR3 Reset: 00H MDU Result Register 3 Bit Field MD4 Reset: 00H MDU Operand Register 4 Bit Field MR4 Reset: 00H MDU Result Register 4 Bit Field MD5 Reset: 00H MDU Operand Register 5 Bit Field MR5 Reset: 00H MDU Result Register 5 Bit Field B2H B3H B4H B4H B5H B5H B6H B6H B7H B7H 3.2.4.3 3 2 1 0 DATA Type rw DATA Type rh DATA Type rw DATA Type rh DATA Type rw DATA Type rh DATA Type rw DATA Type rh DATA Type rw DATA Type rh DATA Type rw DATA Type rh CORDIC Registers The CORDIC SFRs can be accessed in the mapped memory area (RMAP = 1). Table 7 CORDIC Register Overview Addr Register Name Bit 7 6 5 4 3 2 1 0 RMAP = 1 9AH 9BH CD_CORDXL Reset: 00H CORDIC X Data Low Byte Bit Field CD_CORDXH Reset: 00H CORDIC X Data High Byte Bit Field Data Sheet DATAL Type rw DATAH Type rw 34 V1.2, 2009-11 XC878CLM XC878CLM Functional Description Table 7 CORDIC Register Overview (cont'd) Addr Register Name Bit 9CH CD_CORDYL Reset: 00H CORDIC Y Data Low Byte Bit Field CD_CORDYH Reset: 00H CORDIC Y Data High Byte Bit Field CD_CORDZL Reset: 00H CORDIC Z Data Low Byte Bit Field CD_CORDZH Reset: 00H CORDIC Z Data High Byte Bit Field CD_STATC Reset: 00H CORDIC Status and Data Control Register Bit Field CD_CON Reset: 00H CORDIC Control Register Bit Field 9DH 9EH 9FH A0H A1H 7 5 4 3 1 0 rw DATAH Type rw DATAL Type rw DATAH Type Type 2 DATAL Type rw KEEP Z KEEP Y KEEP X DMAP INT_E N EOC ERRO R BSY rw rw rw rw rw rwh rh rh MPS X_USI GN ST_M ODE ROTV EC MODE ST rw rw rw rw rw rwh Type 3.2.4.4 6 System Control Registers The system control SFRs can be accessed in the mapped memory area (RMAP = 0). Table 8 SCU Register Overview Addr Register Name Bit 7 6 5 4 3 2 1 0 RMAP = 0 or 1 SYSCON0 Reset: 04H System Control Register 0 Bit Field 0 IMOD E 0 1 0 RMAP Type 8FH r rw r r r rw RMAP = 0 BFH SCU_PAGE Page Register Reset: 00H Bit Field OP 0 PAGE w Type STNR w r rwh RMAP = 0, PAGE 0 B4H MODPISEL Reset: 00H Peripheral Input Select Register IRCON0 Reset: 00H Interrupt Request Register 0 Bit Field 0 URRIS H JTAGT DIS JTAGT CKS EXINT 2IS EXINT 1IS EXINT 0IS URRIS Type B3H r rw rw rw rw rw rw rw Bit Field 0 EXINT 6 EXINT 5 EXINT 4 EXINT EXINT 2 EXINT 1 EXINT 0 3 Type B6H IRCON1 Reset: 00H Interrupt Request Register 1 IRCON2 Reset: 00H Interrupt Request Register 2 rwh rwh rwh rwh rwh rwh rwh Bit Field 0 CANS RC2 CANS RC1 ADCS R1 ADCS R0 RIR TIR EIR Type B5H r r rwh rwh rwh rwh rwh rwh rwh 0 CANS RC3 0 CANS RC0 Type Data Sheet Bit Field r rwh r rwh 35 V1.2, 2009-11 XC878CLM XC878CLM Functional Description Table 8 SCU Register Overview (cont'd) Addr Register Name Bit B7H EXICON0 Reset: F0H External Interrupt Control Register 0 Bit Field EXINT3 EXINT2 EXINT1 EXINT0 Type rw rw rw rw EXICON1 Reset: 3FH External Interrupt Control Register 1 Bit Field 0 EXINT6 EXINT5 EXINT4 Type r rw rw rw NMICON Reset: 00H NMI Control Register Bit Field 0 NMI ECC NMI VDDP 0 NMI OCDS NMI FLASH NMI PLL NMI WDT Type r rw rw r rw rw rw rw Bit Field 0 FNMI ECC FNMI VDDP 0 FNMI OCDS FNMI FLASH FNMI PLL FNMI WDT Type r rwh rwh r rwh rwh rwh rwh BGSEL NDOV EN BRDIS BRPRE R rw rw rw rw rw BAH BBH BCH BDH NMISR Reset: 00H NMI Status Register BCON Reset: 20H Baud Rate Control Register 7 6 Bit Field Type BEH E9H EAH EBH BG Reset: 00H Baud Rate Timer/Reload Register Bit Field FDSTEP Reset: 00H Fractional Divider Reload Register Bit Field FDRES Reset: 00H Fractional Divider Result Register 4 Bit Field FDCON Reset: 00H Fractional Divider Control Register 5 Bit Field 3 1 0 BR_VALUE Type Type 2 rwh BGS SYNE N ERRS YN EOFS YN BRK NDOV FDM FDEN rw rw rwh rwh rwh rwh rw rw STEP Type rw RESULT Type rh RMAP = 0, PAGE 1 B3H ID Identity Register Reset: 49H Bit Field B4H PMCON0 Reset: 80H Power Mode Control Register 0 Bit Field PRODID Type VERID r r B6H OSC_CON Reset: XXH OSC Control Register WKRS WK SEL SD PD WS rh rwh rwh rw rw rwh rw Bit Field 0 CDC_ DIS CAN_ DIS MDU_ DIS T2CC U_DIS CCU_ DIS SSC_ DIS ADC_ DIS Type PMCON1 Reset: 00H Power Mode Control Register 1 WDT RST Type B5H VDDP WARN r rw rw rw rw rw rw rw PLLRD RES PLLBY P PLLPD 0 XPD OSC SS EORD RES EXTO SCR rwh rwh rw r rw rwh rwh rh NDIV PLLR PLL_L OCK rw rh rh Bit Field Type B7H PLL_CON Reset: 18H PLL Control Register Bit Field Type BAH CMCON Reset: 10H Clock Control Register Bit Field Type Data Sheet KDIV 0 FCCF G CLKREL rw r rw rw 36 V1.2, 2009-11 XC878CLM XC878CLM Functional Description Table 8 SCU Register Overview (cont'd) Addr Register Name Bit BBH Bit Field PASSWD Reset: 07H Password Register 7 6 E9H COCON Reset: 00H Clock Output Control Register Bit Field MISC_CON Reset: 00H Miscellaneous Control Register Bit Field EAH EBH PLL_CON1 Reset: 20H PLL Control Register 1 Bit Field 1 0 PROT ECT_S MODE rh rw TLEN 0 COREL rw rw r rw ADCE TR0_ MUX ADCE TR1_ MUX 0 DFLAS HEN rw rw r rwh NDIV PDIV rw Type Type 2 COUTS Bit Field CR_MISC Reset: 00H or 01H Reset Status Register 3 w Type Type 4 PASS Type BEH 5 rw CCCF G MDUC CFG CCUC CFG T2CCF G 0 HDRS T rw rw rw rw r rwh RMAP = 0, PAGE 3 B5H B6H B7H BAH BBH Bit Field IRCON3 Reset: 00H Interrupt Request Register 3 Bit Field 0 CANS RC5 CCU6 SR1 0 CANS RC4 CCU6 SR0 r rwh rwh r rwh rwh Bit Field 0 CANS RC7 CCU6 SR3 0 CANS RC6 CCU6 SR2 Type B4H XADDRH Reset: F0H On-chip XRAM Address Higher Order Type B3H r rwh rwh r rwh rwh IRCON4 Reset: 00H Interrupt Request Register 4 ADDRH Type rw MODIEN Reset: 07H Peripheral Interrupt Enable Register Bit Field 0 CM5E N CM4E N RIREN TIREN EIREN Type r rw rw rw rw rw MODPISEL1 Reset: 00H Peripheral Input Select Register 1 Bit Field MODPISEL2 Reset: 00H Peripheral Input Select Register 2 UR1RIS T21EX T21EX IS 0 Type rw rw rw r Bit Field 0 T2EXI S T21IS T21IS T2IS T1IS T0IS Type r rw rw rw rw rw BEH EAH MODSUSP Reset: 01H Module Suspend Control Register Bit Field 0 UART 1_DIS T21_D IS Type BDH PMCON2 Reset: 00H Power Mode Control Register 2 EXINT6IS r rw rw Bit Field 0 CCTS USP T21SU T21SU SP T2SUS P T13SU T13SU SP T12SU T12SU SP WDTS USP Type r rw rw rw rw rw rw MODPISEL3 Reset: 00H Peripheral Input Select Register 3 Bit Field 0 CIS SIS MIS Type r rw rw rw MODPISEL4 Reset: 00H Peripheral Input Select Register 4 Bit Field 0 EXINT5IS EXINT4IS EXINT3IS Type r rw rw rw Data Sheet 37 V1.2, 2009-11 XC878CLM XC878CLM Functional Description 3.2.4.5 WDT Registers The WDT SFRs can be accessed in the mapped memory area (RMAP = 1). Table 9 WDT Register Overview Addr Register Name Bit 7 6 5 4 3 2 1 0 RMAP = 1 BBH BCH BDH BEH BFH WDTCON Reset: 00H Watchdog Timer Control Register Bit Field 0 WINB EN WDTP R 0 WDTE N WDTR S WDTI N Type r rw rh r rw rwh rw WDTREL Reset: 00H Watchdog Timer Reload Register Bit Field WDTWINB Reset: 00H Watchdog Window-Boundary Count Register Bit Field WDTL Reset: 00H Watchdog Timer Register Low Bit Field WDTH Reset: 00H Watchdog Timer Register High Bit Field 1 0 3.2.4.6 WDTREL Type rw WDTWINB Type rw WDT Type rh WDT Type rh Port Registers The Port SFRs can be accessed in the standard memory area (RMAP = 0). Table 10 Port Register Overview Addr Register Name Bit 7 6 5 4 3 2 RMAP = 0 B2H PORT_PAGE Page Register Reset: 00H OP Type STNR 0 PAGE w Bit Field w r rwh RMAP = 0, PAGE 0 80H 86H 90H 91H 92H 93H P0_DATA Reset: 00H P0 Data Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rwh rwh rwh rwh rwh rwh rwh rwh P0_DIR Reset: 00H P0 Direction Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw P1_DATA Reset: 00H P1 Data Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rwh rwh rwh rwh rwh rwh rwh rwh P1_DIR Reset: 00H P1 Direction Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw P5_DATA Reset: 00H P5 Data Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rwh rwh rwh rwh rwh rwh rwh rwh P5_DIR Reset: 00H P5 Direction Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw Data Sheet 38 V1.2, 2009-11 XC878CLM XC878CLM Functional Description Table 10 Port Register Overview (cont'd) Addr Register Name Bit B0H P3_DATA Reset: 00H P3 Data Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rwh rwh rwh rwh rwh rwh rwh rwh P3_DIR Reset: 00H P3 Direction Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw P4_DATA Reset: 00H P4 Data Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rwh rwh rwh rwh rwh rwh rwh rwh P4_DIR Reset: 00H P4 Direction Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw P0_PUDSEL Reset: FFH P0 Pull-Up/Pull-Down Select Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw P0_PUDEN Reset: C4H P0 Pull-Up/Pull-Down Enable Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw P1_PUDSEL Reset: FFH P1 Pull-Up/Pull-Down Select Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw P1_PUDEN Reset: FFH P1 Pull-Up/Pull-Down Enable Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw P5_PUDSEL Reset: FFH P5 Pull-Up/Pull-Down Select Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw P5_PUDEN Reset: FFH P5 Pull-Up/Pull-Down Enable Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw P3_PUDSEL Reset: BFH P3 Pull-Up/Pull-Down Select Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw P3_PUDEN Reset: 40H P3 Pull-Up/Pull-Down Enable Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw P4_PUDSEL Reset: FFH P4 Pull-Up/Pull-Down Select Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw P4_PUDEN Reset: 04H P4 Pull-Up/Pull-Down Enable Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw P0_ALTSEL0 Reset: 00H P0 Alternate Select 0 Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw P0_ALTSEL1 Reset: 00H P0 Alternate Select 1 Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw P1_ALTSEL0 Reset: 00H P1 Alternate Select 0 Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw B1H C8H C9H 7 6 5 4 3 2 1 0 RMAP = 0, PAGE 1 80H 86H 90H 91H 92H 93H B0H B1H C8H C9H RMAP = 0, PAGE 2 80H 86H 90H Data Sheet 39 V1.2, 2009-11 XC878CLM XC878CLM Functional Description Table 10 Port Register Overview (cont'd) Addr Register Name Bit 7 6 5 4 3 2 1 0 91H P1_ALTSEL1 Reset: 00H P1 Alternate Select 1 Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw P5_ALTSEL0 Reset: 00H P5 Alternate Select 0 Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw P5_ALTSEL1 Reset: 00H P5 Alternate Select 1 Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw P3_ALTSEL0 Reset: 00H P3 Alternate Select 0 Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw P3_ALTSEL1 Reset: 00H P3 Alternate Select 1 Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw P4_ALTSEL0 Reset: 00H P4 Alternate Select 0 Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw P4_ALTSEL1 Reset: 00H P4 Alternate Select 1 Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw P0_OD Reset: 00H P0 Open Drain Control Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw P0_DS Reset: FFH P0 Drive Strength Control Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw P1_OD Reset: 00H P1 Open Drain Control Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw P1_DS Reset: FFH P1 Drive Strength Control Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw P5_OD Reset: 00H P5 Open Drain Control Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw P5_DS Reset: FFH P5 Drive Strength Control Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw P3_OD Reset: 00H P3 Open Drain Control Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw P3_DS Reset: FFH P3 Drive Strength Control Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw P4_OD Reset: 00H P4 Open Drain Control Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw P4_DS Reset: FFH P4 Drive Strength Control Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw 92H 93H B0H B1H C8H C9H RMAP = 0, PAGE 3 80H 86H 90H 91H 92H 93H B0H B1H C8H C9H Data Sheet 40 V1.2, 2009-11 XC878CLM XC878CLM Functional Description 3.2.4.7 ADC Registers The ADC SFRs can be accessed in the standard memory area (RMAP = 0). Table 11 ADC Register Overview Addr Register Name Bit 7 6 5 4 3 2 1 0 RMAP = 0 D1H ADC_PAGE Page Register Reset: 00H OP STNR 0 PAGE w Bit Field w r rw Type RMAP = 0, PAGE 0 CAH CCH Bit Field ADC_GLOBSTR Reset: 00H Global Status Register Bit Field 0 CHNR 0 SAMP LE BUSY Type CBH ADC_GLOBCTR Reset: 30H Global Control Register r rh r rh rh ADC_PRAR Reset: 00H Priority and Arbitration Register Type Bit Field Type CDH CEH CFH ADC_LCBR Reset: B7H Limit Check Boundary Register ANON DW CTC 0 rw rw rw r ASEN 1 ASEN 0 0 ARBM CSM1 PRIO1 CSM0 PRIO0 rw rw r rw rw rw rw rw Bit Field BOUND1 BOUND0 rw rw Type ADC_INPCR0 Reset: 00H Input Class 0 Register Bit Field ADC_ETRCR Reset: 00H External Trigger Control Register Bit Field STC Type rw SYNE N1 SYNE N0 ETRSEL1 ETRSEL0 Type rw rw rw rw ADC_CHCTR0 Reset: 00H Channel Control Register 0 Bit Field 0 LCC 0 RESRSEL Type r rw r rw ADC_CHCTR1 Reset: 00H Channel Control Register 1 Bit Field 0 LCC 0 RESRSEL Type r rw r rw ADC_CHCTR2 Reset: 00H Channel Control Register 2 Bit Field 0 LCC 0 RESRSEL Type r rw r rw ADC_CHCTR3 Reset: 00H Channel Control Register 3 Bit Field 0 LCC 0 RESRSEL Type r rw r rw ADC_CHCTR4 Reset: 00H Channel Control Register 4 Bit Field 0 LCC 0 RESRSEL Type r rw r rw ADC_CHCTR5 Reset: 00H Channel Control Register 5 Bit Field 0 LCC 0 RESRSEL Type r rw r rw ADC_CHCTR6 Reset: 00H Channel Control Register 6 Bit Field 0 LCC 0 RESRSEL Type r rw r rw ADC_CHCTR7 Reset: 00H Channel Control Register 7 Bit Field 0 LCC 0 RESRSEL Type r rw r rw RMAP = 0, PAGE 1 CAH CBH CCH CDH CEH CFH D2H D3H Data Sheet 41 V1.2, 2009-11 XC878CLM XC878CLM Functional Description Table 11 ADC Register Overview (cont'd) Addr Register Name Bit 7 6 5 4 3 2 1 RESULT 0 VF DRC CHNR rh r rh rh 0 rh RMAP = 0, PAGE 2 ADC_RESR0L Reset: 00H Result Register 0 Low Bit Field ADC_RESR0H Reset: 00H Result Register 0 High Bit Field ADC_RESR1L Reset: 00H Result Register 1 Low Bit Field ADC_RESR1H Reset: 00H Result Register 1 High Bit Field ADC_RESR2L Reset: 00H Result Register 2 Low Bit Field CFH ADC_RESR2H Reset: 00H Result Register 2 High Bit Field D2H ADC_RESR3L Reset: 00H Result Register 3 Low Bit Field ADC_RESR3H Reset: 00H Result Register 3 High Bit Field CAH CBH CCH CDH CEH D3H Type RESULT Type rh RESULT 0 VF DRC CHNR rh r rh rh rh Type RESULT Type rh RESULT 0 VF DRC CHNR rh r rh rh rh Type RESULT Type rh RESULT 0 VF DRC CHNR rh r rh rh rh Type RESULT Type rh RMAP = 0, PAGE 3 ADC_RESRA0L Reset: 00H Result Register 0, View A Low Bit Field ADC_RESRA0H Reset: 00H Result Register 0, View A High Bit Field CCH ADC_RESRA1L Reset: 00H Result Register 1, View A Low Bit Field CDH ADC_RESRA1H Reset: 00H Result Register 1, View A High Bit Field ADC_RESRA2L Reset: 00H Result Register 2, View A Low Bit Field ADC_RESRA2H Reset: 00H Result Register 2, View A High Bit Field ADC_RESRA3L Reset: 00H Result Register 3, View A Low Bit Field ADC_RESRA3H Reset: 00H Result Register 3, View A High Bit Field CAH CBH CEH CFH D2H D3H RESULT VF DRC CHNR rh rh rh rh Type RESULT Type rh RESULT VF DRC CHNR rh rh rh rh Type RESULT Type rh RESULT VF DRC CHNR rh rh rh rh Type RESULT Type rh RESULT VF DRC CHNR rh rh rh rh Type RESULT Type rh RMAP = 0, PAGE 4 CAH ADC_RCR0 Reset: 00H Result Control Register 0 Bit Field Type Data Sheet VFCT R WFR 0 IEN 0 DRCT R rw rw r rw r rw 42 V1.2, 2009-11 XC878CLM XC878CLM Functional Description Table 11 ADC Register Overview (cont'd) Addr Register Name Bit CBH Bit Field ADC_RCR1 Reset: 00H Result Control Register 1 Type CCH ADC_RCR2 Reset: 00H Result Control Register 2 Bit Field Type CDH ADC_RCR3 Reset: 00H Result Control Register 3 Bit Field Type CEH ADC_VFCR Reset: 00H Valid Flag Clear Register 7 6 5 4 3 2 1 0 VFCT R WFR 0 IEN 0 DRCT R rw rw r rw r rw VFCT R WFR 0 IEN 0 DRCT R rw rw r rw r rw VFCT R WFR 0 IEN 0 DRCT R rw rw r rw r rw Bit Field 0 VFC3 VFC2 VFC1 VFC0 Type r w w w w RMAP = 0, PAGE 5 CAH ADC_CHINFR Reset: 00H Channel Interrupt Flag Register Bit Field Type CBH ADC_CHINCR Reset: 00H Channel Interrupt Clear Register Bit Field Type CCH ADC_CHINSR Reset: 00H Channel Interrupt Set Register Bit Field Type CDH CEH ADC_CHINPR Reset: 00H Channel Interrupt Node Pointer Register Bit Field ADC_EVINFR Reset: 00H Event Interrupt Flag Register Bit Field Type Type CFH D2H ADC_EVINCR Reset: 00H Event Interrupt Clear Flag Register Bit Field Type ADC_EVINSR Reset: 00H Bit Field Event Interrupt Set Flag Register Type D3H ADC_EVINPR Reset: 00H Event Interrupt Node Pointer Register Bit Field Type CHINF 7 CHINF 6 CHINF 5 CHINF 4 CHINF 3 CHINF 2 CHINF 1 CHINF 0 rh rh rh rh rh rh rh rh CHINC 7 CHINC 6 CHINC 5 CHINC 4 CHINC 3 CHINC 2 CHINC 1 CHINC 0 w w w w w w w w CHINS 7 CHINS 6 CHINS 5 CHINS 4 CHINS 3 CHINS 2 CHINS 1 CHINS 0 w w w w w w w w CHINP 7 CHINP 6 CHINP 5 CHINP 4 CHINP 3 CHINP 2 CHINP 1 CHINP 0 rw rw rw rw rw rw rw rw EVINF 7 EVINF 6 EVINF 5 EVINF 4 0 EVINF 1 EVINF 0 rh rh rh rh r rh rh EVINC 7 EVINC 6 EVINC 5 EVINC 4 0 EVINC 1 EVINC 0 w w w w r w w EVINS 7 EVINS 6 EVINS 5 EVINS 4 0 EVINS 1 EVINS 0 w w w w r w w EVINP 7 EVINP 6 EVINP 5 EVINP 4 0 EVINP 1 EVINP 0 rw rw rw rw r rw rw RMAP = 0, PAGE 6 CAH CBH ADC_CRCR1 Reset: 00H Conversion Request Control Register 1 Bit Field CH7 CH6 CH5 CH4 0 Type rwh rwh rwh rwh r ADC_CRPR1 Reset: 00H Conversion Request Pending Register 1 Bit Field CHP7 CHP6 CHP5 CHP4 0 rwh rwh rwh rwh r Data Sheet Type 43 V1.2, 2009-11 XC878CLM XC878CLM Functional Description Table 11 ADC Register Overview (cont'd) Addr Register Name Bit CCH ADC_CRMR1 Reset: 00H Conversion Request Mode Register 1 Bit Field ADC_QMR0 Reset: 00H Queue Mode Register 0 Bit Field CDH Type Type CEH ADC_QSR0 Reset: 20H Queue Status Register 0 Bit Field Type CFH D2H D2H ADC_Q0R0 Reset: 00H Queue 0 Register 0 Bit Field ADC_QBUR0 Reset: 00H Queue Backup Register 0 Bit Field ADC_QINR0 Reset: 00H Queue Input Register 0 Bit Field Data Sheet Type Type Type 7 6 5 4 3 2 1 0 Rsv LDEV CLRP ND SCAN ENSI ENTR 0 ENGT r w w rw rw rw r rw CEV TREV FLUS H CLRV 0 ENTR 0 ENGT w w w w r rw r rw Rsv 0 EMPT Y EV 0 FILL r r rh rh r rh EXTR ENSI RF V 0 REQCHNR rh rh rh rh r rh EXTR ENSI RF V 0 REQCHNR rh rh rh rh r rh EXTR ENSI RF 0 REQCHNR w w w r w 44 V1.2, 2009-11 XC878CLM XC878CLM Functional Description 3.2.4.8 Timer 2 Compare/Capture Unit Registers The Timer 2 Compare/Capture Unit SFRs can be accessed in the standard memory area (RMAP = 0). Table 12 T2CCU Register Overview Addr Register Name Bit 7 6 5 4 3 2 1 0 RMAP = 0 C7H T2_PAGE Page Register Reset: 00H Bit Field OP 0 PAGE w Type STNR w r rwh 0 EXEN 2 RMAP = 0, PAGE 0 C0H T2_T2CON Reset: 00H Timer 2 Control Register Bit Field C1H T2_T2MOD Reset: 00H Timer 2 Mode Register Bit Field Type Type TF2 EXF2 r TR2 rwh rw C/T2 CP/ RL2 rw rwh rwh T2RE GS T2RH EN EDGE SEL PREN T2PRE DCEN rw rw rw rw rw rw rw C3H C4H C5H C6H T2_RC2L Reset: 00H Timer 2 Reload/Capture Register Low Bit Field RC2 Type rwh T2_RC2H Reset: 00H Timer 2 Reload/Capture Register High Bit Field RC2 Type rwh T2_T2L Reset: 00H Timer 2 Register Low Bit Field T2_T2H Reset: 00H Timer 2 Register High Bit Field T2_T2CON1 Reset: 03H Timer 2 Control Register 1 Bit Field 0 TF2EN EXF2E N Type C2H r rw rw THL2 Type rwh THL2 Type rwh RMAP = 0, PAGE 1 C0H C1H C2H C3H C4H T2CCU_CCEN Reset: 00H T2CCU Capture/Compare Enable Register Bit Field T2CCU_CCTBSELReset: 00H T2CCU Capture/Compare Time Base Select Register Bit Field CCM3 CCM2 CCM1 CCM0 rw rw rw rw Type Type CASC CCTT OV CCTB 5 CCTB 4 CCTB 3 CCTB 2 CCTB 1 CCTB 0 rw rwh rw rw rw rw rw rw T2CCU_CCTRELLReset: 00H T2CCU Capture/Compare Timer Reload Register Low Bit Field T2CCU_CCTRELHReset: 00H T2CCU Capture/Compare Timer Reload Register High Bit Field T2CCU_CCTL Reset: 00H T2CCU Capture/Compare Timer Register Low Bit Field CCT Type rwh Data Sheet CCTREL Type rw CCTREL Type rw 45 V1.2, 2009-11 XC878CLM XC878CLM Functional Description Table 12 T2CCU Register Overview (cont'd) Addr Register Name Bit C5H T2CCU_CCTH Reset: 00H T2CCU Capture/Compare Timer Register High Bit Field CCT Type rwh T2CCU_CCTCON Reset: 00H T2CCU CaptureCcompare Timer Control Register Bit Field C6H 7 6 3 2 1 0 CCTPRE CCTO VF CCTO VEN TIMSY N CCTS T rw rwh rw rw rw Type 5 4 RMAP = 0, PAGE 2 C0H C1H C2H C3H C4H C5H C6H T2CCU_COSHDWReset: 00H T2CCU Capture/compare Enable Register Bit Field T2CCU_CC0L Reset: 00H T2CCU Capture/Compare Register 0 Low Bit Field T2CCU_CC0H Reset: 00H T2CCU Capture/compare Register 0 High Bit Field T2CCU_CC1L Reset: 00H T2CCU Capture/compare Register 1 Low Bit Field T2CCU_CC1H Reset: 00H T2CCU Capture/compare Register 1 High Bit Field T2CCU_CC2L Reset: 00H T2CCU Capture/compare Register 2 Low Bit Field T2CCU_CC2H Reset: 00H T2CCU Capture/compare Register 2 High Bit Field Type ENSH DW TXOV COOU T5 COOU T4 COOU T3 COOU T2 COOU T1 COOU T0 rwh rwh rwh rwh rwh rwh rwh rwh CCVALL Type rwh CCVALH Type rwh CCVALL Type rwh CCVALH Type rwh CCVALL Type rwh CCVALH Type rwh RMAP = 0, PAGE 3 C0H C1H C2H C3H C4H C5H C6H T2CCU_COCON Reset: 00H T2CCU Compare Control Register Bit Field T2CCU_CC3L Reset: 00H T2CCU Capture/compare Register 3 Low Bit Field T2CCU_CC3H Reset: 00H T2CCU Capture/compare Register 3 High Bit Field T2CCU_CC4L Reset: 00H T2CCU Capture/compare Register 4 Low Bit Field T2CCU_CC4H Reset: 00H T2CCU Capture/compare Register 4 High Bit Field T2CCU_CC5L Reset: 00H T2CCU Capture/compare Register 5 Low Bit Field T2CCU_CC5H Reset: 00H T2CCU Capture/compare Register 5 High Bit Field Data Sheet Type CCM5 CCM4 CM5F CM4F POLB POLA COMOD rw rw rwh rwh rw rw rw CCVALL Type rwh CCVALH Type rwh CCVALL Type rwh CCVALH Type rwh CCVALL Type rwh CCVALH Type rwh 46 V1.2, 2009-11 XC878CLM XC878CLM Functional Description Table 12 T2CCU Register Overview (cont'd) Addr Register Name Bit 7 6 5 4 3 2 1 0 RMAP = 0, PAGE 4 C2H C3H T2CCU_CCTDTCLReset: 00H T2CCU Capture/Compare Timer Dead-Time Control Register Low Bit Field T2CCU_CCTDTCHReset: 00H T2CCU Capture/Compare Timer Dead-Time Control Register High Bit Field 3.2.4.9 DTM Type Type rw DTRE S DTR2 DTR1 DTR0 DTLEV DTE2 DTE1 DTE0 rwh rh rh rh rw rw rw rw Timer 21 Registers The Timer 21 SFRs can be accessed in the mapped memory area (RMAP = 1). Table 13 T21 Register Overview Addr Register Name Bit 7 6 5 4 3 2 1 0 Bit Field TF2 EXF2 0 EXEN 2 TR2 C/T2 CP/ RL2 Type rwh rwh r rw rwh rw rw T2RE GS T2RH EN EDGE SEL PREN rw rw rw rw RMAP = 1 C0H C1H T21_T2CON Reset: 00H Timer 2 Control Register T21_T2MOD Reset: 00H Timer 2 Mode Register Bit Field Type C2H T2PRE rw rw DCEN rw rw C4H C5H C6H Bit Field RC2 Type rwh T21_RC2H Reset: 00H Timer 2 Reload/Capture Register High Bit Field RC2 Type rwh T21_T2L Reset: 00H Timer 2 Register Low Bit Field T21_T2H Reset: 00H Timer 2 Register High Bit Field T21_T2CON1 Reset: 03H Timer 2 Control Register 1 Bit Field 0 TF2EN EXF2E N Type C3H T21_RC2L Reset: 00H Timer 2 Reload/Capture Register Low r rw rw Data Sheet THL2 Type rwh THL2 Type rwh 47 V1.2, 2009-11 XC878CLM XC878CLM Functional Description 3.2.4.10 CCU6 Registers The CCU6 SFRs can be accessed in the standard memory area (RMAP = 0). Table 14 CCU6 Register Overview Addr Register Name Bit 7 6 5 4 3 2 1 0 RMAP = 0 A3H CCU6_PAGE Page Register Reset: 00H OP STNR 0 PAGE w Bit Field w r rwh Type RMAP = 0, PAGE 0 9AH 9BH 9CH CCU6_CC63SRL CC63SRL Reset: 00H Capture/Compare Shadow Register for Channel CC63 Low Bit Field CCU6_CC63SRH CC63SRH Reset: 00H Capture/Compare Shadow Register for Channel CC63 High Bit Field CCU6_TCTR4L Reset: 00H Timer Control Register 4 Low Bit Field Type CCU6_TCTR4H Reset: 00H Timer Control Register 4 High rw CC63SH CC63SH Type Type 9DH CC63SL CC63SL Bit Field Type 9EH CCU6_MCMOUTSL Reset: 00H Multi-Channel Mode Output Shadow Register Low Bit Field 9FH CCU6_MCMOUTSH Reset: 00H Multi-Channel Mode Output Shadow Register High Bit Field CCU6_ISRL Reset: 00H Capture/Compare Interrupt Status Reset Register Low Bit Field CCU6_ISRH Reset: 00H Capture/Compare Interrupt Status Reset Register High Bit Field T12 STD T12 STR 0 DT RES T12 RES T12R S T12R R w w r w w w w T13 STD T13 STR 0 T13 RES T13R S T13R R w w r w w w STRM CM 0 MCMPS w r STRH P 0 CURHS EXPHS w r rw rw RT12 PM RT12 OM RCC6 2F RCC6 2R RCC6 1F RCC6 1R RCC6 0F RCC6 0R w w w w w w w w RSTR RIDLE RWH E RCHE 0 RTRP F RT13 PM RT13 CM Type w w w w r w w w CCU6_CMPMODIFL Reset: 00H Compare State Modification Register Low Bit Field 0 MCC6 3S 0 MCC6 2S MCC6 1S MCC6 0S Type r w r w w w A7H CCU6_CMPMODIFH Reset: 00H Compare State Modification Register High Bit Field 0 MCC6 3R 0 MCC6 2R MCC6 1R MCC6 0R Type r w r w w w FAH CCU6_CC60SRL CC60SRL Reset: 00H Capture/Compare Shadow Register for Channel CC60 Low Bit Field CCU6_CC60SRH CC60SRH Reset: 00H Capture/Compare Shadow Register for Channel CC60 High Bit Field A4H A5H A6H FBH Data Sheet Type rw Type Type rw CC60SL CC60SL Type rwh CC60SH CC60SH Type rwh 48 V1.2, 2009-11 XC878CLM XC878CLM Functional Description Table 14 CCU6 Register Overview (cont'd) Addr Register Name Bit FCH CCU6_CC61SRL CC61SRL Reset: 00H Capture/Compare Shadow Register for Channel CC61 Low Bit Field CCU6_CC61SRH CC61SRH Reset: 00H Capture/Compare Shadow Register for Channel CC61 High Bit Field CCU6_CC62SRL CC62SRL Reset: 00H Capture/Compare Shadow Register for Channel CC62 Low Bit Field CCU6_CC62SRH CC62SRH Reset: 00H Capture/Compare Shadow Register for Channel CC62 High Bit Field FDH FEH FFH 7 6 5 4 3 2 1 0 CC61SL CC61SL Type rwh CC61SH CC61SH Type rwh CC62SL CC62SL Type rwh CC62SH CC62SH Type rwh RMAP = 0, PAGE 1 9AH 9BH 9CH 9DH 9EH 9FH A4H A5H A6H CCU6_CC63RL CC63RL Reset: 00H Capture/Compare Register for Channel CC63 Low Bit Field CCU6_CC63RH CC63RH Reset: 00H Capture/Compare Register for Channel CC63 High Bit Field CCU6_T12PRL T12PRL Reset: 00H Timer T12 Period Register Low Bit Field CCU6_T12PRH T12PRH Reset: 00H Timer T12 Period Register High Bit Field CCU6_T13PRL T13PRL Reset: 00H Timer T13 Period Register Low Bit Field CCU6_T13PRH T13PRH Reset: 00H Timer T13 Period Register High Bit Field Type rwh CCU6_T12DTCL T12DTCL Reset: 00H Dead-Time Control Register for Timer T12 Low Bit Field DTM CCU6_T12DTCH T12DTCH Reset: 00H Dead-Time Control Register for Timer T12 High Bit Field 0 DTR2 DTR1 DTR0 0 DTE2 DTE1 DTE0 Type r rh rh rh r rw rw rw CCU6_TCTR0L Reset: 00H Timer Control Register 0 Low Bit Field CTM CDIR STE1 2 T12R T12 PRE T12CLK T12CLK rw rh rh rh rw rw Type rh CC63VH CC63VH Type rh T12PVL T12PVL Type rwh T12PVH T12PVH Type rwh T13PVL T13PVL Type rwh T13PVH T13PVH Type Type rw FAH FBH FCH Bit Field 0 STE1 3 T13R T13 PRE T13CLK T13CLK Type A7H CCU6_TCTR0H Reset: 00H Timer Control Register 0 High CC63VL CC63VL r rh rh rw rw CCU6_CC60RL CC60RL Reset: 00H Capture/Compare Register for Channel CC60 Low Bit Field CCU6_CC60RH CC60RH Reset: 00H Capture/Compare Register for Channel CC60 High Bit Field CCU6_CC61RL CC61RL Reset: 00H Capture/Compare Register for Channel CC61 Low Bit Field Data Sheet CC60VL CC60VL Type rh CC60VH CC60VH Type rh CC61VL CC61VL Type rh 49 V1.2, 2009-11 XC878CLM XC878CLM Functional Description Table 14 CCU6 Register Overview (cont'd) Addr Register Name Bit FDH CCU6_CC61RH CC61RH Reset: 00H Capture/Compare Register for Channel CC61 High Bit Field CCU6_CC62RL CC62RL Reset: 00H Capture/Compare Register for Channel CC62 Low Bit Field CCU6_CC62RH CC62RH Reset: 00H Capture/Compare Register for Channel CC62 High Bit Field FEH FFH 7 6 5 4 3 2 1 0 CC61VH CC61VH Type rh CC62VL CC62VL Type rh CC62VH CC62VH Type rh RMAP = 0, PAGE 2 CCU6_T12MSELL T12MSELL Reset: 00H T12 Capture/Compare Mode Select Register Low Bit Field CCU6_T12MSELH T12MSELH Reset: 00H T12 Capture/Compare Mode Select Register High Bit Field 9CH CCU6_IENL Reset: 00H Capture/Compare Interrupt Enable Register Low Bit Field 9DH CCU6_IENH Reset: 00H Capture/Compare Interrupt Enable Register High Bit Field CCU6_INPL Reset: 40H Capture/Compare Interrupt Node Pointer Register Low Bit Field 9AH 9BH 9FH A4H A5H A6H A7H MSEL60 MSEL60 rw rw Type Type Type 9EH MSEL61 MSEL61 Type DBYP HSYNC MSEL62 MSEL62 rw rw rw ENT1 2 PM ENT1 2 OM ENCC 62F ENCC 62R ENCC 61F ENCC 61R ENCC 60F ENCC 60R rw rw rw rw rw rw rw rw EN STR EN IDLE EN WHE EN CHE 0 EN TRPF ENT1 3PM ENT1 3CM rw rw rw rw r rw rw rw INPCHE INPCC62 INPCC62 INPCC61 INPCC61 INPCC60 INPCC60 Type rw rw rw rw CCU6_INPH Reset: 39H Capture/Compare Interrupt Node Pointer Register High Bit Field 0 INPT13 INPT13 INPT12 INPT12 INPERR Type r rw rw rw CCU6_ISSL Reset: 00H Capture/Compare Interrupt Status Set Register Low Bit Field CCU6_ISSH Reset: 00H Capture/Compare Interrupt Status Set Register High Bit Field CCU6_PSLR Reset: 00H Passive State Level Register Bit Field Type Type Type ST12 PM ST12 OM SCC6 2F SCC6 2R SCC6 1F SCC6 1R SCC6 0F SCC6 0R w w w w w w w w SSTR SIDLE SWHE SCHE SWH C STRP F ST13 PM ST13 CM w w w w w w w w PSL63 PSL63 0 PSL rwh r rwh CCU6_MCMCTR Reset: 00H Bit Field Multi-Channel Mode Control Register Type SWSYN 0 SWSEL r rw r rw FBH FCH CCU6_TCTR2H Reset: 00H Timer Control Register 2 High CCU6_MODCTRL Reset: 00H Modulation Control Register Low Bit Field 0 T13TED T13TED T13TEC T13TEC T13 SSC T12 SSC Type FAH CCU6_TCTR2L Reset: 00H Timer Control Register 2 Low 0 r rw rw rw rw Bit Field 0 T13RSEL T13RSEL T12RSEL T12RSEL Type r rw rw Bit Field Type Data Sheet MCM EN 0 T12MODEN T12MODEN rw r rw 50 V1.2, 2009-11 XC878CLM XC878CLM Functional Description Table 14 CCU6 Register Overview (cont'd) Addr Register Name Bit FDH Bit Field CCU6_MODCTRH Reset: 00H Modulation Control Register High Type 7 6 5 4 3 2 ECT1 3O 0 T13MODEN T13MODEN rw r 1 0 rw FFH CCU6_TRPCTRL Reset: 00H Trap Control Register Low CCU6_TRPCTRH Reset: 00H Trap Control Register High Bit Field 0 TRPM 2 TRPM 1 TRPM 0 Type FEH r rw rw rw Bit Field TRPP EN TRPE N13 TRPEN Type rw rw rw CCU6_MCMOUTL Reset: 00H Multi-Channel Mode Output Register Low Bit Field 0 R MCMP Type r rh rh CCU6_MCMOUTH Reset: 00H Multi-Channel Mode Output Register High Bit Field 0 CURH EXPH Type r rh rh CCU6_ISL Reset: 00H Capture/Compare Interrupt Status Register Low Bit Field CCU6_ISH Reset: 00H Capture/Compare Interrupt Status Register High Bit Field CCU6_PISEL0L Reset: 00H Port Input Select Register 0 Low Bit Field 9FH CCU6_PISEL0H Reset: 00H Port Input Select Register 0 High Bit Field A4H CCU6_PISEL2 Reset: 00H Port Input Select Register 2 Bit Field 0 IST13HR IST13HR Type r rw CCU6_T12L Reset: 00H Timer T12 Counter Register Low Bit Field CCU6_T12H Reset: 00H Timer T12 Counter Register High Bit Field CCU6_T13L Reset: 00H Timer T13 Counter Register Low Bit Field CCU6_T13H Reset: 00H Timer T13 Counter Register High Bit Field CCU6_CMPSTATL Reset: 00H Compare State Register Low Bit Field 0 CC63 ST CC POS2 CC POS1 CC POS0 CC62 ST CC61 ST CC60 ST Type r rh rh rh rh rh rh rh T13IM T13IM COUT 63PS COUT 62PS CC62 PS COUT 61PS CC61 PS COUT 60PS CC60 PS rwh rwh rwh rwh rwh rwh rwh rwh RMAP = 0, PAGE 3 9AH 9BH 9CH 9DH 9EH FAH FBH FCH FDH FEH FFH CCU6_CMPSTATH Reset: 00H Compare State Register High Type Type T12 OM ICC62 ICC62 F ICC62 ICC62 R ICC61 ICC61 F ICC61 ICC61 R ICC60 ICC60 F ICC60 ICC60 R rh rh rh rh rh rh rh rh STR IDLE WHE CHE TRPS TRPF T13 PM T13 CM rh rh rh rh rh rh rh rh ISTRP ISCC62 ISCC62 ISCC61 ISCC61 ISCC60 ISCC60 rw rw rw rw IST12HR IST12HR ISPOS2 ISPOS1 ISPOS0 rw rw rw Type Type rwh T12CVH T12CVH Type rwh T13CVL T13CVL Type rwh T13CVH T13CVH Type Bit Field rw T12CVL T12CVL Type Type Data Sheet T12 PM rwh 51 V1.2, 2009-11 XC878CLM XC878CLM Functional Description 3.2.4.11 UART1 Registers The UART1 SFRs can be accessed in the mapped memory area (RMAP = 1). Table 15 UART1 Register Overview Addr Register Name Bit 7 6 5 4 3 2 1 0 SM0 SM1 SM2 REN TB8 RB8 TI RI rw rw rw rw rw rwh rwh rwh RMAP = 1 C8H C9H CAH CBH CCH CDH CEH CFH SCON Reset: 00H Serial Channel Control Register Bit Field SBUF Reset: 00H Serial Data Buffer Register Bit Field VAL Type rwh BCON Reset: 00H Baud Rate Control Register Bit Field 0 BRPRE R Type r rw rw BG Reset: 00H Baud Rate Timer/Reload Register Bit Field FDCON Reset: 00H Fractional Divider Control Register Bit Field 0 NDOV FDM FDEN Type r rwh rw rw FDSTEP Reset: 00H Fractional Divider Reload Register Bit Field FDRES Reset: 00H Fractional Divider Result Register Bit Field SCON1 Reset: 07H Serial Channel Control Register 1 Bit Field 0 NDOV EN TIEN