XC6200 XC6216 XC6264 XC6209 XC6236 IOB12 IOB30 XC6000 3001D 3001E 3001F 3000B - Datasheet Archive

 

XC6200 Field Programmable Gate Arrays Table Of Contents Features Description Architecture Logical and Physical Organization

 

® XC6200 XC6200 Field Programmable Gate Arrays Table Of Contents Features Description Architecture Logical and Physical Organization Additional Routing Resources Magic Wires Global Wires Function Unit Cell Logic Functions Routing Switches Clock Distribution Clear Distribution I/O Architecture Pull-Up, Pull-Down And Slew Border Routing GClk, OE And Reset Routing Designing with XC6200 XC6200 Register Access Timing Map Register Mask Register Programming FastMAPTM Parallel CPU Interface Understanding The Configuration Bits Wildcard Registers Device Configuration Register Device Identification Register Control Register Memory Map Serial Programming Interface Reset And Initialization Packaging Pin Descriptions Electrical Parameters Timing Diagrams XC6216 XC6216 Pinouts XC6264 XC6264 Pinouts Ordering Information 1 2 3 3 3 6 6 6 6 7 8 9 10 10 13 13 13 14 16 17 17 19 19 19 20 25 26 26 27 31 35 36 36 37 45 48 56 73 April 24, 1997 (Version 1.10) XC6200 XC6200 Field Programmable Gate Arrays ® April 24, 1997 (Version 1.10) Product Description Features · High-Performance Sea-Of-Gates FPGA - Thousands of configurable cells - Fine-grain architecture, abundant registers, gates and routing resources - Extremely high gate count for structured logic or datapath designs - High-speed SRAM control store - 220 MHz flip-flop toggle rates · Flexible Pin Configuration - All User I/Os programmable as in, out, bidirect, threestate or open drain. - Configurable pull-up/down resistors - CMOS or TTL logic levels · Flexible Interconnect Architecture - Low-delay FastLANETM hierarchical routing scheme gives large number of fast `Longlines' - Any cell can be connected to any other - Suited to both structured synchronous data path type designs or irregular random logic - Completely flexible clocks and asynchronous clears for registers - 4 Global low-skew signals · Extremely Flexible Cell Architecture - Over 50 distinct logic functions per cell - One register and gate/multiplexer possible for every cell · Advanced Processor Compatible Architecture - Xilinx FastMAPTM processor interface - Direct processor read/write access to all internal registers in user design with no logic overhead - All user registers and SRAM control store memory mapped onto processor address space - Programmable data bus width (8, 16 or 32-bits) - Easily interfaced to most microcontrollers and microprocessors · Testability - Pre-tested, high-volume, standard part - JTAG capability with library macrocells · Advanced Dynamic Reconfiguration Capability - High-speed reconfiguration via parallel CPU interface - Full or partial reconfiguration/context switching possible - Unlimited reprogrammability - Ideal for custom computing applications · Sophisticated CAD Tools - Implement designs using familiar tools like Viewlogic and Synopsys - Dedicated XACTstep Series 6000 back-end tools - Use PC or Unix workstation platforms - Fully automatic mapping, placement and routing - Interactive Physical Editor for design optimization - Large Xilinx parts library for schematic capture - VHDL synthesis Table 1: The XC6200 XC6200 Family of Field Programmable Gate Arrays XC6209 XC6209 XC6216 XC6216 XC6236 XC6236 XC6264 XC6264 9000-13000 16000-24000 36000-55000 64000-100000 Number of Cells 2304 4096 9216 16384 Number of Registers 2304 4096 9216 16384 Number of IOBs 192 256 384 512 48x48 64x64 96x96 128x128 Device Typical Gate Count Range Cell Rows x Columns = Planned Product April 24, 1997 (Version 1.10) 2 XC6200 XC6200 Field Programmable Gate Arrays Description The XC6200 XC6200 family is a new type of high performance FPGA from Xilinx. XC6200 XC6200 is a family of fine-grain, sea-of-gates FPGAs. These devices are designed to operate in close co-operation with a microprocessor or microcontroller to provide an implementation of functions normally placed on an ASIC. These include interfaces to external hardware and peripherals, glue logic and custom coprocessors, including bitlevel and systolic operations unsuited to standard processors. The XC6200 XC6200 can provide extremely high gate counts for data path or regular array type designs. In these cases the actual gate count may turn out to be a factor of two or more greater than those given in Table 1. An XC6200 XC6200 part is composed of a large array of simple, configurable cells. Each basic cell contains a computation unit capable of simultaneously implementing one of a set of logic level functions and a routing area through which inter-cell communication can take place. The structure is simple, symmetrical, hierarchical and regular, allowing novice users to quickly make efficient use of the resources available. The nearest-neighbor interconnect of the underlying cells is supplemented with wires of length 4 cells, 16 cells and Chip-Length, which provide low delay paths for longer connections. In addition there are four global input signals which provide a low skew distribution path for critical high fan-out nets such as clocks and initialization signals. XC6200 XC6200 parts are configured by an integral, highly stable six-transistor SRAM control store. This allows XC6200 XC6200 parts to be quickly reconfigured an unlimited number of times. The SRAM control store can be mapped into the address space of a host processor and additional support logic is provided to allow rapid reconfiguration of all or part of the device. In addition, the outputs of function units within the device can be read by a processor through the FastMAPTM. Processors can read or write registers within logic implemented on the device. Data transfers can be 8, 16 or 32 bits wide, even when register bits are distributed over a column of cells. These capabilities allow XC6200 XC6200 FPGAs to support virtual hardware in which circuits running on the FPGA can be saved (`swapped out') to allow the FPGA resources to be assigned to a different task, then restored (`swapped in') at a later time with the same internal state in their registers. Sections of the device can be reconfigured without disturbing circuits running in other sections. Thus an XC6200 XC6200 in a coprocessor application can be shared by several processes running on the host computer. Design entry and proving may be carried out with Xilinx software products using industry standard schematic 3 capture, synthesis and simulation packages such as Viewlogic, Mentor Graphics and Synopsys. A comprehensive library of parts, ranging from simple gate primitives to complex macro-functions, exists to make this an easy task. Below the top level design tools, the XC6200 XC6200 product family is supported by XACTstep Series 6000. This contains tools ranging from simple symbolic editors for high-efficiency user designs to sophisticated cell-compilation tools. These tools help to ensure the design captured is laid out efficiently with no user intervention. Node delays can then be back-annotated to the front-end logic simulator for design proving. The tools allow for manual intervention in the layout process if desired. Incremental design is also supported: if a design is laid out and subsequently changed, only the modified block has to be re-laid out. The functions available within each cell provide a good target for logic synthesis programs. The simple cell architecture allows arbitrary user logic designs to be mapped onto a number of cells, rather than having to split the design up into medium-complexity mini-functions for mapping to a larger configurable logic block. Because each cell can be configured as a register, designs containing far more registers than would be possible with a larger configurable block are achievable. Architecture Logical and Physical Organization The XC6200 XC6200 architecture may be viewed as a hierarchy. At the lowest level of the hierarchy lies a large array of simple cells (Figure 1). This is the `sea of gates'. Each cell is individually programmable to implement a D-type register and a logic function such as a multiplexer or gate. Any cell may also be configured to implement a purely combinatorial function, with no register. This is illustrated in Figure 7. First generation fine-grain architectures implemented only nearest-neighbor interconnection and had no hierarchical routing (Figure 1). XC6200 XC6200 is a second generation finegrain architecture, employing a hierarchical cellular array structure. Neighbor connected cells are grouped into blocks of 4x4 cells (Figure 2) which themselves form a cellular array, communicating with neighboring 4x4 cell blocks. A 4x4 array of these 4x4 blocks forms a 16x16 block (Figure 3). In the XC6216 XC6216 part, a 4x4 array of these 16x16 blocks forms the central 64x64 cell array which is then surrounded by I/O pads (Figure 4). Each level of hierarchy (unit cells, 4x4 cell blocks, 16x16 cell blocks, 64x64, etc.) has its own associated routing resources. Basic cells can route across themselves to connect to their nearest neighbors and thus provide wires April 24, 1997 (Version 1.10) Length 4 FastLANEsTM S4 E4 Cell Cell Cell Cell Cell Cell Cell Cell Cell Cell Cell Cell Cell Cell Cell Cell Cell Cell Cell Cell Cell Cell Cell Cell Cell Cell Cell Cell Cell Cell Cell Cell W4 N4 Figure 2. XC6200 XC6200 4x4 Cell Block Figure 1. Nearest-Neighbor Interconnect Array Structure Four Length 16 FastLANEsTM S16 (Remainder hidden for clarity) Each Arrow = 16 Chip-Length FastLANEsTM (Only 1 shown for clarity) E16 4x4 4x4 4x4 W16 4x4 4x4 4x4 4x4 4x4 4x4 4x4 April 24, 1997 (Version 1.10) 16x16 16x16 16x16 16x16 16x16 16x16 16x16 16x16 16x16 16x16 4x4 4x4 N16 Figure 3. XC6200 XC6200 16x16 Cell Block 16x16 16x16 4x4 16x16 16x16 4x4 16x16 64 User IOBs (1 per border cell) Figure 4. XC6216 XC6216 Device 4 XC6200 XC6200 Field Programmable Gate Arrays of length 1 cell. Note that cells used for interconnect in this manner can still be used to provide a logic function. Wires of length four cells are provided to allow 4x4 cell blocks to route across themselves without using unit cell resources. Similarly 16x16 cell blocks provide additional wires of length 16 cells and the 64x64 array provides Chip-Length wires. Larger XC6200 XC6200 products extend this process to 256x256 cell blocks and so on, scaling by a factor of 4 at each hierarchical level as required. Intermediate array sizes (e.g. 96x96) are created by adding more 16x16 blocks. Switches at the edge of the blocks provide for connections between the various levels of interconnect at the same position in the array (e.g. connecting length 4 wires to neighbor wires). The longer wires provided at each hierarchical level are termed `FastLANEsTM`. it is convenient to visualize the structure in three dimensions with routing at each hierarchical level being conceptually above that in lower hierarchical levels, with the cellular array as the base layer. The length-4 FastLANEsTM are driven by special routing multiplexers within the cells at 4x4 block boundaries. All routing wires are directional. They are always labeled according to the signal travel direction. For example, S4 is a length-4 FastLANETM heading from North to South. In Figures 2, 3 and 4 each individual cell has a length 4, 16 and ChipLength FastLANETM above it. However only a small number are shown for clarity. The benefit of the additional wiring resources provided at each level of the hierarchy is that wiring delays in the XC6200 XC6200 architecture scale logarithmically with distance in cell units rather than linearly as is the case with the first generation neighbor interconnect architectures. Since 4x4 cell block boundaries lie on unit cell boundaries, the switching function provided at 4x4 cell boundaries is a superset of that provided at unit cell boundaries; i.e. it provides for neighbor interconnect between the adjacent cells as well as additional switching options using the length 4 wires. Similarly, the switching unit on 16x16 cell block boundaries provides a superset of the permutations available from that on the 4x4 cell block boundaries. Further switching units are also provided on the 64x64 cell boundaries to provide the Chip-Length FastLANEsTM. CLK S4 S Clr E4 N S E W N4 S4 E4W4 Nout E N E W F X3 N S E W N4 S4 Function Unit X1 N S E W N4 S4 X2 E4 W4 E4 W4 N Wout N S Eout S F W E F F S E W F X2 W X3 W4 Sout Clk MAGIC N N4 CLR Figure 5. XC6200 XC6200 Basic Cell 5 April 24, 1997 (Version 1.10) X1 `TRUE' point for Function Derivation X2 Y2 1 0 CS Multiplexer C RP Multiplexer X3 Y3 D Clk Q S F Q Clr Figure 6. XC6200 XC6200 Function Unit Additional Routing Resources Magic Wires The majority of interconnections are routed using the nearest-neighbor and FastLANEsTM described above. Each cell has a further output (labeled `Magic') which provides an additional routing resource. A cell's Magic output is not always available for routing. Its availability is dependent on the logic function implemented inside the cell. More information on the physical nature of the Magic wires is given in the section "Function Unit" on page 6. Each cell's Magic output is routed to two distinct 4x4 block boundary switches. The Magic wire can be driven by N, S, E or W from adjacent cells or from the N4, S4, E4 or W4 FastLANEsTM passing over the cell. This makes it particularly useful for corner-turning (all other routing resources are straight). The Magic wires are illustrated in Figure 8. Global Wires The XC6200 XC6200 architecture permits registers within a user design to be clocked by different clocks and cleared by different asynchronous clears. Clocks and Clears may be provided by any user I/O pin or generated from user logic internally. In line with good synchronous digital design practices, it is recommended that a single global Clock and Clear are used. This minimizes the likelihood of timing problems and gives more reliable simulations. Four Global wires (G1, G2, GClk and GClr) are provided for low skew, low delay signals. These wires are intended for global Clock and Clear or other high fan-out signals April 24, 1997 (Version 1.10) and are distributed throughout the array in a low skew pattern. A global signal can reach the clock and clear inputs of any cell on the array passing through very few routing switches. The four Globals are very similar. It would be possible to use GClk as a global Clear signal, however for minimum delay, it is recommended that GClk be used for global clocks and GClr for global clears. GClk and GClr can reach the inputs of any register in the array, passing through only a single routing switch. G1 and G2 may be used for secondary global clocks or clears. G1 and G2 have a slightly larger delay than GClk and GClr. Function Unit Figure 5 shows the basic XC6200 XC6200 cell in detail. The inputs from neighboring cells are labeled N, S, E, W and those from length 4 wires N4, S4, E4, W4 according to their signal direction. Additional inputs include Clock and Asynchronous Clear for the Function Unit D-type register. The output from the cell function unit, which implements the gates and registers required by the user's design, is labeled F. The Magic output is used for routing as described earlier. The multiplexers within the cell are controlled by bits within the configuration memory. As can be seen from Figure 5, the basic cells in the array have inputs from the length 4 wires associated with 4x4 cell blocks as well as their nearest neighbor cells. The function unit design allows the cells to efficiently support D-type registers with Asynchronous Clear and 2:1 multiplexers, as well as all Boolean functions of two variables (A and B) chosen from the inputs to the cell (N,S,E,W,N4,S4,E4,W4) (Table 2). Figure 7 shows the schematic representations of the basic cell functions pos- 6 XC6200 XC6200 Field Programmable Gate Arrays A ZERO A B B OR2 ONE BUF B INV M2_1 SEL A A A OR2B1 A A B B A M2_1B1A SEL NOR2 B AND2 A A B A B M2_1B1B NOR2B1 B SEL AND2B1 A A A B XOR2 B B NAND2 M2_1B2 SEL A A B B NAND2B1 XNOR2 A A B D SEL Q F A D F A B F Q RP SEL CLK Q F CLK SEL CLK SEL `Protected Flip-Flop' CLR CLR Figure 7. Cell Logic Functions sible. The Magic routing output can only be used if the signal to be routed can be placed on X2 or X3. Figure 6 shows the implementation of the XC6200 XC6200 function unit. The design uses the fact that any function of two Boolean variables can be computed by a 2:1 multiplexer if suitable values chosen from the input variables and their complements are placed on its inputs. The Y2 and Y3 multiplexers provide for this conditional inversion of the inputs. The CS multiplexer selects a combinatorial or sequential output. The RP multiplexer allows the contents of the register to be `protected'. If register protection is enabled then only the programming interface can write to the register. It does not change when the X inputs to the function unit change, even if it is clocked or cleared. This feature is useful in designs containing control registers which are only to be written by an external microprocessor. The control inputs of all the multiplexers, except the one switched by X1, come from configuration memory bits. Cell Logic Functions Each cell can be configured as any two-input gate function, any flavour of 2:1 multiplexer, constant 0 or 1, single input functions (buffer or inverter) or any of these in addition to a D-type register. This is illustrated in Figure 7. The gate names given correspond to standard Xilinx library part names for these primitives. Although three inputs are shown entering the combinatorial `cloud', dual and single input functions are also possible. e.g. inverter 7 + register or register alone. The buffer symbol is available in the CAD libraries. There is no requirement for the designer to buffer signals with this architecture. This is because signals are regularly buffered by routing multiplexers. Symmetrical functions are also possible but not shown in Figure 7. e.g. A.B (AND2B1) is shown but A.B (AND2B2) is not. This is because A and B are assigned to user signals by the logic mapping software to provide the required function. Thus a multiplexer with inversion on the SEL input is unnecessary because the mapping software can simply swap the signal assignments for A and B. The sources of the X1, X2 and X3 input multiplexers are set automatically by CAD software during the logic mapping phase. Table 2 shows the assignments for all the cell multiplexers to compute the various logic gate functions. A NAND2B1 is equivalent to an OR2B1 with the inputs swapped and a NOR2B1 is equivalent to an AND2B1 with the inputs swapped therefore these gates are not listed in Table 2. The C and S signals are taken as the `true points' for the gate mappings in this table. If the register within a cell is not used in the design then a special `fast' version of most gates can be configured, using the register to provide a constant 1 or 0. For example a fast AND gate (A.B) can be configured by setting the register to 0 during configuration and assigning Q to Y3. A is routed to X1 and B to X2. X2 is assigned to Y2. When A changes to 0, Y3 is selected and F is forced Low as soon as the X1-controlled multiplexer April 24, 1997 (Version 1.10) switches. In the normal AND gate, there would be an additional delay as A propagated through the Y3 multiplexer. Fast or normal gates may be specified by the designer but for optimal layout density this is best left to the logic mapping software. illustrated in Figure 8. These switches also allow higher levels of hierarchical routing (e.g. length-16 and ChipLength FastLANEsTM) to be connected to length-4 FastLANEsTM. Figure 8 also shows the connections for each cell's Magic output. Each Magic output is routed to two destinations for increased routing flexibility. The two connections are labeled M and MA. The Magic wires allow cell outputs to jump to the edge of the 4x4 block and hence onto FastLANEsTM or into the next 4x4 block. They are also a particularly efficient way of making large busses turn corners. The multiplexer functions have a straightforward mapping with fixed assignments to X1,X2 and X3, with Y2 and Y3 providing input inversions as required. Routing Switches As described earlier, each cell within a 4x4 block is able to drive its output to its nearest neighbors to the N,S,E and W. In addition to this, cells at 4x4 block boundaries are also able to drive their outputs onto length-4 FastLANEsTM. Special switch units are provided around each 4x4 block boundary to facilitate these connections. This is N,S,E and W switches are similar, however the N switches contain additional multiplexers to drive the register Clock lines. The contents of the boundary switches are shown in Figures 9 to 12. These multiplexers Table 2: Function Derivation Function X2 X3 Y2 Y3 RP CS Q 0 A A A X2 X3 X C X 1 A A A X2 X3 X C X BUF (Fast) A X X Q Q Q C 0 BUF X A A X2 X3 X C X INV (Fast) A X X Q Q Q C 0 INV X A A X2 X3 X C X A.B (Fast) A B X X2 Q Q C 0 A.B A B A X2 X3 X C X A.B (Fast) A X B Q X3 Q C 0 A.B A A B X2 X3 X C X A.B (Fast) A B X X2 Q Q C 0 A.B A B A X2 X3 X C X A+B (Fast) A X B Q X3 Q C 0 A+B A A B X2 X3 X C X A+B (Fast) A B X X2 Q Q C 0 A+B A B A X2 X3 X C X A+B (Fast) A X B Q X3 Q C 0 A+B A A B X2 X3 X C X AB A B B X2 X3 X C X AB A B B X2 X3 X C X M2_1 SEL A B X2 X3 X C X M2_1B1A SEL A B X2 X3 X C X M2_1B1B SEL A B X2 X3 X C X M2_1B2 April 24, 1997 (Version 1.10) X1 SEL A B X2 X3 X C X 8 XC6200 XC6200 Field Programmable Gate Arrays invert some inputs. This is not shown in the figures. See the "Programming" section for details. The multiplexers driving the NOut, SOut, EOut and WOut lines are actually implemented within the cell adjacent to the switch. These multiplexers take the place of the neighbor multiplexers found in the basic cell (see Figure 5). Boundary cells contain additional RAM bits to control the larger multiplexers. An additional output is available from these multiplexers. This output reflects the output that would have come from the cell's neighbor multiplexer had it been a basic non-boundary cell. To distinguish this from the output of the boundary switch (NOut, SOut, EOut or WOut), it is suffixed with a `C' (Cell). e.g. NC for an Nswitch. NC is one of NIn, E, W, or F depending on the least-significant two bits of the NOut multiplexer select lines. Hence NC is identical to NOut if NOut is one of F, NIn, E or W. If NOut is one of N4In, N16, PS4 or MN then NC is one of F, NIn, E or W depending on which signal is routed to NOut. The `C' signal is one of the upper four inputs to the 8:1 multiplexers shown in Figures 9 to 12, the actual value being selected by the two least-significant multiplexer select lines. Similar `C' signals are generated in the Sswitch, Eswitch, and WSwitch. The S4 input to the NOut multiplexer in the Nswitch is actually the S4 input to the adjacent Sswitch in the 4x4 block immediately to the North of this block. This should not be confused with the S4Out signal from that block's Sswitch. This is also true of some of the other inputs to the multiplexers in other boundary switches. To avoid confusion, these inputs are prefixed with the letter `P' (for Nswitch Wswitch Wswitch Cell Cell Nswitch Cell Cell Nswitch Cell Cell Cell SCIn NCL N16 NCOut ClkIn N4In Eswitch N4Out MNA PS16 SCL F NIn E W N4In N16 NCOut NOut PS4 MN MN MS GClr NCL G1 G2 ClkIn NOut GClk ClkOut Nswitch Figure 9. Contents of Nswitch MN NCL PN16 S4In S16 MS S4Out MSA SCL F E W SIn S16 PN4 SCOut SOut S4In MS SCOut NCIn Sswitch Figure 10. Contents of Sswitch MW MEA PW16 WCL WCIn ECOut E4In Nswitch Cell "CL" = Chip-Length E4Out ME E16 ECL F N EIn S PW4 ME ECOut EOut E16 E4In Eswitch Eswitch Figure 11. Contents of Eswitch Wswitch Wswitch Cell Cell Cell Cell Cell Cell Cell Cell Eswitch Eswitch ECL W4In WCL MWA MW Sswitch Sswitch Sswitch Sswitch MA nets PE16 WCOut ME W16 ECIn W4Out M nets Figure 8. Routing Switches at 4x4 Block Boundary 9 F WIn N S PE4 W16 WCOut WOut MW W4In Wswitch Figure 12. Contents of Wswitch April 24, 1997 (Version 1.10) Previous). e.g. PS4. This feature allows FastLANEsTM to perform U-turns. Clock Distribution As described previously, register clock inputs may be driven from any source but it is recommended that the GClk signal is used. GClk also has the advantage that it can be stopped by writing to the Device Configuration Register (see Table 23). The Global wires enter the part through dedicated input pins and are distributed in a special low-skew `H' pattern (Figure 13). Each vertically aligned (South to North) group of four cells within a 4x4 block is clocked by its own clock source. This is driven from a multiplexer in the Nswitch immediately to the South of the group of cells. The connections for this multiplexer are shown in Figure 9. ClkOut drives the Clk inputs to each of the four cells in the group. As can be seen from Figure 9, the register clock for each group of four cells can be driven by ClkIn, NOut, GClk, GClr, G1, G2 or NCL (N Chip-Length). ClkIn is the ClkOut from the 4x4 block to the South, allowing vertical daisy-chaining of clock signals. NOut is the N output from the cell associated with the Nswitch. This can be used to provide local user-generated or gated clock signals if required. GClk is the Global Clock signal direct from the device GClk input. Clearly this signal only has to pass through one 4:1 multiplexer whereas GClr, G1 and G2 have to pass through two. This is one reason why there is less delay on GClk. It is also possible to route North Chip-Length wires onto the Clock lines. This allows up to 64 (for a XC6216 XC6216) locally used clocks to be provided which can still run the entire length of the chip with minimal skew. These local clock signals may be generated internally (e.g. by dividing a faster clock) or sourced directly from the device programmable I/O pins. 16x16 16x16 16x16 16x16 North Boundary East Boundary West Boundary NCL SCL N16In N4In PS4 NCOut WCL ECL E16In N16Out PW4 E4In WCIn WCL ECL W16In E16Out W4In PE4 WCOut SCIn MN ECOut ME ECIn MW NCL SCL S16In PN4 S4In NCIn South Boundary S16Out GClr ClrIn SCL G2 GClk 0 W16Out ClrOut SOut G1 SCOut MS "CL" = Chip-Length Figure 14. Additional Switches at 16x16 Boundaries Where a fast clock is required by only a small fraction of the logic on the device it may be preferable to employ user interconnect resources rather than a Global or ChipLength signal. This is because limiting fast clock distribution to the area of the device where it is required reduces power consumption. Clear Distribution Register Clear inputs are routed in a similar manner to Clock inputs. In this case vertical groups of 16 cells, within a 16x16 block, share a common Clear. Clear lines run in a Southerly direction and are sourced from the Sswitch unit of 4x4 blocks which also lie on a 16x16 boundary. All of the boundary switches at 16x16 boundaries contain additional switching multiplexers. These are illustrated in Figure 14. These multiplexers invert some inputs. This is not shown in the figures. See the "Programming" section for details. ClrOut drives the Clr inputs to each of the sixteen cells in the group. The S and SCL connections allow the output of a cell to provide a user-generated local Clear signal. I/O Architecture 16x16 16x16 16x16 16x16 16x16 16x16 16x16 16x16 16x16 16x16 16x16 16x16 Global Input Figure 13. Low Skew `H' Distribution Of Global Signals (XC6216 XC6216) April 24, 1997 (Version 1.10) User-configurable Input/Output Blocks (IOBs) provide the interface between external package pins and the internal logic. One IOB is provided for every cell position around the array border. IOBs are connected to fixed pad locations. There are more IOBs than available pads, hence some IOBs are `padless'. However it is still possible to route signals from padless IOBs to device pins. Figure 15 is a simplified diagram of an IOB and its associated IO pad. The IOB is located at the array border and the pad is located close to its device pin. The pad may be located some distance from its associated IOB. The 10 XC6200 XC6200 Field Programmable Gate Arrays IOB IO PAD ControlEnable (EnToPadB) PUp ArrayEnable (EnToPadA) (=L4 output from Array) Slew Enable ArrayDToPad (DToPadA) (=Neighbor output from array) 0 ControlDToPad (DToPadB) V CC 1 DToPad Neighbor Data PIN Signal From Array (PreviousL4) Array Data DelData DELAY DFromPad FastLANETM Data Signals From Array PDn Control Data (DFromPadB) GND L16 Output From Array (DForPadB) Figure 15. Input/Output Architecture mapping of IOBs to device pins is given in the pinout tables starting on page 48. be used to drive the internal CS signal rather than the CS pin. The XC6200 XC6200 IOB architecture incorporates a novel and very powerful feature: every IOB has the capability of routing either an array signal or a control logic signal to/ from the device pin. Every signal, including all the control signals (e.g. CS, RdWr, Address Bus, Data Bus, etc.), passes through an IOB. This means that all the control signals can be routed into the logic array for use in user designs. Similarly, user logic can control the XC6200 XC6200 internal control circuitry. For example a user signal could As an example of the power of this feature, an XC6200 XC6200 design could include an address decoder which decoded microprocessor read/write cycles and produced appropriately retimed signals for all the parts on a board including itself, thereby removing the need for address decoding PALs or discrete logic. ArrayEnable `PADLESS' IOB Enable ArrayEnable ArrayDToPad ArrayData ArrayDToPad ArrayData DToPad DFromPad NORMAL IOB Control Data ControlDToPad Enable DToPad DFromPad ControlEnable IO PAD Figure 16. `Padless' IOB Configuration 11 Each IOB has an array data input and a control data input, labeled ArrayDToPad and ControlDToPad in Figure 15. Associated with these inputs are two enable signals ArrayEnable and ControlEnable. These signals control whether the pad associated with this IOB is in the input or output mode. Each IOB also supplies ArrayData and ControlData when acting as an input. DFromPadB DToPadB EnToPadB The `Control' signals are routed to the internal XC6200 XC6200 control circuitry. If control signals are not required all the time then these IOBs can be used to route other user signals into the array. For example if only eight data bus bits were continuously required, the remaining twentyfour IOBs associated with the data bus could be used to route user signals to/from the array. ControlEnable comes either from the internal XC6200 XC6200 control circuitry if there is a bidirectional control signal or output signal on that IOB, or it is tied inactive. The `Control' signals are also referred to as `B' signals in this data sheet. ControlDToPad = DToPadB, ControlEnable = EnToPadB and Control Data = DFromPadB. The L16 output from the array, which can be routed onto Control Data, is also referred to as DForPadB. The DFromPadB output is unconnected in IOBs which have an output-only 'B' signal, such as SECE. IOBs which have an input-only 'B' signal, such as CS, have the DToPadB input tied Low and the EnToPadB input tied High. IOBs which have no associated 'B' signal also have April 24, 1997 (Version 1.10) DToPadB tied Low, EnToPadB tied High and DFromPadB unconnected. There are less real control signals than IOBs, hence the three signals, DFromPadB, DToPadB and EnToPadB, on some IOBs are not connected to the XC6200 XC6200 control logic. Some of these spare 'B' signals are used to route data to and from the padless IOBs mentioned above. The 'B' signals on the padless IOB are not used. This is illustrated in Figure 16. This arrangement allows data to be routed in or out of the chip via an IOB which has no associated IOPAD. The padless IOBs and their padded partner IOBs are detailed in the pinout tables starting on page 48. For example, in a XC6216 XC6216 IOB W0 is padless and is partnered with IOB S12, which has a pad. The ArrayEnable, Array Data and Control Data multiplexers are controlled by configuration RAM bits. A fixed delay may be optionally applied to Array Data inputs. This allows the input data hold time specification to be removed. The ArrayEnable and ArrayDToPad signals can be configured to constant 0 or 1 values within the logic array. The constant values are particularly useful for the enable signal when the pin is to function as an input or output rather than a bidirectional pin. Constant values on the data signal and a computed value on the enable signal produce open drain pull-up (DToPad=1) or pull-down (DToPad=0) pins. Table 3: Connections Between IOBs And Built-In XC6200 XC6200 Control Logic B Signal Type Example EnToPadB DToPadB DForPadB DFromPadB Input Only CS 1 0 L16 Output From Array Drives XC6200 XC6200 Control Logic CS Input Output Only SECE Driven By XC6200 XC6200 Control Logic SECE Out From XC6200 XC6200 Control Logic L16 Output From Array Not Connected Bidirectional Data Bus Driven By XC6200 XC6200 Control Logic Data-Bus Out From XC6200 XC6200 Control Logic L16 Output From Array Drives XC6200 XC6200 Internal FastMAPTM Data Bus Inputs From Padless IOB South IOB12 IOB12 Enable Output From W0 IOB DToPad Output From W0 IOB L16 Output From Array Drives W0 IOB DFromPad Input None North IOB30 IOB30 1 0 L16 Output From Array Not Connected April 24, 1997 (Version 1.10) 12 XC6200 XC6200 Field Programmable Gate Arrays Border Routing `0' ECLOut PW4In WCLIn WCIn MWIn PW4In ECLOut PW16In WCIn E16Out MWIn WrEn RdEn DelData ControlDToPad DelData ECLOut WCLIn PW16In WCIn E4Out DFromPad MWIn ControlDToPad EOut PW4In Control Enable DelData Figure 17. Array Data Sources In West IOBs Pull-Up, Pull-Down And Slew Three configuration RAM bits within each IOB control the programmable aspects of its IO pad. These RAM bits have no effect for padless IOBs. `PUp' and `PDn' enable the pull-up and pull-down resistors. The resistors may be used to tie floating logic inputs to a known value. `Slew' slows the output transition time to reduce supply noise and ground-bounce. The default condition is pull-up off, pull-down off and slew on. During reset, all the output drivers are disabled and the pull-up resistors are enabled. The pull-up and pull-down RAM control bits have no effect. After a reset the output drivers remain in this state. For the output drivers to be enabled, the global OE signal must be asserted (Low) and a valid configuration must be present in the device ID register. The ID register is usually the last thing to be written during configuration and acts as a check that the programming interface is operating correctly. More details of this are given in the `Programming' section. The OE signal provides a quick way of disabling all the output drivers and may be activated at any time. Only when OE is active and there is a valid ID pattern in the ID register, do the pull-up and pull-down RAM control bits determine the IO-pad resistor configuration. When OE=1 or the ID pattern is not valid, the pull-ups default to on and the pulldowns to off. The only exception to this default occurs in the Leakage Test Mode (see "Serial Interface State Machine", State 1) where all the pull-up/down resistors are disabled. 13 The array signals to and from the IOBs are generally just the signals which would have passed between two cells in the array. The ArrayDToPad signal in Figure 15 is actually the neighbor output from the border cell associated with the IOB. The Array Enable signal is the length-4 FastLANETM output from the same cell. The Array Data multiplexer in Figure 15 is actually a collection of multiplexers which source the neighbor, length-4, length-16 and Chip-Length wires into the array. South IOBs (IOBs at the South edge of the array) also source the local clock signals into the array. North IOBs source the local clear signals. The actual signals which can be routed onto the IOB Array Data outputs are detailed in Tables 14 and 19. This is illustrated for a West IOB in Figure 17. Inversions are not shown. See "Programming" section for details. These multiplexers also allow a number of other internal control signals to be routed into the array: WrEn and RdEn are signals which are active during state register accesses. RegData (available on West ChipLength FastLANEsTM) is the state register output value for this row during a state access. The timing of these signals is described under "Timing" on page 17. Note that in order to provide a minimal delay signal path into the core array, the neighbor data output from the IOB cannot select the delayed version of DFromPad. Only the un-delayed DFromPad and the Previous Length-4 Input can be routed onto the neighbor data output. Therefore the neighbor data output is unaffected by the value of the configuration memory which controls the DelData multiplexer in Figure 15. The length-4 and length-16 routing multiplexers at the array border also expect some inputs which are not available. For example at the West edge, MEIn, ECIn, PE4In and PE16In are non-existent. These inputs are tied to ground or VCC, thereby providing an abundant source of constant zeros and ones at the array border. These can be used to provide constant values to drive the ArrayEnable inputs to IOBs. GClk, OE And Reset Routing The connections from the GClk I/O pad differ from all the other I/O signals. This is necessary because GClk is used to clock all the built-in FPGA control logic. In common with the Reset and OE pads, the GClk pad cannot be enabled as an output pad. However, the main difference between these and all the other control signals is that they are routed to the FPGA control logic directly from the pad and not from the IOB. This means that a user circuit cannot modify them before they reach the control logic. This is illustrated for GClk in Figure 18. GClk to the logic array is supplied from the IOB. It is this signal which passes through the enable circuit controlled by a single bit in the device control register. Thus it is still April 24, 1997 (Version 1.10) FPGA CONTROL LOGIC GClk To Array CS RdWr A(15:0) D(31:0) Clock Enable ArrayData Control Logic Clock OE Reset I/O GClk IOB DFromPadB DFromPad Control Data G1 G2 GClk GClr GClk IO PAD Figure 18. GClk Routing possible to route any signal onto the array GClk net using the L16 output from the array (see Figure 15). However this GClk can only be safely stopped and started (without glitches) if the DFromPadB signal is the DFromPad signal from the GClk I/O pad. Designing with XC6200 XC6200 Designing of XC6200 XC6200 into systems may be partitioned into three distinct activities. 1. Board design with XC6200 XC6200 An XC6200 XC6200 part may be used on a board design as a microprocessor peripheral part, as an ASIC-type device or as both. In the first instance the XC6200 XC6200 part has conventional SRAM data, address and control signals as illustrated in Figure 19. In other cases it may only require the user defined I/O signals of an ASIC. Packaging information for the part is given in section "Packaging" on page 36. The number of user I/O signals depends on the exact package used. Several XC6200 XC6200 devices may be tiled together on a board to form a larger array. The regular array structure of XC6200 XC6200 makes this particularly easy. East I/Os on one chip would connect to West I/Os on the adjacent chip. North I/Os would connect to South I/Os on the adjacent chip and so on until the required array size was reached. It may be required to use the control signal pins, such as the Data and Address busses, on every part in the array. The control signals use every second IOB, leaving evenly April 24, 1997 (Version 1.10) Figure 19. XC6216 XC6216 Logic Symbol distributed IOBs in between which can be used to interconnect the XC6200s. See the device pin-out tables, starting on page 48 for details. The configuration RAM bits in the IOBs allow for a number of different programmable options to make interfacing to other ICs easier. This is more fully defined in the "I/O Architecture" section. 2. Logic design with XC6200 XC6200 This can be approached as an ASIC type design using the function and routing architecture defined in the previous sections. An example design flow is illustrated in Figure 20. The design may be carried out in a variety of different ways. Hardware description languages such as VHDL may be used with the synthesized design targeted to the XC6200 XC6200 architecture. Alternatively, schematic capture, using the extensive Xilinx Unified Library, with commonly used front end design tools (e.g. ViewLogic PROcapture/ViewDraw) may be used. These tools produce an EDIF netlist which is subsequently passed to the underlying XC6200 XC6200 place and route software. This automatically maps the user's design to the XC6200 XC6200 architecture in an efficient way and provides individual node delays which can be passed back to the high level simulation tools such as Viewlogic PROsim/ViewSim for accurate simulation. Simulation may be carried out prior to placement to check the logical correctness of the design using nominal delays. The place and route software also has optimization capability to carry out tasks such as redundant gate removal. A binary configuration file which 14 XC6200 XC6200 Field Programmable Gate Arrays can be written to the XC6200 XC6200 device via the programming interface is also produced automatically. The underlying CAD software is highly integrated with the high level CAD tools, providing user-friendly pull-down menus and dialog boxes to carry out all tasks. These methods allow designers with little or no knowledge of the XC6200 XC6200 architecture to quickly produce large and complex designs. Some designers may wish to carry out detailed hand placement and routing to produce ultraoptimized very high-speed/small area sections in their designs. Others may wish to generate large regular structures such as systolic arrays or perform floor-planning for extra efficiency. For these cases, a sophisticated physical editor is available which allows designers to graphically modify the automatic placement of gates/registers into cells and modify the routing as much as required. Alternatively this software may simply be used to see how the automatic placement and routing software has optimized a design. If a modification is subsequently made then only the modified part of the design needs to be re-laid out. This incremental design process gives a very rapid change cycle during debugging. All the design tasks may be carried out on PC or Unix workstation platforms. As an example, the simple accumulator circuit of Figure 21 is mapped onto the XC6200 XC6200 architecture. Figure 22 shows the resulting layout as displayed by the Physical Editor, running under Microsoft Windows in this case. The M2_1 XOR2 En FDC D The Physical Editor allows cells to be selected and moved. The inter-cell routing rubber-bands and adapts automatically to the new placement. The routing may also be manually modified if desired. Full details of using the software are contained in the online help. An interactive software demonstration is also available. 3. Software design with XC6200 XC6200 This is the design of a program for the host processor which interacts with a design running on the XC6200 XC6200. Here various registers within the XC6200 XC6200 design appear as locations within the processor's memory map. In addition the configuration memory of the device appears Logic Simulation In-System Verification Clk Out Data M2_1 CLR EDIF Netlist ENTITY counter IS PORT (data : IN std_ulogic; en : IN std_ulogic; . out : OUT std_ulogic);. En Cell1 ARCHITECTURE rtl OF counter IS. Data Node Delays CLK Load Load FDC Out D XOR2 CLK Load The inputs and outputs to the function unit are connected to the edges of the cell box. The small squares within each cell represent the input ports (X3, X2, X1) and the output port (F). Automatic Mapping, Place and Route Front End Design Entry Data Physical Editor tools are also available for Unix workstations. The boundaries of basic cells within the array are denoted by the squares, with larger rectangles representing the switch units on 4 cell boundaries. The wiring resources used by the design mapped onto the array are indicated by the darker black lines. When a cell function unit is used by the design it is annotated with the instance names of the mapped primitives. The primary inputs and outputs are not shown in this example. The rectangles around the edge represent IOBs and their pads. CLR Cell2 En Binary Config File Out 00010 10011 00011 10011 00100 Failed Simulation Manual Place and Route using Physical Editor (optional) XOR2 Failed Test M2_1 FDC Figure 20. XC6200 XC6200 Logic Design Flow 15 April 24, 1997 (Version 1.10) within the memory map and portions of the device can be reconfigured as required. Predefined device drivers and an efficient run-time library are available to make optimal use of XC6200 XC6200's high speed reconfiguration capabilities with minimal development time. MUX1 M2_1 D0 IN O D1 COUT CIN S0 Register Access FDC1 XOR2 FDC XOR1 D XC6200 XC6200 supports direct accesses from the processor to nodes within the user's circuit: the output of any cell's function unit can be read and the flip-flop within any cell can be written. During state reads a number of cell outputs are routed onto the CPU data bus. The signal which is actually read is either C or S in Figure 6, depending on whether the combinatorial or sequential output is selected. See Table 11 on page 21 for details of signal inversions. These inversions are cancelled out by the readback circuit so that the true value of C or S is read. Q SUM XOR2 XOR2 C CLR CLK CLR Figure 21. Accumulator Schematic These accesses are carried out through the control store interface and involve no additional wiring within the user's design. The CPU interface signals involved in addressing the cell state can be routed into the configurable array so that user circuits can detect that an access has been made and take appropriate action: for example, calculate a new value for an output register or process a value placed in an input register. Figure 22. Accumulator Physical Editor View April 24, 1997 (Version 1.10) 16 XC6200 XC6200 Field Programmable Gate Arrays In many applications this access to internal nodes is the main path through which data is transferred to the processor and in some coprocessor type applications it may be the only external I/O method: user programmable I/O pads may not be required at all. To allow high bandwidth transfers between the processor and internal nodes it is necessary to be able to transfer a complete processor data word of up to 32 bits in one memory cycle. For this reason state access bits within XC6200 XC6200 are mapped into a separate region of the device address space from configuration bits so that all the bits in a word contain state access bits. Figure 23 is a block diagram of the XC6216 XC6216 part, showing the row and column address decoders. Figure 24 shows the mapping of this area of the address space: there are 64 I/O signals from each column of cells and a 6-bit column address selects a particular column of cells to access. This row and column addressing scheme puts a constraint on the placement of registers within the user's design which are to be accessed word-wide: they must be on the same column of cells within the array. Timing Externally, timing for state accesses is the same as for reads and writes to configuration SRAM. This is illustrated in Figures 30 and 31 and described in the section "Parallel CPU Interface" on page 19. Internally, state accesses differ from configuration SRAM accesses slightly in that writes to registers are synchronous. When the processor writes data to registers, the data is clocked in on a rising edge of the register's clock. The FastMAPTM interface presents the CPU data on the register's `D' input and expects the register to clock it in. The internal timing relationships are shown in Figure 32 on page 46. Data is present on the `D' input from just after the first falling GClk edge of the Write Cycle to the second falling clock edge. If GClk is routed to the register then the data is clocked in at time t2 in Figure 32. If GClk is not being used to clock the register then the designer must ensure that the register's clock has a rising edge during the period the data is present. During state reads there is no requirement for the registers to be clocked. Data is read from the output of the cells and sampled by the FastMAPTM interface at time t2 in Figure 33. Thus the data should be stable before and after this edge of GClk to guarantee a correct read. The internal timing relationships illustrated in Figures 32 and 33 are the same regardless of whether the cycle is stretched by holding CS low, as shown in the extended cycles in Figures 30 and 31. Map Register XC6200 XC6200 provides a mechanism for mapping all the possible cell outputs from a column onto the 8,16 or 32bit external data bus, selecting only those cells which implement bits of the register to be accessed. Without this unit the processor would have to implement a complex sequence of shift and mask operations to discard those bits corresponding to cells not within the register, or the user would have to constrain the layout so that the register bits were in adjacent cells. The mechanism provided by XC6200 XC6200 takes the form of a Map Register, one bit for each row I/O signal from the array. This 64 (63,63) (0,63) 64 I/O North Row D e c o d e 64x64 Cell Array Column Decode Control 64 I/O E A S T Global I/O 57 Row(63:0) SELECT 57 64 I/O W E S T Row Address RA(5:0) 64 I/O South 64 D(8,16 or 31:0) (0,0) (63,0) Column(63:0) Column Address CA(5:0) Figure 23. XC6216 XC6216 Block Diagram 17 Figure 24. Memory Mapped I/O April 24, 1997 (Version 1.10) 8-Bit Data Bus Example XC6200 XC6200 Boundary User-defined register within array Cell Array Map Register 1 1 0 0 Bit 7 Bit 6 1 Data 1 Bus 1 1 1 0 0 0 Bit 5 Bit 4 Bit 3 1 0 Bit 2 1 0 0 Address Bus Address Decode Bit 1 Bit 0 1 1 Cells RdWr CS CPU Interface Write Enable Figure 25. Internal Register Access Map Register can be read and written through the control store interface and is set up prior to state accesses. A logic 0 in the Map Register indicates that the cell in the corresponding row is part of the register to be accessed. The unit maps rows from the cell array onto external data lines starting with the least significant bit: thus the first row with a 0 in the Map Register connects to external data bus bit 0, the second row with a 0 in the Map Register to data bus bit 1 and so on. This technique puts a further constraint on the user's layout: the cells implementing the bits of the register must be ordered so that less significant bits occur below more significant bits. However, there are no constraints about the relative separations of the cells. In practice these two placement constraints: cells occurring in the same April 24, 1997 (Version 1.10) column and in order vertically are easy to meet in datapath type designs. Normally, the Map Register is set once to indicate the placement of the user I/O register which is then accessed many times. Therefore the two write operations required with a 32-bit bus to set up the Map Register represent a small overhead. In data path type designs where several registers are required, for example two input operand registers and a result register, it is easy to ensure that the corresponding bits of the registers occur on the same row but different columns of the array so that the same Map Register value can be used with different column addresses to access the various registers. 18 XC6200 XC6200 Field Programmable Gate Arrays If more 0s exist in the Map Register than there are valid data bus bits then a form of wildcarding occurs during writes. The data bus bits are allocated to the rows of the array with a 0 in their Map Register bit. Once all of the data bus bits have been allocated, Bit 0 of the data bus is allocated to the next row whose Map Register bit is a 0, Bit 1 of the data bus to the next row and so on. This feature means that an entire column of state registers can be written with a single 8-bit write. For example, if the Map Register contains all 0s and the CPU writes FFh to a particular column. All the state registers in that column are written with a 1. The default state of the Map Register is all 0s. During reads, if there are more 0 bits in the Map Register than data bus bits, the first rows with 0 bits are mapped onto the bus. If there are fewer 0s in the Map Register than data bus bits, the upper data bus bits, which are not mapped, are undefined during CPU reads and ignored during CPU writes. An example of Map Register operation is shown in Figure 25. The position of the user-defined register within the cell array is defined by the 0s in the Map Register. Similar registers could be defined for every column in the array if desired. There is a delay of TMPST (see page 43) after a write to the Map Register before the change takes effect. No state accesses should be carried out during this time. There are important notes on the register clocking requirements for reliable register reading and writing in the "Parallel CPU Interface" section. Mask Register A mask unit controlled by a 32-bit register is placed between the external data bus and the internal data connections. When the external data bus is 8 or 16 bits wide only the bottom 8 or 16 bits of this register are significant. A logic `1' in a bit of this register indicates that the corresponding bit of the internal data bus is not relevant. Bit locations corresponding to 1s in the Mask Register retain their values when written. On a write operation the corresponding bit line is not enabled and the state information for that bit is not changed. When the device is reset the Mask Register contains all logic 0s corresponding to all data bus bits valid. During CPU reads, valid register bits which are disabled are read as `0'. Invalid bits (bits which do not physically exist for the register being read) may be read as `0' or `1'. The Mask Register does not affect state register accesses. In this case the Map Register can be used to prevent certain bits being modified. 19 The Mask Register is also ignored during reads and writes to XC6200 XC6200 Control Registers. These are memory locations which control various XC6200 XC6200 functions and are defined in "Address Mode 11 - Programming Control Registers" on page 25 Programming The binary data for configuring XC6200 XC6200, generated by CAD software from the textual description of a user design, must be downloaded into the part itself. This may be performed in several ways. Generally the fastest and most efficient way is by writing directly to the control store, mapped into the address space of a host processor. If a microprocessor or other parallel data source is not available then the serial programming interface may be used. Parallel CPU Interface XC6200 XC6200 has a full parallel CPU interface, referred to as `FastMAPTM`. This makes all the configuration SRAM and logic cells appear as conventional memory mapped SRAM. The FastMAPTM interface is based on Chip Select (CS) and Read/Write (RdWr) control signals. The CS signal can be used to address a single part within an array of devices and allows data to be read or written. Timing for these signals is illustrated in Figures 30 and 31. These figures show that the programming interface is synchronous. The GClk input is used to sample all the interface signals. GClk is also used when accessing user registers as illustrated in Figure 25. This is an important point, as only registers clocked directly by GClk can be reliably read or written using this method. This is because the value written by the CPU is presented to the inputs of the cell registers just before t2 in Figure 30 and held there until GClk goes Low again. Thus it is essential that the register receives a rising clock edge at t2. This can be guaranteed if GClk is used to clock the registers. If another signal is used then it must have a rising edge at t2 for FastMAPTM register writes to work. For reliable register reads, the register contents must be stable between t1 and t2 in Figure 31. This is more fully illustrated in Figure 33. Figure 31 shows two separate read cycles - a normal cycle immediately followed by an extended cycle. In the normal read cycle CS is sampled Low on the first rising GClk edge (t1) and High on the next (t2). The data bus is then driven until the next rising GClk edge (t3). In cases where this is not long enough, the read cycle can be extended by keeping CS asserted beyond t2. This is equivalent to adding wait states. In this case the data bus is driven until CS is deasserted. CS should not be allowed to go High and Low again. This would cause another cycle to begin. CS is sampled on every rising GClk edge. Other CPU interface signals such as RdWr April 24, 1997 (Version 1.10) and the Address Bus are only sampled on the first GClk edge of the cycle (t1 for the first cycle and t3 for the second in the figure examples). Extended write cycles are also possible, however these are functionally no different to normal write cycles, the data and address busses still being sampled on the first rising GClk edge of the cycle (t3 in Figure 30). CS must always be sampled as a `1' before the next cycle can begin. In Figure 31 the extended read cycle starts immediately after the normal read cycle at time t3. A write cycle could not start until the next rising GClk edge as the data from the read cycle is still on the data bus. The SRAM programming interface is supplemented by additional hardware resources designed to minimize the number of processor cycles required for reconfiguration. These resources are initially inactive after a reset so the device looks like an SRAM. Before any data can be read from the device using the FastMAPTM, the Device ID Registers must all be correctly written. This is descibed under "Device Identification Register" on page 26. The control store layout is designed to minimize the overhead of computations required for dynamic access while maintaining adequate density to minimize the external storage required for device configurations. When an external processor is used to configure the device it may be convenient to use a compressed format of the configuration information. A feature of the XC6200 XC6200 architecture is that a rectangular area of cells specified as a hierarchical block within a user's design corresponds directly with a rectangular area within the configuration memory of the XC6200 XC6200 device. This means that a block within the user's design can be dynamically replaced with another block by the host processor, reconfiguring only the corresponding area of the control store. The binary data for both blocks can be precalculated from the cellular design and the actual replacement can be carried out very rapidly using block transfer operations. The format of the address bus to the XC6216 XC6216 device is shown in Table 4. Larger XC6200 XC6200 devices have proportionally more bits allocated to row and column addresses. Mode(1:0) Column(5:0) Column Offset Row(5:0) 15:14 13:8 7:6 5:0 Table 4: Address Bus Format (XC6209 XC6209 and XC6216 XC6216) Mode(1:0) Column(6:0) Column Offset Row(6:0) 17:16 15:9 8:7 6:0 Table 5: Address Bus Format (XC6236 XC6236 and XC6264 XC6264) All the configuration memory can be accessed as 8-bit bytes. When a 16-bit transfer occurs Address is irrelevant. When a 32-bit transfer occurs Address is irrelevant. Data Bus bits are written to the address with Address=00, bits are written to the address with Address = 01, etc. The Address Mode bits are used to determine which area of the control store is to be accessed according to Table 6. Mode1 Mode0 Area Selected 0 0 Cell Configuration and State 0 1 East/West Switch or IOB 1 0 North/South Switch or IOB 1 1 Device Control Registers Table 6: Address Mode Selection Understanding The Configuration Bits The full memory map is given in Tables 26 and 27. From these tables it is possible to work out the address for any bytes of configuration or cell state register in the FPGA. The address/data pairs are normally calculated automatically by XACTstep Series 6000 and written to a .cal file. From Tables 7 to 21 it is possible to work out what data needs to be written to the above addresses to change the configuration of any routing multiplexer or cell in the FPGA. These tables are split into subsections - Cells, East/West Switches and North/South Switches. Within each section, the bytes which control the switches are defined first. This table is then followed by a group of tables which define the coding of the bits within these bytes. This sequence of tables details the coding for the various multiplexer select lines. These are always referred to as `Sel'. The columns refer to the output of the appropriate multiplexer when Sel is at a particular value. As an example, in Table 7, Cell Routing Register Byte 00, Bits [7:6] correspond to the North Neighbor Multiplexer Sel[1:0] in Table 8. When Sel[1:0] = 10, the North output of the cell is routed from the East Neighbor input. As another example, in Table 13, the EOut multiplexer in the West IOB is controlled by Bit4 of Byte 1. This corre- April 24, 1997 (Version 1.10) 20 XC6200 XC6200 Field Programmable Gate Arrays sponds to the single Sel bit in the West IOB block of Table 14. Thus when Bit4=0, EOut=PW4. When Bit4=1, EOut=DFromPad. Table 8: Neighbor Multiplexer Selection Sel[2:0] X1 X2 X3 000 S S S 001 E W E 010 W E W 011 N N N 100 W4 W4 W4 101 S4 E4 S4 110 E4 S4 E4 111 Note that most of the routing multiplexers invert their outputs to reduce propagation delays. This has not been shown in earlier figures. N4 N4 N4 Address Mode 00 - Cell Mode In Mode 00 the 6-bit row and column addresses are effectively a Cartesian coordinate pointer to a particular cell. (0,0) is the cell in the South-West corner of the array. Once a particular cell has been pin-pointed, the 2-bit Column Offset determines which cell configuration RAM byte is accessed. Each cell has 3 separate 8-bit configuration bytes and 1 single-bit state register. The state register is the cell register shown in Figure 6. The three cell configuration bytes are described below. Table 9: X Multiplexer Selection In Mode 00 bytes read from and written to the control store have the format shown in Table 7. Bit 7 is the msb. Column Offset = 00 addresses the neighbor routing multiplexers select lines. Thus a single byte controls all the neighbor routing multiplexers within a basic cell. Bytes 01 and 10 control the remaining cell routing. See Figures 5 and 6 for the connections to these multiplexers. Y3 00 X2 X3 01 Q X3 X2 Q 11 Q Q DATA BIT 7 00 Y2 10 Column Offset Sel[1:0] 6 5 North 01 M East CS 10 4 3 2 1 0 West X2[1:0] X1[2:0] South Table 10: Y Multiplexer Selection X3[1:0] Y2[1:0] Y3[1:0] X2[2] Table 7: Cell Routing CS is the Combinatorial/Sequential multiplexer select line. M is the Magic multiplexer select line and RP is the Register Protect bit for the cell. Column Offset = 11 is used for state accesses. In this case the Data Bus bit values are determined by the Map Register. The Row bits of the address bus are ignored. The multiplexer which selects between Y2 and Y3 in Figure 6 and the RP multiplexer also invert. Thus the inputs to the RP multiplexer are actually C and Q. Sel[1:0] South East West 00 F F F F 01 N E N W 10 E W E N 11 21 North W S S S CS M RP Q X3 NOT PROTECTED (D) 1 X3[2] Sel 0 RP C X2 PROTECTED (Q) Table 11: Remaining Configurable Cell Multiplexers Address Mode 01 - East/West Switches And IOBs Mode 01 addresses the switches which control the East and West FastLANEsTM and the IOBs along the East and West edges. The upper Column address bits pin-point a particular 4x4 block. Column[1:0] then selects which edge of the 4x4 block. Column[1:0] Switches 00 West edge of 4x4 block 01 West IOB (Col[5:2] = 0000) 10 East IOB (Col[5:2] = 1111) 11 East edge of 4x4 block April 24, 1997 (Version 1.10) Table 12: East/West Column Decoding West IOB The IOBs are only addressed if Column[5:2] = 0000 or 1111, in a XC6216 XC6216. Sel[2:0] E4 Mux 001 E16 Mux WCLIn ECL Mux PW4 The Row address bits select an individual row within the array. For example 000000 selects the row at the South edge of the array and 111111 selects the row at the North edge of the array, in a XC6216 XC6216. 010 Having pin-pointed a particular switch group, the Column Offset selects the exact switch required. For length-4 and 16 FastLANETM switches within the array, Column Offset = 00. If an IOB is selected then the Column Offset selects a particular register within the IOB. 101 DToPadB RdEn WrEn 110 EnToPadB DToPadB - PW16 PW4 WCIn 011 WCIn MW 100 MW PW16 111 DelData East IOB East/West IOB Configuration 7 East IOB 6 5 4 3 2 1 En W DfPB Delay E4In PE4 DFromPad 1 DATA BIT Del 0 Column Offset Sel No Delay E4In DFromPad E16 0 00 Del W W16[2:0] 01 West IOB W4[2:0] WCL[2:0] En DfPB Slew PDn PUp Sel[2:0] En ECL[2:0] 000 WCLOut 0 Del E4[2:0] 001 ECLIn PE4 00 PUp PDn Slew DfPB 01 E16[2:0] E Table 13: East/West IOB Configuration Registers East IOB 010 W4 Mux W16 Mux PE16 PE4 WCL Mux ECIn 011 See Figure 15 for details of the IOB architecture. `Del' allows a fixed delay to be added to the DFromPad signal. `E' and `W' are the neighbor outputs into the array. `E4', `W4', etc are the FastLANETM outputs into the array. `DfPB' is the select line for the Control Data (DFromPadB) output from the IOB. `En' allows the Array Enable signal to be inverted. PUp = 1 enables the pad pull-up resistor. PDn = 1 enables the pad pull-down resistor. Slew = 0 causes the output driver to slew its output. See "Pull-Up, Pull-Down And Slew" on page 13. The coding for the individual multiplexers is as follows: West IOB Sel Del En E DfPB 0 Delay W4In PW4 DFromPad 1 No Delay W4In DFromPad W16 West IOB Sel[2:0] 000 E4 Mux E16 Mux ECLOut April 24, 1997 (Version 1.10) ECL Mux 0 ECIn ME 100 ME PE16 101 DToPadB RdEn WrEn 110 EnToPadB DToPadB RegData 111 DelData Table 14: East/West IOB Configuration Coding RdEn and WrEn are signals which are active during reads and writes to state registers in the row corresponding to the IOB. They can be routed back into user designs to detect CPU reads and writes of state registers. The CAD libraries provide special `CBUF' primitives to access this feature. These signals go active after the first rising clock edge of a CPU cycle and go inactive after the second falling clock edge. RegData is the value being written to or read from a state register during a state access. This is illustrated in Figures 32 and 33 on page 46. The FastMAPTM uses a current sensing technique to read RegData internally, therefore if the GClk frequency is high, the voltage on RegData may not actually appear to change during the Read Cycle. For this reason RegData should only be used during Read Cycles if GClk is running at a frequency < TBAns. 22 XC6200 XC6200 Field Programmable Gate Arrays East/West Switch Configuration Column Offsets of 00 select array routing switches at 4x4 or 16x16 boundaries: Multiplexer at the West edge of the array as there are no cells to the West of this multiplexer. In these cases the signals are tied to ground. The only exceptions are the Previous16 inputs to the length-4 multiplexers, which are tied to VCC. Thus for an E4 multiplexer at the extreme Eastern edge of the array, MW=0, PW16=1 and WCIn=0. DATA BIT 7 East 6 5 4 E16[2:0] West 3 2 E[2] 1 0 E4[3:0] W4[3:0] W[2] W16[2:0] Table 15: East/West Routing Configuration Registers The length-16 FastLANETM bits are only of relevance at 16x16 boundaries. The E[2] and W[2] bits are the MSBs controlling the cell neighbor output. The LSBs are the normal neighbor selection bits in the cell routing register. See "Routing Switches" on page 8. Address Mode 10 - North/South Switches And IOBs Mode 10 addresses the switches which control the North and South FastLANEsTM and the IOBs along the North and South edges. Row[5:2] pin-points a particular 4x4 block. Row[1:0] then selects which edge of the 4x4 block. E Mux W Mux E16 Mux F F ECL N W WCIn 010 E N E4In W4In 011 S S PW4 WCOut 100 PW4 PE4 ECOut ECIn 101 ME W16 WCL ECL 110 E16 MW E16 W16 111 E4In W4In ME MW 01 South IOB (Row[5:2] = 0000) North IOB (Row[5:2] = 1111) 11 PE4 South edge of 4x4 block North edge of 4x4 block WCL 001 00 W16 Mux 000 Switches 10 Sel[2:0] Row[1:0] Table 17: North/South Row Decoding The IOBs are only addressed if Row[5:2] = 0000 or 1111. Sel[3:0] E4 Mux W4 Mux Sel[3:0] E4 Mux W4 Mux 0000 MW ECL 1000 ECOut MEA W4In 1001 E4In WCOut 0010 W16* WCL 1010 ME - 0011 WCL MWA 1011 E16 ME 0100 WCIn - 1100 ECL - 0101 - MW 1101 - W16 0110 - - 1110 - - 0111 - E16* 1111 - ECIn Having pin-pointed a particular switch group, the Column Offset selects the exact switch required. If an IOB is selected then the Column Offset selects a particular register within the IOB. - 0001 Column[5:0] selects an individual column within the array. For example 000000 selects the column at the West edge of the array and 111111 selects the column at the East edge of the array. * E4Out at East edge of 16x16 uses PW16. W4Out at West edge of 16x16 uses PE16. North/South IOB Configuration Column Offset DATA BIT 7 North IOB 00 6 5 4 Del En DfPB S 01 10 South IOB SCL[2:0] PUp PDn Slew 00 - 01 10 - - - - 2 1 S16[2:0] S4[0] S4[2:1] Clk[1:0] N16[2:0] 3 N - 0 - - - Clr[2:0] DfPB En Del Clk[2] N4[0] Slew PDn PUp - N4[2:1] NCL[2:0] Table 16: East/West Routing Configuration Coding Table 18: North/South IOB Configuration Registers At the edge of the array some inputs clearly do not make sense. For example there can be no PE4 input to a W 23 April 24, 1997 (Version 1.10) The coding for the individual multiplexers is shown below: North IOB Sel Del En S DfPB 0 Delay N4In PN4 DFromPad 1 No Delay N4In DFromPad where a register must be read before it can be re-written. RegWord is a pulse which starts after the first falling clock edge of a CPU cycle and ends after the second falling clock edge. This is illustrated in Figures 32 and 33 on page 46. The CAD libraries provide special `CBUF' primitives to access this feature. N16 North/South Switch Configuration North IOB Sel[2:0] S4 Mux S16 Mux SCL Mux Clr Mux 000 SCLOut 0 NCLIn PN4 GClk NCIn DATA BIT 7 3 00 - - - - 01 - - - 10 - - - - - 11 G1 6 5 4 - - - - SecClkA[1:0] GClr 001 Column Offset 010 PN16 PN4 011 NCIn MN G2 100 MN PN16 North Switch SOut 101 DToPadB RegWord RegWord 0 110 EnToPadB DToPadB EnToPadB South Switch DelData 1 PrimaryClk[1:0] N16[2:0] 0 N[2] N4[1:0] - N4[3:2] SecClkB[1:0] 00 S[2] S16[2:0] - - - - 01 S4[3:2] DelData 111 - 2 - - - - Clr[2:0] - - - - 10 S4[1:0] SCLOut - Table 20: North/South Routing Configuration Registers South IOB Sel Del En N DfPB 0 Delay S4In PS4 DFromPad 1 No Delay S4In DFromPad S16 South IOB Sel[2:0] N4 Mux N16 Mux NCL Mux Clk Mux 000 NCLOut 0 NCLOut 001 SCLIn PS4 NOut SCIn 0 010 PS16 PS4 011 SCIn MS G1 100 MS PS16 G2 101 DToPadB RegWord RegWord GClr 110 EnToPadB DToPadB EnToPadB GClk 111 DelData Table 19: North/South IOB Configuration Coding RegWord is the Word line which is asserted when state registers in the column corresponding to the IOB are read or written. This may be routed back into user designs as a means of detecting CPU reads and writes of state registers. This has many applications. For example it could be used to implement a `Wait-Signal' semaphore system April 24, 1997 (Version 1.10) The clock multiplexer in each North Switch is split into two sections (see Figure 9 on page 9). The multiplexer which drives ClkOut is referred to as the primary clock multiplexer (PrimaryClk). The multiplexer whose output drives an input of the primary clock multiplexer is referred to as the secondary clock multiplexer (SecClk). Column Offset = 11 in the North Switch addresses the control lines for the secondary clock multiplexers. There is a separate secondary clock multiplexer for each column of cells in a 4x4 block. They are written to in pairs with Column[1:0] determining which pair is addressed. If Column[1:0] = 00 then SecClkA = Column1 (within 4x4 block), SecClkB = Column0. If Column[1:0] = 11 then SecClkA = Column2, SecClkB = Column3. Column[1:0] = 01 and 10 are illegal. Row[1:0] must be set to 11. The length-16 FastLANETM and Clr bits are only of relevance at 16x16 boundaries, otherwise they are non-existent. The N[2] and S[2] bits are the MSBs controlling the cell neighbor output. The LSBs are the normal neighbor selection bits in the cell routing register. See "Routing Switches" on page 8. Sel[2:0] N Mux S Mux N16 Mux S16 Mux Clr Mux 000 F F NCL SCL GClr 001 N E SCL NCL ClrIn 010 E W N16 S16 SCL 24 XC6200 XC6200 Field Programmable Gate Arrays * S4Out at South edge of 16x16 uses PN16. N4Out at North edge of 16x16 uses PS16. Sel[1:0] SecClk GClr ClkIn NCL 10 NOut G1 11 Row Address Decode Row Address Decode Row Address Decode 21 20 SecClk 01 21 PrimaryClk 00 53 52 GClk G2 Table 21: North/South Routing Configuration Coding 23 . . . 16 Address Mode 11 - Programming Control Registers Gross features of the microprocessor interface are controlled by a number of Control Registers. We have already come across some of these in the form of the Map and Mask Registers. All the Programming Control Registers are mapped into the region of the device address space with the mode bits set to 11. Wildcard Registers 000000 010101 Wildcard Address 100001 010101 The FastMAPTM contains additional hardware subsystems which can significantly reduce the processor overhead involved in configuring the device. These units are only active on write cycles. They are also inactive during writes to all Programming Control Registers. 000111 010101 8-Bit Data Bus Figure 26. Row Wildcard Register Sel[2:0] S Mux N16 Mux S16 Mux Clr Mux 011 W S N4In S4In G2 100 N4In S16 PS4 PN4 GClk 101 N16 PN4 NCOut SCOut 0 110 PS4 S4In SCIn NCIn S 111 MN MS MN MS G1 Sel[3:0] N4 Mux S4 Mux Sel[3:0] N4 Mux S4 Mux 0000 SCIn MN 1000 ClkIn SCOut 0001 NCL NCL 1001 N4In - 0010 N16 N16* 1010 - - 0011 NCOut S4In 1011 MNA - 0100 - S16 1100 S16* NCIn 0101 - MS 1101 SCL - 0110 - MSA 1110 MN - 0111 25 N Mux - SCL 1111 MS - The row address decoder is supplemented with a Wildcard Register which can be written through the FastMAPTM. This register has one bit for each bit in the row address. During write cycles, logic one bits in the Wildcard Register indicate that the corresponding bit in the address is to be taken as `don't-care': that is the address decoder matches addresses independent of this bit. When the device is reset this register is initialized to zero so all address bits are treated as significant. Figure 26 shows some examples of the use of this unit assuming an 8-bit external data bus and a XC6216 XC6216 device, so the cell array is eight words high. Outputs from the row address decoder enable bit line circuitry for the appropriate word. The Wildcard Register allows many cell configuration memories within the same column of cells to be written simultaneously with the same data. This is used during device testing to allow regular patterns to be loaded efficiently into the control memory, but is more generally useful, especially with regular bit sliced designs, because it allows many cells to be changed simultaneously. For example, a 16-bit 2:1 multiplexer could be built using cell routing multiplexers and switched between sources using a single control store access. April 24, 1997 (Version 1.10) Similarly, the column address decoder has a Wildcard Register which allows several cells on the same row to be written with the same configuration. The column address decoder drives the word lines to enable particular columns of RAM cells. In this case the number of columns which can be written simultaneously is internally limited to 32: that is, at most five don't care bits can be set. However, to guarantee that cells which are not being written do not overwrite each other, there is a limit on the number of columns which should be written simultaneously. Part Maximum Number Of Column Wildcards XC6209 XC6209 4 XC6216 XC6216 4 XC6236 XC6236 2 XC6264 XC6264 Device Configuration Register This register controls global device functions and modes. The control functions of the bits are given in Table 23. `Config Speed' sets the baud rate of the serial programming interface. `Bus Width' allows selection of external data bus width between 8,16 and 32 bits. The `TTL/ CMOS' bit globally controls the input logic threshold levels for all the I/Os. The default value of `0' causes TTL input thresholds to be used. `1' selects CMOS thresholds. `Clock Enable' allows the user to stop the GClk signal to the cell array. The clock to the control circuitry is not stopped so that CPU cycles, etc. may continue. The default state is Clock Enable = 0, disabling the array GClk. This bit may be modified at any time. Internal circuitry makes sure that the clock is started and stopped in a safe, glitch free manner. Changes to Clock Enable take effect immediately after the write cycle to the Configuration Register. 2 Bit: Table 22: Maximum Number Of Column Wildcards The row and column Wildcard Registers can be used simultaneously to rapidly configure regular structures onto the device. 7 6 5 4 3 Function: - Clock Enable - TTL/CMOS 2 Bus Width 1 0 Config Speed Table 23: Device Configuration Register The row Wildcard Register is ignored in state access mode, as the row decoding is controlled by the Map Register here. The column Wildcard Register may still be used to write to several banks of registers simultaneously. Config. Reg [3:2] Data Bus Width 00 8 01 16 The mask unit, described on page 19, simplifies changing areas of the control store within a single word unit: for example, changing the source of one multiplexer within a cell without affecting the others. Consider changing the source for a cell's North multiplexer without this unit: the following operations are required: 10 32 11 Illegal Table 24: Data Bus Width Coding Config. Reg [1:0] Config Speed 00 GClk/16 1. Read control store at appropriate address. 2. Mask out bits corresponding to North register. 01 GClk/8 3. Get new value for north register bits 6 and 7. Make sure other bits are 0. 10 GClk/4 4. OR new value with value from stage 2. 11 GClk/2 5. Write back. Using the mask unit the following steps suffice (using 8bit transfers): 1. Write Mask Register with binary 00111111. 2. Write new value to control store at appropriate address. The mask and wildcard units can be used together to perform complex operations such as changing the source of the West multiplexer on every second cell at offsets between 0 and 15. April 24, 1997 (Version 1.10) Table 25: Configuration Speed Coding Device Identification Register The ID register is a 16-byte store which must be written with the correct pattern before the device outputs can be enabled. This serves as a check that the programming interface is operating correctly before allowing potentially damaging outputs to be driven. Each byte must be written with the ASCII code for the letters shown in Table 26. The only exception is the last byte. This must be written with a number which distinguishes this part from others within the XC6000 XC6000 group. It is not an ASCII coded number. 26 XC6200 XC6200 Field Programmable Gate Arrays Details of the appropriate ID number for different family members are given in Table 28. Until the ID register is correctly programmed, all the IO pad output drivers are disabled and the pull-up resistors are all enabled. Once a valid ID pattern has been written, the state of the IO pads depends on the OE signal. If OE is High then the output drivers remain disabled with their pull-ups on. When OE is Low individual outputs may be enabled and pulled up depending on their individual control signals. The ID register also provides a means of simultaneously disabling all the device outputs under software control. If any valid ID byte is changed then the outputs are all disabled. The outputs are all re-enabled as soon as the ID byte is written with the correct value. The internal ConfigOK signal is available to user designs to determine when a valid pattern is present. Programming Control Register Memory Map Table 26 lists the address for all the control registers for the XC6209 XC6209 and XC6216 XC6216. Each register may be written in 8-bit bytes. If 16 or 32 data bits are available then less writes are required. For example eight write cycles (to C010, C011,.,C017) are required to change every bit of the Map Register with an 8-bit bus. Only two write cycles (to C010 and C014) are required with a 32-bit bus. If only some bits are to be changed within a particular register then only the appropriate bytes need be written. XC6236 XC6236 and XC6264 XC6264 have 18-bit address busses. The Control Register memory map for these parts is given in Table 27. The full address decoding for the XC6200 XC6200 family is summarized in Tables 29 to 32. A[15:0] Register A[15:0] Register C000 Device Config C031 ID (Byte1) (='i') C004 Row Wildcard C032 ID (Byte2) (='l') C005 Column Wildcard C033 ID (Byte3) (='i') C008 Mask (Byte0) C034 ID (Byte4) (='n') C009 Mask (Byte1) C035 ID (Byte5) (='x') C00A Mask (Byte2) C036 ID (Byte6) (=' ') C00B Mask (Byte3) C037 ID (Byte7) (='X') C010 Map (Byte0) C038 ID (Byte8) (='C') C011 Map (Byte1) C039 ID (Byte9) (='6') C012 Map (Byte2) C03A ID (Byte10) (='0') C013 Map (Byte3) C03B ID (Byte11) (='0') C014 Map (Byte4) C03C ID (Byte12) (='0') C015 Map (Byte5) C03D ID (Byte13) (=' ') C016 Map (Byte6)* C03E ID (Byte14) (=' ') C017 Map (Byte7)* C03F ID (Byte15) (=ID #) C030 ID (Byte0) (='X') Table 26: Control Register Memory Map For XC6209 XC6209 and XC6216 XC6216 * Reserved locations in XC6209 XC6209 27 April 24, 1997 (Version 1.10) A[17:0] Register A[17:0] Register 30000 Device Config 3001D 3001D Map (Byte13)* 30004 Row Wildcard 3001E 3001E Map (Byte14)* 30005 Column Wildcard 3001F 3001F Map (Byte15)* 30008 Mask (Byte0) 30030 ID (Byte0) (='X') 30009 Mask (Byte1) 30031 ID (Byte1) (='i') 3000A Mask (Byte2) 30032 ID (Byte2) (='l') 3000B 3000B Mask (Byte3) 30033 ID (Byte3) (='i') 30010 Map (Byte0) 30034 ID (Byte4) (='n') 30011 Map (Byte1) 30035 ID (Byte5) (='x') 30012 Map (Byte2) 30036 ID (Byte6) (=' ') 30013 Map (Byte3) 30037 ID (Byte7) (='X') 30014 Map (Byte4) 30038 ID (Byte8) (='C') 30015 Map (Byte5) 30039 ID (Byte9) (='6') 30016 Map (Byte6) 3003A ID (Byte10) (='0') 30017 Map (Byte7) 3003B 3003B ID (Byte11) (='0') 30018 Map (Byte8) 3003C 3003C ID (Byte12) (='0') 30019 Map (Byte9) 3003D 3003D ID (Byte13) (=' ') 3001A Map (Byte10) 3003E 3003E ID (Byte14) (=' ') 3001B 3001B Map (Byte11) 3003F 3003F ID (Byte15) (=ID #) 3001C 3001C Map (Byte12)* Table 27: Control Register Memory Map For XC6236 XC6236 and XC6264 XC6264 * Reserved locations in XC6236 XC6236 Device ID Number XC6209 XC6209 2 XC6216 XC6216 1 XC6236 XC6236 4 XC6264 XC6264 3 Table 28: XC6200 XC6200 Family ID Numbers April 24, 1997 (Version 1.10) 28 XC6200 XC6200 Field Programmable Gate Arrays Address Bus Decode A[15:14] 00 Cells (Mode[1:0]) 01 East/West Switch or IOB 10 11 A[13:8] (Column[5:0]) Address Bus Decode A[15:14] 00 Cells (Mode[1:0]) 01 East/West Switch or IOB North/South Switch or IOB 10 North/South Switch or IOB Control Registers 11 Control Registers Cell Mode - Cell column East/West Mode Column[5:2] = 4x4 block number Column[1:0] decoded as: A[13:8] (Column[5:0]) Cell Mode - Cell column East/West Mode Column[5:2] = 4x4 block number Column[1:0] decoded as: 00 West Switch 00 West Switch 01 West IOB (Column[5:2]=0000) 01 West IOB (Column[5:2]=0000) 10 East IOB (Column[5:2]=1011) 10 East IOB (Column[5:2]=1111) 11 East Switch 11 East Switch North/South Mode - Switch column A[7:6] Cell Mode 00 Neighbor Routing 01 Function Input Routing 10 11 (Column Offset[1:0]) North/South Mode - Switch column A[7:6] Cell Mode 00 Neighbor Routing 01 Function Input Routing Function 10 Function State Access (Cell Registers) 11 State Access (Cell Registers) (Column Offset[1:0]) East/West Switch Mode East/West Switch Mode 00 E/W Switch or E/W IOB Reg 0 00 E/W Switch or E/W IOB Reg 0 01 E/W IOB Reg 1 01 E/W IOB Reg 1 North/South Switch Mode 00 00 N/S Switch or N/S IOB Reg 0 N/S Switch or N/S IOB Reg 1 01 N/S Switch or N/S IOB Reg 1 10 N/S Switch or N/S IOB Reg 2 10 N/S Switch or N/S IOB Reg 2 11 (Row[5:0]) N/S Switch or N/S IOB Reg 0 01 A[5:0] North/South Switch Mode Secondary Clock Mux (Column[1:0] = 00 or 11) && (Row[1:0]=11) 11 Secondary Clock Mux (Column[1:0] = 00 or 11) && (Row[1:0]=11) Cell Mode - Cell row East/West Mode - Switch row A[5:0] (Row[5:0]) Cell Mode - Cell row East/West Mode - Switch row North/South Mode Row[5:2] = 4x4 block number Row[1:0] decoded as: North/South Mode Row[5:2] = 4x4 block number Row[1:0] decoded as: 00 South Switch 00 South Switch 01 South IOB (Row[5:2]=0000) 01 South IOB (Row[5:2]=0000) 10 North IOB (Row[5:2]=1011) 10 North IOB (Row[5:2]=1111) 11 North Switch 11 North Switch Table 29: XC6209 XC6209 Memory Map 29 Table 30: XC6216 XC6216 Memory Map April 24, 1997 (Version 1.10) Address Bus Decode A[17:16] 00 Cells (Mode[1:0]) 01 East/West Switch or IOB 10 11 A[15:9] (Column[6:0]) Address Bus Decode A[17:16] 00 Cells (Mode[1:0]) 01 East/West Switch or IOB North/South Switch or IOB 10 North/South Switch or IOB Control Registers 11 Control Registers Cell Mode - Cell column East/West Mode Column[6:2] = 4x4 block number Column[1:0] decoded as: A[15:9] (Column[6:0]) Cell Mode - Cell column East/West Mode Column[6:2] = 4x4 block number Column[1:0] decoded as: 00 West Switch 00 West Switch 01 West IOB (Column[6:2]=00000) 01 West IOB (Column[6:2]=00000) 10 East IOB (Column[6:2]=10111) 10 East IOB (Column[6:2]=11111) 11 East Switch 11 East Switch North/South Mode - Switch column A[8:7] Cell Mode 00 Neighbor Routing 01 Function Input Routing 10 11 (Column Offset[1:0]) North/South Mode - Switch column A[8:7] Cell Mode 00 Neighbor Routing 01 Function Input Routing Function 10 Function State Access (Cell Registers) 11 State Access (Cell Registers) (Column Offset[1:0]) East/West Switch Mode East/West Switch Mode 00 E/W Switch or E/W IOB Reg 0 00 E/W Switch or E/W IOB Reg 0 01 E/W IOB Reg 1 01 E/W IOB Reg 1 North/South Switch Mode 00 00 N/S Switch or N/S IOB Reg 0 N/S Switch or N/S IOB Reg 1 01 N/S Switch or N/S IOB Reg 1 10 N/S Switch or N/S IOB Reg 2 10 N/S Switch or N/S IOB Reg 2 11 (Row[6:0]) N/S Switch or N/S IOB Reg 0 01 A[6:0] North/South Switch Mode Secondary Clock Mux (Column[1:0] = 00 or 11) && (Row[1:0]=11) 11 Secondary Clock Mux (Column[1:0] = 00 or 11) && (Row[1:0]=11) Cell Mode - Cell row East/West Mode - Switch row A[6:0] (Row[6:0]) Cell Mode - Cell row East/West Mode - Switch row North/South Mode Row[6:2] = 4x4 block number Row[1:0] decoded as: North/South Mode Row[6:2] = 4x4 block number Row[1:0] decoded as: 00 South Switch 00 South Switch 01 South IOB (Row[6:2]=00000) 01 South IOB (Row[6:2]=00000) 10 North IOB (Row[6:2]=10111) 10 North IOB (Row[6:2]=11111) 11 North Switch 11 North Switch Table 31: XC6236 XC6236 Memory Map April 24, 1997 (Version 1.10) Table 32: XC6264 XC6264 Memory Map 30 XC6200 XC6200 Field Programmable Gate Arrays Serial Programming Interface All the memory mapped locations in XC6200 XC6200 may be written in parallel or serial mode. All the operations which can be carried out with the FastMAPTM parallel interface may also be done serially. The serial interface gives random access to all the XC6200 XC6200 memory locations. It is designed to operate with any Xilinx serial PROM. A single serial PROM may be used to configure several FPGAs. In this case one of the FPGAs acts as a `Master' and the others as `Slaves'. The Master controls the serial PROM and the Slaves. This is illustrated in Figure 27. The serial PROM interface consists of 6 dedicated I/O pins: Serial Input which controls transitions between states in serial mode state machine. 0 => serial mode, 1 => parallel mode Wait Input which controls transitions between states in serial mode state machine. 0 => continue loading, 1 => pause until Wait deasserted SEReset Output from Master FPGA which resets serial PROM address counter. SECE Output from Master FPGA which enables serial PROM output. SEClk Output from Master FPGA which clocks serial PROM and slave FPGAs. SEData is clocked into the FPGAs on the rising edge of SEClk. SEData Serial data input to FPGA. This is sampled in the FPGA by SEClk and retimed by the FPGA's own GClk. MASTER FPGA Serial Wait In a multi-FPGA configuration a user I/O also has to be available to provide the Wait input to the next device in the chain. On Reset each FPGA examines its Serial and Wait inputs. Any FPGA which sees both these signals Low at this time assumes it is the master and drives SEReset, SECE and SEClk. All User I/Os are held in a high-impedance state (with pull-up) until a valid configuration is loaded. In the Figure 27 example the User I/O's are pulled High on Reset, hence the Wait input to the Slaves is High and they configure as Slaves. A valid configuration is assumed when the device ID register is loaded with the correct ID. Programmable I/Os can only be enabled when this is present. Serial data is loaded in address/data pairs. Once an address/data pair has been shifted into the FPGA, the data word is parallel written to the corresponding address inside the FPGA, just as though a parallel CPU write had occurred. This means it is possible to do all the things which can be accomplished with the FastMAPTM. e.g. use of the Mask Register, writes to cell state registers, etc. The write operation is pipelined so there need be no interruption in the serial data stream. The first address/data pair must be preceded by a Synchronization Byte = 1111_1110. There are no start/stop bits, checksums or error check/correction bits. A full 8-bit Synchronization byte is not actually required by the FPGA. Three or more ones followed by a single zero is interpreted as a valid synchronization pattern. The address and data are shifted in MSB first. The address is always 16-bits. The data word is initially 8-bits but may be increased to 16 or 32 bits by loading the Device Configuration Register with the appropriate code. The bits are shifted in on the rising edge of SEClk. The SEClk rate may also be increased by writing the appropri- SLAVE FPGA 1 Serial User I/O Wait SLAVE FPGA 2 Serial User I/O Wait etc. Gnd SEReset SERIAL SECE PROM SEClk SEClk SEClk SEData SEData SEData Figure 27. Master-Slave Serial Configuration 31 April 24, 1997 (Version 1.10) ate code to the Device Configuration Register. Initially SEClk is 1/16 GClk frequency. It can also be set to 1/8, 1/ 4 or 1/2 GClk. An example is shown in Figure 28. Data1 is loaded into Addr1 after the address lsb has been shifted in. In this example the first write was to the Device Configuration Register and the data bus width was changed from 8 to 32 bits. Data word 2 starts immediately after Addr1 has been shifted in. Due to the new data bus width, 32 data bits are shifted in. If the width had not been changed data word 2 would also have been 8 bits. Data continues to be loaded until Serial goes High or Wait goes High. Serial Interface State Machine The serial interface is controlled by a state machine. This is a synchronous state machine with the state transitions occurring on rising edges of GClk. The transitions between states are mainly controlled by the Serial and Wait inputs. These signals are internally retimed, so it is the value sampled on the rising GClk edge prior to the edge causing the state transition which is used to determine the next state. A state diagram is shown in Figure 29. Transitions which show the state machine remaining in a state are not shown. The behavior is described below: Device remains in this state for TMRR after Reset has been deasserted. The 4th rising GClk edge after TMRR causes the transition to State 0. It is also this 4th clock edge which samples Serial and Wait to determine which state to enter after State 0. Goto State 0 State 0 : Initial State - Determine if this is the Master FPGA. SECE inactive, SEClk Low. if (Serial = 1) then goto State 1 (Parallel) else if (Wait = 1) then goto State 4 (Wait) else goto State 2 (Master Initialize) State 1 : Parallel - Ready to load parallel data via CPU interface. If Master, SECE inactive, SEClk Low. If Wait=1 in this state, and the outputs are disabled (either because OE=1 or the ID registers have not yet been written) , all the FPGA I/ Os enter Leakage Test mode. This mode is for Reset Master = False - i.e. initially this FPGA is not the Master. GClk 3 tCG 1 tDC