XC4000E XC4000E/EX 10K10 10K20 10K40 10K50 10K70 10K100 10K30 - Datasheet Archive

 

XC4000E Select-RAMTM: Maximum Configurability ® XBRF 003 July 11, 1996 (Version 1.0) Application Brief Summary XC4000E

 

APPLICATION BRIEF XC4000E XC4000E Select-RAMTM: Maximum Configurability ® XBRF 003 July 11, 1996 (Version 1.0) Application Brief Summary XC4000E XC4000E Select-RAMTM: Maximum Configurability Xilinx Family XC4000E/EX XC4000E/EX Introduction Configuring FPGA Memory for various design specific needs is a key requirement. Xilinx XC4000E/EX XC4000E/EX offer a wide variety of configuration options from Address and Data width to Dual-Port operation. Detailed analysis shows that Select-RAM is the most silicon efficient implementation for FPGA memory. Due to the Dual-Port RAM capability it also offers maximum bandwidth for most applications. In contrast the Altera FLEX 10K memory can be used efficiently only for a few of the configurations. Also, any implementation requiring FIFOs or Dual-Port operation slows down the FLEX 10K memory drastically since it requires emulation of Dual-Port operation. Maximum Configuration Flexibility The new XC4000E XC4000E CLB can be used as 16X2 or 32X1 memory element. These memory elements can then be cascaded together to form larger memories with various Address and Data options. Altera's large 2K bit memory blocks are wasteful because all of the memory within a block, is seldom utilized. Table 1 shows a broad range of desirable memory configurations. It then shows the number of EABs used for different memory configurations. It also shows the %utilization of FLEX 10K EAB memory for those configurations. A percentage EAB memory utilization at or below 50% is inefficient use of device silicon. Table 1 also shows FLEX 10K10 10K10 with three EABs can efficiently implement only five of the popular memory configurations. Similarly 10K20 10K20 and 10K 30 with six EABs can efficiently implement only four possible configurations. Finally, 10K40 10K40, 10K50 10K50, 10K70 10K70 and 10K100 10K100 can efficiently implement five possible configurations. Dual-Port Access FPGA designs frequently implement large FIFOs/RAM Buffers especially in Datacomm and DSP intensive areas. Most FIFO/RAM Buffer functions require Dual Port RAMs along with fast speed. The Xilinx XC4000E XC4000E Select-RAM now offers Dual-Port RAMs with independent access from both sides. The Altera FLEX 10K requires emulating dual-port RAM which cuts down the available memory size and speed in half! This makes a 20ns memory operate on certain key timings at a slow 40ns speed, eliminating a number of fast speed applications. Memory Depth Table 1: FLEX 10K Memory Implementation: Number of EABs (% EAB Memory Utilization) 8 16 32 64 128 256 512 1024 2048 4096 4 1(2%) 1(3%) 1(6%) 1(13%) 1(25%) 1(50%) 1(100%) 2 4 8 8 1(3%) 1(6%) 1(13%) 1(25%) 1(50%) 1(100%) 2 4 8 XBRF 003 July 11, 1996 (Version 1.0) Memory Width 16 2(3%) 2(6%) 2(13%) 2(25%) 2(50%) 2(100%) 4 8 32 4(3%) 4(6%) 4(13%) 4(25%) 4(50%) 4(100%) 8 64 8(3%) 8(6%) 8(13%) 8(25%) 8(50%) 8(100%) Exceeds 10K Family Limit 10K10 10K10 = 3 10K20 10K20 = 6 10K30 10K30 = 6 10K40 10K40 = 8 10K50 10K50 = 10 10K70 10K70 = 9 10K100 10K100 = 12 1 XC4000E XC4000E Select-RAMTM: Maximum Configurability Routing Impact On Performance Performance Due to the limitations of FLEX 10K column interconnects almost all wide signals use the slowest interconnect path in Altera FLEX devices. For any memory width the device implementation in MAX+PLUS II toolset used the slow rowcolumn-row delay path for addresses, data-in and data-out. This addition delay occurs twice once in address path and second time in the data path for each memory access. This slows down the effective memory access time by additional 5 ns. The performance of the XC4000E XC4000E RAM is superior to the FLEX 10K in a wide variety of sizes and configurations. As shown in Table 2, when configured as single port memory, the Xilinx RAM out performs the Altera memory in the commonly needed scratch pad RAM sizes of 8 to 32 bits deep by 4 to 64 bits wide. Table 3 further shows that the Xilinx XC4000E XC4000E true dual port memory consistently out performs the Altera FLEX 10K emulated dual port memory. Table 2: Xilinx 4KE vs. FLEX 10K Single Port RAM Performance (ns) Memory Depth 4 8 16 32 64 Xilinx 13.9 17.6 19.7 22.6 8 Altera 21.6 21.6 21.6 21.6 Xilinx 17.4 16.8 21.8 25.1 Altera 21.6 21.6 21.6 24.2 Memory Width 16 Xilinx Altera 19.5 21.6 20 24.7 24 25.5 31.7 24.7 32 Xilinx 21.6 29.5 32 64 Altera 36.5 36.5 36.5 Xilinx 34.7 29.8 Altera 36.8 36.8 Table 3: Xilinx 4KE vs. FLEX 10K Dual Port RAM Performance (MHz) Memory Width 4 8 16 32 Memory Depth Xilinx Altera Xilinx Altera Xilinx Altera Xilinx Altera 16 115.3 27.62 102.6 27.62 80.4 26.04 54.2 23.47 32 79.5 27.62 76.6 27.62 58.9 27.62 48 23.26 64 81.7 25.13 67.1 26.04 62.7 26.18 37.1 23.81 128 55.7 26.04 52.3 26.04 47.1 27.62 32.5 25.51 256 43.5 28.09 38.7 26.04 512 33.2 27.62 ® The Programmable Logic CompanySM Headquarters Xilinx, Inc. 2100 Logic Drive San Jose, CA 95124 U.S.A. Tel: 1 (800) 255-7778 or 1 (408) 559-7778 Fax: 1 (800) 559-7114 Net: hotline@xilinx.com Web: http://www.xilinx.com © 1996 Xilinx, Inc. All rights reserved. The Xilinx name and the Xilinx logo are registered trademarks, all XC-designated products are trademarks, and the Programmable Logic Company is a service mark of Xilinx, Inc. All other trademarks and registered trademarks are the property of their respective owners. Xilinx, Inc. does not assume any liability arising out of the application or use of any product described herein; nor does it convey any license under its patent, copyright or maskwork rights or any rights of others. Xilinx, Inc. reserves the right to make changes, at any time, in order to improve reliability, function or design and to supply the best product possible. Xilinx, Inc. cannot assume responsibility for the use of any circuitry described other than circuitry entirely embodied in its products. Products are manufactured under one or more of the following U.S. Patents: (4,847,612; 5,012,135; 4,967,107; 5,023,606; 4,940,909; 5,028,821; 4,870,302; 4,706,216; 4,758,985; 4,642,487; 4,695,740; 4,713,557; 4,750,155; 4,821,233; 4,746,822; 4,820,937; 4,783,607; 4,855,669; 5,047,710; 5,068,603; 4,855,619; 4,835,418; and 4,902,910. Xilinx, Inc. cannot assume responsibility for any circuits shown nor represent that they are free from patent infringement or of any other third party right. Xilinx, Inc. assumes no obligation to correct any errors contained herein or to advise any user of this text of any correction if such be made. 2 XBRF 003 July 11, 1996 (Version 1.0)