XC4000E XC4000 MIL-PRF-38535 XC4005E XC4010E XC4013E XC4025E PG156 CB164 PG191 - Datasheet Archive

 

XC4000E High-Reliability Field Programmable Gate Arrays ® November 21, 1997 (Version 1.3) 0 8* Product Specification XC4000E

 

0 XC4000E XC4000E High-Reliability Field Programmable Gate Arrays ® November 21, 1997 (Version 1.3) 0 8* Product Specification XC4000E XC4000E High-Reliability Features · System featured Field-Programmable Gate Arrays - Select-RAMTM memory: on-chip ultra-fast RAM with - synchronous write option - dual-port RAM option - Abundant flip-flops - Flexible function generators - Dedicated high-speed carry logic - Wide edge decoders on each edge - Hierarchy of interconnect lines - Internal 3-state bus capability - 8 global low-skew clock or signal distribution networks · System Performance beyond 60 MHz · Flexible Array Architecture · Low Power Segmented Routing Architecture · Systems-Oriented Features - IEEE 1149.1-compatible boundary scan logic support - Individually programmable output slew rate - Programmable input pull-up or pull-down resistors - 12-mA sink current per XC4000E XC4000E output · Configured by Loading Binary File - Unlimited reprogrammability · Readback Capability · · · - Program verification - Internal node observability Backward Compatible with XC4000 XC4000 Devices Development System runs on most common computer platforms - Interfaces to popular design environments - Fully automatic mapping, placement and routing - Interactive design editor for design optimization Available in class Q fully compliant QML and Military temperature range only - Certified to MIL-PRF-38535 MIL-PRF-38535, appendix A QML (Qualified Manufacturers Listing) Xilinx High-Reliability XC4000E XC4000E family is supplied under the following standard microcircuit drawings (SMDs): XC4005E XC4005E 5962-97522 XC4010E XC4010E 5962-97523 XC4013E XC4013E 5962-97524 XC4025E XC4025E 5962-97525 For more information contact DSCC (Defense Supply Center Columbus) Columbus, Ohio. Table 1: XC4000E XC4000E Field Programmable Gate Arrays Device XC4005E XC4005E Max. Typical Logic Max. RAM Gate Range Gates Bits (Logic and (No RAM) (No Logic) RAM)* 5,000 6,272 3,000 - 9,000 XC4010E XC4010E 10,000 12,800 XC4013E XC4013E 13,000 18,432 XC4025E XC4025E 25,000 32,768 Total CLBs 196 Number of Flip-Flops 616 Max. Decode Inputs per side 42 Max. User I/O 112 400 1,120 60 160 24 x 24 576 1,536 72 192 32 x 32 1,024 2,560 96 256 CLB Matrix 14 x 14 7,000 - 20,000 20 x 20 10,000 30,000 15,000 45,000 Packages PG156 PG156, CB164 CB164 PG191 PG191, CB196 CB196 PG223 PG223, CB228 CB228 PG299 PG299, CB228 CB228 * Max values of Typical Gate Range include 20-30% of CLBs used as RAM. November 21, 1997 (Version 1.3) 8-11 XC4000E XC4000E High-Reliability Field Programmable Gate Arrays XC4000E XC4000E Switching Characteristics XC4000E XC4000E Absolute Maximum Ratings Symbol VCC VIN VTS TSTG TSOL TJ Note 1: Note 2: Description Supply voltage relative to GND Input voltage relative to GND (Note 1) Voltage applied to 3-state output (Note 1) Storage temperature (ambient) Maximum soldering temperature (10 s @ 1/16 in. = 1.5 mm) Junction temperature Ceramic packages Value -0.5 to +7.0 -0.5 to VCC +0.5 -0.5 to VCC +0.5 -65 to +150 +260 +150 Units V V V °C °C °C Maximum DC overshoot or undershoot above Vcc or below GND must be limited to either 0.5 V or 10 mA, whichever is easier to achieve. During transitions, the device pins may undershoot to -2.0 V or overshoot to Vcc + 2.0 V, provided this over- or undershoot lasts less than 20 ns. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability. XC4000E XC4000E Recommended Operating Conditions Symbol VCC VIH VIL TIN Note: 8-12 Description Supply voltage relative to GND, TC = -55°C to +125°C High-level input voltage Low-level input voltage Input signal transition time TTL inputs TTL inputs Min 4.5 2.0 0 Max 5.5 VCC 0.8 250 Units V V V ns At case temperatures above those listed as Recommended Operating Conditions, all delay parameters increase by 0.35% per °C. Input and output Measurement thresholds are: 1.5V for TTL and 2.5V for CMOS. All specifications are subject to change without notice. November 21, 1997 (Version 1.3) XC4000E XC4000E DC Characteristics Over Operating Conditions Symbol VOH VOL ICCO IL CIN IRIN* IRLL* Note 1: Note 2: * Description High-level output voltage @ IOH = -4.0mA, VCC min TTL outputs Low-level output voltage @ IOL = 12.0mA, VCC min (Note 1) TTL outputs Quiescent FPGA supply current (Note 2) Input or output leakage current Input capacitance (sample tested) Pad pull-up (when selected) @ VIN = 0V (sample tested) Horizontal Longline pull-up (when selected) @ logic Low Min 2.4 -10 -0.02 0.2 Max 0.4 50 +10 16 -0.25 2.5 Units V V mA µA pF mA mA With 50% of the outputs simultaneously sinking 12mA, up to a maximum of 64 pins. With no output current loads, no active input or Longline pull-up resistors, all package pins at Vcc or GND, and the FPGA configured with the development system Tie option. Characterized Only. XC4000E XC4000E Global Buffer Switching Characteristic Guidelines Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605 MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. When fewer vertical clock lines are connected, the clock distribution is faster; when multiple clock lines per column are driven from the same global clock, the delay is longer. For more specific, more precise, and worst-case guaranteed data, reflecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature) Description From pad through Primary buffer, to any clock K From pad through Secondary buffer, to any clock K November 21, 1997 (Version 1.3) Symbol TPG TSG Speed Grade Device XC4005E XC4005E XC4010E XC4010E XC4013E XC4013E XC4025E XC4025E XC4005E XC4005E XC4010E XC4010E XC4013E XC4013E XC4025E XC4025E -4 Max 7.0 11.0 11.5 12.5 7.5 11.5 12.0 13.0 Units ns ns ns ns ns ns ns ns 8-13 XC4000E XC4000E High-Reliability Field Programmable Gate Arrays XC4000E XC4000E Horizontal Longline Switching Characteristic Guidelines Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605 MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all XC4000E XC4000E devices unless otherwise noted. The following guidelines reflect worst-case values over the recommended operating conditions. Description Speed Grade Symbol Device -4 Max Units 5.0 8.0 9.0 11.0 6.0 10.5 11.0 12.0 7.0 8.5 8.7 11.0 1.8 3.0 3.5 4.0 23.0 29.0 32.0 42.0 10.0 13.5 15.0 18.0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns TBUF driving a Horizontal Longline (LL): I going High or Low to LL going High or Low, while T is Low. Buffer is constantly active. (Note1) TIO1 I going Low to LL going from resistive pull-up High to active Low. TBUF configured as open-drain. (Note1) TIO2 T going Low to LL going from resistive pull-up or floating High to active Low. TBUF configured as open-drain or active buffer with I = Low. (Note1) TON T going High to TBUF going inactive, not driving LL TOFF T going High to LL going from Low to High, pulled up by a single resistor. (Note 1) TPUS T going High to LL going from Low to High, pulled up by two resistors. (Note1) TPUF Note 1: 8-14 XC4005E XC4005E XC4010E XC4010E XC4013E XC4013E XC4025E XC4025E XC4005E XC4005E XC4010E XC4010E XC4013E XC4013E XC4025E XC4025E XC4005E XC4005E XC4010E XC4010E XC4013E XC4013E XC4025E XC4025E XC4005E XC4005E XC4010E XC4010E XC4013E XC4013E XC4025E XC4025E XC4005E XC4005E XC4010E XC4010E XC4013E XC4013E XC4025E XC4025E XC4005E XC4005E XC4010E XC4010E XC4013E XC4013E XC4025E XC4025E These values include a minimum load. Use the static timing analyzer to determine the delay for each destination. November 21, 1997 (Version 1.3) XC4000E XC4000E Wide Decoder Switching Characteristic Guidelines Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605 MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all XC4000E XC4000E devices unless otherwise noted. The following guidelines reflect worst-case values over the recommended operating conditions. Description Full length, both pull-ups, inputs from IOB I-pins Symbol TWAF Full length, both pull-ups, inputs from internal logic TWAFL Half length, one pull-up, inputs from IOB I-pins TWAO Half length, one pull-up, inputs from internal logic TWAOL Speed Grade Device XC4005E XC4005E XC4010E XC4010E XC4013E XC4013E XC4025E XC4025E XC4005E XC4005E XC4010E XC4010E XC4013E XC4013E XC4025E XC4025E XC4005E XC4005E XC4010E XC4010E XC4013E XC4013E XC4025E XC4025E XC4005E XC4005E XC4010E XC4010E XC4013E XC4013E XC4025E XC4025E -4 Max 9.5 15.0 16.0 18.0 12.5 18.0 19.0 21.0 10.5 16.0 17.0 19.0 12.5 18.0 19.0 21.0 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Notes: These delays are specified from the decoder input to the decoder output. Fewer than the specified number of pullup resistors can be used, if desired. Using fewer pullups reduces power consumption but increases delays. Use the static timing analyzer to determine delays if fewer pullups are used. November 21, 1997 (Version 1.3) 8-15 XC4000E XC4000E High-Reliability Field Programmable Gate Arrays XC4000E XC4000E CLB Switching Characteristic Guidelines Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605 MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all XC4000E XC4000E devices unless otherwise noted. Description Combinatorial Delays F/G inputs to X/Y outputs F/G inputs via H to X/Y outputs C inputs via H to X/Y outputs CLB Fast Carry Logic Operand inputs (F1, F2, G1, G4) to COUT Add/Subtract input (F3) to COUT Initialization inputs (F1, F3) to COUT CIN through function generators to X/Y outputs CIN to COUT, bypass function generators Sequential Delays Clock K to outputs Q Setup Time before Clock K F/G inputs F/G inputs via H C inputs via H1 through H C inputs via H2 through H C inputs via DIN C inputs via EC C inputs via S/R, going Low (inactive) 8-16 Speed Grade Symbol -4 Min Max Units TILO TIHO THH1O 3.9 5.9 4.9 ns ns ns TOPCY TASCY TINCY TSUM TBYP 4.4 6.8 2.9 5.0 1.0 ns ns ns ns ns TCKO 5.0 ns TICK TIHCK THH1CK THH2CK TDICK TECCK TRCK 4.0 6.1 5.0 4.8 3.0 4.0 4.2 ns ns ns ns ns ns ns November 21, 1997 (Version 1.3) XC4000E XC4000E CLB Switching Characteristic Guidelines (continued) Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605 MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are not measured directly. They are derived from benchmark timing patterns that are taken at device introduction, prior to any process improvements. For more detailed, more precise, and more up-todate information, use the values provided by the static timing analyzer and used in the simulator. The following guidelines reflect worst-case values over the recommended operating conditions. They are expressed in units of nanoseconds and apply to all XC4000E XC4000E devices unless otherwise noted. Description Hold Time after Clock K F/G inputs F/G inputs via H C inputs via H1 through H C inputs via DIN C inputs via EC C inputs via SR, going Low (inactive) Clock Clock High time Clock Low time Set/Reset Direct Width (High) Delay from C inputs via S/R, going High to Q Master Set/Reset Width (High or Low) Delay from Global Set/Reset net to Q November 21, 1997 (Version 1.3) Symbol Speed Grade Device -4 Min Max Units TCKI TCKIH TCKHH1 TCKDI TCKEC TCKR 0 0 0 0 0 0 ns ns ns ns ns ns TCH TCL 4.5 4.5 ns ns TRPW TRIO 5.5 TMRW TMRQ 6.5 4005E 4005E 4010E 4010E 4013E 4013E 4025E 4025E 4005E 4005E 4010E 4010E 4013E 4013E 4025E 4025E ns ns 23.0 60.0 77.0 134.0 ns ns ns ns ns ns ns ns 13.0 55.0 70.0 112.0 8-17 XC4000E XC4000E High-Reliability Field Programmable Gate Arrays XC4000E XC4000E CLB Edge-Triggered (Synchronous) RAM Switching Characteristic Guidelines Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605 MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all XC4000E XC4000E devices unless otherwise noted. Single Port RAM Speed Grade -4 Units Size Symbol Min Max Write Operation Address write cycle time (clock K period) 16x2 32x1 TWCS TWCTS 15.0 15.0 Clock K pulse width (active edge) 16x2 32x1 TWPS TWPTS 7.5 7.5 Address setup time before clock K 16x2 32x1 TASS TASTS 2.8 2.8 ns ns Address hold time after clock K 16x2 32x1 TAHS TAHTS 0 0 ns ns DIN setup time before clock K 16x2 32x1 TDSS TDSTS 3.5 2.5 ns ns DIN hold time after clock K 16x2 32x1 TDHS TDHTS 0 0 ns ns WE setup time before clock K 16x2 32x1 TWSS TWSTS 2.2 2.2 ns ns WE hold time after clock K 16x2 32x1 TWHS TWHTS 0 0 ns ns Data valid after clock K 16x2 32x1 TWOS TWOTS Notes: ns ns 1 ms 1 ms 10.3 11.6 ns ns ns ns Timing for the 16x1 RAM option is identical to 16x2 RAM timing. Applicable Read timing specifications are identical to Level-Sensitive Read timing. Dual-Port RAM Speed Grade -4 Units Size Symbol Min Max Write Operation Address write cycle time (clock K period) Clock K pulse width (active edge) Address setup time before clock K Address hold time after clock K DIN setup time before clock K DIN hold time after clock K WE setup time before clock K WE hold time after clock K Data valid after clock K Note: 8-18 16x1 16x1 16x1 16x1 16x1 16x1 16x1 16x1 16x1 TWCDS TWPDS TASDS TAHDS TDSDS TDHDS TWSDS TWHDS TWODS 15.0 7.5 2.8 0 2.2 0 2.2 0.3 1 ms 10.0 ns ns ns ns ns ns ns ns ns Applicable Read timing specifications are identical to Level-Sensitive Read timing. November 21, 1997 (Version 1.3) XC4000E XC4000E CLB RAM Synchronous (Edge-Triggered) Write Timing TWPS WCLK (K) TWHS TWSS WE TDSS TDHS TASS TAHS DATA IN ADDRESS TILO TILO TWOS DATA OUT OLD NEW X6461 X6461 XC4000E XC4000E CLB Dual-Port RAM Synchronous (Edge-Triggered) Write Timing TWPDS WCLK (K) TWSDS TWHDS TDSDS TDHDS TASDS TAHDS WE DATA IN ADDRESS TILO TILO TWODS DATA OUT OLD NEW X6474 X6474 November 21, 1997 (Version 1.3) 8-19 XC4000E XC4000E High-Reliability Field Programmable Gate Arrays XC4000E XC4000E CLB Level-Sensitive RAM Switching Characteristic Guidelines Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605 MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all XC4000E XC4000E devices unless otherwise noted. Speed Grade -4 Units Description Size Symbol Min Max Write Operation Address write cycle time 16x2 32x1 TWC TWCT 8.0 8.0 ns ns Write Enable pulse width (High) 16x2 32x1 TWP TWPT 4.0 4.0 ns ns Address setup time before WE 16x2 32x1 TAS TAST 2.0 2.0 ns ns Address hold time after end of WE 16x2 32x1 TAH TAHT 2.5 2.0 ns ns DIN setup time before end of WE 16x2 32x1 TDS TDST 4.0 5.0 ns ns DIN hold time after end of WE 16x2 32x1 TDH TDHT 2.0 2.0 ns ns Address read cycle time 16x2 32x1 TRC TRCT 4.5 6.5 ns ns Data valid after address change (no Write Enable) 16x2 32x1 TILO TIHO 16x2 32x1 TICK TIHCK Data valid after WE goes active (DIN stable before WE) 16x2 32x1 TWO TWOT 10.0 12.0 ns ns Data valid after DIN (DIN changes during WE) 16x2 32x1 TDO TDOT 9.0 11.0 ns ns WE setup time before clock K 16x2 32x1 TWCK TWCKT 8.0 9.6 ns ns Data setup time before clock K 16x2 32x1 TDCK TDCKT 7.0 8.0 ns ns Read Operation 3.9 5.9 ns ns Read Operation, Clocking Data into Flip-Flop Address setup time before clock K 4.0 6.1 ns ns Read During Write Read During Write, Clocking Data into Flip-Flop Note: 8-20 Timing for the 16x1 RAM option is identical to 16x2 RAM timing. November 21, 1997 (Version 1.3) XC4000E XC4000E CLB Level-Sensitive RAM Timing Characteristics T WC ADDRESS WRITE TAS T WP T AH WRITE ENABLE T DS DATA IN REQUIRED READ WITHOUT WRITE X,Y OUTPUTS T DH T ILO VALID VALID READ, CLOCKING DATA INTO FLIP-FLOP T ICK T CH CLOCK T CKO VALID (OLD) XQ, YQ OUTPUTS VALID (NEW) READ DURING WRITE T WP WRITE ENABLE T DH DATA IN (stable during WE) T WO X, Y OUTPUTS VALID DATA IN (changing during WE) OLD VALID NEW T DO T WO X, Y OUTPUTS VALID (PREVIOUS) VALID (OLD) VALID (NEW) READ DURING WRITE, CLOCKING DATA INTO FLIP-FLOP T WP WRITE ENABLE T WCK T DCK DATA IN CLOCK T CKO XQ, YQ OUTPUTS X2640 X2640 November 21, 1997 (Version 1.3) 8-21 XC4000E XC4000E High-Reliability Field Programmable Gate Arrays XC4000E XC4000E Guaranteed Input and Output Parameters (Pin-to-Pin, TTL I/O) Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605 MIL-M-38510/605. All devices are 100% functionally tested. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and are guaranteed over worst-case operating conditions (supply voltage and junction temperature). Listed below are representative values for typical pin locations and normal clock loading. For more specific, more precise, and worst-case guaranteed data, reflecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. Values apply to all XC4000E XC4000E devices unless otherwise noted. Description Global Clock to Output (fast) using OFF TPG Symbol TICKOF . . . . . OFF Global Clock-to-Output Delay (Max) Speed Grade Device -4 Units XC4005E XC4005E XC4010E XC4010E XC4013E XC4013E XC4025E XC4025E 14.0 16.0 16.5 17.0 ns ns ns ns XC4005E XC4005E XC4010E XC4010E XC4013E XC4013E XC4025E XC4025E 18.0 20.0 20.5 21.0 ns ns ns ns XC4005E XC4005E XC4010E XC4010E XC4013E XC4013E XC4025E XC4025E 2.0 1.9 1.6 1.5 ns ns ns ns XC4005E XC4005E XC4010E XC4010E XC4013E XC4013E XC4025E XC4025E 4.6 6.0 7.0 8.0 ns ns ns ns XC4005E XC4005E XC4010E XC4010E XC4013E XC4013E XC4025E XC4025E 8.5 8.5 8.5 9.5 ns ns ns ns ns ns ns ns XC4005E XC4005E XC4010E XC4010E XC4013E XC4013E XC4025E XC4025E 0 0 0 0 ns ns ns ns X3202 X3202 Global Clock to Output (slew-limited) using OFF TPG TICKO . . . . . OFF Global Clock-to-Output Delay (Max) X3202 X3202 Input Setup Time, using IFF (no delay) TPSUF D Input Set - Up & Hold Time (Min) IFF TPG X3201 X3201 Input Hold Time, using IFF (no delay) TPHF D Input Set - Up & Hold Time (Min) IFF TPG X3201 X3201 Input Setup Time, using IFF (with delay) TPSU D Input Set - Up & Hold Time (Min) IFF TPG X3201 X3201 Input Hold Time, using IFF (with delay) TPH D Input Set - Up & Hold Time (Min) IFF TPG X3201 X3201 OFF = Output Flip-Flop 8-22 IFF = Input Flip-Flop or Latch November 21, 1997 (Version 1.3) XC4000E XC4000E IOB Input Switching Characteristic Guidelines Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605 MIL-M-38510/605. All devices are 100% functionally tested. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and are guaranteed over worst-case operating conditions (supply voltage and junction temperature). Listed below are representative values for typical pin locations and normal clock loading. For more specific, more precise, and worst-case guaranteed data, reflecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. Values apply to all XC4000E XC4000E devices unless otherwise noted. Description Symbol Speed Grade Device -4 Min Max Units Propagation Delays (TTL Inputs) Pad to I1, I2 Pad to I1, I2 via transparent latch, no delay with delay TPID TPLI TPDLI All devices All devices XC4005E XC4005E XC4010E XC4010E XC4013E XC4013E XC4025E XC4025E 3.0 6.0 12.0 12.2 12.6 15.0 ns ns ns ns ns ns TIKRI TIKLI All devices All devices 6.8 7.3 ns ns TIKPI TIKPID All devices All devices Propagation Delays Clock (IK) to I1, I2 (flip-flop) Clock (IK) to I1, I2 (latch enable, active Low) Hold Times (Note 1) Pad to Clock (IK), no delay with delay Note 1: Note 2: 0 0 ns ns Input pad setup and hold times are specified with respect to the internal clock (IK). For setup and hold times with respect to the clock input pin, see the pin-to-pin parameters in the Guaranteed Input and Output Parameters table. Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the internal pullup (default) or pull-down resistor, or configured as a driven output, or can be driven from an external source. November 21, 1997 (Version 1.3) 8-23 XC4000E XC4000E High-Reliability Field Programmable Gate Arrays XC4000E XC4000E IOB Input Switching Characteristic Guidelines (continued) Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605 MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all XC4000E XC4000E devices unless otherwise noted. Description Setup Times (TTL Inputs) Pad to Clock (IK), no delay with delay (TTL or CMOS) Clock Enable (EC) to Clock (IK), no delay with delay Global Set/Reset (Note 3) Delay from GSR net through Q to I1, I2 GSR width GSR inactive to first active Clock (IK) edge Symbol Note 3: 8-24 Max Units All devices XC4005E XC4005E XC4010E XC4010E XC4013E XC4013E XC4025E XC4025E 4.0 10.9 11.3 11.8 14.0 ns ns ns ns ns ns ns ns ns TECIK TECIKD All devices XC4005E XC4005E XC4010E XC4010E XC4013E XC4013E XC4025E XC4025E 3.5 10.4 10.7 11.1 14.0 ns ns ns ns ns TRRI XC4005E XC4005E XC4010E XC4010E XC4013E XC4013E XC4025E XC4025E XC4005E XC4005E XC4010E XC4010E XC4013E XC4013E XC4025E XC4025E XC4005E XC4005E XC4010E XC4010E XC4013E XC4013E XC4025E XC4025E TRPO Note 2: -4 Min TPICK TPICKD TMRW Note 1: Speed Grade Device 12.0 21.0 23.0 29.0 13.0 55.0 70.0 112.0 15.0 20.3 22.0 28.0 ns ns ns ns ns ns ns ns ns ns ns ns Input pad setup and hold times are specified with respect to the internal clock (IK). For setup and hold times with respect to the clock input pin, see the pin-to-pin parameters in the Guaranteed Input and Output Parameters table. Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the internal pullup (default) or pull-down resistor, or configured as a driven output, or can be driven from an external source. Timing is based on the XC4005E XC4005E. For other devices see the static timing analyzer. November 21, 1997 (Version 1.3) XC4000E XC4000E IOB Output Switching Characteristic Guidelines Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605 MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all XC4000E XC4000E devices unless otherwise noted. Description Propagation Delays (TTL Output Levels) Clock (OK) to Pad, fast slew-rate limited Output (O) to Pad, fast slew-rate limited 3-state to Pad hi-Z (slew-rate independent) 3-state to Pad active and valid, fast slew-rate limited Note 1: Note 2: Speed Grade Symbol -4 Min Max Units TOKPOF TOKPOS TOPF TOPS TTSHZ 7.5 11.5 8.0 12.0 10.0 ns ns ns ns ns TTSONF TTSONS 10.0 13.7 ns ns Output timing is measured at pin threshold, with 50pF external capacitive loads (incl. test fixture). Slew-rate limited output rise/fall times are approximately two times longer than fast output rise/fall times. For the effect of capacitive loads on ground bounce, see the "Additional XC4000 XC4000 Data" section of the Programmable Logic Data Book. Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the internal pullup (default) or pull-down resistor, or configured as a driven output, or can be driven from an external source. November 21, 1997 (Version 1.3) 8-25 XC4000E XC4000E High-Reliability Field Programmable Gate Arrays XC4000E XC4000E IOB Output Switching Characteristic Guidelines (continued) Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605 MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). For Propagation Delays, slew-rate = fast unless otherwise noted. Values apply to all XC4000E XC4000E devices unless otherwise noted. Description Setup and Hold Output (O) to clock (OK) setup time Output (O) to clock (OK) hold time Clock Clock High Clock Low Note 1: Note 2: Note 3: 8-26 Symbol Speed Grade Device -4 Min Max Units TOOK TOKO 5.0 0 ns ns TCH TCL 4.5 4.5 ns ns Output timing is measured at pin threshold, with 50pF external capacitive loads (incl. test fixture). Slew-rate limited output rise/fall times are approximately two times longer than fast output rise/fall times. For the effect of capacitive loads on ground bounce, see the "Additional XC4000 XC4000 Data" section of the Programmable Logic Data Book. Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the internal pullup (default) or pull-down resistor, or configured as a driven output, or can be driven from an external source. Timing is based on the XC4005E XC4005E. For other devices see the static timing analyzer. November 21, 1997 (Version 1.3) XC4000E XC4000E High-Reliability Field Programmable Gate Arrays November 21, 1997 (Version 1.3) 8 Device-Specific Pinout Tables Pin Locations for XC4005E XC4005E Devices XC4005E XC4005E Pad Name VCC I/O (A8) I/O (A9) I/O I/O I/O (A10) I/O (A11) I/O I/O GND I/O (A12) I/O (A13) I/O I/O I/O (A14) I/O, SGCK1 (A15) VCC GND I/O, PGCK1 (A16) I/O (A17) I/O I/O I/O, TDI I/O, TCK GND I/O I/O I/O, TMS I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O, SGCK2 O (M1) GND I (M0) VCC I (M2) I/O, PGCK2 PG 156 H3 H1 G1 G2 G3 F1 F2 E1 E2 F3 E3 C1 C2 D3 B1 B2 C3 C4 B3 A1 A2 C5 B4 A3 C6 B5 B6 A5 C7 B7 A6 A7 A8 C8 B8 C9 B9 A9 B10 C10 A10 A11 B11 C11 B12 A13 A14 C12 B13 B14 A15 C13 A16 C14 B15 B16 CB 164 P145 P146 P147 P148 P149 P150 P151 P152 P153 P154 P157 P158 P160 P161 P162 P163 P164 P1 P2 P3 P4 P5 P7 P8 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P26 P27 P28 P29 P30 P32 P33 P34 P35 P37 P38 P39 P40 P41 P42 P43 P44 Bndry Scan 44 47 50 53 56 59 62 65 68 71 74 77 80 83 86 89 92 95 98 101 104 107 110 113 116 119 122 125 128 131 134 137 140 143 146 149 152 155 158 161 164 167 170 173 174 175 November 21, 1997 (Version 1.3) XC4005E XC4005E Pad Name I/O (HDC) I/O I/O I/O I/O (LDC) GND I/O I/O I/O I/O I/O I/O I/O I/O (INIT) VCC GND I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O, SGCK3 GND DONE VCC PROGRAM I/O (D7) I/O, PGCK3 I/O I/O I/O (D6) I/O GND I/O I/O I/O (D5) I/O (CS0) I/O I/O I/O (D4) I/O VCC GND I/O (D3) I/O (RS) I/O I/O PG 156 D14 C15 D15 E14 C16 F14 F15 E16 F16 G14 G15 G16 H16 H15 H14 J14 J15 J16 K16 K15 K14 L16 M16 L15 L14 P16 M14 N15 P15 N14 R16 P14 R15 P13 R14 T16 T15 R13 P12 T14 T13 P11 R11 T11 T10 P10 R10 T9 R9 P9 R8 P8 T8 T7 T6 R7 CB 164 P45 P46 P48 P49 P50 P53 P54 P55 P56 P57 P58 P59 P60 P61 P62 P63 P64 P65 P66 P67 P68 P69 P70 P71 P72 P75 P76 P77 P78 P79 P80 P81 P82 P83 P84 P85 P86 P87 P89 P90 P91 P94 P95 P96 P97 P98 P99 P100 P101 P102 P103 P104 P105 P106 P107 P108 Bndry Scan 178 181 184 187 190 193 196 199 202 205 208 211 214 217 220 223 226 229 232 235 238 241 244 247 250 253 256 259 262 265 268 271 274 277 280 283 286 289 292 295 298 301 304 307 310 XC4005E XC4005E Pad Name I/O (D2) I/O I/O I/O GND I/O (D1) I/O (RCLK, RDY/BUSY) I/O I/O I/O (D0, DIN) I/O, SGCK4 (DOUT) CCLK VCC O, TDO GND I/O (A0, WS) I/O, PGCK4 (A1) I/O I/O I/O (CS1, A2) I/O (A3) GND I/O I/O I/O (A4) I/O (A5) I/O I/O I/O (A6) I/O (A7) GND 8/13/97 PG 156 P7 T5 R6 T4 P6 T3 P5 CB 164 P109 P110 P111 P112 P113 P115 P116 Bndry Scan 313 316 319 322 325 328 R4 R3 P4 T2 P117 P119 P120 P121 331 334 337 340 R2 P3 T1 N3 R1 P2 N2 M3 P1 N1 L3 L2 L1 K3 K2 K1 J1 J2 J3 H2 P122 P123 P124 P125 P126 P127 P128 P130 P131 P132 P135 P136 P137 P138 P139 P140 P141 P142 P143 P144 0 2 5 8 11 14 17 20 23 26 29 32 35 38 41 - Additional XC4005E XC4005E Package Pins PG156 PG156 A4 D16 M15 T12 8/14/97 N.C. Pins A12 D1 E15 M1 N16 R5 - D2 M2 R12 - N.C. Pins P9 P25 P47 P51 P74 P88 P114 P118 P134 P155 - P31 P52 P92 P129 P156 - CB164 CB164 P6 P36 P73 P93 P133 P159 8/14/97 8-27 XC4000E XC4000E High-Reliability Field Programmable Gate Arrays Pin Locations for XC4010E XC4010E Devices XC4010E XC4010E Pad Name VCC I/O (A8) I/O (A9) I/O (19) I/O (18) I/O I/O I/O (A10) I/O (A11) I/O I/O GND I/O I/O I/O I/O I/O (A12) I/O (A13) I/O I/O I/O (A14) I/O, SGCK1 (A15) VCC GND I/O, PGCK1 (A16) I/O (A17) I/O I/O I/O, TDI I/O, TCK I/O I/O I/O I/O GND I/O I/O I/O, TMS I/O I/O I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O 8-28 PG 191 J4 J3 J2 J1 H1 H2 H3 G1 G2 F1 E1 G3 F2 D1 C1 E2 F3 D2 B1 E3 C2 B2 D3 D4 C3 C4 B3 C5 A2 B4 C6 A3 B5 B6 C7 A4 A5 B7 A6 C8 A7 B8 A8 B9 C9 D9 D10 C10 B10 A9 A10 A11 C11 B11 A12 B12 A13 C12 B13 A14 A15 C13 CB 196 P183 P184 P185 P186 P187 P188 P189 P190 P191 P192 P193 P194 P195 P196 P197 P198 P199 P200 P201 P202 P203 P204 P205 P1 P2 P3 P4 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 P34 P35 P36 P37 P38 P39 P40 Bndry Scan 62 65 68 71 74 77 80 83 86 89 92 95 98 101 104 107 110 113 116 119 122 125 128 131 134 137 140 143 146 149 152 155 158 161 164 167 170 173 176 179 182 185 188 191 194 197 200 203 206 209 212 215 218 221 XC4010E XC4010E Pad Name I/O I/O I/O I/O I/O I/O, SGCK2 O (M1) GND I (M0) VCC I (M2) I/O, PGCK2 I/O (HDC) I/O I/O I/O I/O (LDC) I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O (INIT) VCC GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O, SGCK3 GND DONE VCC PROGRAM I/O (D7) I/O, PGCK3 I/O PG 191 B14 A16 B15 C14 A17 B16 C15 D15 A18 D16 C16 B17 E16 C17 D17 B18 E17 F16 C18 D18 F17 G16 E18 F18 G17 G18 H16 H17 H18 J18 J17 J16 J15 K15 K16 K17 K18 L18 L17 L16 M18 M17 N18 P18 M16 N17 R18 T18 P17 N16 T17 R17 P16 U18 T16 R16 U17 R15 V18 T15 U16 T14 CB 196 P41 P42 P43 P44 P45 P46 P47 P48 P49 P50 P51 P52 P53 P55 P56 P57 P58 P59 P60 P61 P62 P63 P64 P65 P66 P67 P68 P69 P70 P71 P72 P73 P74 P75 P76 P77 P78 P79 P80 P81 P82 P83 P84 P85 P86 P87 P88 P89 P90 P91 P92 P93 P94 P95 P96 P97 P98 P99 P100 P101 P102 P104 Bndry Scan 224 227 230 233 236 239 242 245 246 247 250 253 256 259 262 265 268 271 274 277 280 283 286 289 292 295 298 301 304 307 310 313 316 319 322 325 328 331 334 337 340 343 346 349 352 355 358 361 364 367 370 373 XC4010E XC4010E Pad Name I/O I/O (D6) I/O I/O I/O I/O I/O GND I/O I/O I/O (D5) I/O (CS0) I/O I/O I/O I/O I/O (D4) I/O VCC GND I/O (D3) I/O (RS) I/O I/O I/O I/O I/O (D2) I/O I/O I/O GND I/O I/O I/O I/O I/O (D1) I/O (RCLK, RDY/BUSY) I/O I/O I/O (D0, DIN) I/O, SGCK4 (DOUT) CCLK VCC O, TDO GND I/O (A0, WS) I/O, PGCK4 (A1) I/O I/O I/O (CS1, A2) I/O (A3) I/O I/O I/O I/O GND I/O I/O I/O (A4) I/O (A5) I/O PG 191 U15 V17 V16 T13 U14 V15 V14 T12 U13 V13 U12 V12 T11 U11 V11 V10 U10 T10 R10 R9 T9 U9 V9 V8 U8 T8 V7 U7 V6 U6 T7 V5 V4 U5 T6 V3 V2 CB 196 P105 P106 P107 P108 P109 P110 P111 P112 P113 P114 P115 P116 P117 P118 P119 P120 P121 P122 P123 P124 P125 P126 P127 P128 P129 P130 P131 P132 P133 P134 P135 P136 P137 P138 P139 P140 P141 Bndry Scan 376 379 382 385 388 391 394 397 400 403 406 409 412 415 418 421 424 427 430 433 436 439 442 445 448 451 454 457 460 463 466 469 472 U4 T5 U3 T4 P142 P143 P144 P145 475 478 481 484 V1 R4 U2 R3 T3 U1 P3 R2 T2 N3 P2 T1 R1 N2 M3 P1 N1 M2 M1 L3 P146 P147 P148 P149 P150 P151 P153 P154 P155 P156 P157 P158 P159 P160 P161 P162 P163 P164 P165 P166 0 2 5 8 11 14 17 20 23 26 29 32 35 38 41 44 November 21, 1997 (Version 1.3) XC4010E XC4010E Pad Name I/O I/O I/O I/O (A6) I/O (A7) GND 8/14/97 PG 191 L2 L1 K1 K2 K3 K4 CB 196 P167 P168 P169 P170 P171 P172 Bndry Scan 47 50 53 56 59 - Additional XC4010E XC4010E Package Pins CB196 CB196 P5 P192 8/14/97 N.C. Pins P54 P103 - P152 - Pin Locations for XC4013E XC4013E Devices XC4013E XC4013E Pad Name VCC I/O (A8) I/O (A9) I/O I/O I/O I/O I/O (A10) I/O (A11) VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O (A12) I/O (A13) I/O I/O I/O I/O I/O (A14) I/O, SGCK1 (A15) VCC GND I/O, PGCK1(A16) I/O (A17) I/O I/O I/O, TDI I/O, TCK I/O I/O I/O I/O I/O I/O GND I/O I/O I/O, TMS I/O I/O I/O I/O I/O I/O PG 223 J4 J3 J2 J1 H1 H2 H3 G1 G2 H4 G4 F1 E1 G3 F2 D1 C1 E2 F3 D2 F4 E4 B1 E3 C2 B2 D3 D4 C3 C4 B3 C5 A2 B4 C6 A3 B5 B6 D5 D6 C7 A4 A5 B7 A6 D7 D8 C8 A7 B8 CB 228 P201 P202 P203 P204 P205 P206 P207 P208 P209 P210 P211 P212 P213 P214 P215 P216 P217 P218 P219 P220 P221 P222 P223 P224 P225 P226 P227 P228 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 Bndry Scan 74 77 80 83 86 89 92 95 98 101 104 107 110 113 116 119 122 125 128 131 134 137 140 143 146 149 152 155 158 161 164 167 170 173 176 179 182 185 188 191 194 197 200 203 206 November 21, 1997 (Version 1.3) XC4013E XC4013E Pad Name I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O, SGCK2 O (M1) GND I (M0) VCC I (M2) I/O, PGCK2 I/O (HDC) I/O I/O I/O I/O (LDC) I/O I/O I/O I/O I/O I/O GND I/O I/O PG 223 A8 B9 C9 D9 D10 C10 B10 A9 A10 A11 C11 D11 D12 B11 A12 B12 A13 C12 D13 D14 B13 A14 A15 C13 B14 A16 B15 C14 A17 B16 C15 D15 A18 D16 C16 B17 E16 C17 D17 B18 E17 F16 C18 D18 F17 E15 F15 G16 E18 F18 CB 228 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 P34 P35 P36 P37 P38 P39 P40 P41 P42 P43 P44 P45 P46 P47 P48 P49 P50 P51 P52 P53 P54 P55 P56 P57 P58 P59 P60 P61 P62 P63 P64 P65 P66 P67 P68 P69 P70 P71 P72 P73 P74 Bndry Scan 209 212 215 218 221 224 227 230 233 236 239 242 245 248 251 254 257 260 263 266 269 272 275 278 281 284 287 290 293 294 295 298 301 304 307 310 313 316 319 322 325 328 331 334 XC4013E XC4013E Pad Name I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O (INIT) VCC GND I/O I/O I/O I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O, SGCK3 GND DONE VCC PROGRAM I/O (D7) I/O, PGCK3 I/O I/O I/O I/O I/O (D6) I/O I/O PG 223 G17 G18 H16 H17 G15 H15 H18 J18 J17 J16 J15 K15 K16 K17 K18 L18 L17 L16 L15 M15 M18 M17 N18 P18 M16 N15 P15 N17 R18 T18 P17 N16 T17 R17 P16 U18 T16 R16 U17 R15 V18 T15 U16 T14 U15 R14 R13 V17 V16 T13 CB 228 P75 P76 P77 P78 P79 P80 P81 P82 P83 P84 P85 P86 P87 P88 P89 P90 P91 P92 P93 P94 P95 P96 P97 P98 P99 P100 P101 P102 P103 P104 P105 P106 P107 P108 P109 P110 P111 P112 P113 P114 P115 P116 P117 P118 P119 P120 P121 P122 P123 P124 P125 Bndry Scan 337 340 343 346 349 352 355 358 361 364 367 370 373 376 379 382 385 388 391 394 397 400 403 406 409 412 415 418 421 424 427 430 433 436 439 442 445 448 451 454 457 460 463 8-29 XC4000E XC4000E High-Reliability Field Programmable Gate Arrays XC4013E XC4013E Pad Name I/O I/O I/O GND I/O I/O I/O I/O I/O (D5) I/O (CS0) I/O I/O I/O I/O I/O (D4) I/O VCC GND I/O (D3) I/O (RS) I/O I/O I/O I/O I/O (D2) I/O VCC PG 223 U14 V15 V14 T12 R12 R11 U13 V13 U12 V12 T11 U11 V11 V10 U10 T10 R10 R9 T9 U9 V9 V8 U8 T8 V7 U7 - CB 228 P126 P127 P128 P129 P130 P131 P132 P133 P134 P135 P136 P137 P138 P139 P140 P141 P142 P143 P144 P145 P146 P147 P148 P149 P150 P151 P152 Bndry Scan 466 469 472 475 478 481 484 487 490 493 496 499 502 505 508 511 514 517 520 523 526 529 532 - XC4013E XC4013E Pad Name I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O (D1) I/O (RCLK, RDY/BUSY) I/O I/O I/O (D0, DIN) I/O, SGCK4 (DOUT) CCLK VCC O, TDO GND I/O (A0, WS) I/O, PGCK4 (A1) I/O I/O PG 223 V6 U6 R8 R7 T7 R6 R5 V5 V4 U5 T6 V3 V2 CB 228 P153 P154 P155 P156 P157 P158 P159 P160 P161 P162 P163 P164 P165 Bndry Scan 535 538 541 544 547 550 553 556 559 562 565 568 U4 T5 U3 T4 P166 P167 P168 P169 571 574 577 580 V1 R4 U2 R3 T3 U1 P3 R2 P170 P171 P172 P173 P174 P175 P176 P177 0 2 5 8 11 CB 228 P223 P224 P225 P226 P227 P228 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 - PG 299 C2 F5 E4 D3 C3 A2 B1 D4 B2 B3 E6 D5 C4 A3 D6 E7 B4 C5 A4 D7 C6 E8 B5 A5 B6 D8 C7 B7 A6 C8 Bndry Scan 179 182 185 188 191 194 197 200 203 206 209 212 215 218 221 224 227 230 233 236 239 242 245 248 251 254 XC4013E XC4013E Pad Name I/O (CS1, A2) I/O (A3) I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VCC I/O (A4) I/O (A5) I/O I/O I/O I/O I/O (A6) I/O (A7) GND 8/14/97 PG 223 T2 N3 P4 N4 P2 T1 R1 N2 M3 P1 N1 M4 L4 M2 M1 L3 L2 L1 K1 K2 K3 K4 CB 228 P178 P179 P180 P181 P182 P183 P184 P185 P186 P187 P188 P189 P190 P191 P192 P193 P194 P195 P196 P197 P198 P199 P200 Bndry Scan 14 17 20 23 26 29 32 35 38 41 44 47 50 53 56 59 62 65 68 71 - XC4025E XC4025E Pad Name CB 228 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 P34 P35 P36 P37 P38 P39 P40 P41 PG 299 E9 A7 D9 B8 A8 C9 B9 E10 A9 D10 C10 A10 A11 B10 B11 C11 E11 D11 A12 B12 A13 C12 D12 E12 B13 A16 A14 C13 B14 D13 Bndry Scan 257 260 263 266 269 272 275 278 281 284 287 290 293 296 299 302 305 308 311 314 317 320 323 326 329 332 335 Pin Locations for XC4025E XC4025E Devices XC4025E XC4025E Pad Name VCC I/O (A8) I/O (A9) I/O I/O I/O I/O I/O (A10) I/O (A11) I/O I/O I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O (A12) I/O (A13) I/O I/O I/O 8-30 CB 228 P201 P202 P203 P204 P205 P206 P207 P208 P209 P210 P211 P212 P213 P214 P215 P216 P217 P218 P219 P220 P221 P222 PG 299 K1 K2 K3 K5 K4 J1 J2 H1 J3 J4 J5 H2 G1 E1 H3 G2 H4 F2 F1 H5 G3 D1 G4 E2 F3 G5 C1 F4 E3 D2 Bndry Scan 98 101 104 107 110 113 116 119 122 125 128 131 134 137 140 143 146 149 152 155 158 161 164 167 170 173 176 XC4025E XC4025E Pad Name I/O I/O I/O I/O (A14) I/O, SGCK1 (A15) VCC GND I/O, PGCK1 (A16) I/O (A17) I/O I/O I/O, TDI I/O, TCK I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O, TMS I/O VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O November 21, 1997 (Version 1.3) XC4025E XC4025E Pad Name GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O, SGCK2 O (M1) GND I (M0) VCC I (M2) I/O, PGCK2 I/O (HDC) I/O I/O I/O I/O (LDC) I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O (INIT) VCC GND I/O I/O I/O I/O I/O I/O CB 228 P42 P43 P44 P45 P46 P47 P48 P49 P50 P51 P52 P53 P54 P55 P56 P57 P58 P59 P60 P61 P62 P63 P64 P65 P66 P67 P68 P69 P70 P71 P72 P73 P74 P75 P76 P77 P78 P79 P80 P81 P82 P83 P84 P85 P86 P87 P88 P89 P90 P91 P92 PG 299 A15 B15 E13 C14 A17 D14 B16 C15 E14 A18 D15 C16 B17 B18 E15 D16 C17 A20 A19 C18 B20 D17 B19 C19 F16 E17 D18 C20 F17 G16 D19 E18 D20 G17 F18 H16 E19 F19 E20 H17 G18 G19 H18 VCC* J16 G20 J17 H19 H20 J18 J19 K16 J20 K17 K18 K19 L20 K20 L19 L18 L16 L17 M20 M19 Bndry Scan 338 341 344 347 350 353 356 359 362 365 368 371 374 377 380 383 386 389 390 391 394 397 400 403 406 409 412 415 418 421 424 427 430 433 436 439 442 445 448 451 454 457 460 463 466 469 472 475 478 481 484 487 490 493 496 499 502 November 21, 1997 (Version 1.3) XC4025E XC4025E Pad Name I/O I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O, SGCK3 GND DONE VCC PROGRAM I/O (D7) I/O, PGCK3 I/O I/O I/O I/O I/O I/O I/O (D6) I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VCC I/O (D5) I/O (CS0) I/O I/O I/O I/O I/O I/O I/O I/O CB 228 P93 P94 P95 P96 P97 P98 P99 P100 P101 P102 P103 P104 P105 P106 P107 P108 P109 P110 P111 P112 P113 P114 P115 P116 P117 P118 P119 P120 P121 P122 P123 P124 P125 P126 P127 P128 P129 P130 P131 P132 P133 P134 P135 P136 P137 P138 P139 PG 299 N20 M18 M17 M16 N19 P20 T20 N18 P19 N17 R19 R20 N16 P18 U20 P17 T19 R18 P16 V20 R17 T18 U19 V19 R16 T17 U18 X20 W20 V18 X19 U17 W19 W18 T15 U16 V17 X18 U15 T14 W17 V16 X17 U14 V15 T13 W16 W15 X16 U13 V14 W14 V13 X15 T12 X14 U12 W13 X13 V12 W12 T11 X12 U11 Bndry Scan 505 508 511 514 517 520 523 526 529 532 535 538 541 544 547 550 553 556 559 562 565 568 571 574 577 580 583 586 589 592 595 598 601 604 607 610 613 616 619 622 625 628 631 634 637 640 643 646 649 652 655 658 661 664 667 670 XC4025E XC4025E Pad Name I/O (D4) I/O VCC GND I/O (D3) I/O (RS) I/O I/O I/O I/O I/O I/O I/O I/O I/O (D2) I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O (D1) I/O (RCLK, RDY/BUSY) I/O I/O I/O I/O I/O (D0, DIN) I/O, SGCK4 (DOUT) CCLK VCC O, TDO GND I/O (A0, WS) I/O, PGCK4 (A1) I/O I/O I/O (CS1, A2) I/O (A3) I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O CB 228 P140 P141 P142 P143 P144 P145 P146 P147 P148 P149 P150 P151 P152 P153 P154 P155 P156 P157 P158 P159 P160 P161 P162 P163 P164 P165 PG 299 V11 W11 X10 X11 W10 V10 T10 U10 X9 W9 X8 V9 U9 T9 W8 X7 X5 V8 W7 U8 W6 X6 T8 V7 X4 U7 W5 V6 T7 X3 U6 V5 Bndry Scan 673 676 679 682 685 688 691 694 697 700 703 706 709 712 715 718 721 724 727 730 733 736 739 742 745 748 751 754 P166 P167 P168 P169 W4 W3 T6 U5 V4 X1 757 760 763 766 769 772 P170 P171 P172 P173 P174 P175 P176 P177 P178 P179 P180 P181 P182 P183 P184 P185 P186 P187 P188 P189 V3 VCC* U4 GND* W2 V2 R5 T4 U3 V1 R4 P5 U2 T3 U1 P4 R3 N5 T2 R2 T1 N4 P3 P2 0 2 5 8 11 14 17 20 23 26 29 32 35 38 41 44 47 50 53 56 8-31 XC4000E XC4000E High-Reliability Field Programmable Gate Arrays XC4025E XC4025E Pad Name I/O VCC I/O I/O I/O I/O I/O (A4) I/O (A5) I/O I/O I/O I/O I/O (A6) I/O (A7) GND 8/14/97 8-32 CB 228 P190 P191 P192 P193 P194 P195 P196 P197 P198 P199 P200 PG 299 N3 R1 M5 P1 M4 N2 N1 M3 M2 L5 M1 L4 L3 L2 L1 Bndry Scan 59 62 65 68 71 74 77 80 83 86 89 92 95 - November 21, 1997 (Version 1.3) Ordering Information Example for SMD Part: 5962-97523 01 Q X C Generic Standard Microcircuit Drawing (SMD) Prefix Device Type XC4005E XC4005E = 97522 XC4010E XC4010E = 97523 XC4013E XC4013E = 97524 XC4025E XC4025E = 97525 Lead Finish C = Gold Package Type X = Pin Grid Y = Quad Flatpack (Base Mark) Z = Quad Flatpack (Lid Mark) QML Certified Speed Grade 01 = -4 Example for XC4010E XC4010E -4 PG 191 M Military Tempeture Only Part: Device Type XC4005E XC4005E XC4010E XC4010E XC4013E XC4013E XC4025E XC4025E Speed Grade November 21, 1997 (Version 1.3) Temperature Range M = Military (TC = -55o C to +125o C) Number of Pins Package Type CB = Top Braxed Ceramic Quad Flat Pack PG = Ceramic Pin Grid Array 8-33