XC2064 XC3090 XC4005 XC-DS501 XC4000XL XC4000XV XC9500 XC9536 XC9572 XC95108 - Datasheet Archive

 

Programmable Logic Data Book April 1998 R , XILINX, XACT, XC2064, XC3090, XC4005, XC-DS501, FPGA Architect, FPGA Foundry, NeoCAD,

 

The Programmable Logic Data Book April 1998 R , XILINX, XACT, XC2064 XC2064, XC3090 XC3090, XC4005 XC4005, XC-DS501 XC-DS501, FPGA Architect, FPGA Foundry, NeoCAD, NeoCAD EPIC, NeoCAD PRISM, NeoROUTE, Plus Logic, Plustran, P+, Timing Wizard, and TRACE are registered trademarks of Xilinx, Inc. , all XC-prefix product designations, XACTstep, XACTstep Advanced, XACTstep Foundry, XACT-Floorplanner, XACT-Performance, XAPP, XAM, X-BLOX, X-BLOX plus, XChecker, XDM, XDS, XEPLD, XPP, XSI, Foundation Series, BITA, Configurable Logic Cell, CLC, Dual Block, FastCLK, FastCONNECT, FastFLASH, FastMap, HardWire, LCA, Logic Cell, LogiCore, LogicProfessor, MicroVia, PLUSASM, PowerGuide, PowerMaze, Select-RAM, SMARTswitch, TrueMap, UIM, VectorMaze, VersaBlock, VersaRing, Spartan, Spartan-XL and ZERO+ are trademarks of Xilinx, Inc. The Programmable Logic Company and The Programmable Gate Array Company are service marks of Xilinx, Inc. All other trademarks are the property of their respective owners. Xilinx does not assume any liability arising out of the application or use of any product described or shown herein; nor does it convey any license under its patents, copyrights, or maskwork rights or any rights of others. Xilinx reserves the right to make changes, at any time, in order to improve reliability, function or design and to supply the best product possible. Xilinx will not assume responsibility for the use of any circuitry described herein other than circuitry entirely embodied in its products. Xilinx devices and products are protected under one or more of the following U.S. Patents: 4,642,487; 4,695,740; 4,706,216; 4,713,557; 4,746,822; 4,750,155; 4,758,985; 4,820,937; 4,821,233; 4,835,418; 4,853,626; 4,855,619; 4,855,669; 4,902,910; 4,940,909; 4,967,107; 5,012,135; 5,023,606; 5,028,821; 5,047,710; 5,068,603; 5,140,193; 5,148,390; 5,155,432; 5,166,858; 5,224,056; 5,243,238; 5,245,277; 5,267,187; 5,291,079; 5,295,090; 5,302,866; 5,319,252; 5,319,254; 5,321,704; 5,329,174; 5,329,181; 5,331,220; 5,331,226; 5,332,929; 5,337,255; 5,343,406; 5,349,248; 5,349,249; 5,349,250; 5,349,691; 5,357,153; 5,360,747; 5,361,229; 5,362,999; 5,365,125; 5,367,207; 5,386,154; 5,394,104; 5,399,924; 5,399,925; 5,410,189; 5,410,194; 5,414,377; 5,422,833; 5,426,378; 5,426,379; 5,430,687; 5,432,719; 5,448,181; 5,448,493; 5,450,021; 5,450,022; 5,453,706; 5,466,117; 5,469,003; 5,475,253; 5,477,414; 5,481,206; 5,483,478; 5,486,707; 5,486,776; 5,488,316; 5,489,858; 5,489,866; 5,491,353; 5,495,196; 5,498,979; 5,498,989; 5,499,192; 5,500,608; 5,500,609; 5,502,000; 5,502,440; RE 34,363, RE 34,444, and RE 34,808. Other U.S. and foreign patents pending. Xilinx, Inc. does not represent that devices shown or products described herein are free from patent infringement or from any other third party right. Xilinx assumes no obligation to correct any errors contained herein or to advise any user of this text of any correction if such be made. Xilinx will not assume any liability for the accuracy or correctness of any engineering or software support or assistance provided to a user. Xilinx products are not intended for use in life support appliances, devices, or systems. Use of a Xilinx product in such applications without the written consent of the appropriate Xilinx officer is prohibited. Copyright 1998 Xilinx, Inc. All Rights Reserved. R The Programmable Logic Data Book Xilinx Home Page (WWW): XDOCS E-mail Document Server: Application Service Centers North America Hotline: Email: United Kingdom Hotline: Fax: Email: France Hotline: Fax: Email: http://www.xilinx.com/ ("Answers" Database, File Download) xdocs@xilinx.com send E-mail with help in the header 1-408-879-5199 (USA, Xilinx headquarters) 1-800-255-7778 (North America) 1-408-879-4442 (FAX) hotline@xilinx.com (44) 1932-820821 (44) 1932-828522 ukhelp@xilinx.com (33) 1-3463-0100 (33) 1-3463-0959 frhelp@xilinx.com Germany Hotline: Fax: Email: (49) 89-93088-130 (49) 89-93088-188 dlhelp@xilinx.com Japan Hotline: Fax: Email: (81) 3-3297-9163 (81) 3-3297-0067 jhotline@xilinx.com Korea Hotline: Fax: Email: (82) 2-761-4277 (82) 2-761-4278 korea@xilinx.com Hong Kong Hotline: Fax: Email: Software Authorization and Licensing: On-Line Authorization: (85) 2-2424-5200 (85) 2-2424-7159 hongkong@xilinx.com 1-800-624-4782 www.xilinx.com 2100 Logic Drive San Jose, California 95124 United States of America Telephone: (408) 559-7778 Fax: (408) 559-7114 On behalf of the employees of Xilinx, our sales representatives, our distributors, and our manufacturing partners, welcome to our 1998 Data Book, and thank you for your interest in Xilinx products and services. As the inventor of Field Programmable Gate Array technology and the world's leading supplier of programmable logic, we would like to pledge our continuing commitment to providing you, our users, with the best possible integrated circuit components, development systems, and technical and sales support. Over the past year, we have substantially enhanced our product line with the introduction of the XC4000XL XC4000XL, XC4000XV XC4000XV, and Spartan series of FPGAs, as well as XH3 FpgASIC Hardwire technology. We have continued to enhance our leading-edge products with new speed grades and improved pricing. The Alliance and Foundation series products have set a new standard for functionality and ease-of-use in programmable logic development systems. You can expect this pace of innovation to continue, and even increase, as we maintain our leadership role in bringing leading-edge programmable logic solutions to the market. We look forward to satisfying all of your programmable logic needs. Sincerely, Wim Roelandts Chief Executive Officer ® Section Titles 1 Introduction 2 Development System Products and CORE Solutions Products 3 CPLD Products 4 FPGA Products 5 SPROM Products 6 3V Products 7 HardWire FpgASIC Products 8 High-Reliability and QML Military Products 9 Programming Support 10 Packages and Thermal Characteristics 11 Testing, Quality, and Reliability 12 Technical Support and Services 13 Product Technical Information 14 Index ® Table of Contents Introduction An Introduction to Xilinx Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 Development System Products and CORE Solutions Products Development Systems: Products Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 Development Systems: Product Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 CORE Solutions Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13 CPLD Products XC9500 XC9500 Series Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 XC9500 XC9500 In-System Programmable CPLD Family. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 XC9536 XC9536 In-System Programmable CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21 XC9572 XC9572 In-System Programmable CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-29 XC95108 XC95108 In-System Programmable CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-37 XC95144 XC95144 In-System Programmable CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-45 XC95216 XC95216 In-System Programmable CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-55 XC95288 XC95288 In-System Programmable CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-65 FPGA Products XC4000E XC4000E and XC4000X XC4000X Series Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 XC4000E XC4000E and XC4000X XC4000X Series Field Programmable Gate Arrays . . . . . . . . . . . . . . . . . . 4-5 XC4000XV XC4000XV Family Field Programmable Gate Arrays . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-155 XC4000XLT XC4000XLT Family Field Programmable Gate Arrays . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-175 Spartan and Spartan-XL Families Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-187 Spartan and Spartan-XL Families Field Programmable Gate Arrays . . . . . . . . . . . . . . . 4-189 XC5200 XC5200 Series Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-243 XC5200 XC5200 Series Field Programmable Gate Arrays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-247 XC3000 XC3000 Series Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-319 XC3000 XC3000 Series Field Programmable Gate Arrays (XC3000A/L XC3000A/L, XC3100A/L XC3100A/L). . . . . . . . . . 4-321 SPROM Products XC1701L XC1701L (3.3V), XC1701 XC1701 (5.0V) and XC17512L XC17512L (3.3V) Serial Configuration PROMs . . . 5-1 XC1700E XC1700E Family of Serial Configuration PROMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 Spartan and Spartan-XL Families of Serial Configuration PROMs . . . . . . . . . . . . . . . . . 5-23 3V Products 3.3 V and Mixed Voltage Compatible Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 HardWire FpgASIC Products Xilinx HardWireTM FpgASIC Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 High-Reliability and QML Military Products High-Reliability and QML Military Products. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 XC4000X XC4000X Series High-Reliability Field Programmable Gate Arrays . . . . . . . . . . . . . . . . 8-7 XC4000E XC4000E High-Reliability Series Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-9 XC4000E XC4000E High-Reliability Field Programmable Gate Arrays . . . . . . . . . . . . . . . . . . . . . . 8-11 Programming Support HW-130 HW-130 Programmer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 Packages and Thermal Characteristics Packages and Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1 Package Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-21 Testing, Quality, and Reliability Quality Assurance and Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1 Technical Support and Services Technical Support And Services . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1 Product Technical Information XC3000 XC3000, XC4000 XC4000, and XC5200 XC5200: A Technical Overview for the First-Time User . . . . . . . 13-5 Choosing a Xilinx Product Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-7 I/O Characteristics of the `XL FPGAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-13 XC4000 XC4000 Series Technical Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-15 XC3000 XC3000 Series Technical Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-19 FPGA Configuration Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-31 Configuring Mixed FPGA Daisy Chains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-39 Configuration Issues: Power-up, Volatility, Security, Battery Back-up . . . . . . . . . . . . . 13-41 Dynamic Reconfiguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-45 Metastable Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-47 Set-up and Hold Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-50 Overshoot and Undershoot. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-51 Boundary Scan in XC4000 XC4000 and XC5200 XC5200 Series Devices . . . . . . . . . . . . . . . . . . . . . . . . . . 13-52 Index Book Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1 ® Introduction 1 Introduction 2 Development System Products and CORE Solutions Products 3 CPLD Products 4 FPGA Products 5 SPROM Products 6 3V Products 7 HardWire FpgASIC Products 8 High-Reliability and QML Military Products 9 Programming Support 10 Packages and Thermal Characteristics 11 Testing, Quality, and Reliability 12 Technical Support and Services 13 Product Technical Information 14 Index ® Introduction Table of Contents An Introduction to Xilinx Products About this Book . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Sheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Book Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . About the Company . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Line Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programmable Logic vs. Gate Arrays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Faster Design and Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Design Changes without Penalty . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Shortest Time-to-Market . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Component Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Field Programmable Gate Arrays (FPGAs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Complex Programmable Logic Devices (CPLDs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HardWire devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial PROMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . High-Reliability Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Development System Products. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Technical Support and Service . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC3000 XC3000 Series Product Selection Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC4000 XC4000 Series Product Selection Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Spartan Series Product Selection Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC5200 XC5200 Series Product Selection Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC9500 XC9500 Series Product Selection Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1-1 1-1 1-2 1-2 1-3 1-3 1-3 1-3 1-3 1-4 1-4 1-4 1-4 1-5 1-5 1-5 1-6 1-6 1-7 1-7 1-8 1 ® November 10, 1997 An Introduction to Xilinx Products 1 1* About this Book This Data Book provides a "snapshot in time" in its listing of IC devices and development system software available from Xilinx as of late 1997. New devices, speed grades, package types and development system products are continually being added to the Xilinx product portfolio. Users are encouraged to contact their local Xilinx sales representative and consult the WebLINX World Wide Web site and the quarterly XCELL newsletter for the latest information regarding new product availability. This book covers the current XC4000E/EX/XL XC4000E/EX/XL, XC4000XV XC4000XV, XC4000XLT XC4000XLT, Spartan, XC5200 XC5200, XC3000A/L XC3000A/L, XC3100A/L XC3100A/L, XC9500 XC9500, XC1700D/L XC1700D/L and XC1701L XC1701L. Chapter 2 contains a discussion of the overall design methodology when using Xilinx programmable logic and descriptions of Xilinx development system products. This chapter is placed at the beginning of the book since these development tools are needed to design with any of the Xilinx programmable logic devices. Chapter 3 contains the product descriptions for the Xilinx Complex Programmable Logic Device (CPLD) products, including the XC9000 XC9000 series. Chapter 4 includes the product descriptions for the Xilinx static-memory-based Field Programmable Gate Array (FPGA) products, including the XC3000 XC3000, XC4000 XC4000, XC5000 XC5000, and Spartan series. The product specifications for several older Xilinx FPGA families are not included in this Data Book. This does not imply that these products are no longer available. However, for new designs, users are encouraged to use the newer products described in this book, which offer better performance at lower cost than the older technologies. Product specifications for the older products are available at WebLINX, the Xilinx site on the World Wide Web, or through your local Xilinx sales representative. Chapter 5 holds the product descriptions for the XC1701L XC1701L and XC1700D XC1700D families of Serial PROM devices. These Serial PROMs provide a convenient, low-cost means of storing configuration programs for the SRAM-based FPGAs described in Chapter 4. Data Sheet Categories Chapter 7 contains a brief overview of the HardWire product line. Detailed product specifications are available in separate Xilinx data sheets. In order to provide the most up-to-date information, some component products included in this book may not have been fully characterized at the time of publication. In these cases, the AC and DC characteristics included in the data sheets will be marked as Advance or Preliminary information. (Not withstanding the definitions of such terms, all specifications are subject to change without notice.) These designations have the following meaning: · · · Advance - Initial estimates based on simulation and/or extrapolation from other speed grades, devices, or device families. Use as estimates, but not for final production. Preliminary - Based on preliminary characterization. Changes are possible, but not expected. Final (unmarked) - Specifications not identified as either Advance or Preliminary are to be considered final. Data Book Contents Chapter 1 is a general overview of the Xilinx product line, and is recommended reading for designers who are new to the field of high-density programmable logic. November 10, 1997 Chapter 6 is an overview of Xilinx components appropriate for 3.3 V and mixed-voltage systems. This chapter will refer you back to the appropriate product descriptions in the earlier chapters. Chapter 8 is an overview of Xilinx High-Reliability/Military products. Detailed product specifications are available in separate Xilinx data sheets. Chapter 9 describes the HW130 HW130 device programmer for the XC170X XC170X series of Serial PROMs and the XC9500 XC9500 series of CPLDs. Chapter 10 contains a description of all the physical packages for the various IC products, including information about the thermal characteristics of those packages. Chapter 11 discusses the testing, quality, and reliability of Xilinx component products. Chapter 12 includes a listing of all the technical support facilities provided by Xilinx. Chapter 13 contains additional information about Xilinx components that is not provided in the product specifications of the earlier chapters. This includes some additional electrical parameters that are not in the product specifications because they are not part of the manufacturing test program for the particular device, but may be of interest to the user. Also included in this chapter is a discussion of the 1-1 An Introduction to Xilinx Products JTAG boundary test scan logic found in several Xilinx component families. The final two sections contain an index to the topics included in this Data Book and a listing of Xilinx sales offices, sales representatives, and distributors. About the Company Xilinx, Inc., offers the industry's broadest selection of programmable logic devices. With 1997 revenues of over $560 million, Xilinx is the world's largest supplier of programmable logic, and the market leader in Field Programmable Gate Arrays (FPGAs). Xilinx was founded in 1984, based on the revolutionary idea of combining the logic density and versatility of gate arrays with the time-to-market advantages and convenience of user-programmable standard parts. One year later, Xilinx introduced the world's first Field Programmable Gate Array. Since then, through a combination of architectural and manufacturing process improvements, the company has continually increased device performance, in terms of capacity, speed, and ease-of-use, while lowering costs. In 1992, Xilinx expanded its product line to include advanced Complex Programmable Logic Devices (CPLDs). For the user, CPLDs are an attractive complement to FPGAs, offering simpler design software and more predictable timing. 1-2 As the market leader in one of the fastest growing segments of the semiconductor industry, Xilinx strategy is to focus its resources on creating new ICs and development system software, providing world-class technical support, developing markets, and building a diverse customer base across a broad range of geographic and end-use application segments. The company has avoided the large capital commitment and overhead burden associated with sole ownership and operation of a wafer fabrication facility. Instead, Xilinx has established alliances with several high-volume, state-of-the-art CMOS IC manufacturers. Using standard, high-volume processes assures low manufacturing costs, produces programmable logic devices with well-established reliability, and provides for early access to advances in CMOS processing technology. Xilinx headquarters are located in San Jose, California. The company markets its products worldwide through a network of direct sales offices, manufacturers' representatives, and distributors (as listed in the back of this book). The company has representatives and distributors in over 38 countries. Product Line Overview Field Programmable Gate Arrays (FPGAs) and Complex Programmable Logic Devices (CPLDs) can be used in virtually any digital logic system. Over 50 million Xilinx components have been used in a wide variety of end-equipment applications, ranging from supercomputers to hand-held November 10, 1997 instruments, from central office switches to centrifuges, and from missile guidance systems to guitar synthesizers. Xilinx achieved its leading position through a continuing commitment to provide a complete product solution. This encompasses a focus on all three critical areas of the high-density programmable solution "triangle": components (silicon), software, and service (Figure 2). Programmable Logic vs. Gate Arrays Xilinx programmable logic devices provide the benefits of high integration levels without the risks or expenses of semi-custom and custom IC development. Some of the benefits of programmable logic versus mask-programmed gate arrays are briefly discussed below. Faster Design and Verification Xilinx FPGAs and CPLDs can be designed and verified quickly while the same process requires several weeks with gate arrays. There are no non-recurring engineering (NRE) costs, no test vectors to generate, and no delay while waiting for prototypes to be manufactured. Design Changes without Penalty Because the devices are software-configured and user-programmed, modifications are much less risky and can be made anytime - in a manner of minutes or hours, as opposed to the weeks it would take with a gate array. This results in significant cost savings in design and production. Shortest Time-to-Market When designing with Xilinx programmable logic, time-to-market is measured in days or a few weeks, not the months often required when using gate arrays. A study by market research firm McKinsey & Co. concluded that a six-month delay in getting to market can cost a product one-third of its lifetime potential profit. With mask-programmed gate arrays, design iterations can easily add that much time, and more, to a product schedule. Once the decision has been made to use Xilinx programmable logic, a choice must be made from a number of product families, device options, and product types. The information in the product selection matrices that follow can help guide that selection; detailed product specifications are available in subsequent chapters of this book. Since many component products are available in common packages with common footprints, designs often can be migrated to higher or lower density devices, or even across some product families, without any printed circuit board changes. Design ideas, represented in text or schematic format, are converted into a configuration data file for an FPGA or CPLD device using the Xilinx XACTstep development software running on a PC or workstation. Component Products Xilinx offers the broadest line of programmable logic devices available today, with hundreds of products featuring various combinations of architectures, logic densities, package types, and speed grades in commercial, industrial, and military grades. This breadth of product offerings allows the selection of the programmable logic device that is best suited for the target application. Xilinx programmable logic offerings include several families of reprogrammable FPGAs and FLASH-memory-based CPLDs (Figure 3). HardWire devices are mask-programmed versions of the reprogrammable FPGAs, and provide a transparent, no-risk migration path to lower-cost devices for high-volume, stable designs. Additionally, a family of Serial PROM devices is available to store configuration programs for the reprogrammable FPGA devices. Many devices are available in military temperature range · Optimized circuits/architectures · Powerful but easy N CO · Seamless integration into customer CAE system RE SI LI WA · Unmatched quality and reliability · Integrated across families FT · Deep submicron processes SO · Highest performance/densities S E RV I C E · Global world class sales/distribution support · Global world class technical support: FAEs/support center/on-line/internet · Global world class manufacturing: quality/capacity/delivery X5955 X5955 Figure 2: The Xilinx Programmable Solution Triangle November 10, 1997 1-3 An Introduction to Xilinx Products and/or MIL-STD-883B MIL-STD-883B versions, for high-reliability and military applications. Field Programmable Gate Arrays (FPGAs) FPGA devices feature a gate-array-like architecture, with a matrix of logic cells surrounded by a periphery of I/O cells, as diagrammed in Figure 4. Segments of metal interconnect can be linked in an arbitrary manner by programmable switches to form the desired signal nets between the cells. FPGAs combine an abundance of logic gates, registers, and I/Os with fast system speed. Xilinx offers several families of reprogrammable, static-memory-based (SRAM-based) FPGAs, including the XC3000 XC3000, XC4000 XC4000, XC5000 XC5000, and XC6000 XC6000 series. ASIC Alternatives Gate Arrays Custom Highest Density ASIC Tools Xilinx Product Line CPLD ISP PAL Architecture Medium Density Simple Tools FPGA Programmable Gate Array Architecture High Density ASIC Tools HardWireTM Custom Transparent Conversion 100% Tested PAL Devices Programmable AND/OR Architecture Low Density Simple Tools Complex Programmable Logic Devices (CPLDs) Designers more comfortable with the speed, design simplicity, and predictability of PALs may prefer CPLD devices. Conceptually, CPLDs consist of multiple PAL-like function blocks that can be interconnected through a switch matrix (Figure 5). The XC9000 XC9000 CPLD series features 5V in-system programmable FLASH technology, and, like most of the FPGA families, includes built-in JTAG boundary scan test logic. HardWire devices HardWire devices are masked-programmed versions of the SRAM-based FPGAs. The HardWire products provide an easy, transparent migration path to a cost-reduced device without the engineering burden associated with conventional gate array re-design. The HardWire gate array is architecturally identical to its FPGA counterpart, but the programmable elements in the FPGA are replaced with fixed metal connections. The resulting die is considerably smaller, with a correspondingly lower cost. Using proprietary automatic test vector generation software and patented test logic, Xilinx guarantees over 95% fault coverage, while eliminating the need for user-generated test vectors. The mask and test programs are generated automatically by Xilinx from the user's existing FPGA design file. Serial PROMs X5957 X5957 The XC1700 XC1700 family features one-time programmable serial PROMs ranging in density from about 18,000 bits to over 260,000 bits. These serial PROMs are an easy-to-use, cost-effective method for storing configuration data for the SRAM-based FPGAs. Figure 3: Application-Specific IC Products PROGRAMMABLE INTERCONNECT I/O BLOCKS X1153 X1153 LOGIC BLOCKS Figure 4: FPGA Architecture 1-4 November 10, 1997 , FB FB FB FB Interconnect Matrix I/O I/O FB FB FB FB X5956 X5956 Figure 5: CPLD Architecture High-Reliability Devices Xilinx was the first company to offer high-reliability FPGAs by introducing MIL-STD-883B MIL-STD-883B qualified XC2000 XC2000 and XC3000 XC3000 series devices in 1989. MIL-STD-883B MIL-STD-883B members of the XC4000 XC4000 FPGA series are currently available, and qualified versions of additional Xilinx families are in development. The product line also includes Standard Microcircuit Drawing (SMD) versions of several families. Some Xilinx devices are available in tested die form through arrangements with manufacturing partners. Development System Products Xilinx offers a complete software environment for the implementation of logic designs in Xilinx programmable logic devices. This environment combines powerful technology with a flexible, easy-to-use graphical interface to help users achieve the best possible designs, regardless of experience level. The user has a wide range of choices between a fully-automatic implementation and detailed involvement in the layout process. The development system provides all the implementation tools required to design with Xilinx logic devices, including the following: · · · · · · forms include the ubiquitous PC and several popular workstations. Technical Support and Service Providing global, world-class manufacturing, technical support, and sales/distribution support is an essential foundation of the Xilinx product strategy. Xilinx manufacturing facilities have earned ISO9002 ISO9002 certification, and Xilinx quality and reliability achievements are among the world's best - not just for programmable logic suppliers, but among all semiconductor companies. Comprehensive technical support facilities include training courses, extensive product documentation and application notes, a quarterly technical newsletter, the WebLINX World Wide Web site, technical support hotlines, and a cadre of Field Application Engineers. Sales support is provided by a worldwide network of representatives and distributors. libraries and interfaces for popular schematic editors, logic synthesis tools, and simulators design manager/flow engine module generator map, place, and route compilation software static timing analyzer hardware debugger Xilinx is committed to an "open system" approach to front-end design creation, synthesis, and verification. Xilinx devices are supported by the broadest number of EDA vendors and synthesis vendors in the industry. Supported plat- November 10, 1997 1-5 An Introduction to Xilinx Products Low Cost/ Low Power XC3190L XC3190L XC3142L XC3142L XC3195A XC3195A XC3190A XC3190A XC3164A XC3164A XC3142A XC3142A XC3130A XC3130A XC3120A XC3120A XC3090A/L XC3090A/L XC3064A/L XC3064A/L XC3042A/L XC3042A/L XC3030A/L XC3030A/L KEY FEATURES XC3000 XC3000 Series XC3020A/L XC3020A/L DEVICES XC3000 XC3000 Series Product Selection Matrix Low Voltage (3.3 V) High Performance High Performance DENSITY Max Logic Gates (K) 1.5 2 3 4.5 6 1.5 2 3 4.5 6 7.5 3 6 Max RAM Bits N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A 1-1.5 1.5-2 2-3 3.5-4.5 5-6 1-1.5 1.5-2 2-3 3.5-4.5 5-6 6.5-7.5 2-3 5-6 CLBs 64 100 144 224 320 64 100 144 224 320 484 144 320 Flip-Flops FEATURES Typical Gate Range (K) 928 256 360 480 688 928 256 360 480 688 928 1320 480 Output Drive (mA) 4 4 4 4 4 8 8 8 8 8 8 4 4 JTAG (IEEE 1149.1) N N N N N N N N N N N N N N N N N N N N N N N N N N 8 8 8 8 8 8 1.5 1.5 -09 -09 -09 -09 -09 -09 -2 -2 Dedicated Arithmetic Quiescent Current (mA) Fastest Speed Grade 0.5/0.02 0.5/0.02 0.5/0.02 0.5/0.02 0.5/0.02 -6/-8 -6/-8 -6/-8 -6/-8 -6/-8 DENSITY FEATURES XC4085XL XC4085XL XC4062XL XC4062XL XC4052XL XC4052XL XC4044XL XC4044XL XC4036EX/XL XC4036EX/XL XC4028EX/XL XC4028EX/XL XC4025E XC4025E XC4020E/XL XC4020E/XL XC4013E/XL XC4013E/XL XC4010E/XL XC4010E/XL XC4008E XC4008E XC4006E XC4006E XC4005E/XL XC4005E/XL XC4003E XC4003E XC4000 XC4000 Series KEY FEATURES DEVICES XC4000 XC4000 Series Product Selection Matrix High Density High Performance Select-RAMTM Memory System Gate Range* (Logic and RAM) (K) Logic Cells Max Logic Gates, (no RAM) (K) Max RAM Bits (no Logic) CLBs Flip-Flops Output Drive (mA) JTAG (IEEE 1149.1) Dedicated Arithmetic Quiescent Current (mA) Fastest Speed Grade 2-5 238 3 3200 100 360 12 Y Y 10 -1 3-9 466 5 6272 196 616 12 Y Y 10 -09 4-12 6-15 7-20 608 770 950 6 8 10 8192 10368 12800 256 324 400 768 936 1120 12 12 12 Y Y Y Y Y Y 10 10 10 -1 -1 -09 10-30 1368 13 18432 576 1536 12 Y Y 10 -09 13-40 1862 20 25088 784 2016 12 Y Y 10 -09 15-45 2432 25 32768 1024 2560 12 Y Y 10 -1 18-50 2432 28 32768 1024 2560 12 Y Y 10 -09 22-65 3078 36 41472 1296 3168 12 Y Y 10 -09 27-80 33-100 40-130 55-180 3800 4598 5472 7448 44 52 62 85 51200 61952 73728 100352 1600 1936 2304 3136 3840 4576 5376 7168 12 12 12 12 Y Y Y Y Y Y Y Y 10 10 10 10 -09 -09 -09 -09 *Maximum System gates assume 20% of CLBs used as RAM 1-6 November 10, 1997 FEATURES DENSITY KEY FEATURES DEVICES Spartan Series Product Selection Matrix Spartan Series XCS05 XCS05 XCS05-XL XCS05-XL XCS10 XCS10 XCS10-XL XCS10-XL XCS20 XCS20 XCS20-XL XCS20-XL XCS30 XCS30 XCS30-XL XCS30-XL XCS40 XCS40 XCS40-XL XCS40-XL High Density High Performance Select-RAMTM Memory Low Cost System Gate Range* (Logic and RAM) (K) Logic Cells Max Logic Gates, (no RAM) (K) Max RAM Bits (no Logic) CLBs Flip-Flops Output Drive (mA) JTAG (IEEE 1149.1) Dedicated Arithmetic Quiescent Current (mA) Fastest Speed Grade 2-5 238 3 3200 100 360 12 Y Y 3 -4 3-10 466 5 6272 196 616 12 Y Y 3 -4 7-20 950 10 12800 400 1120 12 Y Y 3 -4 10-30 1368 13 18432 576 1536 12 Y Y 3 -4 13-40 1862 20 25088 784 2016 12 Y Y 3 -4 XC5204 XC5204 XC5206 XC5206 XC5210 XC5210 XC5215 XC5215 16 N/A 10-16 324 1296 8 Y Y 15 -3 23 N/A 15-23 484 1936 8 Y Y 15 -3 *Maximum System gates assume 20% of CLBs used as RAM FEATURES DENSITY KEY FEATURES DEVICES XC5200 XC5200 Series Product Selection Matrix XC5200 XC5200 Series XC5202 XC5202 High Density Low Cost Max Logic Gates (K) Max RAM Bits Typical Gate Range (K) CLBs/Logic Cells Flip-Flops Output Drive (mA) JTAG (IEEE 1149.1) Dedicated Arithmetic Quiescent Current (mA) Fastest Speed Grade November 10, 1997 3 N/A 2-3 64 256 8 Y Y 15 -3 6 N/A 4-6 120 480 8 Y Y 15 -3 10 N/A 6-10 196 784 8 Y Y 15 -3 1-7 An Introduction to Xilinx Products FEATURES KEY DENSITY FEATURES DEVICES XC9500 XC9500 Series Product Selection Matrix 1-8 CPLD Families XC9536 XC9536 XC9572 XC9572 XC95108 XC95108 XC95144 XC95144 XC95216 XC95216 XC95288 XC95288 4.8 216 216 24 Y N ­ -10 6.4 288 288 24 Y N ­ -10 JTAG 5 V ISP 3 V or 5 V I/O Gates (K) Macrocells Flip-Flops Output Drive (mA) JTAG (IEEE 1149.1) Dedicated Arithmetic Quiescent Current (mA) Fastest Speed Grade 0.8 36 36 24 Y N ­ -5 1.6 72 72 24 Y N ­ -7 2.4 108 108 24 Y N 140 -7 3.2 144 144 24 Y N ­ -7 November 10, 1997 fq ® Development System Products and CORE Solutions Products 1 Introduction 2 Development System Products and CORE Solutions Products 3 CPLD Products 4 FPGA Products 5 SPROM Products 6 3V Products 7 HardWire FpgASIC Products 8 High-Reliability and QML Military Products 9 Programming Support 10 Packages and Thermal Characteristics 11 Testing, Quality, and Reliability 12 Technical Support and Services 13 Product Technical Information 14 Index ® Development System Products Table of Contents Development System Products and CORE Solutions Products Development Systems: Products Overview Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flexible Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Foundation Series. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Alliance Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Alliance Series Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Xilinx M1 Software Technology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Increased Design Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . M1 Technical Benefits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2-1 2-1 2-1 2-1 2-2 2-2 2-2 2-2 Development Systems: Product Descriptions Development Systems Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Foundation Series: Foundation Base System (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Foundation Series: Foundation Base-Express System with VHDL/Verilog Synthesis (PC) . . . . . . . . . . Foundation Series: Foundation Standard System (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Foundation Series: Foundation Express System (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Alliance Series: Alliance Base (PC or Workstation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Alliance Series: Alliance Standard (PC or Workstation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Alliance Series Options (PC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2-4 2-5 2-6 2-7 2-8 2-10 2-12 CORE Solutions Overview Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CORE Solutions Products. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CORE Solutions Data Book . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LogiCORE Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Xilinx CORE Generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Xilinx PCI Solutions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Xilinx DSP Solutions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Acquiring LogiCORE Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AllianceCORE Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AllianceCORE Criteria . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Acquiring AllianceCORE Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13 2-13 2-13 2-13 2-13 2-14 2-14 2-14 2-14 2-14 2-15 2-15 1 Development Systems: Products Overview ® March 24, 1998 (Version 2.0) 1 2* Product Overview Introduction Leading-edge silicon products, state-of-the art software solutions and world-class technical support make up the total solution delivered by Xilinx. The software component of this solution is critical to the success of every design project. Xilinx Software Solutions provide powerful tools which make designing with programmable logic simple. Push button design flows, integrated on-line help, multimedia tutorials, plus high performance automatic and autointeractive tools, help designers achieve optimum results. And the industry's broadest array of programmable logic technology and EDA integration options deliver unparalleled design flexibility. Product Overview Xilinx Software Solutions are available in two different product series making it easy for designers to choose the right system for their needs. These two series support the industry's broadest array of programmable logic IC families. This allows users to standardize their design tools for all programmable logic applications and use these tools to realize the benefits of the industry's highest performance and density FPGAs and CPLDs. It also makes it easy to migrate designs to new technologies and re-use existing designs in new applications. The Xilinx Foundation Series provides designers with a complete, ready-to-use solution for programmable logic design. The Xilinx Alliance Series provides designers powerful integration of Xilinx design tools with their existing EDA environment. Flexible Configurations Xilinx Software Solutions are available in two device configurations giving designers a cost-effective way to match their tools to the design methodologies they require. These configurations are available for both the Foundation and Alliance Series. · · Base configurations provide push button design flows and support a broad array of FPGA and CPLD devices targeted for low density and high volume applications. Standard configurations combine push button flows with powerful auto-interactive tools. These tools give designers more influence and control over implementation while maintaining the benefits of design automation. Standard configurations include support for March 24, 1998 (Version 2.0) all Xilinx programmable logic devices, featuring the industry's largest FPGA devices. Foundation Series The Xilinx Foundation Series provides everything required to design a programmable logic device in an easy-to-use environment. This fully integrated tool set allows users to access design entry, synthesis, implementation and simulation tools in a ready-to-use package. Every step in the design process is accomplished using graphical tool bars, icons and pop-up menus supported by interactive tutorials and comprehensive on-line help. The Xilinx Foundation Series features support for standards based HDL design. All configurations support the popular ABEL language, with integrated compilers optimized for each target architecture. HDL configurations include integrated VHDL/Verilog synthesis from Synopsys with tutorials and graphical HDL design entry tools to turn new users into experts quickly and easily. HDL Configurations HDL configurations of the Foundation Series contain integrated VHDL/Verilog synthesis and graphical interactive HDL entry tools with the following features: · · · · · On-line tutorial teaches the art of VHDL design. Xilinx HDL Editor provides color coding, syntax checking and single click error navigation making it easy to create and debug VHDL, Verilog and ABEL designs. Graphical State Machine editor makes the design of simple or complex state machines simple and intuitive. HDL Language Assistant provides libraries of common functions with optimized VHDL, Verilog and ABEL code. FPGA and CPLD specific synthesis and optimization from Synopsys tools produce high-utilization, highperformance results Alliance Series The Alliance Series provides powerful and integrated design tools for users who require a quality solution for their chosen EDA design solution. With the Alliance Series, users can choose from a wide range of design techniques including schematic capture, module-based design and HDL design solutions. With standard based design interfaces including EDIF, VITAL, VHDL, Verilog and SDF, this series provides maximum flexibility, portability, mixed vendor support, and design reuse. 2-1 Development Systems: Products Overview Quality integration with leading EDA vendors such as ALDEC, Exemplar, Cadence, Mentor Graphics, Model Technology, OrCAD, Synopsys, Synplicity, Veribest and VIEWlogic provide tightly-coupled environments that make it easy to move through the design process and through a mixed EDA vendor flow. The EDA vendors are supported through the Xilinx Alliance Program, insuring high quality tools and accuracy of results. Information on Xilinx Alliance Program vendors can be found on the Xilinx WEB page www.xilinx.com. The Alliance Series includes an enhanced set of easy-touse features including, design manager, flow engine, installation, on-line documentation, and answer database. In addition, the Alliance Series includes a powerful and complete implementation toolset, LogiBLOX (next generation module generation), fully integrated EDA vendor support, and a powerful gate-level optimizer. Also included are new advanced place and route software that has incremental design capabilities and SMARTspecs (a robust timing constraint language). Users can achieve up to 25% performance improvements with no additional elapse time through the use of the Alliance Series Turns Engine. The Turns Engine uses networked workstations to run multiple place and route passes for a single design. This feature is included with the Alliance Series BASE and Standard workstation development systems. The libraries and interface provide Xilinx Unified Library schematic symbols, HDL synthesis libraries, VITAL(VHDL) and Verilog simulation models with timing information and translators through a standard netlist format. All of these tools provide a complete spectrum of high density design methodologies from fully-automatic to hand-crafted and close integration with Xilinx LogiCores and AllianceCore partners. Alliance Series Options VIEWlogic Workview Office Development System options as part of the Alliance Series are intended for users who want the integration of a complete solution with the power to access board and system level design tools. These products include VIEWlogic Workview Office schematic capture and simulation tools. Xilinx M1 Software Technology M1 technology represents Xilinx's next generation software technology. This advanced technology developed as a result of the Xilinx merger with NeoCAD Inc., enables digital system designers to increase design performance, leverage standards-based, high-level design methodologies and quickly receive new software features and device support through Xilinx Foundation Series and Alliance Series software solutions. which delivers push-button design flows and incremental design capabilities. These Xilinx-exclusive capabilities leverage results from previous design iterations to reduce runtimes and shorter design iterations to less than ten minutes. As engineers design complex circuits incrementally, this technology allows them to work in their preferred methodology. M1 Technology also delivers advanced timing driven placeand route capabilities to deliver maximum design performance through push-button flows. M1 Technical Benefits Maximum Design Performance M1 technology enables the user to achieve maximum design performance by providing a unique combination of advanced algorithms and interactive tools. Designer productivity is greatly enhanced through use of simple, pushbutton flows and optional auto-interactive tools. Customer testing has shown that M1 technology used with XC4000XL/XV XC4000XL/XV devices results in 70 percent shorter run times, up to a 25 percent performance improvement, and the ability to place and route devices with up to 100 percent utilization with a push-button flow. Modular Software System The modular architecture of the Xilinx M1 technology allows rapid delivery of incremental technologies, new features, device support, and versions of its leading software product families. New feature sets can now be released independently resulting in users' ability to quickly complete designs without having to re-learn new tools as enhancements are made. The investment Xilinx has made in the M1 technology ensures that the continuous delivery of innovative device architectures and improved software solutions can be done more rapidly, and predictably than previous software versions. Methodology Flexibility High-level design methodologies are becoming the methodology choice for the design of complex programmable logic. M1 technology delivers programmable logic specific high-level flows. The flows provide high-quality, high performance optimized results, and afford fast, flexible design changes and iterations to match the way engineers design. Designers employ a mixture of graphical and languagebased design entry methods while providing an easy-tolearn environment for Hardware Description Language (HDL) based design. Xilinx recognizes that design environments are variant and, therefore, has created a flexible system enabling the customer to choose the best methodology for their environment or design challenge. Increased Design Performance The M1 technology provides dramatically improved design performance through advanced place-and-route software 2-2 March 24, 1998 (Version 2.0) 1 Development Systems: Product Descriptions ® November 25, 1997 (Version 2.0) 1 2* Development Systems Descriptions It's simple to order a Xilinx Development System. Just choose a Foundation or Alliance Series and a few options. Give your local Xilinx Sales Office a call for information about our evaluation kits. Foundation Series · · · · Foundation Base System (PC) Foundation Base-Express System (PC) Foundation Standard System (PC) Foundation Express System (PC) Alliance Series · · Alliance Base (PC or Workstation) Alliance Standard (PC or Workstation) Alliance Series Options · VIEWlogic Workview Office Standard Development System Options (PC) November 25, 1997 (Version 2.0) 2-3 Development Systems: Product Descriptions Foundation Series: Foundation Base System (PC) Overview The Foundation Series provides a complete, ready-to-use design system for the design of Xilinx programmable logic devices. The Foundation Base System provides design entry (schematic and Abel HDL), simulation, and device implementation tools for a broad array of FPGA and CPLD devices targeted for low density and high volume applications. System Features · · · · · · · · Project manager Schematic editor Integrated HDL editor with support for the Abel 6 HDL Functional and timing simulator EDIF, VHDL (VITAL compliant), and Verilog / SDF design interfaces Device implementation software for Xilinx CPLDs and FPGAs Comprehensive on-line help, on-line documentation, and software tutorials Software maintenance, including hotline support and software updates Device Support · · CPLDs: - XC9500 XC9500 FPGAs: - XC4000E/X XC4000E/X Up to XC4010E/X XC4010E/X - Spartan - XC3x00A/L - XC5200 XC5200 Up to XC5210 XC5210 FPGAs Package Features - Foundation Base System Feature CPLD Devices FPGA Devices Libraries and Interface Schematic Editor HDL Editor Graphical State Editor ABEL 6 Entry / Synthesis VHDL Entry / Synthesis Verilog Entry / Synthesis Schematic-centric Synthesis HDL-centric Synthesis Simulator Device Implementation Maintenance2 FND FND FND FND BAS STD BSX EXP 1 1 11/12/97 Notes: 1. Spartan, XC3x00A/X, XC4000E/X XC4000E/X up to XC4010E/X XC4010E/X, and XC5200 XC5200 up to XC5210 XC5210. 2. A period of maintenance is included with new design system licenses, after which annual maintenance contracts may be purchased. Contact your Xilinx sales representative for more information. Required Hardware Environment · · · Windows 95 and Windows NT 4.0 compatible PCs Minimum memory requirements: 32 MB RAM, 32-64 MB Virtual Memory CD-ROM drive 2-4 November 25, 1997 (Version 2.0) Foundation Series: Foundation Base-Express System with VHDL/Verilog Synthesis (PC) Overview The Foundation Series provides a complete, ready-to-use design system for the design of Xilinx programmable logic devices. The Foundation Express System incorporates advanced synthesis technology from Synopsys, and provides design entry (schematic and HDL), VHDL and Verilog synthesis, simulation, and device implementation tools for a broad array of FPGA and CPLD devices targeted for low density and high volume applications. System Features · · · · · · · · · Project manager Schematic editor Integrated HDL editor with support for VHDL, Verilog, and Abel 6 HDL VHDL and Verilog synthesis, including compilation and optimization Functional and timing simulator EDIF, VHDL (VITAL compliant), and Verilog / SDF design interfaces Device implementation software for Xilinx CPLDs and FPGAs Comprehensive on-line help, on-line documentation, and software tutorials Software maintenance, including hotline support and software updates Device Support · · Package Features - Foundation Base-Express System Feature CPLD Devices FPGA Devices Libraries and Interface Schematic Editor HDL Editor Graphical State Editor ABEL 6 Entry / Synthesis VHDL Entry / Synthesis Verilog Entry / Synthesis Schematic-centric Synthesis HDL-centric Synthesis Simulator Device Implementation Maintenance2 FND FND FND FND BAS STD BSX EXP 1 1 11/12/97 Notes: 1. Spartan, XC3x00A/L, XC4000E/X XC4000E/X up to XC4010E/X XC4010E/X, and XC5200 XC5200 up to XC5210 XC5210. 2. A period of maintenance is included with new design system licenses, after which annual maintenance contracts may be purchased. Contact your Xilinx sales representative for more information. CPLDs: - XC9500 XC9500 FPGAs: - XC4000E/X XC4000E/X Up to XC4010E/X XC4010E/X - Spartan - XC3x00A/L - XC5200 XC5200 Up to XC5210 XC5210 FPGAs Required Hardware Environment · · · Windows 95 and Windows NT 4.0 compatible PCs Minimum memory requirements: 32 MB RAM, 32-64 MB Virtual Memory CD-ROM drive November 25, 1997 (Version 2.0) 2-5 Development Systems: Product Descriptions Foundation Series: Foundation Standard System (PC) Overview The Foundation Series provides a complete, ready-to-use design system for the design of Xilinx programmable logic devices. The Foundation Standard System provides design entry (schematic and Abel HDL), simulation, and device implementation tools for all Xilinx CPLDs and Xilinx FPGAs. System Features · · · · · · · · Project manager Schematic editor Integrated HDL editor with support for the Abel 6 HDL Functional and timing simulator EDIF, VHDL (VITAL compliant), and Verilog / SDF design interfaces Device implementation software for Xilinx CPLDs and FPGAs Comprehensive on-line help, on-line documentation, and software tutorials Software maintenance, including hotline support and software updates Device Support · · CPLDs: - XC9500 XC9500 FPGAs: - XC4000E/X XC4000E/X - Spartan - XC3x00A/L - XC5200 XC5200 Package Features - Foundation Base System Feature CPLD Devices FPGA Devices Libraries and Interface Schematic Editor HDL Editor Graphical State Editor ABEL 6 Entry / Synthesis VHDL Entry / Synthesis Verilog Entry / Synthesis Schematic-centric Synthesis HDL-centric Synthesis Simulator Device Implementation Maintenance2 FND FND FND FND BAS STD BSX EXP 1 1 11/12/97 Notes: 1. Spartan, XC3x00A/L, XC4000E/X XC4000E/X up to XC4010E/X XC4010E/X, and XC5200 XC5200 up to XC5210 XC5210. 2. A period of maintenance is included with new design system licenses, after which annual maintenance contracts may be purchased. Contact your Xilinx sales representative for more information. Required Hardware Environment · · · Windows 95 and Windows NT 4.0 compatible PCs Minimum memory requirements - Small Devices (< 10K gates): 32 MB RAM, 32-64 MB Virtual Memory - Medium Devices (10K to 30K gates): 64 MB RAM, 64-128 MB Virtual Memory - Large Devices (> 30K gates): 128 MB RAM, 128-256 MB Virtual Memory CD-ROM drive 2-6 November 25, 1997 (Version 2.0) Foundation Series: Foundation Express System (PC) Overview The Foundation Series provides a complete, ready-to-use design system for the design of Xilinx programmable logic devices. The Foundation Express System incorporates advanced synthesis technology from Synopsys, and provides design entry (schematic and HDL), VHDL and Verilog synthesis, simulation, and device implementation tools for all Xilinx CPLDs and Xilinx FPGAs. System Features · · · · · · · · · Project manager Schematic editor Integrated HDL editor with support for VHDL, Verilog, and Abel 6 HDL VHDL and Verilog synthesis, including compilation and optimization Functional and timing simulator EDIF, VHDL (VITAL compliant), and Verilog / SDF design interfaces Device implementation software for Xilinx CPLDs and FPGAs Comprehensive on-line help, on-line documentation, and software tutorials Software maintenance, including hotline support and software updates Device Support · · Package Features - Foundation Base System Feature CPLD Devices FPGA Devices Libraries and Interface Schematic Editor HDL Editor Graphical State Editor ABEL 6 Entry / Synthesis VHDL Entry / Synthesis Verilog Entry / Synthesis Schematic-centric Synthesis HDL-centric Synthesis Simulator Device Implementation Maintenance2 FND FND FND FND BAS STD BSX EXP 1 1 11/12/97 Notes: 1. Spartan, XC3x00A/L, XC4000E/X XC4000E/X up to XC4010E/X XC4010E/X, and XC5200 XC5200 up to XC5210 XC5210. 2. A period of maintenance is included with new design system licenses, after which annual maintenance contracts may be purchased. Contact your Xilinx sales representative for more information. CPLDs: - XC9500 XC9500 FPGAs: - XC4000E/X XC4000E/X - Spartan - XC3x00A/L - XC5200 XC5200 Required Hardware Environment · · · Windows 95 and Windows NT 4.0 compatible PCs Minimum memory requirements - Small Devices (< 10K gates): 32 MB RAM, 32-64 MB Virtual Memory - Medium Devices (10K to 30K gates): 64 MB RAM, 64-128 MB Virtual Memory - Large Devices (> 30K gates): 128 MB RAM, 128-256 MB Virtual Memory CD-ROM drive November 25, 1997 (Version 2.0) 2-7 Development Systems: Product Descriptions Alliance Series: Alliance Base (PC or Workstation) Overview Libraries and Interfaces Next generation FPGA/CPLD design solutions leveraging "Open Systems" integration with premier EDA partners for devices up to 10,000 gates. Cadence Base System Features: · · · · · · · · · · · · EDA Libraries & Interfaces Design Manager and Flow Engine LogiBLOX Module Generator Gate Optimizer Complete HDL design methodology support Incremental design capabilities Place and route utilizing SMARTspecs Re-entrant router Multi-pass PAR Timing Analyzer Standard netlist and backannotation (EDIF, SDF, VITAL VHDL and Verilog) Xchecker Hardware Debugger (workstation only) Package Includes: · · · · · · · · Alliance Quick Start Guide Alliance Release Document Answer Database Core Technology CD CAE Libraries CD On-line Documentation CD with DynaText browser Hardware Cable Demoboard Device Support: · · CPLDs: - XC9500 XC9500 FPGAs: - XC4000E/X XC4000E/X Up to XC4010E/X XC4010E/X - Spartan - XC3x00A/L - XC5200 XC5200 Up to XC5210 XC5210 FPGAs · Mentor · · Falcon Framework schematic capture library and ModelSim simulation models Leonardo synthesis libraries and interfaces are available from Mentor or Exemplar Logic Synopsys · · · · HDL Design Solutions (VHDL and Verilog) Design Compiler, FPGA Compiler II, FPGA Express, VSS Vital Simulation models DesignWare arithmetic modules * No libraries required to support FPGA Express VIEWlogic · Workview Office schematic capture library and functional and timing simulation interface Exemplar · Leonardo and Galileo synthesis libraries and interfaces are available from Exemplar Logic Synplicity · Synplify synthesis libraries and interfaces are available from Synplicity Model Technology · ModelSim, V-System HDL simulation libraries and interface Contact your local EDA sales office to purchase these EDA tools. Support and Updates Include: · · · · · · · · 2-8 Concept schematic libraries and Verilog-XL simulation models Answers Database - http://www.xilinx.com or Answers electronic book included. Hotline Telephone Support Apps FAX and E-Mail Online Documentation World Wide Web Access Technical Newletter Extensive Application Notes Software Updates (for in-maintenance customers) - A period of maintenance is included with new design system licenses, after which annual maintenance contracts may be purchased. Contact your Xilinx sales representative for more information November 25, 1997 (Version 2.0) Required Hardware Environment (PC) · · · · · · · · · Fully IBM compatible PC486/Pentium - NEC98 NEC98 supported Windows 95, Windows NT 4.0 - Chinese, Korean and Japanese versions Minimum 300 Mbytes hard-disk space CD-ROM drive VGA display Serial port mouse One parallel and two serial ports 32 MB RAM (Use additional RAM to increase performance) 32 MB - 64 MB Virtual Memory November 25, 1997 (Version 2.0) Required Hardware Environment (Workstation) · · · · · · Ultra Sparc (or equivalent) - Sun OS 4.1.3 and 4.1.4 - Solaris 2.5 HP715 HP715 (or equivalent) - HP-UX 10.2 RS6000 RS6000 - AIX 4.1.5 (no GUIs) 64 MB RAM (Use additional to increase performance) 64MB min Swap Space Color Monitor 2-9 Development Systems: Product Descriptions Alliance Series: Alliance Standard (PC or Workstation) Overview Libraries and Interfaces Next generation FPGA/CPLD design solutions leveraging "Open Systems" integration with premier EDA partners for unlimited gate capacity. Cadence Base System Features: Mentor · · · · · · · · · · · · · EDA Libraries & Interfaces Design Manager and Flow Engine LogiBLOX Module Generator Gate Optimizer Full HDL design methodology support Incremental design capabilities Place and route utilizing SMARTspecs Re-entrant router Multi-pass PAR Timing Analyzer Standard netlist and backannotation (EDIF, SDF, VITAL VHDL and Verilog) Xchecker Hardware Debugger (workstation only) Package Includes: · · · · · · · · Alliance Quick Start Guide Alliance Release Document Answer Database Core Technology CD CAE Libraries CD On-line Documentation CD with DynaText browser Hardware Cable Demoboard · · Concept schematic libraries and Verilog-XL simulation models Falcon Framework schematic capture library and ModelSim simulation models Leonardo synthesis libraries and interfaces are available from Mentor or Exemplar Logic Synopsys · · · · HDL Design Solutions (VHDL and Verilog) Design Compiler, FPGA Compiler II, FPGA Express, VSS Vital Simulation models DesignWare arithmetic modules * No libraries required to support FPGA Express VIEWlogic · Workview Office schematic capture library and functional and timing simulation interface Exemplar · Leonardo and Galileo synthesis libraries and interfaces are available from Exemplar Logic Synplicity · Synplify synthesis libraries and interfaces are available from Synplicity Model Technology Device Support: · · CPLDs: - XC9500 XC9500 FPGAs: - XC4000E/X XC4000E/X - Spartan - XC3x00A/L - XC5200 XC5200 · Contact your local EDA sales office to purchase these EDA tools. Support and Updates Include: · · · · · · · · 2-10 ModelSim, V-System HDL simulation libraries and interface Answers Database - http://www.xilinx.com or Answers electronic book included. Hotline Telephone Support Apps FAX and E-Mail Online Documentation World Wide Web Access Technical Newletter Extensive Application Notes Software Updates (for in-maintenance customers) - A period of maintenance is included with new design system licenses, after which annual maintenance contracts may be purchased. Contact your Xilinx sales representative for more information November 25, 1997 (Version 2.0) Required Hardware Environment (PC) · · · · · · · · · · Fully IBM compatible PC486/Pentium - NEC98 NEC98 supported Windows 95, Windows NT 4.0 - Chinese, Korean and Japanese versions Minimum 300 Mbytes hard-disk space CD-ROM drive VGA display Serial port mouse One parallel and two serial ports Small Devices: (8K or ) XC4036XL XC4036XL - XC4062XL XC4062XL - 128K RAM (Use additional RAM to increase performance) - 128 - 256 MB Virtual Memory November 25, 1997 (Version 2.0) Required Hardware Environment (Workstation) · · · · · · Ultra Sparc (or equivalent) - Sun OS 4.1.3 and 4.1.4 - Solaris 2.5 HP715 HP715 (or equivalent) - HP-UX 10.2 RS6000 RS6000 - AIX 4.1.5 (no GUIs) Small Devices: (28K or ) XC4036XL XC4036XL - XC4062XL XC4062XL - 128 MB RAM (Use additional RAM to increase performance) - 128 MB min Swap Space Color Monitor 2-11 Development Systems: Product Descriptions Alliance Series Options (PC) Overview Support and Updates Include: VIEWlogic Workview Office schematic capture and gate simulator development system with libraries and interfaces for Xilinx FPGAs and CPLDs. · Workview Office Standard Features: · · · · · Workview Office schematic editor Workview Office gate simulator Libraries and interfaces Hotline support Software maintenance for 90-days Libraries Support: · · CPLDs: - XC9500 XC9500 FPGAs: - XC4000E/X XC4000E/X - Spartan - XC3x00A/L - XC5200 XC5200 2-12 · · · · · · · Answers Database - http://www.xilinx.com or Answers electronic book included. Hotline Telephone Support Apps FAX and E-Mail Software Updates (for in-maintenance customers) Online Documentation World Wide Web Access Technical Newletter Extensive Application Notes Required Hardware Environment: · · · · · · · · Fully IBM compatible PC486/Pentium Windows 95, Windows NT 4.0 - Chinese, Korean and Japanese versions Minimum 500 Mbytes hard-disk space CD-ROM drive VGA display Serial port mouse One parallel and two serial ports 64 Mbytes RAM recommended (increase to improve performance) November 25, 1997 (Version 2.0) 0 ® September 5, 1997 (Version 1.0) CORE Solutions Overview 0 2* Background The ASIC core industry has been developing for over a decade. Today there exists a wealth of intellectual property (IP) that is readily available from numerous sources. During this time, however, programmable logic did not have the density or the performance needed to accommodate large IP cores. Today, things have changed considerably. Xilinx is shipping FPGAs like the XL family that have usable densities up to 125,000 gates. Now, not only is the use of pre-defined logic functions in programmable logic a possibility, it is becoming a requirement to meet ever-shrinking product development cycles. Product Overview view) which lists all of the functions available today. This table will be your best guide to locating a specific product. If you don't see what you need, check the AllianceCORE Partner Profiles, Areas of Expertise section, for each of our AllianceCORE partners. Our partners will be more than willing to discuss the possibility of producing a core specifically for your needs. Data Book Contents The contents of the data book are as follows: · · As a result, many ASIC core vendors and system designers are beginning to look at using cores for their programmable logic designs. It is for this reason that Xilinx created the CORE Solutions portfolio of products. CORE Solutions Products · CORE Solutions products support four application areas. The application areas are as follows: · · · · Standard Bus Interfaces - such as PCI, PCMCIA, USB and Plug-and-Play ISA. DSP Functions - These range from small building blocks such adders, registers and multipliers, to larger system-level functions such as FIR filters and ReedSolomon coders. Telecom and Networking - building blocks for popular communications standards. Base-Level Functions - a broad category of functions used across many application segments. These include the every small parameterizable LogiBLOX macros up through larger functions such as UARTs and DMA controllers. CORE Solutions Data Book The goal of the CORE Solutions portfolio of products is to provide cores with the shortest time-to-market and best possible device utilization the programmable logic industry has to offer. Xilinx has published a brand new data book focused entirely on programmable logic cores and related products. Now there is one definitive sourcebook with detailed descriptions of all Xilinx CORE Solutions. When you receive your copy of the CORE Solutions Data Book, become familiar with the Product Listing by Application Segment Table, (reproduced at the end of this over- September 5, 1997 (Version 1.0) · · · Introduction - Program Overview - Product Listing by Application Segment LogiCORE Products, sold and supported by Xilinx - Product Overview - PCI - DSP - CORE Generator products AllianceCORE Products, sold and supported by Xilinx' Partners - Program Overview - Products - AllianceCORE Partner Profiles LogiBLOX, GUI-based small function generator Reference Designs Sales Offices, Representatives and Distributors Ordering Information To order a copy, request the CORE Solutions Data Book from the Xilinx Literature Department. In the US call 1-800231-3386. For international locations call 1-408-879-5017 or you can send an E-mail request to: literature@xilinx.com. An electronic version of the CORE Solutions Data Book (1.2M Adobe Acrobat .pdf format) can also be downloaded from: www.xilinx.com/products/logicore/core_sol.pdf LogiCORE Products LogiCORE products are sold, licensed and supported by Xilinx. They are developed internally by Xilinx or jointly with a partner. The cores that Xilinx provides as LogiCORE products typically fall into one of two categories.The first are high-performance interface cores that require a thorough understanding and control of the FPGA technology and 2-13 CORE Solutions Overview implementation software in order to achieve the desired performance and complexity. An example of a core in this category is the LogiCORE PCI interface. The second category are cores that benefit from a very specialized implementation in the FPGA. An example is the LogiCORE DSP modules that are implemented using a unique algorithm, Distributed Arithmetic. This algorithm fits the lookup-table-based architecture of the FPGA. The result is outstanding performance and device utilization, often more than 10 times better than generic HDL descriptions. Xilinx CORE Generator In addition to actual cores, Xilinx is committed to develop enabling design tools and methodologies to facilitate usage of cores with FPGAs. The first products available in this category are the web-based CORE Generator for PCI and the CORE Generator for DSP (available on CD). This innovative methodology for acquiring and using cores combines the benefits of · · a firm core with predictable performance, and the flexibility of system level design, facilitated by behavioral languages such as VHDL and Verilog. In addition, because Xilinx is using the web as a distribution mechanism, you always have access to the latest versions and enhancements of the cores at: www.xilinx.com/products/logicore/logicore.htm The LogiCORE products are customized to fit your specific application using an intuitive graphical user interface. Based on your inputs, the tool then generates a proven core with highly predictable timing that can be integrated using any VHDL-, Verilog- or schematic-based design flow. As a result, you can integrate several individually proven cores with given performance into one system on a single FPGA. Because each core is already verified, the time-tomarket benefits are maintained for high-complexity FPGAs. PCI is an extremely high-performance and complex specification that is challenging to meet in any technology. To meet the stringent PCI specification the core is carefully hand-tuned for the targeted architecture. Placement and routing for the critical parts of the core is locked down to ensure that timing can be met every time the core is used. To achieve our goals, the LogiCORE development team is working closely with both the IC and Software teams. As an example of this teamwork, new methodologies for characterizing and modeling our FPGAs have been developed. The result is access to state of the art technology and expertise, that allows you to complete your PCI application in record time. Xilinx has sold over 250 licenses of the LogiCORE PCI interface and has built up solid knowledge about PCI. We are committed, and will continuously develop our PCI products to remain state of the art. Xilinx DSP Solutions Using an FPGA to implement high performance DSP functions often allows a radical performance advantage over fixed processors while maintaining maximum flexibility and the shortest time-to-market. Until now, tools to automate the design process have been lacking and most designs have been completed manually by experienced FPGA designers. With the introduction of Xilinx' CORE Generator for DSP, complex parameterized DSP building blocks can be implemented automatically with performance and density equal to or better than a hand-tuned implementation. LogiCORE DSP modules can be used with VHDL-, Verilog- or schematic based design methodologies. Higher level DSP cores are available from our AllianceCORE partners. Acquiring LogiCORE Products Xilinx' PCI solution includes devices, tools and cores needed to build a cost-effective single-chip PCI system in record time. LogiCORE products are available from your local Xilinx sales representative similar to other Xilinx software products. Xilinx and your local sales representative will also be your primary source for support of the core, the devices and the design tools. · LogiCORE PCI - the only proven PCI core with predictable timing XC4000E/XL XC4000E/XL - the industry's fastest FPGAs that allow you to integrate the PCI interface plus 5 to 60 thousand gates of user designed logic HardWire - an automatic migration path to a low-cost chip for volume production CORE Generator - for easy configuration and integration of the LogiCORE PCI module You can also send email questions to: 3rd party Design Centers - with PCI expertise available for special applications and customization of the core Xilinx takes an active role with its partners in the process of productizing AllianceCOREs. This is unique to the AllianceCORE program. Because the process is so involved, Xilinx PCI Solutions · · · · 2-14 logicore@xilinx.com. AllianceCORE Overview The AllianceCORE program is a cooperative effort between Xilinx and independent third-party core developers. It is designed to produce a broad selection of industry-standard solutions dedicated for use in Xilinx programmable logic. September 5, 1997 (Version 1.0) we work closely with our partners to select the right cores first. This naturally limits the number of partners we can work with at any one time and subsequently the number of available cores. At the same time it raises the quality and usability of the cores that are offered. AllianceCORE Criteria A core must meet a minimum set of criteria before it can receive the AllianceCORE label. Core Selection The AllianceCORE program looks at cores from a practical point of view. A programmable logic version of a core must have value over an ASIC or standard product version of the same function. It must be cost effective and make sense for use in a programmable device in a production system. If a candidate core does not pass these simple tests, then it does not make sense to invest the effort to convert it to an AllianceCORE module. Core Qualification Generic, synthesizable cores offer maximum flexibility for users with unique requirements. This is typically the format for cores provided to the ASIC market. With programmable logic, however, this flexibility can come at the expense of efficiency and performance. It can take a considerable amount of effort to get a specific core to synthesize in a way that meets density and timing requirements. Time spent trying to accomplish this can quickly reduce the time-tomarket advantage of using programmable logic and cores in the first place. Xilinx is not interested in promoting generic, synthesizable functions as AllianceCOREs. Instead, AllianceCOREs are generally provided as parameterizable black-boxes that allow customization in critical areas. This guarantees that the implementation is optimized for density while still meeting performance, preserving the time-to-market value of programmable logic. Flexibility is provided by allowing you to quickly implement your unique logic on the same device. Source code versions of the cores are also available from the partners at additional cost for those who need ultimate flexibility. Announced AllianceCOREs have been implemented and verified in a Xilinx device. They are available immediately for purchase in a Xilinx-specific format. Timing-critical cores designed to adhere to an industry standard also come with appropriate constraints files in order to guaran- September 5, 1997 (Version 1.0) tee functionality and compliance. AllianceCOREs originated from either schematic or HDL entry tools. Core Integration AllianceCOREs are not just cores, they are complete solutions for system designs. While cores by themselves have value, in many cases it is often not enough to just supply a generic core. You may need additional tools such as system software and prototyping equipment to help you rapidly integrate the core into your design, perform system debug in a real-world environment, and then quickly convert the prototype to a production unit. This is particularly true of complex functions. Many AllianceCORE functions are supported by Xilinxbased demonstration or prototyping boards. Some also have system simulation models or debug software. All of this allows you to evaluate and work with the function before you have to layout your board. These tools are provided by the AllianceCORE partner, usually at additional cost. Descriptions of the support tools available for each core are included in the CORE Solutions Data Book. Complete solutions like these help preserve the value of using programmable logic while minimizing the support burden for the core provider. Acquiring AllianceCORE Products AllianceCORE products are sold and serviced directly by the AllianceCORE partners since they are the experts for their particular products. They are responsible for pricing, licensing terms, delivery and technical support. Contact information for each partner is included in the AllianceCORE Partner Profiles section of the CORE Solutions Data Book. If you want additional information about the AllianceCORE program or are interested in becoming a partner, contact Xilinx directly. Xilinx, Inc. 2100 Logic Drive San Jose, CA 95124 Attn: Mark Bowlby, AllianceCORE Product Manager Phone: +1 408-879-5381 Fax: +1 408-879-4780 E-mail: alliancecore@xilinx.com URL: www.xilinx.com/products/logicore /alliance/tblpart.htm 2-15 CORE Solutions Overview Table 1: Product Listing by Application Segment Check www.xilinx.com/products/logicore/tbls_cores.htm for the latest listing of available Cores Function Standard Bus Interfaces IIC Two-Wire Serial Interface ISA Plug and Play Interface ISA Interface for JPEG Motion Codec PCI Master/Slave Interfaces 1.2.0 PCI Master/Slave Interfaces 2.0.0 PCMCIA Fax/Modem PCMCIA Library USB - Low-Speed Function Controller USB - Full-Speed Function Controller USB - 3-Port Hub Controller DSP Functions 1's Complement Accumulator, Scaled by 1/2 Adder, Registered Adder, Registered Loadable Adder, Registered Scaled Adder, Registered Serial Adders, Subtractors, Accumulators Comb Filter Correlator, 1-D RAM Based Correlator, 1-D ROM Based Delay Element FIR Filter, 16-Tap, 8-Bit FIR Filter - Serial Distributed Arithmetic FIR Filter - Dual Channel Serial Distributor Arithmetic Integrator Memory - 16-Word Deep Register Look-up Table Memory - 32-Word Deep Register Look-up Table Memory - 16-Word Deep Registered RAM Memory - 32-Word Deep Registered RAM Memory - Registered Synchronous RAM Memory - Registered ROM Multiplier, Constant Coefficient Multiplier, Constant Coefficient (pipelined) Multipliers, Parallel - Area Optimized Multipliers, Parallel - Performance Optimized Parallel to Serial Converter Reed-Solomon Decoder Reed-Solomon Encoder SDA FIR Control Logic Sine/Cosine Square Root Subtracter, Registered Subtracter, Registered Loadable 2-16 CORE Solution AllianceCORE Reference Design Reference Design LogiCORE LogiCORE AllianceCORE AllianceCORE AllianceCORE AllianceCORE AllianceCORE LogiCORE LogiCORE LogiCORE LogiCORE LogiCORE LogiCORE Reference Design LogiCORE LogiCORE LogiCORE LogiCORE Reference Design LogiCORE LogiCORE LogiCORE LogiCORE LogiCORE LogiCORE LogiCORE LogiCORE LogiCORE LogiCORE LogiCORE LogiCORE LogiCORE LogiCORE AllianceCORE AllianceCORE LogiCORE LogiCORE LogiCORE LogiCORE LogiCORE September 5, 1997 (Version 1.0) Table 1: Product Listing by Application Segment (Continued) Check www.xilinx.com/products/logicore/tbls_cores.htm for the latest listing of available Cores Function Time Skew Buffer - Non-Symmetric 16-Deep Time Skew Buffer - Non-Symmetric 32-Deep Time Skew Buffer - Symmetric 16-Deep Transform, DFT Transform, FFT Base-Level Functions 16450 UART 16550A UART with RAM 8250 Asynchronous Communications 8254 Programmable Timer M8255 M8255 Programmable Peripheral Interface XF8255 XF8255 Programmable Peripheral Interface Accumulator Adder/Subtracter Clock Divider Comparator Constant Constant Counter Counter, Loadable Binary Counter, Ultra-Fast Synchronous Counter, Accelerating Loadable Data Register Decoder FIFOs in XC4000 XC4000 RAM FIFO, High-Performance RAM-Based FIFO, Register-Based Frequency/Phase Comparator for PLL Gates, Simple Harmonic Frequency Synthesizer and FSK Modulator Input/Output Microcontroller, Dynamic Memory (ROM, RAM, Synch-RAM, Dual Port RAM) Multiplexer Multiplexers, Barrel Shifters Multiplexer, Two Input Multiplexer, Three Input Multiplexer, Four Input Pad Pulse-Width Modulation Register Serial Code Conversion between BCD and Binary Shift Register Tristate September 5, 1997 (Version 1.0) CORE Solution LogiCORE LogiCORE LogiCORE LogiCORE LogiCORE AllianceCORE AllianceCORE AllianceCORE AllianceCORE AllianceCORE AllianceCORE LogiBLOX LogiBLOX LogiBLOX LogiBLOX LogiCORE LogiBLOX LogiBLOX Reference Design Reference Design Reference Design LogiBLOX LogiBLOX Reference Design Reference Design Reference Design Reference Design LogiBLOX Reference Design LogiBLOX Reference Design LogiBLOX LogiBLOX Reference Design LogiCORE LogiCORE LogiCORE LogiBLOX Reference Design LogiCORE Reference Design LogiBLOX LogiBLOX 2-17 CORE Solutions Overview 2-18 September 5, 1997 (Version 1.0) ® CPLD Products 1 Introduction 2 Development System Products and CORE Solutions Products 3 CPLD Products 4 FPGA Products 5 SPROM Products 6 3V Products 7 HardWire FpgASIC Products 8 High-Reliability and QML Military Products 9 Programming Support 10 Packages and Thermal Characteristics 11 Testing, Quality, and Reliability 12 Technical Support and Services 13 Product Technical Information 14 Index ® CPLD Products Table of Contents CPLD Products XC9500 XC9500 Series Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 XC9500 XC9500 In-System Programmable CPLD Family. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 XC9536 XC9536 In-System Programmable CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21 XC9572 XC9572 In-System Programmable CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-29 XC95108 XC95108 In-System Programmable CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-37 XC95144 XC95144 In-System Programmable CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-45 XC95216 XC95216 In-System Programmable CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-55 XC95288 XC95288 In-System Programmable CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-65 1 ® XC9500 XC9500 Series Table of Contents 1 3* XC9500 XC9500 In-System Programmable CPLD Family Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Family Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Architecture Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Function Block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Macrocell. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Term Allocator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FastCONNECT Switch Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin-Locking Capability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . In-System Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Endurance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IEEE 1149.1 Boundary-Scan (JTAG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Design Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low Power Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-Up Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Development System Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FastFLASH Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3-5 3-5 3-7 3-8 3-10 3-13 3-14 3-15 3-16 3-16 3-16 3-16 3-16 3-17 3-17 3-18 3-19 3-19 XC9536 XC9536 In-System Programmable CPLD Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended Operating Conditions1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Endurance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics Over Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC9536 XC9536 I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC9536 XC9536 Global, JTAG and Power Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Component Availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21 3-21 3-21 3-23 3-23 3-23 3-24 3-24 3-25 3-26 3-26 3-27 3-27 XC9572 XC9572 In-System Programmable CPLD Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended Operation Conditions1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Endurance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics Over Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC9572 XC9572 I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC9572 XC9572 Global, JTAG and Power Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-29 3-29 3-29 3-31 3-31 3-31 3-32 3-32 3-33 3-34 3-35 3-36 3-1 XC9500 XC9500 Series Table of Contents Component Availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-36 XC95108 XC95108 In-System Programmable CPLD Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended Operation Conditions1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Endurance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics Over Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC95108 XC95108 I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC95108 XC95108 I/O Pins (continued) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC95108 XC95108 Global, JTAG and Power Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Component Availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-37 3-37 3-37 3-39 3-39 3-39 3-40 3-40 3-41 3-42 3-43 3-43 3-44 3-44 XC95144 XC95144 In-System Programmable CPLD Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended Operation Conditions1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Endurance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics Over Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC95144 XC95144 I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC95144 XC95144 I/O Pins (continued) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC95144 XC95144 Global, JT