XC166 C166S IEC61508 XC167CI XC161CJ 80C196 20MIPS 40MIPS RS485 XC161 XC164 - Datasheet Archive

 

The INSIDER GUIDE to Planning XC166 Family Designs An Engineers Introduction to the XC166 Family Microcontrollers February 2006

 

Insider Guide V 1.0 The INSIDER GUIDE to Planning XC166 XC166 Family Designs An Engineers Introduction to the XC166 XC166 Family Microcontrollers February 2006 An Insiders Guide to Planning XC166 XC166 Family Designs © Copyright Hitex (UK) Ltd. 19/12/2005 Edition 2006-02-22 Published by Infineon Technologies AG 81726 München, Germany All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of noninfringement, regarding circuits, descriptions and charts stated herein. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. Insiders Guide 2 V1.0, 2006-02 An Insiders Guide to Planning XC166 XC166 Family Designs Revision History: 2006-02 Previous Version: none Page V1.0 Subjects (major changes since last revision) We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: mcdocu.comments@infineon.com Insiders Guide 3 V1.0, 2006-02 An Insiders Guide to Planning XC166 XC166 Family Designs Credits Authors: Editor: Michael Beach David Greenhill Alison Wenlock Acknowledgements The authors would like to thank Karl Smith, Mike Copeland and Manfred Choutka of Infineon Technologies plus Joachim Klein of Hitex Development Tools GmbH. for their contributions to this book. Preface This guide contains basic information that is useful when doing your first XC166 XC166 family design. There are many simple facts which, if they are known at the outset, can save a lot of time and money. Overall, it is intended to complement the user manuals by putting things into a practical context. Some of the material can be found in the XC166 XC166 family databooks but most of it is simply the result of our practical experience and so is only to be found here. The topics covered are those that are not obvious or are often missed out. Where the user manuals provide a satisfactory explanation, you will be referred back to them, rather than duplicating information here. This is by no means a complete reference work and a lot of additional information can be found on the Infineon website. Note: While every effort has been made to ensure the accuracy of the information contained within this guide, Hitex cannot be held responsible for the consequences of any errors contained therein. Any subjective or anecdotal information presented is not necessarily the official view of either Hitex Development Tools Ltd. or Infineon Technologies AG. Prepared By: Michael Beach David Greenhill With additional material from: Karl Smith, Infineon Technologies UK Joachim Klein, Hitex Development Tools Insiders Guide 4 V1.0, 2006-02 An Insiders Guide to Planning XC166 XC166 Family Designs Contents 1 1.1 1.2 1.2.1 1.3 1.3.1 1.3.2 1.3.3 1.3.4 1.4 1.4.1 1.5 RISC Architectures For Embedded Applications 11 Introduction .11 Behind The C166S C166S V2's Near-RISC Core .11 Conventional CISC Bottle-necks.12 The RISC Architecture For Embedded Control.13 Bus Interface.13 RISC Interrupt Response.14 Registers And Multi-Tasking .14 Coping With RISC Instruction Set (Apparent) Omissions .17 RISC And Real World Peripherals .18 RISC Benefits In Embedded Applications.19 Traditional RISC v New RISC .20 2.1 2.1.1 2.1.2 2.1.3 2.2 2.2.1 2.3 2.3.1 2.3.2 2.4 2.5 2.5.1 2.5.2 2.5.3 2.5.4 2.5.5 2.6 2.6.1 2.6.2 2.6.3 2.6.4 2.6.5 2.6.6 2.7 2.8 Getting Started With The XC166 XC166 23 Basic Considerations .23 Family Overview .23 Fundamental Design Factors.23 Setting The CPU Hardware Configuration Options.23 Calculating The Pull-Down Resistor Values.25 Pull-Up Resistor Calculations .26 Start-Up Configuration .27 Internal Start Configuration .27 External Start Configuration.28 Reset Control.30 Clock Speeds And Sources .31 PLL Start Up .32 External Bus Start.32 Internal ROM Start.33 Choice Of Clock Speed .33 Choosing The PLLCON Values .35 Generating The Clock.37 Designing Clock Circuits .37 Oscillator Modules .37 Designing Crystal Oscillator Circuits.38 Crystal Oscillator Components Test Procedure .38 Laying Out Clock Circuits.41 Symptoms Of A Poor Clock .41 Real Time Clock Oscillator.42 Further Information On Oscillator Design .42 3.1 3.1.1 3.2 3.2.1 3.2.2 3.3 3.3.1 3.3.2 3.3.3 3.3.4 3.3.5 Bus Modes And Timings 43 Flexible Bus Interface .43 Integral Chip Selects.43 Setting The Bus Mode .44 On-Chip Boot .44 External Boot .44 Setting The Overall Addressing Capabilities.45 External Memory Access Times .45 Calculating The Bus Timing Parameters For A Multiplexed Bus.46 Calculating The Bus Timing For A Demultiplexed Bus .48 A Tool For Calculating The Bus Timing Parameters.49 Bus Settings For Commonly-Used Memory Devices .49 2 3 Insiders Guide 5 V1.0, 2006-02 An Insiders Guide to Planning XC166 XC166 Family Designs 4 4.1 4.2 4.3 4.4 4.5 4.5.1 4.5.2 4.5.3 4.5.4 4.5.5 4.5.6 4.5.7 Interfacing To External Memory Devices 51 Using 16-Bit Memory Devices.52 Using Byte-Wide Memory Devices In 16-bit XC166 XC166 Systems .55 Using The XC166 XC166 With Byte-Wide Memories And #BHE .56 Using DRAM With The XC166 XC166 Family .57 Using FLASH Memory Cards With The XC166 XC166 .58 Cheap Gigabyte Storage .58 Using CompactFLASH Cards For XC166 XC166 Program Updates .58 Interfacing SD/Multimedia Cards .59 Interfacing To CompactFLASH .60 Managing Large FLASH Cards.60 File System API To Embedded C Programs.61 Resources To Implement A File System On The XC166 XC166.61 5.1 5.2 5.2.1 5.3 5.3.1 5.3.2 5.4 5.4.1 5.4.2 5.4.3 5.5 5.5.1 5.6 5.6.1 5.7 5.8 5.9 5.10 5.11 5.12 5.13 In-Circuit Reprogrammable FLASH EPROM 64 Introduction .64 Internal FLASH Layout .64 FLASH Identification .65 FLASH Reliability.65 Dynamic Error Correction .65 FLASH Endurance.66 Managing FLASH Under Extreme Conditions.66 When To Manage FLASH.66 Dynamic Recovery From Double Bit Errors .67 Predicting Future FLASH Failures .67 Tools For Programming FLASH.69 Programming XC166 XC166 FLASH In Production.69 Introduction To Bootstrap Loader Programs .70 The XC166 XC166 Serial Bootstrap Loader .70 Testing FLASH Programmers Under IEC61508 IEC61508 And Other Standards.71 Bootstrap Mode Debugging Problems With JTAG.71 Bootstrap Mode Debugging Using An In-Circuit Emulator .72 Hardware Aspects Of In-Circuit FLASH Programming .72 In-Circuit FLASH Programming Via CAN Bootstrap Mode .73 In-Circuit FLASH Programming Via SSC0 Bootstrap Mode.74 In-Situ FLASH Programming Without Bootstrap Mode .74 6.1 6.1.1 6.1.2 6.1.3 6.2 6.2.1 6.2.2 6.3 6.4 6.5 6.6 Planning The Memory Map 76 Understanding The DPPs .76 Fast DPP-Based Data Access .76 Accessing Large Data Objects.77 Data Addressing Impact On C/C+ Compilers .77 Planning the Memory Map and Configuring the C Compiler. .78 Using The DPPs .78 Using the PSRAM.78 External Bus Factors .80 Internal FLASH .80 External ROM .80 Implications Of Bus Mode/Trading Port Pins For IO .80 7.1 7.2 7.3 Power Consumption 83 Reducing Power Consumption By Optimising Clock Speed .83 Comparing Current Consumptions .84 Supply Voltage.84 5 6 7 Insiders Guide 6 V1.0, 2006-02 An Insiders Guide to Planning XC166 XC166 Family Designs 8 8.1 8.1.1 8.1.2 8.2 8.2.1 8.2.2 8.2.3 8.2.4 8.2.5 8.3 8.3.1 8.3.2 8.3.3 8.3.4 8.3.5 8.4 8.4.2 8.5 8.6 8.6.1 8.6.2 8.6.3 8.7 8.7.1 8.7.2 9 System Programming 85 Serial Port Baud Rates .85 The Synchronous Serial Ports .85 I2C Module .85 Adding USB Communications To The XC166 XC166 Family.87 The XC166 XC166 End Of The USB Link .87 Hardware Issues.87 XC166 XC166 Software.88 PC Software.88 Getting Started With USB .89 Interrupt Performance.89 Interrupt Latencies .89 Software Interrupts .89 Hardware Traps .90 Interrupt Structure.90 Interrupt System Usage Notes.90 Event-Driven Data Transfers Via The PEC System.92 Extending The PEC Address Ranges And Sizes Above 64K .93 XC166 XC166 Family Stacks .94 The XC166 XC166 DSP Co-Processor .95 Adding DSPs To Microcontrollers .95 Compiler Handling Of The MAC .95 Infineon DSP Libraries .96 Special CAN Module Possibilities .97 Time Triggered CAN Using The TwinCAN Module.97 CAN Loop-Back Mode .97 Allocating Pins/Port Pins In Your Application 99 9.1 General Points About Parallel IO Ports.99 9.2 Allocating Port Pins To Your Application .99 9.3 Port 0 .99 9.3.1 Port 0 Pin Allocations:.100 9.4 Port 1 .100 9.5 Port 2 .100 9.5.1 The CAPCOM Units.100 9.5.2 Time-Processor Unit Versus CAPCOM .101 9.5.3 32-bit Period Measurements.101 9.5.4 Generating PWM With The XC166 XC166 CAPCOM Unit .101 9.5.5 Sinewave Synthesis Using The CAPCOM.102 9.5.6 The CAPCOM6E Motor Drive Peripheral.102 9.5.7 Automotive Applications Of CAPCOM1 .105 9.5.8 Digital To Analog Conversion Using The CAPCOM Unit .105 9.5.9 Multiple Independent Timebase Generation .106 9.5.10 Software UARTs .106 9.6 Port 3 .107 9.6.1 Using GPT1 .107 9.6.2 Using GPT2 .108 9.6.3 Combining CAPCOM, GPT1 & GPT2 For Crank Synchronisation.108 9.7 Port 4 .110 9.7.1 Interfacing To CAN Networks .110 9.8 Port 5 .113 9.8.1 XC166 XC166 Analog To Digital Converter.113 9.8.2 ADC Basic Conversion Clock .114 9.8.3 ADC Calibration .114 Insiders Guide 7 V1.0, 2006-02 An Insiders Guide to Planning XC166 XC166 Family Designs 9.8.4 9.8.5 9.8.6 9.9 9.9.1 9.9.2 9.9.3 9.10 9.10.1 9.10.2 9.10.3 9.10.4 9.11 9.12 9.13 9.14 9.15 9.15.1 Over-Voltage Protected Analog Inputs .114 Matching The A/D Inputs To Signal Sources .115 Analog Reference Voltage.117 Board Design Issues.117 Component Placement .117 Power Supply.117 Ground Planes.117 Connecting The ADC To Signal Sources.118 Ratiometric Mode.118 Fixed Precision Reference.119 Corrected Conversion Mode .120 Interfacing To Analog Voltages Greater Than 5v.121 Port 6 .122 Port 7 .122 Port 9 .122 Port 20 .122 Summary Of Port Pin Interrupt Capabilities .123 Interrupts From Port Pins.123 10 Typical XC166 XC166 Family Applications 125 10.1 Automotive Applications.125 10.2 Industrial Control Applications .126 10.3 Telecommunications Applications.126 10.3.1 Transport Applications .126 10.4 Consumer Applications .127 10.5 Instrumentation Applications.127 10.6 High Integrity, Aerospace, Medical .127 11 XC166 XC166 Compatibility With Other Architectures 12 12.1 12.1.1 12.2 12.2.1 12.2.2 12.3 12.3.1 12.3.2 12.3.3 12.3.4 12.3.5 12.4 12.4.1 12.4.2 Mounting XC166 XC166 Family Devices On PCB's 131 Package Types .131 Table Of Common XC166 XC166 Derivatives.131 Connecting Emulators To XC166 XC166 Family Devices .131 Socketed Devices .131 Debugging XC Family Applications.132 Connecting An In-Circuit Emulator.133 The QuadConnect .133 Yamaichi Socket .134 The Solder-In Stack .134 Emulating Soldered-Down CPU's .134 "PressOn" Emulation Adaptors .135 XC166 XC166 Family PCBs .136 Grounding Arrangements.136 Electromagnetic Compatibility (EMC) .136 13 13.1 13.1.1 13.2 13.3 13.3.1 13.3.2 13.3.3 13.3.4 Getting New Boards Up-And-Running 138 Useful Equipment .138 (Almost) Free TantinoXC JTAG Debugger .138 Before Applying Power.139 Testing The Board .139 External Start Applications.139 Using Serial Bootstrap Mode And MINIMON To Test New Boards .140 Using JTAG For Testing New Boards.142 Common External Bus Problems.145 Insiders Guide 8 129 V1.0, 2006-02 An Insiders Guide to Planning XC166 XC166 Family Designs 13.4 13.5 Internal Start Designs .145 Testing The System.145 14 Conclusion 147 15 Acknowledgements 147 16 Feedback 147 17 Further Reading 147 18 Contact Addresses 147 19 Appendix 1 - Infineon XC166 XC166 Family Part Numbers 150 20 20.1 20.2 20.3 Appendix 2 ­ Pinout Of Common XC166 XC166 Derivatives 152 XC167CI XC167CI Pinout .152 XC161CJ XC161CJ Pinout .153 XC164Cx Pinout .154 Insiders Guide 9 V1.0, 2006-02 An Insiders Guide to Planning XC166 XC166 Family Designs Insiders Guide 10 V1.0, 2006-02 An Insiders Guide to Planning XC166 XC166 Family Designs 1 RISC Architectures For Embedded Applications 1.1 Introduction RISC microcontrollers are becoming increasingly popular. The C166S C166S V2 CPU core used in the XC166 XC166 series makes extensive use of Reduced Instruction Set Computer (RISC) concepts to achieve its blend of very high performance at modest cost. To understand why RISC techniques are especially suited to high-speed real time embedded systems, it is useful to examine in detail how they grew out of the traditional Complex Instruction Set Computers (CISC) that reached their peak in the late 1980's to mid 1990's. However despite the many inherent advantages of RISC for microcontroller applications, not all RISC microcontrollers fully exploit them for legacy reasons. This section examines some of the critical issues. 1.2 Behind The C166S C166S V2's Near-RISC Core The quest for ever-greater throughput has been the reason behind the abandonment of traditional Complex Instruction Set Computers (CISC). The demands of workstations involved in CAD tasks and latterly, advanced video games, have been the real driving force behind this. Traditionally, microprocessors have been designed with assembler instruction sets that have been geared towards making the assembler programmer's life easier through the extensive use of microcode to produce ever more powerful instructions. By providing single assembler instructions that perform, for instance, three-operand multiplication, the assembler programmer (and HLL compiler writer) has been relieved of the job of achieving the same result with simpler instructions. As the CPU needs to be able to recognize and act on (decode) many hundreds of different instructions, it requires complex silicon and many clock cycles. The greater the silicon area, the greater the cost of the device and power consumed. With physical limitations acting to restrict achievable clock speeds on silicon devices, the number of cycles per instruction is obviously very significant in gaining higher performance. RISCs tend to shift the burden of programming from the microcoder to the assembler programmers and compiler writers. Work within academia and commercial manufacturers has proved that a suitably-programmed RISC machine can achieve a far higher throughput than a CISC for a given clock speed. Strangely, the mid-range embedded world has been slow to question the suitability of the CISC-based microcontroller. At the very top end, RSIC devices such as ARM9, MIPS and Hyperstone provide stiff competition to the conventional CISC PowerPC and Pentium but for more commonplace embedded tasks, RISC is still relatively uncommon. With the increasing complexity of modern control algorithms, the need for greater processing power is set to become an issue in anything but the simplest applications. In addition, here more than in the workstation world, the worst-case response time to non-deterministic events is crucial, an area where CISCs are especially poor and where most ARM-based RISCs are by no means outstanding. Many current mid-range 16-bit microcontrollers are based on existing CISC architectures such as the S12, H8, M16C etc., which in common with 8-bit devices such as the 8051, have an internal structure that dates back 20 years or more. With the silicon vendor's need to give existing users an upgrade path, apparently new CPU designs are often based closely on the existing architecture/instruction set, so protecting the user's investment in expensive assembler code. Like workstations, microcontrollers are programmed in a high level language (HLL) to reduce coding times and enhance maintainability. Inevitably, even with the best compilers, some loss of performance is encountered, emphasizing again the need for improved CPU performance. In addition to straightforward data processing, microcontrollers must also handle real-world peripherals such as A/D converters, PWMs, timers, Ports, PLLs etc., all of which require real time processing and fast interrupt response. Insiders Guide 11 V1.0, 2006-02 An Insiders Guide to Planning XC166 XC166 Family Designs 1.2.1 Conventional CISC Bottle-necks 1. Long And Unpredictable Interrupt Latencies Complicated "labour-saving" instructions must hold the CPU's entire attention during execution, thus preventing real-world generated interrupts from being serviced. Unpredictable latency times result, which can cause serious problems in hard real-time systems. One approach to overcoming the CISC's poor real-time response has been to bolt a secondary "time processor unit" or other such auxiliary processor onto the core to try and off-load the time-critical portions. However, this results in an awkward design and the need to use a very terse microcode to program it, in addition to the more usual C and assembler for the CISC core itself. 2. Vast Instruction Sets Give Slow Decoding Loaded instructions must be recognised from potentially many hundreds or even thousands of possibilities. Decoding is thus complicated and lengthy. 3. Frequent Accesses To Slow Memory Devices Data is typically fetched from off-chip memory and placed in accumulator-type registers. Mathematical or logical operations are performed and the then is result written back to memory. The value is likely to be required again in the course of the procedure, thus requiring further movements to and from off-chip memory. 4. Slow Procedure Calling When calling subroutines with parameters (essential in good HLL programming), parameters must be individually pushed on to stack. They must then be moved through accumulator register(s) for processing before being returned via stack to caller. 5. Strictly One Job At A time Each peripheral device or interrupt source must have a dedicated service routine which at the very least will require the PSW and PC to be stacked and restored and data removed from or fed to the peripheral device. 6. Software Has To Be Structured To Suit Architecture. Embedded systems frequently contain many separate real time tasks which together form a complete system. Conventional CPUs make switching between tasks slow. Often, many registers have to be stacked to free them up for the incoming task. This problem is aggravated by the use of HLL compilers which tend to use a large number of local variables in library functions which must be preserved. 7. Redundant Instructions And Addressing Modes With the almost universal use of high level languages, compilers are tending to dictate which instructions should be provided in silicon. In practice, compilers tend to only make use of a small number of addressing modes. This results in a large number of unused addressing modes that serve only to complicate the opcode decoding process. 8. Inconsistent Instruction Sets Instruction sets that have evolved tend to be difficult to use due to large number of different basic types and the inconsistent addressing modes allowed. 9. Bus Not Fully Utilised Whilst complex instructions are being executed, the bus is idle. Insiders Guide 12 V1.0, 2006-02 An Insiders Guide to Planning XC166 XC166 Family Designs 1.3 The RISC Architecture For Embedded Control To show how RISC design is used to improve microcontroller throughput, the C166S C166S V2 is used as an example. Basic Definitions: 1 state time = 1/oscillator frequency - fundamental unit of time recognised within processor system. 1 machine cycle = state time - minimum time required to perform the simplest meaningful task within CPU. The unit of state times is used when making comparisons between RISCs and CISCs as this removes any dependency on clock frequency. - All state time counts are given in single chip operation mode for both S12X and C166S C166S V2. 1.3.1 Bus Interface To maximise the rate at which instructions are executed, RISC CPUs are very heavily pipelined. Here, on any given machine cycle, up to 4 instructions may be processed by overlapping the various steps. Simplified for clarity, the stages are: FETCH: DECODE: EXECUTE: WRITE-BACK: - get opcode from program store - identify opcode from a small list and fetch operands - perform operation denoted by opcode - result returned to specified location Thus although the instruction takes four machine cycles, it is apparently executed in just one (1 state time). Pipelining has considerable benefits for speeding sequential code execution as the bus is guaranteed to be fully occupied. Some more advanced RISC devices (like the C166S C166S V2) add an extra ADDRESS stage to make a total of 5 pipeline stages and also add a 2-part "PREFETCH" unit: Instruction Fetch Unit (IFU) PREFETCH: - Get instructions from the program memory in the order predicted. Any branches are detected and prediction logic decides if the branches will be taken or not. FETCH: Pipeline Unit DECODE: ADDRESS: MEMORY: EXECUTE: WRITE BACK: - The address of the next instruction to be fetched is calculated using the branch prediction rules. - The instructions are decoded and, if required, the register file is accessed to read the GPR used in indirect addressing modes. - All the operand addresses are calculated. - All the required operands are fetched from RAM and registers. - perform the operation denoted by opcode - result returned to specified location This theoretically gives a doubling in performance on straight-line code. However even though there is a branch prediction unit to minimise the loss of performance caused by branches in real programs, not quite twice the throughput can be achieved. Insiders Guide 13 V1.0, 2006-02 An Insiders Guide to Planning XC166 XC166 Family Designs 1.3.2 RISC Interrupt Response In the C166S C166S V2 core, branches to interrupts make use of the injected instruction technique and so vectoring to a service routine is achieved in only 5 machine cycles. The effect of complex but necessary instructions such as MUL and DIV (1 and 21 cycles respectively) stretch this but it is interesting to note that the C166S C166S V2 does provide the DIV as a partially-interruptible instruction. The first 4 cycles lock out all interrupts but the remaining 17 cycles may be interrupted. Very fast interrupt service is crucial in high-end applications such as engine management systems, servo drives and radar systems where real-world timings are used in DSP-style calculations. As these normally form part of a larger closed control loop, erratic latency times manifest themselves as an undesirable jitter in the controller output. 1.3.3 Registers And Multi-Tasking Traditional microcontrollers have one or more special registers that can be used for mathematical, logical or Boolean operations. In the 8051, there is a single "accumulator" with 8 other registers which may be used for handling local variables or intermediate results in complex calculations. These additional registers are also used to access memory locations via indirect and/or indexed addressing. As pointed out in items 3 and 4 above, conventional CPUs spend much time moving data from slow memory areas into active registers. The RISC CPU offers a very large number of general purpose registers which may be used for locals, parameters and intermediates. The C166S C166S V2 provides 16 word-wide general purpose registers (GPRs), each of which is effectively an accumulator, indirect pointer and index. With such a large number of GPRs available, it becomes realistic to keep all locals and intermediates within the CPU throughout quite large procedures. This can yield a great increase in speed. Further significant benefits are derived from the RISC technique of register windowing. As has been said, up to 16 registers are available for use by the program. However, by making the active register bank movable within a larger on-chip RAM, the job of real-time multi-tasking is considerably eased. Central to this is the concept of a "Context Pointer" (CP), which defines the current absolute base address of the active registerbank in the program memory space. Thus a reference to "R0" means the register at the address indicated by the CP (typically address 0xFD00). Thereafter, the 16 registers originating from CP are accessed by a fast 4-bit offset. The best example of how the CP is exploited is perhaps a background task and a real-time interrupt co-existing. When the interrupt occurs, rather than pushing all GPRs onto the stack, the CP of the current register bank is stacked and simply switched to a new value, determined at link time, to yield a fresh register bank. This results in a complete context switch in just one instruction but it does rule out the use of recursion. A hybrid method, which permits re-entrancy, uses the stack pointer to calculate the new CP dynamically. Here, on entering the interrupt, the number of registers now required is subtracted from the current SP and the result placed in CP, with the old CP stacked. Thus the new register bank is located at the top of the old stack, with the old CP and then the new stack following on immediately afterwards. On exiting the interrupt routine, the original registerbank is restored by POPping the old CP from the stack. The SP is reinstated by adding the size of the new register bank onto the current SP. Insiders Guide 14 V1.0, 2006-02 An Insiders Guide to Planning XC166 XC166 Family Designs A further RISC refinement is register window overlapping whereby when a new procedure is called, part of the new register bank defined by CP is coincident with the original at CP: CP' CP R7 R6 R5 R4 R3 R2 R1 R0 R3' R2' R1' R0' ; Register for subroutine's locals and intermediates ; Register for subroutine's locals and intermediates ; Common register, R7 = R1' ; Common register, R6 = R0' ; Register for caller's locals and intermediates ; Register for caller's locals and intermediates ; Register for caller's locals and intermediates ; Register for caller's locals and intermediates ; Register for caller's locals and intermediates ; Register for caller's locals and intermediates MODULE 1 ; * Assignment Of GPRs To Local Variables - Caller * x_var y_var LIT LIT `R0' `R1' ; Local variable ; Local variable parm1 parm2 LIT LIT `R6' `R7' ; Passed parameter 1 ; Passed parameter 2 result LIT `R6' ; Value returned from sub routine ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ MODULE 2 ; * Assignment Of GPRs To Local Variables - Sub Routine * a_var b_var LIT LIT `R2' `R3' ; Local variable ; Local variable input1 input2 ret1 LIT LIT LIT `R0' `R1' `R0' ; Received parameter 1 ; Received parameter 2 ; Final result returned in R0 Fig. A - Giving GPRs Meaningful Names The programmer should plan for any value to be passed to the subroutine to be located in the common area, so that all the normal loading and unloading of parameters is avoided. This technique can be used in either absolute or SP-relative registerbank modes. Insiders Guide 15 V1.0, 2006-02 An Insiders Guide to Planning XC166 XC166 Family Designs The ability to switch to a new set of working registers by changing the context pointer register is useful when responding to interrupts, as it avoids the need to save the current registerbank contents before executing the service routine instructions. This can be time-consuming if all 16 registers are to be saved. Typically this requires one instruction (here a switch context "SCXT ") at the start of the interrupt routine to change the registerbank base and a second instruction at the end to restore the original one. R15' 0xFD20 R0' 0xFD20 0xFD20 R15 R15 R0 0xFD00 CP = 0xFD00 Background 0xFD00 CP = 0xFD20 Interrupt Service R0 0xFD00 CP = 0xFD00 Background Another method possible on some RISC devices relies on "alternative" register sets that become visible when a predefined interrupt source is activated, so that no saving of current register contents is required. ARM7-TDMI RISC devices typically replace the upper 8 registers in the registerbank when the FIQ (Fast Interrupt reQuest) fires, whereas the C166S C166S V2 has two complete "local" banks of sixteen registers that can be made to appear when either of two interrupt sources is triggered. Unlike conventional registerbanks, these registers do not usually exist in the normal memory space of the CPU and so no context switching is required, thus saving time1. To get the best from a RISC's registers, the location of data needs close consideration: although highly orthogonal, the limited number of addressing modes provided for MUL and DIV for example, can appear somewhat restrictive. Fortunately though, most operands involved will already be in registers, so eliminating the need for many addressing techniques. As might be expected, the instructions with the widest range of addressing modes are the simple data moves - the fact that RISCs are the result of very careful analysis of the requirements for fast execution becomes obvious after a short acquaintance! 1 In fact the current local registerbank is can be given a physical address and made visible by setting the appropriate bits in the BANK field of the PSW register. Insiders Guide 16 V1.0, 2006-02 An Insiders Guide to Planning XC166 XC166 Family Designs 1.3.4 Coping With RISC Instruction Set (Apparent) Omissions With largely single machine cycle execution, some conventional "fast" instructions such as CLEAR, INC and DEC become redundant. Therefore, to keep the total number of instructions to a minimum, RISCs simply omit them. Examples are given below: Instruction 80C196 80C196 States C166S C166S V2 States -Clear Word CLR 4 AND Rn,#0 2 Decrement Word DEC 4 SUB Rn,#01 2 Increment Word INC 4 ADD Rn,#01 2 - all direct addressing mode Three-operand instructions are also commonplace in CISCs but not present in RISCs. Although additional instructions are required, the overall number of states is still less than the three-operand CISC equivalent, plus the shorter RISC instructions allow greater opportunity for interrupt servicing. The following example illustrates this: Perform: z = x + y 80C196 80C196 (CISC) z, x and y are directly addressed memory locations x y z DW DW DW 1 1 1 ADD z,x,y ; 5 states - no interrupt possible C166S C166S V2 (RISC) z, x and y are memory locations, Rw is a GPR x y z DW DW DW 1 1 1 MOV Rw,x ADD Rw,y MOV z,Rw ; ; ; ; ; ; ; 2 states * Interruptable here 2 states * Interruptable here 2 states - 6 states One extra state required when using RISC approach. Insiders Guide 17 V1.0, 2006-02 An Insiders Guide to Planning XC166 XC166 Family Designs However, if the variables are assigned recognising that this is a RISC: x and y are memory locations, z is a GPR x y DW DW 1 1 z LIT `R0' ; z is assigned to GPR R0 via a LITeral definition MOV z,x ADD z,y ; ; ; ; ; 2 states * Interruptable here 2 states - 4 states - 1 state saved over CISC. The above was chosen as a worst case RISC, best case CISC example. For a normal 2 operand ADD, the RISC uses two states compared to the CISC's 4, a 50% improvement. - Assigning all variables to GPRs would probably make sense in the context of a real program. - This trivial example shows how familiarity with RISC's programming techniques improves performance. 1.4 RISC And Real World Peripherals Within the workstation or desktop computer RISC, superscalar operation allows parallel execution of instructions, made possible by having discrete addition, multiplication, shift and other dedicated units, each with their own pipelines. No RISC microcontroller (yet) quite offers this (although the 32-bit Tricore is heading this way) but something similar is possible to service on-chip peripherals such as an A/D converter. A common situation occurs in conventional microcontrollers whereby some regular event requires attention from the CPU to load or unload data. Typically, an A/D converter will cyclically read a number of channels, causing an interrupt when completed or simply waiting for the CPU to poll its status. The net result is the valuable CPU time is spent doing what even for a microcontroller is a simple, repetitive task. The RISC C166S C166S V2 allows the interrupt service routine to be serviced and completed in a single machine cycle (via the "Peripheral Event Controller", described in section 8.4). In the case of a periodic A/D conversion, on each conversion the result from the "ADDAT" register is stored in a table from where the readings may be later retrieved by the CPU. This mechanism requires the CPU to perform only a one single-cycle instruction equivalent to "MOV [table_addr+],ADDAT" after each conversion. At the end of the table, a traditional interrupt routine is required to reset the table pointer to permit another series of conversions and automatic result transfers. Any real-world generated data can be handled in this way, leaving the CPU free for data processing rather than simple data collection. For many applications, a close coupling between the CPU and IO pins is useful for the detection and generation of real time pulses. Traditional RISC CPUs often have lengthy and unpredictable delays between for example, software setting a port pin and the actual pin changing state. For input, the reverse situation applies. Such delays are caused by the RISC core not being adapted to hard real-time use and communicating with peripherals through the VLSI (very large scale integration) bus. The C166S C166S V2, being designed as a real-time controller does not suffer from this kind of problem and there is a direct connection between the CPU core and the peripheral set. Insiders Guide 18 V1.0, 2006-02 An Insiders Guide to Planning XC166 XC166 Family Designs 1.4.1 RISC Benefits In Embedded Applications 1. Near-DSP throughput For example, the XC166 XC166 can achieve 20 million instructions per second (20MIPS 20MIPS) at a 20MHz clock (50ns machine cycle time). At 40MHz this rises to 40MIPS 40MIPS with a 25ns cycle time. This is a result of pipelining and the ability to contain the active data for entire procedures within the CPU registers. 2. Simpler Assembler Coding Although the instruction set is less diverse, the consistency of addressing modes makes assembler coding easier. 3. Very Fast Response To Non-Deterministic Events By eliminating instructions that take many cycles, interrupt response is improved. Smaller instructions effectively yield higher "sampling rate" for real world events. 4. Single Machine Cycle Context Switching By careful use of multiple register banks controlled by a base pointer, context switching in a multitasking system can be performed in just one instruction. In addition, parameter passing overhead to subroutines is eliminated by use of overlapping register windows, so that parameters lie in the common area. 5. Alternate or Local Registerbanks By planning the use of interrupts carefully, zero-time context switching is possible. Insiders Guide 19 V1.0, 2006-02 An Insiders Guide to Planning XC166 XC166 Family Designs 1.5 Traditional RISC v New RISC Although RISC is inherently conducive to fast interrupt response/low latency, the legacy of having RISC designs with their roots in 1980s desktop computers means that although the handling of single interrupts may be fast and reasonably deterministic, with interrupt-intensive applications, some problems can be experienced. Interrupt systems have changed a lot since the days of a single IRQ input with multiple sources requesting interrupt service through it. Here the single interrupt vector required the user to check the source of the interrupt before servicing it. This ruled out the nesting of interrupts with the result that in systems with significant interrupt activity, effective latency times could become very long and completely unpredictable, despite the very high straight line speed of the CPU core. Interrupt sources ADC // // Non-Vectored Interrupt Service Routine // Timers void NonVectoredIRQ (void) _attribute_ (interrupt("IRQ") { // Test for the interrupt source SPI IRQ CPU Pipeline UART If(VICIRQStatus & 0x00008000) { // Set the LED pins IOSET1 = 0x00FF0000; // Clear the peripheral interrupt flag EXTINT = 0x00000002; } // Dummy write to signal end of interrupt VICVectAddr = 0x00000000; Interrupt Request Handling in 1980's Style RISC CPU However, many traditional RISC CPUs still have interrupt management of this type (or some variation of it) which unfortunately negates the inherent advantages of fast interrupt response conferred by the RISC approach. The net effect is that although the best-case interrupt latency is good, the worst case figure is almost impossible to predict. Thus it cannot be taken for granted that all RISC microcontroller CPUs will be suitable for hard real-time systems. Insiders Guide 20 V1.0, 2006-02 An Insiders Guide to Planning XC166 XC166 Family Designs Later RISC devices like the C166S C166S V2 use a more up to date approach to interrupt handling, designed to make best use of the RISC inherently short interrupt latencies. Here interrupt sources can be freely assigned to up to 15 different levels, which are prioritised to allow full interrupt nesting. This allows the short interrupt latency times permitted by RISC to be fully exploited and both the best and worst case latencies can be estimated with a high degree of certainty. Interrupt sources IRQ0 ADC UART Timers IRQ2 void timer3_int(void) interrupt 0 {} IRQ1 IRQ3 CAPCOM PWM I2C IRQ4 CPU Pipeline SPI void serial_rx_interrupt(void) interrupt 1 {} void RS485 RS485_timeout(void) interrupt 2 {} void serial_tx_interrupt(void) interrupt 3 {} void communication_timeout(void) interrupt 4 {} void timer1_int(void) interrupt 5 {} IRQx void trip_period_interrupt(void) interrupt 6 {} Interrupt Request Handling In The XC16x RISC CPU Insiders Guide 21 V1.0, 2006-02 An Insiders Guide to Planning XC166 XC166 Family Designs Insiders Guide 22 V1.0, 2006-02 An Insiders Guide to Planning XC166 XC166 Family Designs 2 Getting Started With The XC166 XC166 2.1 Basic Considerations 2.1.1 Family Overview The XC166 XC166 family currently includes three main variants, the XC161 XC161, the XC164 XC164 and the XC167 XC167, although with different memory and peripheral options this adds up to considerably more in reality. According to the XC166 XC166 th User Manual, the XC family is the 4 generation of Infineon's 16-bit Microcontroller. The first family member was the 80C166 80C166, available in masked ROM, FLASH EPROM (88C166 88C166) and ROMless versions. The second member was the C167 which had an expanded addressing capability, integral chip selects plus many more peripherals and introduced some new assembler instructions. The third generation added flexible power management. Although the XC is binary compatible with the C167 (`Classic 167'), many enhancements have been made to increase performance. The XC166 XC166 family uses the C166S C166S V2 core which includes a number of important enhancements. The MAC-unit adds DSP-functionality to handle digital filter algorithms and greatly reduces the execution time of multiplications. The 5-stage pipeline, single-cycle execution of most instructions, and PECtransfers within the complete addressing range increase system performance. Debugging the target system is supported by integrated functions for On-Chip Debug Support (OCDS). The other major enhancement is the addition of full automotive spec on-chip FLASH. 2.1.2 Fundamental Design Factors When starting out on a XC166 XC166 family design, there are a number of basic things you must decide. Wrong decisions here can have expensive consequences later in the project. There are a good many features of the architecture that can be a bit puzzling to those used to conventional devices. What follows is a simple guide to what you really need to know to get the best from this ingenious and powerful microcontroller family! · · · · · · · · · · · · · · · · · What clock speed is required to achieve the necessary CPU processing power? What sort of clock source is suitable? What sort of reset circuit should be used? What CPU sockets are available How is the CPU configured? Will the CPU boot into internal or external ROM? How is the on-chip FLASH EPROM to be programmed? How is external FLASH EPROM to be programmed? How can any external memory be added? Is a full 16-bit external bus necessary or will an 8-bit bus be sufficient? Is an external bus required at all? Will there be some external peripheral chips that will require different bus modes? How much IO is required to implement the application? Should WRH/WRL be used? Should the chip selects be used? Which peripheral pins are best allocated to the various different signal processing or generation functions in the application? And many others. 2.1.3 Setting The CPU Hardware Configuration Options In common with many modern microcontrollers, between the /RESIN pin going high and the rising edge of the first ALE pulse, the XC reads its start up configuration. This is read from one of two places depending on whether the processor is booting from internal or external memory. This is determined from the level of the /EA pin at start up. If /EA is High, then the processor will boot from internal memory. In this case the startup configuration is read from the RD, WR and ALE pins. With only three pins available, only a minimum configuration can be achieved, the configuration is completed in software during the start up. Insiders Guide 23 V1.0, 2006-02 An Insiders Guide to Planning XC166 XC166 Family Designs The following settings are available for an internal start: * * * Boot from the standard or alternate reset vector Enable the standard or alternate bootstrap mode Use P20.12 as either /RSTOUT or GPIO If /EA is Low, then the processor will boot with the external bus enabled. The configuration is read from the bit pattern on Port 0 to determine the following fundamental settings: * * * * * * * What the default bus mode is How many pins on port 6 should be used as chip selects How many segment address lines should be used Whether the on-circuit emulation mode is to be entered Whether the WRITEHIGH/WRITELOW mode required Whether the BOOTSTRAP mode is to be activated What clock factor is to be used The pattern is placed onto the port by the user attaching pull-down resistors to the appropriate pins. For example, to get the processor booting from internal memory and in bootstrap mode, /EA will be High and /RD will need to be pulled Low through a resistor. To set 16 bit non-multiplexed bus mode from an external start, /EA will be Low and a pull-down resistor is added to Port 0.7, while Port 0.6 floats high. The values of the pull-down resistors should be calculated with reference to the overall loading on Port 0, from external memory devices etc., using the formulae given in section 2.2. The value required for a typical 1 EPROM + 1 RAM system is 8K0, this representing the stated maximum value. It covers 90% of all designs seen to date. In extreme cases, as little as 1K8 can be used but this is exceptional as the leakage currents from modern memory devices are extremely small. Overall, the user is simply advised to check the situation in the design and not to just to blindly accept the usual 4k7 value! Note: The databooks frequently refer to port 0 either as a 16-bit port or as two 8-bit ports, made up of Port 0L (LOW) and Port 0H (HIGH). Thus Port 0.15 is bit-16 on port 0 which is also Port 0H.7. By the same convention, Port 0.7 is also known as Port 0L.7. Insiders Guide 24 V1.0, 2006-02 An Insiders Guide to Planning XC166 XC166 Family Designs 2.2 Calculating The Pull-Down Resistor Values Finding the value of the pull-down resistors for your design is fairly straightforward. You will need to know the leakage current from the devices such as RAMs, ROMs etc that are attached to the bus. input leakage current input current Vcc RESET IP0L >= 100uA I SYSL Port 0 I PD R PD VIN = VILMAX System. XC16x Pull-Down Resistor Current Flow VILMAX = Highest voltage that will be accepted as a `0' ISYSL = Leakage current from RAMs, ROMs etc. IP0L = Current flow from XC166 XC166's Port 0 when pin is at VILMAX RPD = Pull down resistor on Port 0 From XC166 XC166 Datasheet: VILMAX = (0.2 x Vcc) - 0.1V => 0.8V 4.5V =< Vcc =< 5.5V Pull Down Resistor Calculation RPD < VILMAX = IPD VILMAX IP0L + ISYSL Example Without System Leakage Current, ISYSL: RPD < VILMAX = 0.8V IP0L 100uA = 8K0 Thus the maximum recommended value is RPD = 8K0. In practice, 5K6 to 8K2 is almost always used, the former value taking account of typical leakage currents from memory devices on the bus. Insiders Guide 25 V1.0, 2006-02 An Insiders Guide to Planning XC166 XC166 Family Designs 2.2.1 Pull-Up Resistor Calculations In some designs, the loading on the bus can be such that there is a net flow of current into the external devices to ground, i.e. the bus sinks current. In extreme cases, this can cause the Port 0 pattern read by the XC166 XC166 to be incorrect. It must be stressed that this is very rare but can easily be compensated for by using a high-value pullup resistor. Such measures are only required if the current sunk into the external device ISYSH, is greater or equal to 10uA. Before finalising any design the condition should be checked for and a pull-up resistor added if necessary. The procedure for calculating the pull-up resistor is as follows: Vcc input leakage current input current Vcc R PU RESET I PU IP0H 1.8V 4.5V =< VCC =< 5.5V Pull Up Resistor Calculation RPu < VPU IPD = VCCMIN - VIHMIN ISYSH - IP0H Example: ISYSL = 50uA RPU < 4.5v - 1.8v 50uA - 10uA Insiders Guide = 67.6K 26 V1.0, 2006-02 An Insiders Guide to Planning XC166 XC166 Family Designs 2.3 Start-Up Configuration 2.3.1 Internal Start Configuration If /EA is High, the processor boots from internal memory. This diagram shows the possible configuration functions: /EA 1 /RD 0 ALE 0 /WR 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 Description Standard start, ASC0 bootloader enabled (Addr. C0'0000H 0000H), use P20.12 as GPIO Standard start, ASC0 bootloader enabled (Addr. C0'0000H 0000H), use P20.12 as RSTOUT Alternate start (CAN) bootloader enabled (Addr. C1'0000H 0000H), use P20.12 as GPIO Alternate start (CAN) bootloader enabled (Addr. C1'0000H 0000H), use P20.12 as RSTOUT Standard internal Start (Addr. C0'0000H 0000H), use P20.12 as GPIO 1 1 0 1 Standard internal Start (Addr. C0'0000H 0000H), use P20.12 as RSTOUT 1 1 1 0 Alternate internal Start (Addr. C1'0000H 0000H), use P20.12 as GPIO 1 1 1 1 Alternate internal Start (Addr. C1'0000H 0000H), use P20.12 as RSTOUT All other startup configuration initially defaults to a `safe' worst case mode. The clock generation in bypass mode with a 2:1 factor ensuring proper operation for the defined input frequency range of up to 50MHz. The RSTCFG register default vale is 0x0DFF. Changes to this configuration can be made in software. Another consideration that should be made is with regard to the /EA pin itself. Although this pin needs to be High for internal start, the recommendation is that this should be pulled high through a resistor rather than being connected directly to the rail. This is discussed in more detail in chapter 11, but should it become necessary to connect a full in-circuit emulator to a board, the emulator will need to be able to pull /EA low. In the majority of XC166 XC166 designs, the internal start mode should be used. If an external bus is required then this can be enabled through software running from the internal FLASH. Insiders Guide 27 V1.0, 2006-02 An Insiders Guide to Planning XC166 XC166 Family Designs 2.3.2 External Start Configuration This diagram gives the individual configuration functions of the Port 0 pins when the CPU is between the end of reset and the rising edge of the first ALE: P0.15 P0.7 P0.0 P0H.7 P0L.7 P0L.0 CLKCFG Clock Generator 11 10 9 SASEL CSSEL Port 4 Logic 8 7 Port 6 Logic 6 5 4 3 2 SMOD BUSTYP 1 0 EMU 12 ADP 13 BSL 14 WRC 15 Bootstrap mode select EBCMOD0 FCONCS0 XC16x Special Function Registers Port 0 Pin Functions ­ RSTCFG Register Layout ROC - When pulled Low, /RSTOUT is deactivated automatically at the end or reset, otherwise it is deactivated by user software ADP - On-circuit emulation mode puts all the XC's pins into a high-impedance tristate condition so that an emulator's clip-over adaptor can be attached to a soldered-in device. Note that if the clock source is a crystal, pin XTAL2 must be disconnected from the processor so that the emulator's CPU can pick up the clock. DO NOT FIT A PULL DOWN RESISTOR ON THIS PIN! SMOD - Special Modes for bootstrap loader P0L.5 P0L.4 P0L.3 P0L.2 Boot Mode 0 1 1 1 Alternate start ­ 0xC10000 1 0 0 1 Alternate TwinCAN bootstrap mode ­ 0xC10000 1 0 1 1 Standard ASC0 bootstrap mode ­ 0xC00000 1 1 1 1 Standard start (default) ­ 0xC00000 1 0 0 0 Alternate SSC0 bootstrap mode ­ 0xC00000 All other combinations are reserved for future use. BUSTYP - The external bus type can be set as shown below. These two pins form the BUSTYP field in the FCONCS0 special function register, where it can be modified by software. P0L.7 0 0 1 1 WRC Insiders Guide P0L.6 0 1 0 1 External Bus Mode 8-bit non-multiplexed 8-bit multiplexed 16-bit non-multiplexed 16-bit multiplexed (default) - Cause the /WR pin to become /WRH (write high) and /BHE to become /WRL (write low) to make the use of 8-bit RAMs in a 16-bit system easier. See section 4.2. 28 V1.0, 2006-02 An Insiders Guide to Planning XC166 XC166 Family Designs CSSEL - The number of chip selects that are to be enabled on Port 6 (or Port 4 on the XC164 XC164) P0H.2 0 0 1 1 SALSEL P0H.3 0 1 0 1 Segment Address Lines On Port 4 Four: A16 - A19 None: Eight: A16 - A23 Two: A16, A17 (default) - Programming for processor clock input, with optional phase lock loop (PLL) clock multiplier. P0H.7 0 0 0 0 1 1 1 1 Insiders Guide Chip Select Lines Three: /CS2, /CS1, /CS0 Two: /CS1, /CS0 None: Four: /CS3, /CS2, /CS1, /CS0 (default) - Number of "segment address" lines, i.e. how many additional address lines above A15 will be enabled. P0H.4 0 0 1 1 CLKCFG P0H.1 0 1 0 1 P0H.6 0 0 1 1 0 0 1 1 P0H.5 0 1 0 1 0 1 0 1 Clock Generator fmc = fosc /2, fmc = fosc x 2.5, fmc = fosc x 2.5, fmc = fosc, fmc = fosc x 5, fmc = fosc x 2, fmc = fosc x 4.5, fmc = fosc x 3, 29 Frequency Multiplier Control fosc = 1 ­ 50MHz fosc = 12 ­ 16MHz fosc = 8 ­ 12MHz fosc = 1 ­ 40MHz fosc = 4 ­ 6MHz fosc = 12.5 ­ 18.7MHz fosc = 5.6 ­ 8.3MHz fosc = 8.3 ­ 12.5MHz (default) V1.0, 2006-02 An Insiders Guide to Planning XC166 XC166 Family Designs 2.4 Reset Control The XC family has two reset pins, /RSTIN and /RSTOUT. The former is a conventional active-low reset input while /RSTOUT is an output, the operation of which is configurable. For single chip applications /RSTOUT will probably not be needed and consequently can be configured as a general purpose IO pin. If it is being used, it will go low at the same time as /RSTIN and stays low either by software when the CPU executes the EINIT (end-ofinitialisation) instruction, or until it is deactivated automatically at the end of the internal reset. /RESOUT is thus a means of keeping peripheral devices in a reset state until the CPU is fully initialised. The /RESIN input must be kept low until the power supply has reached 2.25v for the Vddi rail and 4.5v for Vddp. Once stable, any low level on /RSTIN of more than two state times (50ns @ 40MHz) will reset the CPU. Low times of less than this must be avoided. The pin has no internal pull-up resistance, so the simplest reset circuit is a pull up resistor and a capacitor to ground. The value must be chosen to give a time constant long enough for the power supply to stabilize. However, such a simple arrangement is not suitable for use in those situations where the power supply could suffer from instability or brown-outs. In most commercial products, the use of a proper microprocessor power supply and RESET manager such as the TLE7469 TLE7469 is highly recommended. This device provides both the 5v and 2.5v supplies and the CPU's RESET. VDD 50K - 250K /RESIN RESET 22uF XC16x GND Very Simple Reset Scheme Insiders Guide 30 V1.0, 2006-02 An Insiders Guide to Planning XC166 XC166 Family Designs 2.5 Clock Speeds And Sources The basic unit of time in the C166S C166S V2 core is a single state time, corresponding to 25ns at 40MHz. Most instructions execute in one state time, i.e. 25ns. Oscillator modules must have a rise and fall time of better than 8ns. The XC166 XC166 is equipped with a PLL system to generate the clock from an external crystal. Exactly how this is handled is determined by the boot mode. The PLL has a series of multipliers and dividers which can be configured by the user directly via the PLL control registers or indirectly via the top three Port0H configuration bits. PLL PLL Lock OSC VCO P:1 K:1 1:N Bypass P = PLLIDIV + 1 N = PLLMULL + 1 Testmode K = PLLODIV + 1 Internal Clock Distribution Scheme The output frequency fPLL is calculated as: fPLL = fosc * N/(P * K) This signal is then used to drive the whole XC166 XC166 device. The only notable exception is the real time clock, which may be driven either from main system clock or the auxiliary oscillator. One Master clock period is known as "TCM". Insiders Guide 31 V1.0, 2006-02 An Insiders Guide to Planning XC166 XC166 Family Designs Master Clock PLL TwinCAN (LX Bus) CPU Core N:1 Peripherals (PD Bus) PLL Output Distribution To XC16x Modules The clock is distributed from the PLL as shown. The clock to the CPU and peripherals may be further divided by up to a factor of N = 2 using the CPSYS bit in the SYSCON1 register, although this is rarely necessary. Relationship between internal clocks fCPU = fPLL / N fSYS = fPLL / N fMC = fPLL 2.5.1 PLL Start Up The PLL will provide a stable clock even if there is no external crystal or oscillator fitted so that the CPU can run, albeit at a low frequency. In fact this clock is used until the PLL has synchronized to any external oscillator. The base frequency is selected in software by the PLL VCO band select (PLLVB field in PLLCON) which defaults to 20MHz. The K factor (PLL output divider) is set to divide by 16 under these conditions so that the CPU will be running at 3.75MHz. The PLL starts to run once the 2.5v rail reaches around 1.5v. It is running at 3.75MHz at this point and begins monitoring the incoming oscillator signal for stability over 2000 cycles before attempting to synchronize. If the processor is in bootstrap mode, there is an internal timeout of 30ms after which no further attempt to synchronize is made and the PLL remains at the base frequency. Under these conditions, Baud rates above 9600 are unlikely to work. PLL bypass mode can give very low clock speeds to reduce power consumption. Here just the K & P dividers are used to give a maximum division of 60. 2.5.2 External Bus Start There are very few cases where the XC166 XC166 would be started in external bus mode. In almost all cases, the internal start should be used! For external start, the state of Port0H pins are read coming out of RESET, as explained in the previous section. The value of the top three bits is used to form a value that is written into the RSTCFG register. This value is the used automatically to configure the clock multiplier. If the pins are not pulled-down then the multiplier is set to divide by 2, as with classic C167 devices. However when planning the pull-down resistor configuration, the user must make sure that the input crystal frequency is within the acceptable range for the required CPU frequency. For example, to use the x5 multiplier, the input frequency must be in the range of 4-6MHz (see the CLKCFG table in section 2.3.2). The reason for these limited ranges can be seen when the internal structure of the PLL is examined in detail ­ see below. Insiders Guide 32 V1.0, 2006-02 An Insiders Guide to Planning XC166 XC166 Family Designs The user may also select suitable values of P, K & N directly to get the required multiplier by changing the value of the PLLCON register. This procedure is covered in detail in the next section. 2.5.3 Internal ROM Start In this mode, the Port0H pins are not examined for any pattern and it is up to the user to set the clock multiplier manually. The default clock multiplier will be divided by 2 which typically means that on an 8MHz crystal, the CPU will only be running at 4MHz. This can have some side effects, such as preventing the on-chip bootstrap loader from being able to auto-baudrate-detect at greater than 19200 Baud. This is a problem if any FLASH programmer (such as MEMTOOL or FLASHXC.DLL) using the ASC0 bootstrap mode wants to run at 115200 Baud to minimize download time. Any change to PLLCON aimed at changing the clock multiplier will require the PLL to re-lock. This typically takes around 30us but a maximum of 200us is possible worst-case. Note that the values of K, N & P put into this register must have one subtracted from them i.e.: PLLMUL = N ­ 1 PLLODIV = K ­ 1 PLLIDIV = P - 1 Note: The input divider "P" must be at least 2 (divide by 2) if the input clock does not have a guaranteed 50/50 duty ratio. 2.5.4 Choice Of Clock Speed As the XC166 XC166 is really intended as a single-chip microcontroller with code storage in internal FLASH, there is no real reason to run at anything other than the full 40MHz permitted by current silicon. Access to external RAM and ROM may require waitstates (see chapter 3) but assuming that all time-critical code execution will be from internal FLASH then it makes sense to run as fast as possible. Generally the XC166 XC166 family needs 1 wait state for 40 MHz operation and 0 waitstates for 20 MHz operation. However there is an exception for XC166-32F XC166-32F devices which come into two versions ­ "Grade A" and "Standard". Grade A devices support 1 waitstate operation at 40 MHz and 0 waitstates at 20 MHz. Standard devices need an additional wait state (i.e. 2 waitstates) at 40 MHz and 1 waitstate at 20 MHz. The addition of the waitstate to the internal FLASH causes on average a 5-15% performance reduction in typical applications. The 5-stage pipeline combined with the 64-bit FETCH from the on-chip FLASH mean that up to 2 waitstates can be added without prejudicing throughput on linear code, any loss being due to the number of wrongly-predicted branches that will occur in real programs. If the system contains external FLASH then the number of waitstates is set independently using the external chip select control registers. Insiders Guide 33 V1.0, 2006-02 An Insiders Guide to Planning XC166 XC166 Family Designs 2.5.4.1 Choosing The N, K & P Values For any combination of oscillator frequency and required CPU frequency (Master Clock when CPSYS = 0), there are usually several combinations of K, P & N that will give the required result. The question is therefore how to choose the best combination of values. As the Master Clock is usually driven from the PLL, there is inevitably some jitter on the output as the PLL VCO is continuously adjusted to keep the frequency at the required value. The PLL design is such that abrupt changes in frequency are prevented but there is a small cycle-to-cycle variation in period (the jitter) that needs to be considered in the hardware design. 2.5.4.2 Implications of Jitter Jitter on the master clock can affect the timings of: · · · Memory accesses CAN bit period Peripheral timebase accuracy However in almost all situations the level of jitter from the XC166 XC166 PLL system extremely small but it still ought to be taken into account. The quality of the clock source also should be considered, as it is common for poorlydesigned crystal circuits (see later) to cause significant variation in the period-to-period timing. In extreme cases, a poor clock combined with a non-optimal choice of PLLCON parameters can cause transmission errors on the CAN peripheral. In addition, memory access calculations can be upset as the jitter can reduce the bus cycle time and thus increase the apparent clock frequency so that data is misread. Timing errors are less of a problem with peripherals such as the CAPCOM or ASC0 as they tend to deal with time periods in the microsecond to millisecond range. If the oscillator design is good and the K, N & P values properly chosen, then PLL jitter effects on the CAN module can be regarded as insignificant, although they still need to be examined in the light of any external bus devices that may be present in the design. As an example of how calculated memory access times must allow for PLL jitter, consider the jitter across one bus cycle: One bus cycle requires = 4 TCM (or TCP if the CPUSYS divider is 1). From the XC166 XC166 datasheet: Jitter (N)(ns) = +/-(1.5 + 6.32 * (N)/fMC) Where N = Number Of TCM's in period over which jitter is to be estimated. Note that this formula assumes that the highest possible K factor is used (output divider). For 4 TCM's at 40MHz, Jitter = +/-(1.5 + 6.32 * 4/40) Jitter = +/- 2.132ns Any other K value would increase jitter by an indeterminate amount. Therefore it is important to choose the highest possible K. Thus when calculating the bus timings, this 2.132ns must be added to the worst-case PhaseE. In addition, any oscillator tolerance must be allowed for in a similar way. This tolerance will be the sum of the frequency, temperature and the ageing tolerances and is typically not to be more than around 0.02% per period. Insiders Guide 34 V1.0, 2006-02 An Insiders Guide to Planning XC166 XC166 Family Designs 2.5.5 Choosing The PLLCON Values Knowing that jitter is significant, how does its reduction influence the choice of PLLCON parameters? Example: As above, XTAL frequency = 8MHz, Master Clock frequency fMC = 40MHz. This gives at least three possible combinations of N, K & P, as shown. (i) PLLCON = 0x7884 (default value from DaVE) (ii) PLLCON = 0x7D12 (iii) PLLCON = 0x7D85 N = 25 K=5 P= 1 N = 30 K=3 P=2 N = 30 K=6 P=1 Which of these three combinations to use depends on several factors: 1. 2. 3. PLLCON = 0x7D12 has the input divider P at 2 so that a clock source with a non-50/50 duty ratio such as an oscillator module may be used as the clock source. 0x7884 uses a lower N multiplier and higher K divider than 0x7D12. This reduces the PLL jitter on the fPLL output compared with (i). 0x7D85 gives the lowest clock jitter of all as K = 6. Therefore (iii) is to be preferred where an external crystal is being used. Insiders Guide 35 V1.0, 2006-02 An Insiders Guide to Planning XC166 XC166 Family Designs Approximate Accumulated PLL Jitter Bold lines indicate the minimum possible jitter. These can only be achieved by setting the maximum possible K for the combination of required fMC and crystal frequency. Insiders Guide 36 V1.0, 2006-02 An Insiders Guide to Planning XC166 XC166 Family Designs 2.6 Generating The Clock 2.6.1 Designing Clock Circuits There are two basic choices of clock source, the crystal or a self-contained oscillator module. The design of a traditional clock circuit is not a trivial task and requires some care to get reliable start-up when production tolerances and component ageing is taken into account. The XC166 XC166 is family is no more demanding in this area than any other microcontroller ,so the hints given in the following section should be considered for any clock circuit design. XC16x XC16x A0-A18 A0-A18.A23 A0-A18 A0-A18.A23 XTAL2 XTAL2 XTAL1 XTAL1 RX RX 4MHz 4MHz CX1 CX2 Rq GND GND GND Iq From Current Probe Test Configuration Fundamental Mode Operation 2.6.2 Oscillator Modules Using an oscillator module is very simple, as the operating point calculations will have been taken care of by the manufacturer. The EMC emissions are also less as the metal case is always grounded and there will be a shorter signal path. The only critical factor is that the rise and fall time should be less than 5ns. There is a small price premium over the conventional crystal-plus-capacitors approach but this is not great. Indeed, it is only if the microcontroller is going to be used in a 25k+ per annum quantity that the extra cost of a module is going to become significant. The oscillator output should be connected to the XC166 XC166's XTAL1 pin. Insiders Guide 37 V1.0, 2006-02 An Insiders Guide to Planning XC166 XC166 Family Designs 2.6.3 Designing Crystal Oscillator Circuits The traditional clock circuit usually comprises a parallel resonant fundamental crystal plus two capacitors and a resistor to limit the current through the resonant device. The XC166 XC166 uses crystals in the range of 4 to 16MHz. The selection of the series resistor value Rx must be made so that the oscillator is guaranteed to start within 0.1ms to 5ms, even after mass production tolerances and ageing effects are taken into account. It must also be chosen to keep the power drive level of the crystal between typically 50uW to 800uW, although the device's datasheet should be consulted. The process of defining RX and the "load capacitors", CX1 and CX2, is aimed at making sure that there is sufficient current flowing through crystal to drive the on-chip inverter that produces the oscillation. The crystal has a characteristic resistance known as the "equivalent series resistance" or "load resonant resistance", which is a combination of its typical resistance (R1typ) and residual capacitance (C0typ), as stated by the manufacturer, plus reactive effects due to the oscillation and the load capacitors CX1 and CX2. This equivalent resistance is given by: RL = R1typ x (1 + (C0typ/CL)2) Where: CL = (CX1 x CX2)/(CX1 + CX2) + CS (CS = the stray capacitance of clock circuit) During this Rx definition phase, a small value resistor, Rq, should be inserted in series with the crystal. The temporary resistor, Rq, must be increased until the oscillator does not start automatically when the 166 is powered up for different values of load capacitor. This value will be Rqmax. For ease of adjustment, an RF potentiometer can be used but you must bear in mind that this is RF engineering and the value of Rq so arrived at must be verified by replacing the potentiometer with an equivalent SMD or RF resistor and repeating the test. The ratio of Rqmax to the equivalent series resistance is the "Safety Factor" and is a measure of how much spare capacity there is in the circuit to overcome tolerance and ageing effects: Safety Factor (SF) = Rqmax/RL A current probe should be used to measure the peak-to-peak current (Ipp), converted to drive power with: Pw = (Ipp x Ipp x RL)/8 The resulting relationships between safety factor and power drive versus load capacitor value should be plotted on graph paper. From both curves, a value of load capacitors that gives the best combination of safety factor and power consumption can be chosen. 2.6.4 Crystal Oscillator Components Test Procedure 1. Select a value for Rx 2. Fit load capacitors, CX1 and CX2 of the value given in the table 3. Adjust Rq until oscillation will not self-start in less than 5ms when the XC166 XC166 is powered-on. Record this resistance in a table, similar to that given below: Test Record For Rx = 680R CX1 = CX2 Ipp Pw Rqmax 0.0pF 0.002075 25.27 150 2.2pF 0.0023 26.09 500 4.7pF 10pF 0.00255 0.0031 27.48 32.17 750 600 22pF 47pF 0.00455 0.008 51.59 122.5 250 60 4. Select the next value of load capacitors and repeat steps 2 to 4 5. Now pick another value for Rx and repeat the procedure. Insiders Guide 38 V1.0, 2006-02 An Insiders Guide to Planning XC166 XC166 Family Designs After a number of Rx values have been tested in this way, the resulting curves should be examined for the resistor and load capacitor values that give the best safety factor at a power level of 50uW-800uW. Having selected the values, the resistor Rq should be removed and the current and start-up times rechecked. If an adequate safety factor cannot be achieved, particularly above 20MHz, it is possible to add a series 1-10M 1-10M resistor to increase the feedback to the XTAL1 input pin. Otherwise, a third-overtone mode must be used. Unfortunately, the component selection process is more complex and when it is considered that an extra inductor and capacitor will be required to damp-out the fundamental frequency, it might prove more cost-effective to use an oscillator module! To simplify the selection process, Infineon can provide an Excel spreadsheet template at www.infineon.com/xc166-family that automates the conversion of test results and characteristic curve plotting, as Excel Spreadsheet For Oscillator Component Evaluation illustrated below: Insiders Guide 39 V1.0, 2006-02 An Insiders Guide to Planning XC166 XC166 Family Designs The clock circuit will in fact produce two drive currents: until the RESOUT pin goes high, (after the EINIT instruction is executed), the current drive of the clock will be greater to ensure that the CPU is less likely to be upset during the potentially noisy initialisation phase. It also helps to overcome the initial high resistance of the crystal during the startup phase. Typical load capacitor values are 22pF with Rx around 1K. However, you should not rely on these and for any serious project, the selection procedure given earlier should be followed. 2.6.4.1 Typical Component Values The table gives typical values for a selection of commercially available crystals. These must not be used as they stand without testing - we deliberately have not given the brand names for this reason! It is recommended that you compare the characteristics C0typ, R1typ (in the shaded panels) and fundamental frequency of your device with the examples in the table and pick the one which is closest. CX1 (pF) CX2 (pF) CL (pF) C0typ (pF) R1typ (Ohm) R1max (Ohm) R1max (TK) (Ohm) Pw (uW) 0 12 15 13 7 10 50 60 420 300 2.11 32 0 12 15 11 5 15 50 60 520 390 3.07 24 180 15 22 12 5 15 50 60 510 390 3.24 20 390 8.2 39 10 4 20 60 80 375 560 3.57 18 390 12 39 14 4 20 60 80 335 540 4.08 16 390 12 47 13 4 20 60 80 353 580 4.24 12 390 15 47 13 4 30 70 90 312 1000 6.50 10 390 15 47 14 3 30 80 100 216 1200 8.14 8 390 15 47 15 3 35 80 100 372 1800 12.50 6 390 15 47 14 3 35 80 140 100 2200 10.66 5 390 22 47 18 3 35 80 140 110 2700 14.17 4 390 22 47 16 4 20 80 150 46 Safety Factor (SF) Rx2 (Ohm) 40 Rqmax (Ohm) Frequency (MHz) Make up a clock circuit using the load capacitors CX1 and CX2 plus the series resistor Rx and perform the check of safety factor and drive power given in the previous section. The chances are that the results will be within limits but it would be very embarrassing if reliability problems occur in production and you have to admit that you never verified the component values in the clock circuit. 3300 14.08 Typical Crystal Characteristics And Component Values Insiders Guide 40 V1.0, 2006-02 An Insiders Guide to Planning XC166 XC166 Family Designs 2.6.5 Laying Out Clock Circuits The layout of the clock circuit can be critical in determining both the RF emissions and susceptibility of a XC166 XC166 design. As with any high frequency system, the loop areas must kept as small as possible, meaning in practice that all components must be located as close as is practicable to each other and to the XTAL1/XTAL2 pins on the CPU. With metal-canned crystals, the case should be soldered to a grounded area on the top surface plus it should be connected to the main ground layer in a multi-layer board. This will also improve the mechanical stability of the part. XC16x Decoupling capacitor on reverse of board CB Vcc XTAL1 Vss RX XTAL2 CX1 = Connections to ground layer CX2 Crystal Sample Oscillator Circuit Layout Inductive and capacitive coupling can be reduced by eliminating parallel runs of tracks either on the same layer or between layers. The grounding of the load capacitors should have a generous track width and be connected directly to the ground layer to avoid ground loops, which are a major source of RF emissions. 2.6.6 Symptoms Of A Poor Clock It must be emphasised that the series resistor value must be chosen with care. An incorrect value is unlikely to result in a total CPU failure, or even in erratic operation of the core, timers or A/D converter. However, the first symptom of a poor choice is that an unexpectedly large number of bus errors on the CAN peripheral may be seen, or the ALE timing is erratic for no readily apparent reason. Such behaviour should never be ignored - try shorting the resistor out to see if the problem goes away. Insiders Guide 41 V1.0, 2006-02 An Insiders Guide to Planning XC166 XC166 Family Designs 2.7 Real Time Clock Oscillator A Real Time Clock (RTC) is available on the XC161 XC161 and XC167 XC167 that can optionally have its own clock crystal. The main oscillator (divided by 8) can be used as the input and will still allow the real time clock operation to be continued during XC166 XC166 sleep mode. For maximum time-keeping accuracy though, an external 32.768kHz "watch" crystal needs to be provided on the X3 & X4 pins. Before entering sleep mode the RTCCM bit in SYSCON0 must be set to 1 to enter the "asynchronous" mode, provided FCPU is greater than 4 x Fcount. However as this dedicated oscillator is not synchronised to the CPU clock, the time registers cannot be read or written. Therefore after a system reset, the operating mode must be set back to synchronous (RTCCM = 0). The current consumption during sleep mode with the RTC running is around 100uA. A complete powering down of the device that requires a power-on reset to restart will leave the real time clock registers undefined i.e. any accumulated time will be lost. 2.8 Further Information On Oscillator Design Application notes AP24205 AP24205 and AP242401 AP242401 available from www.infineon.com/xc166-family that cover crystal oscillator and ceramic resonator design in detail. Insiders Guide 42 V1.0, 2006-02 An Insiders Guide to Planning XC166 XC166 Family Designs 3 Bus Modes And Timings 3.1 Flexible Bus Interface The XC166 XC166 family is primarily intended for single chip applications with variants having up to 256k of automotive on-chip flash and up to 12k of RAM. However, the provision has been made for a very flexible external bus interface. The basic philosophy behind the XC's bus interface is simplicity, even in external bus systems; by providing 8- and 16-bit non-multiplexed modes, it is possible to dispense with an address latch and provide just a FLASH and RAM to make a working system. The integral software-programmable chip selects can make most address decoder logic redundant. Thus, despite its 20 fold improvement in performance, an XC's digital design can be simpler than that of an 8031! If an external bus is required, one of the XC's most useful features is its ability to support two different bus configurations in a single hardware design. Thus whilst the external FLASH and RAM areas (if needed) can be 16-bit non-multiplexed with zero waitstates for best speed, slow (and low cost) peripherals such as RTCs can be addressed with, for example, an 8-bit bus with 3 waitstates. 3.1.1 Integral Chip Selects The XC family can have up to 5 external chip select regions. Chip selects 1 to 4 each have ADDRSEL, FCON and TCON registers that individually control the bus mode, timing and range of the Chip Select region. CS0 doesn't have an ADDRSEL register and is active for any addresses that aren't covered by another Chip Select (or the internal memory / registers). While looking at the user manual it may seem that CS 5,6 & 7 are also present, but in reality these are used to address internal LX bus peripherals. CS 5 & 6 are reserved for future use and CS7 is for the TwinCAN Module and is located at 0x200000. XC16x TCONCS2 = 0x29A8 FCONCS2 = 0x0001 /CS2 /CE UART 8 Bit Non-Multiplex Bus 1 Waitstates ADDRSEL2 = 0x3000 Base Addr = 0x300000 Length = 4k RAM 16 Bit Non-Multiplex Bus PhaseE = 2 cycles TCONCS1 = 0x2868 FCONCS1 = 0x0021 /CS1 /CE ADDRSEL1 = 0x1006 TCONCS0 = 0x2868 FCONCS0 = 0x0021 WRCFG /EA 10K Insiders Guide 0 0 /CE P0.7 P0.6 P0.8 5K6 /CS0 BTYP 1 EBCMOD0 = 0x0800 EPROM Base Addr = 0x100000 Length = 256k 5K6 5K6 43 V1.0, 2006-02 An Insiders Guide to Planning XC166 XC166 Family Designs Chip Select /CS0 /CS1 /CS2 /CS3 /CS4 Pin Name P6.0 P6.1 P6.2 P6.3 P6.4 Control Register TCONCS0, FCONCS0 TCONCS1, FCONCS1 TCONCS2, FCONCS2 TCONCS3, FCONCS3 TCONCS4, FCONCS4 Address Range Register Not Applicable ADDRSEL1 ADDRSEL2 ADDRSEL3 ADDRSEL4 It is essential when setting up the ADDRSEL, FCON and TCON registers to make sure that you configure the ADDRESELx before the corresponding FCONCSx and TCONCSx. If you do not, the CPU will enable the ADDRSEL for an undefined bus configuration and a crash will ensue! Also note that while you may initialise these registers from C, any variables located in an region controlled by them will not be zeroed before main() by the compiler start-up code as the corresponding chip select will not be activated (low). 3.1.1.1 Overlapping Chip Selects It is possible to overlap the regions covered by external chip selects, provided that certain rules are observed. When an address is generated that is to be accessed, the CPU decides which device on the bus receives the address according to the following rules: First the CPU checks whether the address corresponds to an on-chip memory region or peripheral and directs the access internally so that it will not appear on the external bus. Thus for example, external memory areas that partially overlap internal resources will be inaccessible. Next registers ADDRSEL2 & 4 are checked to see what areas they cover. A match with one of these registers directs the access to the respective external area. Thus ADDRSEL 2 & 4 regions can overlap ADDRSEL1, 2 & 7 but not each other. The overlapping of windows of ADDRSEL2 & 4 gives undefined behaviour. Next ADDRSEL1, 3 & 7 are checked and if the address lies in an area covered by one of these. Again, ADDRSEL1, 3 & 7 may not overlap. However ADDRSEL2 & 1 may overlap each other, as can 4 & 3. These pairings are the only ones that are allowed. Finally, addresses that are not in the range of any other ADDRSEL register cause chip select 0 to be used. Thus chip select 0 can overlap all other chip selects. 3.2 Setting The Bus Mode 3.2.1 On-Chip Boot If the /EA pin is pulled high during reset, the processor will boot from the internal flash and the external bus controller will be disabled. If required, the external bus can be configured through software. In single chip mode virtually all of the signals used by an external bus are available for use as I/O. Two External Bus Controller Mode Registers (EBCMOD 0 and 1) configure things such as the number of CS signals and segment address lines required, enabling the ALE and /BHE signals as well as selecting ports 1 and 2 as address and data busses. 3.2.2 External Boot With /EA low during reset, the XC reads the pattern of user-defined pull-down resistors on the P0.6 and P0.7 to set the default bus mode. In fact, the pull-down resistor pattern is placed into the BTYP field in the FCON0 register where it can be changed by software, although it is definitely not recommended to do this on external ROM designs. The number of chip selects and the overall address range of the processor are also set via Port 0 pull-down resistors, covered in section 2. These can also be changed in software by modifying the EBCMODx registers but this should not be necessary. Insiders Guide 44 V1.0, 2006-02 An Insiders Guide to Planning XC166 XC166 Family Designs 3.3 Setting The Overall Addressing Capabilities By enabling up to 8 segment address lines over and above the 16 lines of Port 0 as segment address lines (in demultiplexed bus mode), a 16MB memory device can be used. Assuming the processor's chip select signals are going to be used, the number of segment address lines required is determined by the largest device to be connected. For example, if a 256KB 256KB memory was connected to CS1 and an Ethernet controller (with a much smaller address range) was connected to CS2, only two segment address lines would need to be enabled. By setting the ADDRSEL1 and 2 registers the devices could be enabled (pretty much) anywhere in the 16M address space. 3.3.1 External Memory Access Times The bus access mode used by the XC166 XC166 is Intel-style. The timing for each of the processor's 5 chip select regions is configured by its TCONx register. A bus cycle is divided into six different timing phases and the number of clock cycles for each of these phases is set in the TCONx register. The phases are: A Phase B Phase C Phase D Phase E Phase F Phase /CS Changing phase Address Setup /ALE Phase Delay Phase Write Data Setup / MUX Tristate Phase RD/WR Command Phase Address / Write Data Hold Phase 0 ­ 3 clock cycles 1 ­ 2 clock cycles 0 ­ 3 clock cycles 0 ­ 1 clock cycles 1 ­ 32 clock cycles 0 ­ 3 clock cycles This allows a great deal of control over a bus cycle to cater for different characteristics of external devices. In most applications, Phase A will be equal to 0. If the TWINCAN module is being used, it will always be 0. Insiders Guide 45 V1.0, 2006-02 An Insiders Guide to Planning XC166 XC166 Family Designs 3.3.2 Calculating The Bus Timing Parameters For A Multiplexed Bus AB C ALE A0-A15 A0-A15 Low Address A0-A15 A0-A15 (ALEOUT) Bus Timing Example (multiplexed) The bus timings are based on devices used on Infineon starter kits. In this example, Samsung K6R4016C1D K6R4016C1D SRAM is fitted. This memory device is organised as 256K x 16 and have an access time of 12ns. The bus is multiplexed. The bus timings will be calculated with a 40MHz CPU clock. The timing is always designed for the worst-case manufacturing tolerances. Please note that the XC-microcontroller's signals do not always appear in sync. at the output as the rise/fall time is up to 4ns. The delay on the falling edges of the CS, RD and WR-signals can amount to up to 13ns. In the case of rising edges, this can be up to 6ns. At 40MHz, one clock has a duration of 25ns. Phase A: 0 Clocks Phase A is only necessary when working with more than one chip select and when it is not certain if the bus is still being driven from a previous write- or read access. Phase A clocks will only be inserted when the address being accessed causes a change of chip select, such as might happen when code being fetched from external FLASH accesses data in external RAM. Most XC166 XC166 designs use on-chip FLASH and the only external access might be to an external SRAM, so no chip select changes will occur. Here it is assumed that we are only working with 1 chip select and have set the value to 0, as in fact is almost always the case. Phase B: 1 Clock This clock is required in order for the address latch to capture the data. As a rule, the address latch is not critical at high clock speeds. However please note that the guaranteed high-time only amounts to 2ns. Phase C: 1 Clock Phase C serves to delay and through this, the address latch is able to accept the data. In a worstcase scenario, the ALE can still be 10ns long. High < 1 Clock. Insiders Guide 46 V1.0, 2006-02 An Insiders Guide to Planning XC166 XC166 Family Designs Phase D: 1 Clock The microcontroller puts address lines i