XC164CS-16F C166SV2 XC164-16 XC164 GPT12E XC166 SAK-XC164CS-16F40F

XC164CS-16F 16-Bit Single-Chip Microcontroller with C166SV2 Core Microcontrollers Edition 2006-03 Published by Infineon

D a ta S h e e t, V 2 . 2 , M a r c h 20 0 6 XC164CS-16F XC164CS-16F 16-Bit Single-Chip Microcontroller with C166SV2 C166SV2 Core Microcontrollers Edition 2006-03 Published by Infineon Technologies AG 81726 München, Germany © Infineon Technologies AG 2006. All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics ("Beschaffenheitsgarantie"). With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of noninfringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. D a ta S h e e t, V 2 . 2 , M a r c h 20 0 6 XC164CS-16F XC164CS-16F 16-Bit Single-Chip Microcontroller with C166SV2 C166SV2 Core Microcontrollers XC164-16 XC164-16 Derivatives XC164 XC164 Revision History: V2.2, 2006-03 Previous Version(s): V2.1, 2003-06 V2.0, 2003-01 V1.0, 2002-03 Page Subjects (major changes since last revision) all Layout of graphics and text structures has been adapted to the new company documentation rules. 55 Footnote about leakage current at P3.15 added. 67 Minimum oscillator period corrected 71 Output delay/hold time of A23 . A16 moved from tc11->tc12, tc21->tc23 74 Chapter "Package and Reliability" added. We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: mcdocu.comments@infineon.com Data Sheet V2.2, 2006-03 XC164-16 XC164-16 Derivatives Table of Contents Table of Contents 1 Summary of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 2.1 2.2 General Device Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Pin Configuration and Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory Subsystem and Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Bus Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Central Processing Unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . On-Chip Debug Support (OCDS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Capture/Compare Units (CAPCOM1/2) . . . . . . . . . . . . . . . . . . . . . . . . . . . The Capture/Compare Unit CAPCOM6 . . . . . . . . . . . . . . . . . . . . . . . . . . . General Purpose Timer (GPT12E GPT12E) Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . Real Time Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A/D Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Asynchronous/Synchronous Serial Interfaces (ASC0/ASC1) . . . . . . . . . . High Speed Synchronous Serial Channels (SSC0/SSC1) . . . . . . . . . . . . TwinCAN Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 18 20 21 23 28 29 32 33 37 39 40 41 42 44 45 45 47 48 4 4.1 4.2 4.3 4.4 4.4.1 4.4.2 4.4.3 4.4.4 4.4.5 Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Analog/Digital Converter Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Definition of Internal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . On-chip Flash Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Clock Drive XTAL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Testing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 51 54 59 62 62 66 67 68 69 5 5.1 5.2 Package and Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Flash Memory Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Data Sheet 3 V2.2, 2006-03 16-Bit Single-Chip Microcontroller with C166SV2 C166SV2 Core XC166 XC166 Family 1 · · · · · · · XC164 XC164 Summary of Features High Performance 16-bit CPU with 5-Stage Pipeline 25 ns Instruction Cycle Time at 40 MHz CPU Clock (Single-Cycle Execution) 1-Cycle Multiplication (16 × 16 bit), Background Division (32 / 16 bit) in 21 Cycles 1-Cycle Multiply-and-Accumulate (MAC) Instructions Enhanced Boolean Bit Manipulation Facilities Zero-Cycle Jump Execution Additional Instructions to Support HLL and Operating Systems Register-Based Design with Multiple Variable Register Banks Fast Context Switching Support with Two Additional Local Register Banks 16 Mbytes Total Linear Address Space for Code and Data 1024 Bytes On-Chip Special Function Register Area (C166 Family Compatible) 16-Priority-Level Interrupt System with up to 75 Sources, Sample-Rate down to 50 ns 8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via Peripheral Event Controller (PEC), 24-Bit Pointers Cover Total Address Space Clock Generation via on-chip PLL (factors 1:0.15 . 1:10), or via Prescaler (factors 1:1 . 60:1) On-Chip Memory Modules 2 Kbytes On-Chip Dual-Port RAM (DPRAM) 2/4 Kbytes On-Chip Data SRAM (DSRAM)1) 2 Kbytes On-Chip Program/Data SRAM (PSRAM) 64/128 Kbytes On-Chip Program Memory (Flash Memory or Mask ROM)1) On-Chip Peripheral Modules 14-Channel A/D Converter with Programmable Resolution (10-bit or 8-bit) and Conversion Time (down to 2.55 µs or 2.15 µs) Two 16-Channel General Purpose Capture/Compare Units (12 Input/Output Pins) Capture/Compare Unit for flexible PWM Signal Generation (CAPCOM6) (3/6 Capture/Compare Channels and 1 Compare Channel) Multi-Functional General Purpose Timer Unit with 5 Timers Two Synchronous/Asynchronous Serial Channels (USARTs) Two High-Speed-Synchronous Serial Channels On-Chip TwinCAN Interface (Rev. 2.0B active) with 32 Message Objects (Full CAN/Basic CAN) on Two CAN Nodes, and Gateway Functionality On-Chip Real Time Clock Idle, Sleep, and Power Down Modes with Flexible Power Management 1) Depends on the respective derivative. The derivatives are listed in Table 1. Data Sheet 4 V2.2, 2006-03 XC164-16 XC164-16 Derivatives Summary of Features · · · · · · · Programmable Watchdog Timer and Oscillator Watchdog Up to 12 Mbytes External Address Space for Code and Data Programmable External Bus Characteristics for Different Address Ranges Multiplexed or Demultiplexed External Address/Data Buses Selectable Address Bus Width 16-Bit or 8-Bit Data Bus Width Four Programmable Chip-Select Signals Up to 79 General Purpose I/O Lines, partly with Selectable Input Thresholds and Hysteresis On-Chip Bootstrap Loader Supported by a Large Range of Development Tools like C-Compilers, Macro-Assembler Packages, Emulators, Evaluation Boards, HLL-Debuggers, Simulators, Logic Analyzer Disassemblers, Programming Boards On-Chip Debug Support via JTAG Interface 100-Pin TQFP Package, 0.5 mm (19.7 mil) pitch Ordering Information The ordering code for Infineon microcontrollers provides an exact reference to the required product. This ordering code identifies: · · the derivative itself, i.e. its function set, the temperature range, and the supply voltage the package and the type of delivery. For the available ordering codes for the XC164 XC164 please refer to the "Product Catalog Microcontrollers", which summarizes all available microcontroller variants. Note: The ordering codes for Mask-ROM versions are defined for each product after verification of the respective ROM code. This document describes several derivatives of the XC164 XC164 group. Table 1 enumerates these derivatives and summarizes the differences. As this document refers to all of these derivatives, some descriptions may not apply to a specific product. For simplicity all versions are referred to by the term XC164 XC164 throughout this document. Data Sheet 5 V2.2, 2006-03 XC164-16 XC164-16 Derivatives Summary of Features Table 1 XC164 XC164 Derivative Synopsis Derivative1) Temp. Range SAK-XC164CS-16F40F SAK-XC164CS-16F40F, SAK-XC164CS-16F20F SAK-XC164CS-16F20F -40 °C to 128 Kbytes 2 Kbytes DPRAM, ASC0, ASC1, 125 °C Flash 4 Kbytes DSRAM, SSC0, SSC1, 2 Kbytes PSRAM CAN0, CAN1 SAK-XC164CS-16R40F SAK-XC164CS-16R40F, SAK-XC164CS-16R20F SAK-XC164CS-16R20F -40 °C to 128 Kbytes 2 Kbytes DPRAM, ASC0, ASC1, 125 °C ROM 4 Kbytes DSRAM, SSC0, SSC1, 2 Kbytes PSRAM CAN0, CAN1 SAF-XC164CS-16F40F SAF-XC164CS-16F40F, SAF-XC164CS-16F20F SAF-XC164CS-16F20F -40 °C to 128 Kbytes 2 Kbytes DPRAM, ASC0, ASC1, 85 °C Flash 4 Kbytes DSRAM, SSC0, SSC1, 2 Kbytes PSRAM CAN0, CAN1 SAF-XC164CS-16R40F SAF-XC164CS-16R40F, SAF-XC164CS-16R20F SAF-XC164CS-16R20F -40 °C to 128 Kbytes 2 Kbytes DPRAM, ASC0, ASC1, 85 °C ROM 4 Kbytes DSRAM, SSC0, SSC1, 2 Kbytes PSRAM CAN0, CAN1 SAK-XC164CS-8F40F SAK-XC164CS-8F40F, SAK-XC164CS-8F20F SAK-XC164CS-8F20F -40 °C to 64 Kbytes 125 °C Flash 2 Kbytes DPRAM, ASC0, ASC1, 2 Kbytes DSRAM, SSC0, SSC1, 2 Kbytes PSRAM CAN0, CAN1 SAK-XC164CS-8R40F SAK-XC164CS-8R40F, SAK-XC164CS-8R20F SAK-XC164CS-8R20F -40 °C to 64 Kbytes 125 °C ROM 2 Kbytes DPRAM, ASC0, ASC1, 2 Kbytes DSRAM, SSC0, SSC1, 2 Kbytes PSRAM CAN0, CAN1 SAF-XC164CS-8F40F SAF-XC164CS-8F40F, SAF-XC164CS-8F20F SAF-XC164CS-8F20F -40 °C to 64 Kbytes 85 °C Flash 2 Kbytes DPRAM, ASC0, ASC1, 2 Kbytes DSRAM, SSC0, SSC1, 2 Kbytes PSRAM CAN0, CAN1 SAF-XC164CS-8R40F SAF-XC164CS-8R40F, SAF-XC164CS-8R20F SAF-XC164CS-8R20F -40 °C to 64 Kbytes 85 °C ROM 2 Kbytes DPRAM, ASC0, ASC1, 2 Kbytes DSRAM, SSC0, SSC1, 2 Kbytes PSRAM CAN0, CAN1 Program Memory On-Chip RAM Interfaces 1) This Data Sheet is valid for devices starting with and including design step AD of the Flash version, and design step AA of the ROM version. Data Sheet 6 V2.2, 2006-03 XC164-16 XC164-16 Derivatives General Device Information 2 General Device Information 2.1 Introduction The XC164 XC164 derivatives are high-performance members of the Infineon XC166 XC166 Family of full featured single-chip CMOS microcontrollers. These devices extend the functionality and performance of the C166 Family in terms of instructions (MAC unit), peripherals, and speed. They combine high CPU performance (up to 40 million instructions per second) with high peripheral functionality and enhanced IO-capabilities. They also provide clock generation via PLL and various on-chip memory modules such as program ROM or Flash, program RAM, and data RAM. VAREF VAGND VDDI/P VSSI/P PORT0 16 bit XTAL1 PORT1 16 bit XTAL2 NMI Port 3 14 bit RSTIN RSTOUT XC164 XC164 Port 4 8 bit EA Port 20 5 bit ALE RD WR/WRL Port 5 14 bit Port 9 6 bit TRST JTAG Debug via Port 3 MCA05554 MCA05554_XC164 XC164 Figure 1 Data Sheet Logic Symbol 7 V2.2, 2006-03 XC164-16 XC164-16 Derivatives General Device Information 2.2 Pin Configuration and Definition P1L.7/A7/CTRAP/CC22IO 7/A7/CTRAP/CC22IO P1L.6/A6/COUT63 6/A6/COUT63 P1L.5/A5/COUT62 5/A5/COUT62 P1L.4/A4/CC62 4/A4/CC62 P1L.3/A3/COUT61 3/A3/COUT61 P1L.2/A2/CC61 2/A2/CC61 P1L.1/A1/COUT60 1/A1/COUT60 P1L.0/A0/CC60 0/A0/CC60 P0H.7/AD15 7/AD15 P0H.6/AD14 6/AD14 P0H.5/AD13 5/AD13 VSSP VDDP P1H.7/A15/CC27IO/EX7IN 7/A15/CC27IO/EX7IN P1H.6/A14/CC26IO/EX6IN 6/A14/CC26IO/EX6IN P1H.5/A13/CC25IO/EX5IN 5/A13/CC25IO/EX5IN P1H.4/A12/CC24IO/EX4IN 4/A12/CC24IO/EX4IN P1H.3/A11/T7IN/SCLK1/EX3IN/E 3/A11/T7IN/SCLK1/EX3IN/E*) P1H.2/A10/C6P2/MTSR1/EX2IN 2/A10/C6P2/MTSR1/EX2IN P1H.1/A9/C6P1/MRST1/EX1IN P1H.0/A8/C6P0/CC23IO/EX0IN 0/A8/C6P0/CC23IO/EX0IN VSSI VDDI 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 XTAL1 XTAL2 The pins of the XC164 XC164 are described in detail in Table 2, including all their alternate functions. Figure 2 summarizes all pins in a condensed way, showing their location on the 4 sides of the package. E*) and C*) mark pins to be used as alternate external interrupt inputs, C*) marks pins that can have CAN interface lines assigned to them. RSTIN P20.12/RSTOUT 12/RSTOUT NMI P0H.0/AD8 P0H.1/AD9 P0H.2/AD10 2/AD10 P0H.3/AD11 3/AD11 VSSP VDDP P9.0/CC16IO/C 0/CC16IO/C*) P9.1/CC17IO/C 1/CC17IO/C*) P9.2/CC18IO/C 2/CC18IO/C*) P9.3/CC19IO/C 3/CC19IO/C*) P9.4/CC20IO 4/CC20IO P9.5/CC21IO 5/CC21IO VSSP VDDP XC164 XC164 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 P0H.4/AD12 4/AD12 P0L.7/AD7 P0L.6/AD6 P0L.5/AD5 P0L.4/AD4 P0L.3/AD3 P0L.2/AD2 P0L.1/AD1 P0L.0/AD0 P20.5/EA P20.4/ALE P20.1/WR/WRL P20.0/RD VSSP VDDP P4.7/A23/C 7/A23/C*) P4.6/A22/C 6/A22/C*) P4.5/A21/C 5/A21/C*) P4.4/A20/C 4/A20/C*) P4.3/A19/CS0 3/A19/CS0 P4.2/A18/CS1 2/A18/CS1 P4.1/A17/CS2 1/A17/CS2 P4.0/A16/CS3 0/A16/CS3 P3.15/CLKOUT/FOUT 15/CLKOUT/FOUT P3.13/SCLK0/E 13/SCLK0/E*) Figure 2 Data Sheet P3.1/T6OUT/RxD1/TCK/E*) P3.2/CAPIN/TDI P3.3/T3OUT/TDO P3.4/T3EUD/TMS P3.5/T4IN/TxD1/BRKOUT P3.6/T3IN P3.7/T2IN/BRKIN P3.8/MRST0 P3.9/MTSR0 P3.10/TxD0/E*) P3.11/RxD0/E*) P3.12/BHE/WRH/E 12/BHE/WRH/E*) VSSP VDDP TRST VSSI VDDI P5.12/AN12/T6IN 12/AN12/T6IN P5.13/AN13/T5IN 13/AN13/T5IN P5.14/AN14/T4EUD 14/AN14/T4EUD P5.15/AN15/T2EUD 15/AN15/T2EUD VAREF VAGND P5.6/AN6 P5.7/AN7 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 P5.0/AN0 P5.1/AN1 P5.2/AN2 P5.3/AN3 P5.4/AN4 P5.5/AN5 P5.10/AN10/T6EUD 10/AN10/T6EUD P5.11/AN11/T5EUD 11/AN11/T5EUD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 MCP06457 MCP06457 Pin Configuration (top view) 8 V2.2, 2006-03 XC164-16 XC164-16 Derivatives General Device Information Table 2 Pin Definitions and Functions Symbol Pin Num. Input Outp. Function RSTIN I Reset Input with Schmitt-Trigger characteristics. A low level at this pin while the oscillator is running resets the XC164 XC164. A spike filter suppresses input pulses 100 ns safely pass the filter. The minimum duration for a safe recognition should be 100 ns + 2 CPU clock cycles. 1 Note: The reset duration must be sufficient to let the hardware configuration signals settle. External circuitry must guarantee low level at the RSTIN pin at least until both power supply voltages have reached the operating range. P20.12 2 IO For details, please refer to the description of P20. NMI 3 I Non-Maskable Interrupt Input. A high to low transition at this pin causes the CPU to vector to the NMI trap routine. When the PWRDN (power down) instruction is executed, the NMI pin must be low in order to force the XC164 XC164 into power down mode. If NMI is high, when PWRDN is executed, the part will continue to run in normal mode. If not used, pin NMI should be pulled high externally. P0H.0P0H.3 4.7 IO For details, please refer to the description of PORT0. Data Sheet 9 V2.2, 2006-03 XC164-16 XC164-16 Derivatives General Device Information Table 2 Pin Definitions and Functions (cont'd) Symbol Pin Num. Input Outp. Function P9 IO Port 9 is a 6-bit bidirectional I/O port. Each pin can be programmed for input (output driver in high-impedance state) or output (configurable as push/pull or open drain driver). The input threshold of Port 9 is selectable (standard or special). The following Port 9 pins also serve for alternate functions:1) CC16IO CC16IO CAPCOM2: CC16 Capture Inp./Compare Outp., CAN2_RxD CAN Node 2 Receive Data Input, EX7IN Fast External Interrupt 7 Input (alternate pin B) CC17IO CC17IO CAPCOM2: CC17 Capture Inp./Compare Outp., CAN2_TxD CAN Node 2 Transmit Data Output, EX6IN Fast External Interrupt 6 Input (alternate pin B) CC18IO CC18IO CAPCOM2: CC18 Capture Inp./Compare Outp. CAN1_RxD CAN Node 1 Receive Data Input, EX7IN Fast External Interrupt 7 Input (alternate pin A) CC19IO CC19IO CAPCOM2: CC19 Capture Inp./Compare Outp., CAN1_TxD CAN Node 1 Transmit Data Output, EX6IN Fast External Interrupt 6 Input (alternate pin A) CC20IO CC20IO CAPCOM2: CC20 Capture Inp./Compare Outp. CC21IO CC21IO CAPCOM2: CC21 Capture Inp./Compare Outp. P9.0 10 P9.1 11 P9.2 12 P9.3 13 P9.4 P9.5 14 15 I P5 P5.0 P5.1 P5.2 P5.3 P5.4 P5.5 P5.10 P5.11 P5.6 P5.7 P5.12 P5.13 P5.14 P5.15 I/O I I I/O O I I/O I I I/O O I I/O I/O 18 19 20 21 22 23 24 25 26 27 30 31 32 33 Data Sheet I I I I I I I I I I I I I I Port 5 is a 14-bit input-only port. The pins of Port 5 also serve as analog input channels for the A/D converter, or they serve as timer inputs: AN0 AN1 AN2 AN3 AN4 AN5 AN10, T6EUD GPT2 Timer T6 Ext. Up/Down Ctrl. Inp. AN11, T5EUD GPT2 Timer T5 Ext. Up/Down Ctrl. Inp. AN6 AN7 AN12, T6IN GPT2 Timer T6 Count/Gate Input AN13, T5IN GPT2 Timer T5 Count/Gate Input AN14, T4EUD GPT1 Timer T4 Ext. Up/Down Ctrl. Inp. AN15, T2EUD GPT1 Timer T2 Ext. Up/Down Ctrl. Inp. 10 V2.2, 2006-03 XC164-16 XC164-16 Derivatives General Device Information Table 2 Pin Definitions and Functions (cont'd) Symbol Pin Num. Input Outp. Function TRST I Test-System Reset Input. A high level at this pin activates the XC164 XC164's debug system. For normal system operation, pin TRST should be held low. IO Port 3 is a 14-bit bidirectional I/O port. Each pin can be programmed for input (output driver in high-impedance state) or output (configurable as push/pull or open drain driver). The input threshold of Port 3 is selectable (standard or special). The following Port 3 pins also serve for alternate functions: T6OUT GPT2 Timer T6 Toggle Latch Output, RxD1 ASC1 Data Input (Async.) or Inp./Outp. (Sync.), EX1IN Fast External Interrupt 1 Input (alternate pin A), TCK Debug System: JTAG Clock Input CAPIN GPT2 Register CAPREL Capture Input, TDI Debug System: JTAG Data In T3OUT GPT1 Timer T3 Toggle Latch Output, TDO Debug System: JTAG Data Out T3EUD GPT1 Timer T3 External Up/Down Control Input, TMS Debug System: JTAG Test Mode Selection T4IN GPT1 Timer T4 Count/Gate/Reload/Capture Inp TxD1 ASC0 Clock/Data Output (Async./Sync.), BRKOUT Debug System: Break Out T3IN GPT1 Timer T3 Count/Gate Input T2IN GPT1 Timer T2 Count/Gate/Reload/Capture Inp BRKIN Debug System: Break In MRST0 SSC0 Master-Receive/Slave-Transmit In/Out. MTSR0 SSC0 Master-Transmit/Slave-Receive Out/In. TxD0 ASC0 Clock/Data Output (Async./Sync.), EX2IN Fast External Interrupt 2 Input (alternate pin B) RxD0 ASC0 Data Input (Async.) or Inp./Outp. (Sync.), EX2IN Fast External Interrupt 2 Input (alternate pin A) BHE External Memory High Byte Enable Signal, WRH External Memory High Byte Write Strobe, EX3IN Fast External Interrupt 3 Input (alternate pin B) SCLK0 SSC0 Master Clock Output / Slave Clock Input., EX3IN Fast External Interrupt 3 Input (alternate pin A) CLKOUT System Clock Output (= CPU Clock), FOUT Programmable Frequency Output 36 P3 P3.1 39 P3.2 40 P3.3 41 P3.4 42 P3.5 43 P3.6 P3.7 44 45 P3.8 P3.9 P3.10 46 47 48 P3.11 49 P3.12 50 P3.13 51 P3.15 52 Data Sheet O I/O I I I I O O I I I O O I I I I/O I/O O I I/O I O O I I/O I O O 11 V2.2, 2006-03 XC164-16 XC164-16 Derivatives General Device Information Table 2 Pin Definitions and Functions (cont'd) Symbol Pin Num. Input Outp. Function P4 IO Port 4 is an 8-bit bidirectional I/O port. Each pin can be programmed for input (output driver in high-impedance state) or output (configurable as push/pull or open drain driver). The input threshold of Port 4 is selectable (standard or special). Port 4 can be used to output the segment address lines, the optional chip select lines, and for serial interface lines:1) A16 Least Significant Segment Address Line, CS3 Chip Select 3 Output A17 Segment Address Line, Chip Select 2 Output CS2 A18 Segment Address Line, CS1 Chip Select 1 Output A19 Segment Address Line, CS0 Chip Select 0 Output A20 Segment Address Line, CAN2_RxD CAN Node 2 Receive Data Input, EX5IN Fast External Interrupt 5 Input (alternate pin B) A21 Segment Address Line, CAN1_RxD CAN Node 1 Receive Data Input, EX4IN Fast External Interrupt 4 Input (alternate pin B) A22 Segment Address Line, CAN1_TxD CAN Node 1 Transmit Data Output, EX5IN Fast External Interrupt 5 Input (alternate pin A) A23 Most Significant Segment Address Line, CAN1_RxD CAN Node 1 Receive Data Input, CAN2_TxD CAN Node 2 Transmit Data Output, EX4IN Fast External Interrupt 4 Input (alternate pin A) P4.0 53 P4.1 54 P4.2 55 P4.3 56 P4.4 57 P4.5 58 P4.6 59 P4.7 60 Data Sheet O O O O O O O O O I I O I I O O I O I O I 12 V2.2, 2006-03 XC164-16 XC164-16 Derivatives General Device Information Table 2 Pin Definitions and Functions (cont'd) Symbol Pin Num. Input Outp. Function P20 IO Port 20 is a 5-bit bidirectional I/O port. Each pin can be programmed for input (output driver in high-impedance state) or output. The input threshold of Port 20 is selectable (standard or special). The following Port 20 pins also serve for alternate functions: RD External Memory Read Strobe, activated for every external instruction or data read access. WR/WRL External Memory Write Strobe. In WR-mode this pin is activated for every external data write access. In WRL-mode this pin is activated for low byte data write accesses on a 16-bit bus, and for every data write access on an 8-bit bus. ALE Address Latch Enable Output. Can be used for latching the address into external memory or an address latch in the multiplexed bus modes. EA External Access Enable pin. A low level at this pin during and after Reset forces the XC164 XC164 to latch the configuration from PORT0 and pin RD, and to begin instruction execution out of external memory. A high level forces the XC164 XC164 to latch the configuration from pins RD, ALE, and WR, and to begin instruction execution out of the internal program memory. "ROMless" versions must have this pin tied to `0'. RSTOUT Internal Reset Indication Output. Is activated asynchronously with an external hardware reset. It may also be activated (selectable) synchronously with an internal software or watchdog reset. Is deactivated upon the execution of the EINIT instruction, optionally at the end of reset, or at any time (before EINIT) via user software. P20.0 63 O P20.1 64 O P20.4 65 O P20.5 66 I P20.12 2 O Note: Port 20 pins may input configuration values (see EA). Data Sheet 13 V2.2, 2006-03 XC164-16 XC164-16 Derivatives General Device Information Table 2 Pin Definitions and Functions (cont'd) Symbol Pin Num. Input Outp. Function PORT0 IO PORT0 consists of the two 8-bit bidirectional I/O ports P0L and P0H. Each pin can be programmed for input (output driver in high-impedance state) or output. In case of an external bus configuration, PORT0 serves as the address (A) and address/data (AD) bus in multiplexed bus modes and as the data (D) bus in demultiplexed bus modes. Demultiplexed bus modes: 8-bit data bus: P0H = I/O, P0L = D7 - D0 16-bit data bus: P0H = D15 - D8, P0L = D7 - D0 Multiplexed bus modes: 8-bit data bus: P0H = A15 - A8, P0L = AD7 - AD0 16-bit data bus: P0H = AD15 - AD8, P0L = AD7 - AD0 P0L.0P0L.7 67 - 74 P0H.0P0H.3 P0H.4P0H.7 4-7 75 - 78 Note: At the end of an external reset (EA = 0) PORT0 also may input configuration values IO PORT1 P1L.0 P1L.1 P1L.2 P1L.3 P1L.4 P1L.5 P1L.6 P1L.7 79 80 81 82 83 84 85 86 I/O O I/O O I/O O O I I/O P1H . Data Sheet PORT1 consists of the two 8-bit bidirectional I/O ports P1L and P1H. Each pin can be programmed for input (output driver in high-impedance state) or output. PORT1 is used as the 16-bit address bus (A) in demultiplexed bus modes (also after switching from a demultiplexed to a multiplexed bus mode). The following PORT1 pins also serve for alt. functions: CC60 CAPCOM6: Input / Output of Channel 0 COUT60 COUT60 CAPCOM6: Output of Channel 0 CC61 CAPCOM6: Input / Output of Channel 1 COUT61 COUT61 CAPCOM6: Output of Channel 1 CC62 CAPCOM6: Input / Output of Channel 2 COUT62 COUT62 CAPCOM6: Output of Channel 2 COUT63 COUT63 Output of 10-bit Compare Channel CTRAP CAPCOM6: Trap Input CTRAP is an input pin with an internal pull-up resistor. A low level on this pin switches the CAPCOM6 compare outputs to the logic level defined by software (if enabled). CC22IO CC22IO CAPCOM2: CC22 Capture Inp./Compare Outp. . continued . 14 V2.2, 2006-03 XC164-16 XC164-16 Derivatives General Device Information Table 2 Pin Definitions and Functions (cont'd) Symbol Pin Num. Input Outp. Function PORT1 (cont'd) P1H.0 89 IO . continued . I I I/O I I I/O I I I/O I I/O I I I/O I I/O I I/O I I/O I CC6POS0 EX0IN CC23IO CC23IO CC6POS1 EX1IN MRST1 CC6POS2 EX2IN MTSR1 T7IN SCLK1 EX3IN EX0IN CC24IO CC24IO EX4IN CC25IO CC25IO EX5IN CC26IO CC26IO EX6IN CC27IO CC27IO EX7IN CAPCOM6: Position 0 Input, Fast External Interrupt 0 Input (default pin), CAPCOM2: CC23 Capture Inp./Compare Outp. CAPCOM6: Position 1 Input, Fast External Interrupt 1 Input (default pin), SSC1 Master-Receive/Slave-Transmit In/Out. CAPCOM6: Position 2 Input, Fast External Interrupt 2 Input (default pin), SSC1 Master-Transmit/Slave-Receive Out/Inp. CAPCOM2: Timer T7 Count Input, SSC1 Master Clock Output / Slave Clock Input, Fast External Interrupt 3 Input (default pin), Fast External Interrupt 0 Input (alternate pin A) CAPCOM2: CC24 Capture Inp./Compare Outp., Fast External Interrupt 4 Input (default pin) CAPCOM2: CC25 Capture Inp./Compare Outp., Fast External Interrupt 5 Input (default pin) CAPCOM2: CC26 Capture Inp./Compare Outp., Fast External Interrupt 6 Input (default pin) CAPCOM2: CC27 Capture Inp./Compare Outp., Fast External Interrupt 7 Input (default pin) P1H.1 90 P1H.2 91 P1H.3 92 P1H.4 93 P1H.5 94 P1H.6 95 P1H.7 96 XTAL2 XTAL1 99 100 O I XTAL2: XTAL1: VAREF VAGND VDDI 28 Reference voltage for the A/D converter. 29 Reference ground for the A/D converter. 35, 97 Data Sheet Output of the oscillator amplifier circuit Input to the oscillator amplifier and input to the internal clock generator To clock the device from an external source, drive XTAL1, while leaving XTAL2 unconnected. Minimum and maximum high/low and rise/fall times specified in the AC Characteristics must be observed. Digital Core Supply Voltage (On-Chip Modules): +2.5 V during normal operation and idle mode. Please refer to the Operating Condition Parameters 15 V2.2, 2006-03 XC164-16 XC164-16 Derivatives General Device Information Table 2 Pin Definitions and Functions (cont'd) Symbol Pin Num. Input Outp. Function VDDP 9, 17, 38, 61, 87 Digital Pad Supply Voltage (Pin Output Drivers): +5 V during normal operation and idle mode. Please refer to the Operating Condition Parameters VSSI VSSP 34, 98 Digital Ground. Connect decoupling capacitors to adjacent VDD/VSS pin pairs as close as possible to the pins. All VSS pins must be connected to the ground-line or groundplane. 8, 16, 37, 62, 88 1) The CAN interface lines are assigned to ports P4 and P9 under software control. Data Sheet 16 V2.2, 2006-03 XC164-16 XC164-16 Derivatives Functional Description 3 Functional Description The architecture of the XC164 XC164 combines advantages of RISC, CISC, and DSP processors with an advanced peripheral subsystem in a very well-balanced way. In addition, the on-chip memory blocks allow the design of compact systems-on-silicon with maximum performance (computing, control, communication). The on-chip memory blocks (program code-memory and SRAM, dual-port RAM, data SRAM) and the set of generic peripherals are connected to the CPU via separate buses. Another bus, the LXBus, connects additional on-chip resources as well as external resources (see Figure 3). This bus structure enhances the overall system performance by enabling the concurrent operation of several subsystems of the XC164 XC164. The following block diagram gives an overview of the different on-chip components and of the advanced, high bandwidth internal bus structure of the XC164 XC164. DPRAM CPU Osc / PLL Clock Generator RTC WDT EBC LXBus Control External Bus Control C166SV2 C166SV2 - Core LXBus XTAL OCDS Debug Support DSRAM DMU ProgMem Flash/ROM 64/128 Kbytes PMU PSRAM Interrupt & PEC ADC 8-Bit/ 10-Bit 14 Ch GPT T2 ASC0 ASC1 SSC0 SSC1 SPI SPI CC1 CC2 CC6 T0 T7 T12 T1 T8 T13 USART USART T3 T4 T5 T6 P 20 P 9 5 Peripheral Data Bus Interrupt Bus Twin CAN A B BRGen BRGen BRGen BRGen Port 5 Port 4 Port 3 PORT1 PORT0 14 8 14 16 16 6 MCB04323 MCB04323_X416 Figure 3 Data Sheet Block Diagram 17 V2.2, 2006-03 XC164-16 XC164-16 Derivatives Functional Description 3.1 Memory Subsystem and Organization The memory space of the XC164 XC164 is configured in a Von Neumann architecture, which means that all internal and external resources, such as code memory, data memory, registers and I/O ports, are organized within the same linear address space. This common memory space includes 16 Mbytes and is arranged as 256 segments of 64 Kbytes each, where each segment consists of four data pages of 16 Kbytes each. The entire memory space can be accessed bytewise or wordwise. Portions of the onchip DPRAM and the register spaces (E/SFR) have additionally been made directly bitaddressable. The internal data memory areas and the Special Function Register areas (SFR and ESFR) are mapped into segment 0, the system segment. The Program Management Unit (PMU) handles all code fetches and, therefore, controls accesses to the program memories, such as Flash memory, ROM, and PSRAM. The Data Management Unit (DMU) handles all data transfers and, therefore, controls accesses to the DSRAM and the on-chip peripherals. Both units (PMU and DMU) are connected via the high-speed system bus to exchange data. This is required if operands are read from program memory, code or data is written to the PSRAM, code is fetched from external memory, or data is read from or written to external resources, including peripherals on the LXBus (such as TwinCAN). The system bus allows concurrent two-way communication for maximum transfer performance. 64/128 Kbytes1) of on-chip Flash memory or mask-programmable ROM store code or constant data. The on-chip Flash memory is organized as four 8-Kbyte sectors, one 32-Kbyte sector, and one 64-Kbyte sector. Each sector can be separately write protected2), erased and programmed (in blocks of 128 Bytes). The complete Flash or ROM area can be read-protected. A password sequence temporarily unlocks protected areas. The Flash module combines very fast 64-bit one-cycle read accesses with protected and efficient writing algorithms for programming and erasing. Thus, program execution out of the internal Flash results in maximum performance. Dynamic error correction provides extremely high read data security for all read accesses. For timing characteristics, please refer to Section 4.4.2. 2 Kbytes of on-chip Program SRAM (PSRAM) are provided to store user code or data. The PSRAM is accessed via the PMU and is therefore optimized for code fetches. 2/4 Kbytes1) of on-chip Data SRAM (DSRAM) are provided as a storage for general user data. The DSRAM is accessed via the DMU and is therefore optimized for data accesses. 2 Kbytes of on-chip Dual-Port RAM (DPRAM) are provided as a storage for user defined variables, for the system stack, and general purpose register banks. A register 1) Depends on the respective derivative. The derivatives are listed in Table 1. 2) Each two 8-Kbyte sectors are combined for write-protection purposes. Data Sheet 18 V2.2, 2006-03 XC164-16 XC164-16 Derivatives Functional Description bank can consist of up to 16 wordwide (R0 to R15) and/or bytewide (RL0, RH0, ., RL7, RH7) so-called General Purpose Registers (GPRs). The upper 256 bytes of the DPRAM are directly bitaddressable. When used by a GPR, any location in the DPRAM is bitaddressable. 1024 bytes (2 × 512 bytes) of the address space are reserved for the Special Function Register areas (SFR space and ESFR space). SFRs are wordwide registers which are used for controlling and monitoring functions of the different on-chip units. Unused SFR addresses are reserved for future members of the XC166 XC166 Family. Therefore, they should either not be accessed, or written with zeros, to ensure upward compatibility. In order to meet the needs of designs where more memory is required than is provided on chip, up to 12 Mbytes (approximately, see Table 3) of external RAM and/or ROM can be connected to the microcontroller. Table 3 XC164 XC164 Memory Map1) Address Area Start Loc. End Loc. Area Size2) Notes Flash register space FF'F000H F000H FF'FFFFH 4 Kbytes Flash only3) Reserved (Acc. trap) F8'0000H 0000H FF'EFFFH < 0.5 Mbytes Minus Flash register space Reserved for PSRAM E0'0800H 0800H F7'FFFFH < 1.5 Mbytes Minus PSRAM Program SRAM E0'0000H 0000H E0'07FFH 07FFH 2 Kbytes Maximum Reserved for program memory C2'0000H 0000H DF'FFFFH < 2 Mbytes Minus Flash/ROM Program Flash/ROM C0'0000H 0000H C1'FFFFH 128 Kbytes 4) Reserved BF'0000H 0000H BF'FFFFH 64 Kbytes External memory area 40'0000H 0000H BE'FFFFH < 8 Mbytes Minus reserved segment External IO area5) 20'0800H 0800H 3F'FFFFH < 2 Mbytes Minus TwinCAN TwinCAN registers 20'0000H 0000H 20'07FFH 07FFH 2 Kbytes External memory area 01'0000H 0000H 1F'FFFFH < 2 Mbytes Minus segment 0 Data RAMs and SFRs 00'8000H 8000H 00'FFFFH 32 Kbytes Partly used4) External memory area 00'0000H 0000H 00'7FFFH 32 Kbytes 1) Accesses to the shaded areas generate external bus accesses. 2) The areas marked with "