XAPP659 UG012 XAPP653 XAPP646 LVCMOS25 PCI33 PCI66 LVDCI33 XAPP623 UG112 - Datasheet Archive

 

R Virtex-II Pro / Virtex-II Pro X 3.3V I/O Design Guidelines XAPP659 (v1.7) April 24, 2007 Summary This application note

 

Application Note: Virtex-II Pro / Virtex-II Pro X Family R Virtex-II Pro / Virtex-II Pro X 3.3V I/O Design Guidelines XAPP659 XAPP659 (v1.7) April 24, 2007 Summary This application note describes guidelines on interfacing 3.3V I/O standards (PCI, LVTTL, and LVCMOS) in a VirtexTM-II Pro / Virtex-II Pro X system design. Topics include overshoot/undershoot considerations, external regulator and bus switch solutions, device configuration, and other board level design techniques. For guidelines applicable to other FPGA families, refer to their respective user guides or data sheets. Introduction New system I/O standards continue the trend of lowering supply voltage to gain higher throughput performance. Still, many 3.3V I/O standards, including LVTTL, LVCMOS, and PCI, are prevalent to accommodate legacy requirements. To support all popular design requirements, Virtex-II Pro / Virtex-II Pro X devices offer a range of 3.3V to 1.5V I/O standards. Despite internal device power of 1.5V, the I/Os are designed to meet every system design challenge. To achieve maximum performance and get the best the Virtex-II Pro / Virtex-II Pro X devices have to offer, several 3.3V I/O designs and techniques are highlighted in this application note. This includes managing overshoot/undershoot with termination techniques, regulating VCCO at 3.0V with a voltage regulator, using external bus switches, reviewing configuration methods, and other design considerations. I/O Standard Design Rules Overshoot / Undershoot Undershoot and overshoot voltages on I/Os operating at 3.3V should not exceed the absolute maximum ratings of ­0.3V to 4.05V, respectively, when VCCO is 3.75V. These absolute maximum limits are stated in the absolute maximum ratings table in Table 1 of the Virtex-II Pro and Virtex-II Pro X Platform FPGA Complete Data Sheet, Module 3. However, the maximum undershoot value is directly affected by the value of VCCO. Table 1 describes the worst-case undershoot and overshoot at different VCCO levels. The voltage across the gate oxide at any time must not exceed 4.05V. Consider the case in which the I/O is either an input or a 3-stated buffer as shown in Figure 1. The gate of the output PMOS transistor Po and NMOS transistor No is connected essentially to VCCO and ground, respectively. The amount of undershoot allowed without overstressing the PMOS transistor Po is the gate voltage minus the gate oxide limit, or VCCO ­ 4.05V. Likewise, the absolute maximum overshoot allowed without overstressing the NMOS transistor No is the gate voltage plus the gate oxide limit, or Ground + 4.05V. © 2002­2007 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and further disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design, code, or information as one possible implementation of this feature, application, or standard, Xilinx makes no representation that this implementation is free from any claims of infringement. You are responsible for obtaining any rights you may require for your implementation. Xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of the implementation, including but not limited to any warranties or representations that this implementation is free from claims of infringement and any implied warranties of merchantability or fitness for a particular purpose. XAPP659 XAPP659 (v1.7) April 24, 2007 www.xilinx.com 1 R Output Driver Input Buffer VCCO VCCO Po Power Clamp Diode External Pin Pi DP No Ni Ground Clamp Diode DG GND GND x659_09_111103 Figure 1: Virtex-II Pro / Virtex-II Pro X I/O: 3-Stated Output Driver The lower absolute maximum has a direct relationship with VCCO. It is further extended as VCCO drops below 3.75V. Table 1 summarizes the absolute maximum undershoot and overshoot at different VCCO levels. Note the absolute maximum overshoot value does not change with the VCCO level. Table 1: Absolute Maximum Undershoot and Overshoot VCCO (V) Maximum Undershoot (V) Maximum Overshoot (V) 3.75 ­0.30 4.05 3.6 ­0.45 4.05 3.45 ­0.60 4.05 3.3 ­0.75 4.05 3.0 ­1.05 4.05 The clamp diodes offer protection against transient voltage beyond approximately VCCO + 0.5V and Ground ­ 0.5V. Note the voltage across the diode increases proportionally to the current going through it. Therefore the clamped level is not fixed and can vary depending on the board design. The absolute maximum I/O limits might be exceeded even if the clamp diode is active. The IBIS models contain the voltage-current characteristics of the I/O drivers and clamp diodes. To verify overshoot and undershoot are within the I/O absolute maximum specifications, Xilinx recommends proper I/O termination and performing IBIS simulation. "Appendix A: Termination" summarizes the needs for and methods of termination. XAPP659 XAPP659 (v1.7) April 24, 2007 www.xilinx.com 2 R LVTTL / LVCMOS In general, the LVTTL and LVCMOS drivers should match the board trace impedance to within ±10% to minimize overshoot and undershoot. Source termination is often used for unidirectional interfaces. The Virtex-II Pro / Virtex-II Pro X digitally controlled impedance (DCI) feature has built-in source termination on all user output pins. It compensates for impedance changes due to voltage and/or temperature fluctuations, and can match the reference resistor values. Assuming the reference resistor values are the same as the board trace impedance, the output impedance of the driver will closely match with the board trace. The LVDCI_33 standard is used to enable the DCI features for 3.3V I/O operations. As shown in Figure 2, the OBUF_LVDCI_33 primitive is used to implement the source termination function in Virtex-II Pro / Virtex-II Pro X output drivers. The pull-up resistor connected to VRN and the pull-down resistor connected to VRP determine the output impedance of all the output drivers in the same bank. For more details on using DCI, see UG012 UG012, Virtex-II Pro and Virtex-II Pro X FPGA User Guide. Since the LVDCI_33 standard does not offer input termination, source termination must be implemented on the driver side. Figure 2 shows the recommended external source termination resistors to be incorporated on the external device side. The total impedance of the LVTTL/LVCMOS driver added to the series termination resistor R0 must match the board trace impedance ±10 percent to minimize overshoot and undershoot. An IBIS simulation is advised for calculating the exact value needed for R0. VCCO = 3.3V RREF R0 VRN VRP IBUF_LVDCI_33 Z0 LVTTL/ LVCMOS Driver VCCO R0 + RDriver = Z0 = 50 (typical) RREF Virtex-II Pro / Virtex-II Pro X Any 3.3V I/O Device Z0 OBUF_LVDCI_33 External Device x659_01_060205 Figure 2: Connecting LVTTL or LVCMOS Using the LVDCI_33 Standard The connection scheme shown in Figure 3 is for a bidirectional bus scenario. The signal performance may be degraded by R0. Therefore, it is also recommended to verify the R0 value and performance with an IBIS simulation. OBUFT_LVDCI_33 R0 Z0 IBUF_LVDCI Virtex-II Pro FPGA External Device x659_01_042803 Figure 3: 3.3V I/O Configuration XAPP659 XAPP659 (v1.7) April 24, 2007 www.xilinx.com 3 R The following list contains helpful information for designing with the LVDCI_33 standard: · The output drive strength and slew rates are not programmable. The output impedance references the VRP and VRN resistors, and the output current is determined by the output impedance. · If only LVDCI_33 inputs are used, it is not necessary to connect VRP and VRN to external reference resistors. The implementation pad report does not record VRP and VRN being used. External reference resistors are required only if LVDCI_33 outputs are present in a bank. · LVDCI_33 is compatible with LVTTL and LVCMOS standards only. · Refer to UG012 UG012 on how to use DCI. The user guide shows an HDL example as well as other DCI design considerations. In addition, changing the slew rate from fast to slow and/or reducing the current drive could significantly reduce overshoot and undershoot. The Xilinx Signal Integrity Central website contains additional design information to assist PCB designers and signal integrity engineers. PCI Interface Some interfaces such as PCI do not allow terminations. This section discusses alternatives for managing overshoot and undershoot for such applications. As stated in Table 1, when VCCO is lowered to 3.0V, the absolute maximum level remains at 4.05V. The power clamp diode limits overshoot at about 3.5V, preventing the upper absolute maximum level from being exceeded. Similarly, the lower absolute maximum limit is ­1.05V when VCCO is 3.0V. In this case, the ground clamp diode clips undershoot at around ­0.5V, preventing the lower absolute maximum level from being exceeded. Therefore, lowering VCCO to 3.0V addresses the PCI overshoot and undershoot specifications. Refer to XAPP653 XAPP653, 3.3V PCI Design Guidelines, for more implementation details. External Bus Switch Another alternative to address overshoot and undershoot uses an external bus switch. XAPP646 XAPP646, Connecting Virtex-II Devices to a 3.3V/5V PCI Bus, discusses using IDT QuickSwitch devices to buffer between Virtex-II Pro / Virtex-II Pro X I/Os and external device driving signals between 3.3V to 5V. Device Configuration Virtex-II Pro / Virtex-II Pro X devices can be configured through a JTAG interface port, a serial PROM, or by a System ACE controller. Dedicated configuration pins such as CCLK, PROG_B, DONE, M2, M1, and M0 are powered by VCCAUX at 2.5V, including the PWRDWN_B and HSWAP_EN pins. Dual-purpose configuration pins such as DIN, D1:D7, CS_B, RDWR_B, BUSY/DOUT, and INIT_B can be either 2.5V or 3.3V. See Table 2 for details. This section describes 3.3V I/O interface considerations for each configuration method. For further information on configuration, refer to UG012 UG012. XAPP659 XAPP659 (v1.7) April 24, 2007 www.xilinx.com 4 R Table 2: Virtex-II Pro / Virtex-II Pro X Pins and Bias Voltages Pin Name Bias Direction Voltage (V) Comments Input/ Output 2.5 Pin is biased by VCCAUX. Input should not be driven by a 3.3V signal unless a 100 series resistor is used. Output is LVCMOS25 LVCMOS25 and compatible with LVTTL. Input 2.5 Pin is biased by VCCAUX (2.5V). It should not be pulled up to 3.3V unless a 100 resistor is used. Open-drain output 2.5 Pin is biased by VCCAUX (2.5V). It should not be pulled up to 3.3V unless a 470 pull-up resistor is used. M2, M1, M0 Input 2.5 Pin is biased by VCCAUX (must be 2.5V). These pins should not connect to 3.3V unless 100 series resistors are used. HSWAP_EN Input 2.5 Pin is biased by VCCAUX (must be 2.5V). This pin should not connect to 3.3V unless a 100 series resistor is used. TDI Input 2.5/3.3 Powered by VCCAUX. Although pin is 3.3V tolerant. TMS Input 2.5/3.3 Powered by VCCAUX. Although pin is 3.3V tolerant. TCK Input 2.5/3.3 Powered by VCCAUX. Although pin is 3.3V tolerant. TDO Open-drain Output 2.5/3.3 Pin is open-drain and can be pulled to 3.3V. The external pull-up is recommended to be greater than 200. There is no internal pull-up. CCLK PROG_B DONE Pin is biased by VCCAUX (2.5V). It has an internal pullup. Do not pull up externally to 3.3V unless a 100 series resistor is used. This pin does not support the power-down feature. Input 2.5 Input/ Output 2.5/3.3 Pins are biased by VCCO CS_B Input 2.5/3.3 Pins are biased by VCCO RDWR_B Input 2.5/3.3 Pins are biased by VCCO BUSY/DOUT Input 2.5/3.3 Pins are biased by VCCO Input/ Output 2.5/3.3 Pins are biased by VCCO VRP Input N/A VRN Input 2.5/3.3 Reference resistor must be pulled to VCCO VREF Input 2.5/3.3 Depends on the I/O standard used. DXN, DXP N/A N/A These are the cathode and anode of the temperature diode VBATT Input 3.0 Battery supply for the encryption keys Input/ Output Various PWRDWN_B DIN/D0-D7 INIT_B User I/O XAPP659 XAPP659 (v1.7) April 24, 2007 www.xilinx.com Reference resistor pulled to GND All regular user I/Os support the following 3.3V signaling standards: LVTTL, LVCMOS, PCI33 PCI33, PCI66 PCI66, PCIX, LVDCI33 LVDCI33 5 R Dedicated Configuration Pins Dedicated configuration pins such as CCLK, PROG_B, DONE, M2, M1, and M0 are powered by VCCAUX at 2.5V, so they must not be exposed to 3.3V signals. However, in those cases in which these pins must be connected to 3.3V, Xilinx highly recommends either one of the following courses of action: · Connect the pins to 42 series resistors before they connect to 3.3V. · Ensure that no more than 8 mA of current goes through these pins at any time. The DONE pin can connect through a 470 series resistor to 3.3V. If the DONE pins of multiple FPGAs are connected together and the pull-up resistor values recommended by the other FPGA family are larger than 470, use the larger value for the connected DONE pin. JTAG Configuration Although JTAG pins are powered by VCCAUX (2.5V), all JTAG input pins are 3.3V compatible and operate between 2.5V and 3.3V TTL levels. The JTAG output pin, TDO, is an open-drain output. It does not have an internal pull-up resistor and must be pulled up with an external resistor on the PCB. The maximum pull-up voltage is 3.3V. It is recommended to use an external pull-up resistor greater than 200. Different resistor values yield different JTAG performance. Perform IBIS simulation to verify the speed. Series resistors are not needed for JTAG pins because they do not have clamp diodes. Serial PROM Configuration Xilinx recommends using the XCFxxP/XCFxxS series of Platform Flash In-System Programmable Configuration PROMs. The XC18Vxx configuration PROMs also can be used. These families provide 3.3V or 2.5V output capabilities. When interfacing to the Virtex-II Pro / Virtex-II Pro X device in master serial mode, the VCCO of the PROM and the VCCO of the Virtex-II Pro / Virtex-II Pro X device should connect to the same voltage level (2.5V or 3.3V). Figure 4 shows the Virtex-II Pro / Virtex-II Pro X FPGA and the configuration PROM in master serial configuration. VCCO = 2.5V/3.3V Platform Flash PROM CLK DO CE RESET/OE VCCO = 2.5V/3.3V VCCAUX = 2.5V CCLK DIN Virtex-II Pro FPGA INIT_B DONE M0 M1 M2 GND x659_07_041307 Figure 4: Virtex-II Pro / Virtex-II Pro X FPGA and PROM in Master Serial Configuration Although the noise margin of LVCMOS_25 driving LVTTL is 100 mV, the LVCMOS25 LVCMOS25 driver will drive from rail-to-rail if the devices are connected as shown in Figure 4. In slave serial mode, the VCCO of the FPGA can be either 2.5V or 3.3V. However, ensure the CCLK pin of the FPGA is not exposed to 3.3V unless a 100 series resistor is used or the current is less than 3 mA. System ACE Configuration When interfacing a System ACE controller to a Virtex-II Pro / Virtex-II Pro X FPGA, set the VCCO of the System ACE controller to either 1.8V or 2.5V, depending upon system DC power availability. For more information, see the System ACE website. XAPP659 XAPP659 (v1.7) April 24, 2007 www.xilinx.com 6 R Further System Design Considerations Supported 3.3V I/O Standards The Virtex-II Pro / Virtex-II Pro X family supports the following 3.3V I/O standards: · LVTTL: 24 mA, 16 mA, 12 mA, 8 mA, 6 mA, 4 mA, and 2 mA · LVCMOS_33: 24 mA, 16 mA, 12 mA, 8 mA, 6 mA, 4 mA, and 2 mA · PCI_33, PCI_66, and PCI_X · LVDCI_33 DC Power Distribution System Designers need to consider power distribution in their system designs. Many systems have 5V, 3.3V, 2.5V, 1.8V, 1.5V, and other DC power requirements. Use XAPP623 XAPP623, Power Distribution System (PDS) Design: Using Bypass/Decoupling Capacitors, as a guide to determine board level decoupling requirements for a successful system design Package Thermal Management The absolute maximum junction temperature (TJ) is 125°C for 3.3V I/O operation for the Virtex-II Pro / Virtex-II Pro X FPGA. Use Xilinx package guide UG112 UG112, Device Package User Guide, as a design resource for thermal measurement techniques, package thermal characteristics, and options for power management in a system environment. The document also contains some references for heat-sink and interface material suppliers. LVDS Although the Virtex-II Pro / Virtex-II Pro X Platform FPGA does not support LVDS_33, its input and output specifications are compatible with LVDS_25. It is acceptable to use LVDS_25 in place of LVDS_33. Choosing Solutions Both XAPP653 XAPP653 and XAPP646 XAPP646 have been fully verified. Xilinx recommends XAPP653 XAPP653 for designing Virtex-II Pro / Virtex-II Pro X systems in a PCI 3.3V environment, as it is PCI-compliant and provides a lower cost solution than XAPP646 XAPP646. Table 3 lists application notes to consult for guidance, based on the PCI signaling environment. Table 3: Reference Application Notes Signaling Environment Virtex-II Devices Virtex-II Pro / Virtex-II Pro X Devices PCI 3.3V Not Required XAPP653 XAPP653 or XAPP646 XAPP646 PCI 5.0V XAPP646 XAPP646 XAPP646 XAPP646 LVTTL/LVCMOS33 LVTTL/LVCMOS33 Not Required XAPP659 XAPP659 Mixing Techniques Either using LVDCI_33 standard or lowering the VCCO to 3.0V is a good approach to address overshoot and undershoot. It is also acceptable to combine both methods. When VCCO is lowered to 3.0V, it is not necessary to adjust the reference resistors VRP and VRN. The VRP and VRN values should always be the same as the board trace impedance. XAPP659 XAPP659 (v1.7) April 24, 2007 www.xilinx.com 7 R Conclusion Virtex-II Pro / Virtex-II Pro X devices support 3.3V I/O standards (LVTTL, LVCMOS33 LVCMOS33, LVDCI33 LVDCI33, PCI33/66 PCI33/66, and PCI-X) when the following guidelines are met: 1. Keep signal overshoot and undershoot within the absolute maximum FPGA device specifications. Four methods are discussed: a. Source termination using LVDCI_33 b. Slow slew rate and/or reduced drive current c. Voltage regulation at 3.0V for PCI d. External high-speed bus switches for PCI 2. For PCI bus solutions, use either XAPP653 XAPP653 or XAPP646 XAPP646. 3. Dedicated I/O pins are restricted to 2.5V only. 4. The absolute maximum junction temperature (TJ) is 125°C for 3.3V I/O operation. Appendix A: Termination Transmission line effects can cause voltage deviations at both the driver and receiver. The worst of these effects causes voltage doubling. For example, a 3.3V I/O standard signal can double to 6.6V at the load when termination effects are ignored. Clock frequency is not a parameter of interest. Transmission line effects cannot be ignored simply because a design uses a relatively slow clock frequency. Transmission line effects become prevalent when the time it takes a signal to propagate from the driver to the receiver and back to the driver is longer than 1/6th the I/O rise or fall time. Typical transmission speeds on a printed circuit board (PCB) are 200 ps per inch. Figure 5 shows the difference between the LVCMOS 24mA fast slew rate driver (24F) and LVCMOS 2mA slow slew rate driver (2S) when driving into an unterminated load. The respective rise times are approximately 1 ns vs. 7 ns, or a 7:1 variation. The maximum trace length before transmission line effects become prominent for a 1 ns rise time is (1/6) * (1 ns) * (1/2) * (1 inch/0.2 ns), or 0.42 inches. For a 7 ns rise time, the result is (1/6) * (7 ns) (1/2) (1 inch/0.2 ns), or 2.9 inches. lvcm3 into high-Z input 4.9 3.9 Voltage 2.9 1.9 0.9 -0.1 5.0E-10 0E-10 -1.1 2.5E-09 5E-09 24F 4.5E-09 5E-09 2S 6.5E-09 5E-09 Time 8.5E-09 5E-09 1.1E-08 1E-08 1.3E-08 3E-08 x659_10_041307 Figure 5: Rise Time Comparison between Slowest and Fastest LVCMOS I/O Selections To satisfy high-speed memory design requirements, faster I/O drivers typically are chosen. Typical memory, processor, and FPGA device packages exceed 0.4 inches in size. Therefore, it is realistic to expect transmission line effects for virtually all practical memory PCB layouts. XAPP659 XAPP659 (v1.7) April 24, 2007 www.xilinx.com 8 R Xilinx recommendeds that the slowest I/O speed possible is used for a given application, which might contradict the high-speed memory application requirements above. Nevertheless, serious consideration must given to using the slowest slew rate possible. Figure 6 depicts the receiver signals for two different slew rate selections with the same 50, 0.5 ns long transmission line interconnect. From the figure, the slower slew rate does not suffer the same magnitude overshoot and undershoot issues at the receiver. Virtex-II Pro LVCMOS 324F vs 312S, 0.5 ns, 50 Unterminated Transmission Line 4.0 3.0 Voltage 2.0 1.0 0.0 0.0E+00 -1.0 2.0E-08 0E-08 LVCM324F LVCM324F 4.0E-08 0E-08 LVCM312S LVCM312S 6.0E-08 0E-08 Time 8.0E-08 0E-08 1.0E-07 0E-07 1.2E-07 2E-07 x659_11_041307 Figure 6: Example Slew Rate Impact at the Receiver on Overshoot and Undershoot Transmission line effects are captured by the reflection equation that states the voltage excursion at the load follows the relationship: (RLOAD ­ Z0)/(RLOAD + Z0) An unterminated high-impedance condition at the receiver causes voltage doubling at the receiver. In this situation, RLOAD (load input impedance) is very high-much greater than the transmission line impedance, Z0. Because typical transmission line impedances range from 45 to 65 and receiver input impedances are in the mega-ohms, large voltage overshoots and undershoots can occur easily in unterminated situations. The undershoot condition suffers the same consequence, that is, simply a negative overshoot. The impact of implementing LVCMOS versus LVTTL drivers into an unterminated receiver is illustrated in Figure 7. XAPP659 XAPP659 (v1.7) April 24, 2007 www.xilinx.com 9 R Virtex-II Pro LVCMOS & LVTTL into a 1M Load 5.5 5.7v 5.5v 4.5 3.5 Voltage 2.5 1.5 0.5 -0.5 0.0E+00 2.0E-09 0E-09 4.0E-09 0E-09 6.0E-09 0E-09 8.0E-09 0E-09 1.0E-08 0E-08 1.2E-08 2E-08 1.4E-08 4E-08 1.6E-08 6E-08 1.8E-08 8E-08 2.0E-08 0E-08 -1.5 -2.5 LVCM324F LVCM324F_1MegLd LVTTL24F LVTTL24F_1MegLd -3.5 Time x659_12_041307 Figure 7: Overshoot and Undershoot Effects Various configurations of passive components, referred to as terminations, can significantly reduce overshoot and undershoot voltage excursions. Some of the most basic configurations are Series, Parallel, and Split Parallel. These three configurations are described below along with their subsequent impact. Series Source Termination Series Resistor (RS) Source Termination is accomplished by placing a resistor in series with the driver pin. PCB trace having impedance Z0. The resistor should be placed close to the driver to minimize the effect of reflections between the driver and the resistor. Figure 8 depicts the classic series termination technique. RSOURCE Z0 C xapp659_14_011604 Figure 8: Series Source Termination Topology As indicated previously, Z0 represents the impedance of the PCB trace and is assumed to be one uniform value over the trace length. The capacitor in the schematic represents the connection capacitance from the receiver to the driver reference and is composed mainly of the component package connection and receiver die capacitance. Using one capacitance value is a low frequency approximation, which is valid as long as the rise time of the arriving signal is significantly less than the propagation time from the package pin to the die. Many rules of thumb exist, but one in common practice is 1/6th of the package propagation time. Overshoot and undershoot are minimized by choosing the series resistor's value in the following manner: RSOURCE = Z0 ­ Driver Output Impedance Driver Output Impedance varies with the SelectIOTM resource, but typically ranges between 15 and 45. Using an IBIS simulation in conjunction with Xilinx IBIS models is the recommended way to optimize driver impedance determination and subsequent selection of RSOURCE. XAPP659 XAPP659 (v1.7) April 24, 2007 www.xilinx.com 10 R By following this technique, the transmitted I/O standard voltage high state is reduced to half. The technique relies on the assumption that the receiver input impedance is very high. Therefore, by the reflection equation, the transmitted voltage doubles at the receiver. Subsequently, this doubled voltage reflects back toward the driver. But, in choosing RSOURCE as indicated above, the load impedance matches Z0 and the reflection ceases at the driver. This technique works best for unidirectional interfaces. In particular, clocks, address, and control signals benefit from this topology. Figure 9 shows a 25 series termination example with Virtex-II Pro / Virtex-II Pro X LVCMOS 324F drivers. Virtex-II Pro LVCM324F LVCM324F Virtex-II Pro LVCM324F LVCM324F CELL:B0 25.0 ohms RS(B0) CELL:C0 50.0 ohms 500.000 ps Simple xapp659_15_011604 Figure 9: Series Termination Schematic Figure 10 shows the effects of RSOURCE in this circuit, comparing RSOURCE values of 0 and 25. A distinct advantage of Series Source Termination is that the resistor limits trace current, which helps in reducing overall power consumption and electromagnetic emissions (EMI). Virtex-II Pro LVCMOS324F LVCMOS324F, 200 MHz Clk Series Termination Example 4.0 Voltage 3.0 2.0 1.0 0.0 0.0E+00 1.0E-09 0E-09 25 Rs 2.0E-09 0E-09 3.0E-09 0E-09 4.0E-09 0E-09 5.0E-09 0E-09 6.0E-09 0E-09 7.0E-09 0E-09 8.0E-09 0E-09 9.0E-09 0E-09 1.0E-08 0E-08 0 Rs -1.0 Time x659_16_041307 Figure 10: Waveforms Generated by the Series Termination Schematic XAPP659 XAPP659 (v1.7) April 24, 2007 www.xilinx.com 11 R Parallel Termination Figure 11 shows the parallel termination topology, where a terminating resistor (RL) is placed at the receiver to an AC voltage reference. The resistor needs to be placed as closely to the receiver as feasible to minimize reflections between the receiver and the resistor. The simplest reference for the terminating resistor is ground. The I/O standard driving waveform propagates at full magnitude toward the receiver. If RL is matched with Z0, the reflection equation produces a result of zero, indicating that a reflection is not produced. Check VOH/ RL for current drain and power consumption to ensure that neither the driver or resistor specifications are violated. Z0 RL C xapp659_17_020304 Figure 11: Parallel Termination Topology Figure 12 shows the schematic for Parallel termination. Virtex-II Pro LVCM324F LVCM324F Virtex-II Pro LVCM324F LVCM324F CELL:D0 50.0 ohms 500.000 ps CELL:E0 50.0 ohms RD(E0) Simple VpullDn=0.000V xapp659_18_020304 Figure 12: Parallel Termination Schematic Figure 13 presents waveforms for two Parallel termination schematic cases: matched termination and unterminated instances are shown (RL is absent). A pseudo random bitstream (PRBS) pattern is shown instead of the clock pattern to better represent this technique's application, which typically is an address bus. Virtex-II Pro LVCMOS324F LVCMOS324F, 2.5 ns/bit PRBS Data Pattern 4.0 3.0 Voltage 2.0 1.0 0.0 0.0E+00 -1.0 1.0E-08 0E-08 Unterminated 2.0E-08 0E-08 3.0E-08 0E-08 50 to GND 4.0E-08 0E-08 Time 5.0E-08 0E-08 6.0E-08 0E-08 7.0E-08 0E-08 x659_19_041307 Figure 13: Waveforms Generated by the Parallel Termination to Ground Schematic XAPP659 XAPP659 (v1.7) April 24, 2007 www.xilinx.com 12 R Split Parallel Termination Figure 14 shows the Split Parallel Termination topology. The additional resistor offers adjustment of a driver's high versus low output impedance. If this impedance is symmetrical, then R1 = R2. Further, the parallel combination of R1 and R2 must match Z0. VCC R1 Z0 R2 C xapp659_20_011604 Figure 14: Split Parallel Termination Topology VCC may be chosen to center the driver output swing near the receiver logic switch level threshold, thereby minimizing terminator power consumption, maximizing frequency of operation, and minimizing duty cycle distortion. This termination technique creates a more symmetrical waveform at the receiver and should be used when duty cycle is critical. Power consumption of the VCC supply as well as the power dissipated in the termination resistors and driver must be considered. Figure 15 shows a schematic of this termination technique. VpullUp=3.300V Virtex-II Pro LVCM324F LVCM324F Virtex-II Pro LVCM324F LVCM324F CELL:D0 50.0 ohms 500.000 ps Simple 100.0 ohms RP(E0) CELL:E0 100.0 ohms RD(E0) VpullDn=0.000V xapp659_21_011604 Figure 15: Split Parallel Termination Schematic Figure 16 shows example waveforms generated by the schematic in Figure 15 using a PRBS pattern was used. Note that undershoot must be reduced compared to the simple parallel termination technique. XAPP659 XAPP659 (v1.7) April 24, 2007 www.xilinx.com 13 R Split Parallel Termination 100/100 3.3V/Gnd Example Virtex-II Pro LVCMOS324F LVCMOS324F, 2.5 ns/bit PRBS Data Pattern 4.0 3.0 Voltage 2.0 1.0 0.0 0.0E+00 -1.0 1.0E-08 0E-08 Unterminated 2.0E-08 0E-08 3.0E-08 0E-08 100/100 3.3V/GND 4.0E-08 0E-08 5.0E-08 0E-08 6.0E-08 0E-08 Time 7.0E-08 0E-08 x659_22_041307 Figure 16: Waveforms Generated by the Split Parallel Termination Schematic Xilinx offers an integrated solution for SSTL and HSTL technologies. This solution is referred to as DCI and effectively creates a split parallel termination or series termination associated with the SSTL and HSTL standards. An SSTL example is depicted in Figure 17. Virtex-II Pro SSTL2C2 Virtex-II Pro DCISSTL2C2_I CELL:B4 50.0 ohms 500.000 ps Simple CELL:C4 xapp659_23_011604 Figure 17: SSTL Schematic The waveforms generated by this schematic are shown in Figure 18. XAPP659 XAPP659 (v1.7) April 24, 2007 www.xilinx.com 14 R SSTL2C2 with and without DCI 4.0 3.0 Voltage 2.0 1.0 0.0 0.0E+00 -1.0 1.0E-08 0E-08 without DCI 2.0E-08 0E-08 3.0E-08 0E-08 DCI engaged 4.0E-08 0E-08 5.0E-08 0E-08 6.0E-08 0E-08 7.0E-08 0E-08 Time x659_24_041307 Figure 18: Waveforms Generated by SSTL2C2 Schematic DCI is an effective mechanism to prevent unwanted overshoot and undershoot. Refer to UG012 UG012 to view all DCI options. Additionally, parasitics such as vias, lead wires, solder bumps and packaging as well as temperature and silicon process variations affect the exact nature of reflections. Therefore, a safety margin is recommended when dealing with overshoot and undershoot. Revision History The following table shows the revision history for this document. Date 10/25/02 1.0 Initial Xilinx release. 01/06/03 1.1 Add PCIX, LVTTL_33 and LVCMOS_33 support. Removed 3.3V banking restrictions 01/07/03 1.2 Added new sub-section on supported 3.3V I/O standards. 05/06/03 1.3 Revised "Serial PROM Configuration" section. Added Table 2. Removed implementation support section since the tools have been updated. Revised "Further System Design Considerations". Clarified 100°C for 3.3V I/O operation in "Package Thermal Management". 12/01/03 XAPP659 XAPP659 (v1.7) April 24, 2007 Version Revision 1.4 Revised "Overshoot / Undershoot", "PCI Interface", and "Serial PROM Configuration" sections. Updated series and pull-up resistor information for Table 2. Added "Dedicated Configuration Pins" sections describing series resistor requirements for dedicated configuration pins. Revised absolute maximum junction temperature to 125·C. Added slow slew rate and/or reduced drive current bullet to "Conclusion". Added Appendix A containing voltage-current characteristics for I/O protection diodes. www.xilinx.com 15 R Date Version 02/04/04 1.5 Replaced "Appendix A: Termination" with transmission line and termination information. Moved "Conclusion" above the appendix. 06/09/05 1.6 · Corrected all references to Virtex-II Pro devices to include Virtex-II Pro X devices. · Deleted redundant material already covered in XAPP653 XAPP653 and XAPP646 XAPP646, replacing it with references to these application notes. · Revised Table 2. · Revised "Dedicated Configuration Pins" section. · Revised "Package Thermal Management" section. 04/24/07 XAPP659 XAPP659 (v1.7) April 24, 2007 1.7 Revision www.xilinx.com 16