XAPP079 XC9500 XC9536 XC4025E XC9536-15PC44 HW-130 XC4010EX/XL XC4013EX/XL - Datasheet Archive

 

XAPP079 September, 1997 (Version 1.2) 4Mbit Virtual SPROM Application Note Summary This application note describes the design of

 

® XAPP079 XAPP079 September, 1997 (Version 1.2) 4Mbit Virtual SPROM Application Note Summary This application note describes the design of a very low cost, CPLD-based virtual SPROM for downloading programming information to the Xilinx high density XC4000-Series FPGAs. Xilinx Family XC9500 XC9500 Introduction Typically, designers of embedded applications use serial PROMs (SPROMs) to store and download the configuration data for XC4000-Series FPGAs. SPROMs yield faster configuration rates and reduce the amount of circuitry required to program FPGAs. As FPGA densities continue to grow, so do their configuration memory requirements; the SPROM program memory requirements for a high density XC4000-Series FPGA can be 512K bits or more. The virtual serial PROM (VSPROM) solution described in this application note uses a low cost XC9536 XC9536 CPLD, a standard byte-wide EPROM, and an on-board crystal oscillator to support embedded programming of high density XC4000Series FPGAs. Design Description Figure 2 shows the schematic of the circuitry used to configure an XC4025E XC4025E FPGA using the VSPROM design. The XC4025E XC4025E requires 422,128 configuration bits, which are supplied by U4, a 64Kx8 (512K bits) UV EPROM. U1 is an XC9536-15PC44 XC9536-15PC44 CPLD, used to read the data from the EPROM and download it to the FPGA. An on-board crystal oscillator clocks the VSPROM design and supplies configuration clocks (CCLKs) to the FPGA. The FPGA is connected in SLAVE SERIAL MODE (see the Xilinx Data Book for information on XC4000-Series configuration modes). You can use this reference design as-is, or you can modify the design as required. The XC9536 XC9536 acts as an intelligent state machine monitoring the FPGA's INIT and DONE pins while pumping serial configuration data into the FPGA's DIN pin. Figure 1 shows the state diagram. The configuration process is started on the falling edge of the FPGA INIT pin. Data is continually read and shifted into the FPGA until the rising edge of the DONE pin. If INIT goes low during configuration, the XC9536 XC9536 will pulse the FPGA's /PROGRAM pin low, reset the state machine, and consequently restart the configuration process. Figure 3 shows the ABEL code describing the VSPROM design. Bits d7 through d0 are data bus interface pins to XAPP079 XAPP079 September, 1997 (Version 1.2) the EPROM. Data registers data7 through data0 are internal nodes used to latch and shift the incoming configuration data from the EPROM. The data registers are broken into two busses of four bits each: busA and busB. State SHIFT_A shifts busA while loading EPROM data into busB. State SHIFT_B shifts busB while loading EPROM data into busA. This provides a continual stream of data into the FPGA with no interruption in CCLK. The state machine enters the LASTCLKS state on the rising edge of the DONE pin to provide the last few CCLKs to the FPGA. This is required to bring the FPGA out of configuration and enable its I/O. Finally, the state machine enters the DONE state to complete the process. CCLK from the XC9536 XC9536 to the FPGA is output-enabled to ensure that the FPGA doesn't receive stray clocks while the VSPROM state machine is in the DONE state. Since the CCLK output goes into a high impedance condition while in the DONE state, resistor R6 is tied to ground to ensure that CCLK is always in a known state. Design Implementation This VSPROM design is fully verified with both functional and timing vectors. Figure 4 shows the timing simulation waveforms created with Viewlogic's ViewSimTM. Configuration rates up to 10MHz were successfully simulated. The XC9536 XC9536 CPLD was programmed with a Xilinx HW-130 HW-130 V4.0 programmer, and the EPROM was programmed with a generic EPROM programmer. The XC9536 XC9536 is an IEEE 1149.1 compliant ISP CPLD, and therefore could be programmed in-system via the JTAG port, TDI, TCK, TMS, and TDO. To verify the design, XACTstep was used to implement a simple Johnson Counter in the XC4025E XC4025E FPGA. The design was placed and routed using default settings. The PROM File Formatter utility in XACTstep produced a byte wide 64Kx8 (512K bits) MCS EPROM file using default settings for starting address and loading direction. The design was assembled on a generic prototyping board and configuration rates up to 5 MHz were verified. The XC4025E XC4025E FPGA used in this application note requires 422,128 program bits. Therefore, only address lines 0 through 15 were 1 4Mbit Virtual SPROM required. A total of 19 address lines (4Mbits addressable space) are available for different configurations. in mixed voltage systems (ie 5v/3.3v) by connecting it's Vccio pin to the appropriate voltage source. See the XC9500 XC9500 Data Sheets for more information. Table 1 shows the EPROM and address line requirements for each XC4000-Series device that requres more than 256Kbits of SPROM memory (see Xilinx Data Book, June 16, 1997 for more information). Use the Xilinx PROM File Formatter in XACTstep to determine the approximate EPROM size for daisy chains. If required, connect up to 3 additional address lines. Finally, the XC9536 XC9536 may be used Conclusion This Virtual SPROM application note provides an ultra low cost solution to support embedded programming of high density XC4000-Series FPGAs. !INIT DONE INIT AND !DONEPIN !INIT !INIT Counter = 3 SHIFT_B SHIFT_A Counter = 3 Counter = 3 DONEPIN DONEPIN LASTCLKS Figure 1: State Diagram FPGA Target Device XC4010EX/XL XC4010EX/XL XC4013EX/XL XC4013EX/XL XC4020E XC4020E XC4020EX/XL XC4020EX/XL Req. Program Bits 283,376 393,580 329,264 521,832 Req. EPROM Bits 283,424 393,632 329,312 521,880 XC4025E XC4025E XC4028EX/XL XC4028EX/XL 422,128 668,132 422,176 668,184 XC4036EX/XL XC4036EX/XL 832,480 832,528 XC4044EX/XL XC4044EX/XL 1,014,876 1,014,928 XC4052EX/XL XC4052EX/XL 1,215,320 1,215,368 XC4062EX/XL XC4062EX/XL 1,433,812 1,433,864 XC4085EX/XL XC4085EX/XL 1,924,940 1,924,992 CPLD Requirements XC9536 XC9536 (using design as shown) XC9536 XC9536 (using design as shown) XC9536 XC9536 (using design as shown) XC9536 XC9536 (connect address lines 0 thru 16 to standard 1M EPROM) XC9536 XC9536 (using design as shown) XC9536 XC9536 (connect address lines 0 thru 16 to standard 1M EPROM) XC9536 XC9536 (connect address lines 0 thru 16 to standard 1M EPROM) XC9536 XC9536 (connect address lines 0 thru 16 to standard 1M EPROM) XC9536 XC9536 (connect address lines 0 thru 17 to standard 2M EPROM) XC9536 XC9536 (connect address lines 0 thru 17 to standard 2M EPROM) XC9536 XC9536 (connect address lines 0 thru 17 to standard 2M EPROM) Table 1: EPROM and CPLD Requirements 2 XAPP079 XAPP079 September, 1997 (Version 1.2) XAPP079 XAPP079 September, 1997 (Version 1.2) D 1 XC4025 XC4025.SCH 2 M2 M1 M0 3 R3 5.1K MODE PINS M2 M1 M0 DONE /INIT R6 5.1K 4 U8 VCC I/O I/O I/O GND I/O I/O I/O I/O TDI TMS I/O R4 5.1K 7 8 9 10 11 12 13 14 15 16 17 R5 5.1K 28 27 26 25 24 23 22 21 20 19 18 DONE /INIT ADR9 ADR0 ADR1 4 I/O I/O I/O I/O I/O GND I/O VCCINT I/O I/O I/O DIN /PROGRAM CCLK XC4025E XC4025E CCLK /PROGRAM D2 D3 D1 D5 D0 D4 3 ADR10 ADR10 I/O VCCINT I/O I/O I/O I/O I/O I/O I/O I/O I/O C 2 ADR13 ADR13 ADR12 ADR12 ADR11 ADR11 40 41 42 43 44 1 2 3 4 5 6 B A 1 ADR15 ADR15 ADR14 ADR14 CLK D6 D7 Figure 2: VSPROM Schematic 3 I/O I/O I/O I/O I/O I/O I/O VCCIO GND TDO I/O 5 D[0.7] DOUT ADR2 ADR3 ADR4 ADR5 ADR6 ADR7 ADR8 ADR[0.15] XC9536 XC9536 39 38 37 36 35 34 33 32 31 30 29 U1 5 6 6 R1 5.1K U6 VCC R2 5.1K U5 GND ADR0 ADR1 ADR2 ADR3 ADR4 ADR5 ADR6 ADR7 ADR8 ADR9 ADR10 ADR10 ADR11 ADR11 ADR12 ADR12 ADR13 ADR13 ADR14 ADR14 ADR15 ADR15 U3 GND 20 22 10 9 8 7 6 5 4 3 25 24 21 23 2 26 27 1 7 1 7 27512 UV-EPROM CE OE A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 U4 O0 O1 O2 O3 O4 O5 O6 O7 OUT VCC CRYSTAL GND NC U2 7 8 11 12 13 15 16 17 18 19 14 D0 D1 D2 D3 D4 D5 D6 D7 U7 VCC 8 8 D C B A 4Mbit Virtual SPROM MODULE VSPROM TITLE ` Virtual 4Mbit SPROM to configure XC4K FPGAs. VERSION: 1.2 DATE: 9/97' "inputs init, donepin, clk d7.d0 pin 24,25,28; pin 26,27,40,5,14,13,7,42; "outputs adr18.adr0, program pin istype `reg'; cclk dout pin 11; pin 29; "nodes data7.data0, count1, count0, s1, s0 node istype `reg'; outen, reset node istype `com, keep'; declarations counter = [count1.count0]; address = [adr18.adr0]; busA = [data3.data0]; busB = [data7.data4]; inA = [d3.d0]; inB = [d7.d4]; inAB = [d7.d0]; XEPLD PROPERTY `LOGIC_OPT OFF outen, reset'; XEPLD PROPERTY `PWR LOW program'; Z, C, X = .Z., .C., .X.; @DCSET; "State values DONE =^b00; SHIFT_A =^b11; SHIFT_B =^b10; LASTCLKS =^b01; VSPROM = [s1.s0]; equations VSPROM.clk = clk; address.clk = clk; counter.clk = clk; busA.clk = clk; busB.clk = clk; program.clk = clk; program.ar = !init & s1; cclk = !clk; cclk.oe = outen; counter := !reset & (counter + 1); when reset then address := 0; else when (VSPROM = SHIFT_A) & (counter = 3) & !reset) then address := address + 1; else address := address; when (VSPROM = DONE) then reset = 1; else when (VSPROM = SHIFT_A) # (VSPROM = SHIFT_B) & donepin) then reset = 1; else reset = 0; when (VSPROM = DONE) then {outen = 0; busA := inA; busB := inB; program := 1; dout = data0;} Figure 3: ABEL Code for VSPROM 4 XAPP079 XAPP079 September, 1997 (Version 1.2) when (VSPROM = SHIFT_A) then {outen = 1; program := 1; busB := inB; data0 := data1; data1 := data2; data2 := data3; dout = data0;} else when (VSPROM = SHIFT_B) then {outen = 1; program := 1; busA := inA; data4 := data5; data5 := data6; data6 := data7; dout = data4;} else when (VSPROM = SHIFT_A) & (counter = 3) then dout = data0; else when (VSPROM = SHIFT_B) & (counter = 3) then dout = data4; else when (VSPROM = LASTCLKS) then {program := 1; outen = 1;} state_diagram VSPROM; state DONE: if (!init) then DONE; else if (!donepin) then SHIFT_A; else DONE; state SHIFT_A: if (!init) then DONE; else if (donepin) then LASTCLKS; else if (VSPROM = SHIFT_A) & (counter = 3) then SHIFT_B; else SHIFT_A; state SHIFT_B: if (!init) then DONE; else if (donepin) then LASTCLKS; else if (VSPROM = SHIFT_B) & (counter = 3) then SHIFT_A; else SHIFT_B; state LASTCLKS: if (VSPROM = LASTCLKS) & (counter = 3) then DONE; else LASTCLKS; end; Figure 3 - Continued XAPP079 XAPP079 September, 1997 (Version 1.2) 5 4Mbit Virtual SPROM DONEPIN 1 INIT 0 DATAIN CLK FF\H FF 20 67 11 FF 20 67 11 0 D VSPROM X\H i 0 3 2 3 2 3 2 3 0 3 2 3 2 3 2 1 0 g i t CCLK X a l DOUT ADDRESS X XXXX\H OUTEN 0002 0003 0000 0001 0002 0003 0000 X T(DONEPIN) 0001 X PROGRAM 0000 0 0 1u 2u 3u 4u 5u 6u 7u Time (Seconds) Figure 4: Simulation Waveforms 6 XAPP079 XAPP079 September, 1997 (Version 1.2)