X5163/323/643 X5163 78K-SERIES 1-888-INTERSIL uPD7824x 0FE00H 0FE20H 9000H - Datasheet Archive

 

Supervisors to NEC 78K Microcontrollers ® Application Note June 13, 2005 AN98.0 Author: Applications Staff Introduction The

 

Interfacing the Intersil X5163/323/643 X5163/323/643 CPU Supervisors to NEC 78K Microcontrollers ® Application Note June 13, 2005 AN98.0 Author: Applications Staff Introduction The Intersil CPU Supervisors have an on-chip programmable watchdog timer and nonvolatile EEPROM memory. These features, coupled with the 3-line Serial Peripheral Interface (SPI) and the 78K-series microcontroller from NEC, make for an effective combination of features and performance. This application note will explore some possibilities and will provide example schematics and software. Interface The 78K-Series microcontroller typically has two serial ports. One of these, a synchronous three-line interface, can be used with the SPI watchdog timer (SPI WDT). This interface requires only one additional line, a chip select. Figure 1 shows a possible configuration. As illustrated this connection requires no additional components. Sample code, provided in a later section, is written to support the hardware shown in Figure 1. Implementation While the interface and code implementation is not complex, there are some areas where care must be taken to achieve functional code. A write enable command (WREN) must precede each write operation, including a write to the status register. The WREN command begins with the CS line going LOW and completed with the CS line returning HIGH. Once writes have been enabled, they are active only during a byte, page, or status register write. This means a WREN command must precede each write operation. The write enable bit is also reset automatically upon power-up. It is possible to write a block of data in a single operation. However, each block is 32 bytes long and a block write cannot cross a block boundary. The block boundaries begin at addresses where bits A4 through A0 are "0". As previously described, a WREN command is required before a new block can be written. This block write mechanism is implemented in the sample firmware code. 1 78K-Series VCC X5163 X5163 RESET P60 SCK SI SO 7 1 RESET VCC CS 6 SCK 2 SO 5 SI WP VSS 8 3 4 FIGURE 1. INTERFACING THE INTERSIL X5163 X5163 CPU SUPERVISOR TO THE 78K-SERIES 78K-SERIES µC USING THE SYNCHRONOUS SERIAL PORT It is possible to write new values into the status register to change block protection and change the watchdog timer value. Since the status register is nonvolatile, a write to the register must follow the same restrictions as other nonvolatile writes. This means that a write to the status register will take a maximum of 10ms to complete, and cannot occur concurrently with data write operations. When using the watchdog timer, a RESET signal is sent out after a selectable period of time. If the microcontroller does not respond in this amount of time, it will be reset. By toggling the CS line, the watchdog RESET can be held-off. The sample firmware code does not include this watchdog timer RESET hold-off operation. The circuit of Figure 1 shows a pull-up resistor on the RESET line. This is required, since the SPI WDT has an open drain output. Typically, however, the microcontroller has a RESET circuit that allows a user initiated re-start. In this case, the resistor shown in the figure is not an additional component, but part of the reset mechanism. CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners. Application Note 98 Code Listings The listing for the interface firmware is included on following pages. The code consists of a test program that moves a block of data from ROM to the EEPROM, then moves the block from EEPROM to the 78K2 internal RAM. The EEPROM-specific routines takes less than 170 bytes of code. These routines are: Init_SIO-This routine will set up the synchronous serial port to communicate with the SPI WDT. Put_Byte-This routine sends a data byte to the EEPROM using the internal hardware shifter of the microcontroller. Write_Stat-This routine will write a value into the EEPROM status register. Block_Read-This routine will read a block of data from the EEPROM and will save the block in RAM. The EEPROM source address pointer and the destination address pointer, along with the block size in bytes, are pre-specified. Block_Write-This routine writes a block of data to the EEPROM. The data source address pointer and the EEPROM destination address pointer are pre-specified, as is the number of bytes in the block. This routine handles data blocks that do not begin on an EEPROM border and can handle blocks greater than 32 bytes. Read_Stat-This routine will return the current value in the EEPROM Status register. Conclusion Wait_EE-This routine will wait for a EEPROM write to complete. Few members of NEC's 78K-series microcontrollers come equipped with an on-board watchdog timer and only one family (the uPD7824x uPD7824x) has on-chip EEPROM. The introduction of the SPI WDT by Intersil removes these two limitations with a single 8-lead device. Since this combination requires no interface hardware and minimal code, it is the perfect combination for many industrial control applications. E2_Command_Fix-This routine will send one of the various commands to the EEPROM. Additional Intersil code can be found on the World Wide Web at http://www. intersil.com. Get_Byte-This routine gets a byte from the EEPROM using the internal hardware shifter of the microcontroller. Wait_COM-After writing a byte to the microcontroller internal hardware shift register, this routine will wait for a byte transmit to complete. 2 AN98.0 June 13, 2005 Application Note 98 $ TITLE ('X25163Interface') ; File Name: MPC $ PC(213) ;_ ; ; OPERATION: ; ; This program will access the Intersil Serial EEPROM ; with Serial Peripheral Interface (SPI) and watchdog timer ; ; This routine is set up for an EEPROM that uses the ; synchronous serial I/O port of the K-series devices. ; ; This program is written for the DDB. ;_ ; TESTPG: ;_ ; ; Define Equates ; WREN equ 06H ; Command: Write enable WRDI equ 04H ; Command: Write Disable RDSR equ 05H ; Command: Read Status Register WRSR equ 01H ; Command: Write Status Register READ equ 03H ; Command: Read EEPROM WRITE equ 02H ; Command: Write EEPROM ; WIP equ A.0 ; EEPROM Write in Progress CE_ equ P6.0 ; Chip enable line Msg1 equ 5 ; Start address of EEPROM block ; NUM_TRY equ 50 ; read WIP this long before giving up ; ; Define Stack area ; STKSEG DSEG AT 0FE00H 0FE00H DS 32 STACK: ; ; Define Variables ; VARIAB DSEG AT 0FE20H 0FE20H BYTE_COUNT: DS 1 MESSAGE: DS 40 ; Where data is to be moved. ; ; Used for a test program., ; ; Vector Table ; VRESET CSEG AT 9000H 9000H ; BR START ; CMAIN CSEG AT 9080H 9080H ;_ ; Main Routine ;_ ; ; Initialize System. ; START: di ; Disable interrupts mov MM, #00010111B 00010111B ; Ext ROM Fetch,no ext addr,1 wait 3 AN98.0 June 13, 2005 Application Note 98 mov mov movw RFM, #00000000B 00000000B PM6, #00000000B 00000000B SP, #STACK ; Disable refresh pulse out ; Select Mem bank 0, P64-67 P64-67=output ; Set stack pointer call !Init_SIO ; Initialize Serial I/O port Turn on Xmit & Recv ; ; ; mov PM0, #0 mov P0, #0H set1 CE_ ; Disable the EEPROM ;_ ; ; The following is a Test program that writes a block of ; data into the EEPROM from ROM, then reads it back into ; the 78K2 internal RAM area. ;_ ; TEST: movw HL, #MSG_ROM ; Location of message in ROM movw DE, #Msg1 ; Location of message 1 in EEPROM mov BYTE_COUNT, #35 ; Write 35 bytes to EEPROM call !Block_Write ; Write the block movw movw mov HL, #MESSAGE DE, #Msg1 BYTE_COUNT, #35 ; Location of message in RAM ; Location of message 1 in EEPROM ; Read 35 bytes from EEPROM call !Block_Read mov call X, #10H !Write_Stat ; Set WD Timer to 600 mSec ; Set WD Timer call !Fini_SIO ; Turn off Serial I/O port LOOP: NOP BR LOOP MSG_ROM: DB 'This is a test of the Serial EEPROM' ;= ; Following are the various routines to complete the ; above operation. ; ; Init_SIO Initialize the Serial I/O Port ; Fini_SIO Turn off the Serial I/O ; ; Wait_COM Wait for the communication to complete ; Wait_EE Wait for EEPROM Write to complete ; ; Put_Byte Sends one byte to the EEPROM ; Get_Byte Gets one Byte from the EEPROM ; ; E2_Command_Fix Sends one of 6 commands ; ; WREN (Write Enable) ; WRDI (Write Disable) ; RDSR (Read Status register) ; WRSR ( Write Status Register) 4 AN98.0 June 13, 2005 Application Note 98 ; READ (Read EEPROM) ; WRITE (Write EEPROM) ; ; Read_Stat Reads the EEPROM Status register ; Write_Stat Writes the EEPROM Status Register ; ; Block_Read Reads a block of data from the EEPROM ; Block_Write Writes a block of data to the EEPROM ; ;= ; ;_ ; Init_SIO ; ; This routine will initialize the Serial I/O port for ; Synchronous operation, using internal clocking at 750K bps. ; ; Routines Called: None ; Input: None ; Output: None ; Registers used: A ;_ ; Init_SIO: or or mov set1 set1 MK0H, #10000000B 10000000B ; Disable serial interrupt PMC3, #0CH ; Use SO and SCK CSIM, #2 ; Set Serial clock to fCLK/8 CTXE ; Turn on transmit mode CRXE ; Turn on receive mode End_Ser_Setup: clr1 clr1 ret WUP CSIIF ; Interrupt gen after each xfer ; Clear Sync Serial Intr Flag ; ;_ ; Fini_SIO ; ; This routine will initialize the Serial I/O port for ; Synchronous operation, using internal clocking at 750K bps. ; ; Routines Called: None ; Input: None ; Output: None ; Registers used: A ;_ ; Fini_SIO: clr1 CTXE ; Turn off transmit mode clr1 CRXE ; Turn off receive mode br End_Ser_Setup ;_ ; Wait_COM ; ; This routine will wait for an interrupt to signal a xmit or ; recv complete ; ; Routines Called: None 5 AN98.0 June 13, 2005 Application Note 98 ; Input: None ; Output: None ; Registers used: None ;_ ; Wait_COM: btclr br CSIIF, $Return Wait_COM ; Wait for completion of Xmit/Rcv return: ret ;_ ; Wait_EE ; ; This routine will wait for the EEPROM write sequence to ; complete. ; ; Routines Called: None ; Input: None ; Output: None ; Registers used: A, B ;_ ; Wait_EE: mov B, #NUM_TRY ; Maximum number of samples Wait_EE_LP: call !Read_Stat ; Read the Status Register bf dbnz WIP, $Wait_done ; If Write complete, done. B, $Wait_EE_LP ; If not done, give it more time ; but not too much. Wait_done: ret ; else, return ;_ ; Put_Byte ; ; This routine will move one byte of data from memory pointed ; to by the HL register to the EEPROM. ; ; Routines Called: None ; Input: HL = Address of data to send ; Output: HL = Next address of data to send ; Registers used: A, HL, B ;_ ; Put_Byte: mov SIO, A ; Put byte to serial port br Wait_COM ; Wait for byte to be sent ;_ ; Get_Byte ; ; This routine will move one byte of data from the EEPROM ; to memory pointed to by the HL register. ; 6 AN98.0 June 13, 2005 Application Note 98 ; Routines Called: None ; Input: None ; Output: A = Returned byte ; Registers used: AX, B ;_ ; Get_Byte: mov SIO, #0 ; Send dummy byte to activate recv call !Wait_COM ; Wait for byte to be recv'd mov A, SIO ; Get byte ret ;_ ; E2_Command_Fix ; ; This routine will send a control signal to the EEPROM ; ; 06H ; Command: Write enable ; 04H ; Command: Write Disable ; 05H ; Command: Read Status Register ; 01H ; Command: Write Status Register ; 03H ; Command: Read EEPROM ; 02H ; Command: Write EEPROM ; ; Routines Called: None ; Input: A = Command; DE = Address in EEPROM ; Output: None ; Registers used: None ;_ ; E2_Command_Fix: clr1 br CE_ Put_byte ; Enable EEPROM ; Write a Command to serial port ;_ ; Read_Stat ; ; This routine will read a value from the status register ; ; Routines Called: None ; Input: None ; Output: A = Status Reg value ; Registers used: A ;_ ; Read_Stat: mov call A, #RDSR ; Read Status Register !E2_Command_Fix call set1 !Get_byte CE_ ; ; Disable the chip ret ;_ ; Write_Stat ; ; This routine will write a value to the status register ; 7 AN98.0 June 13, 2005 Application Note 98 ; Routines Called: None ; Input: X = Status register data ; Output: None ; Registers used: A, X ;_ ; Write_Stat: mov call set1 A, #WREN ; Prepare to enable writing !E2_Command_Fix ; Send a WREN command CE_ ; Disable EEPROM mov call A, #WRSR ; Write Status Register !E2_Command_Fix mov mov call set1 A, X P0, #1 !Put_byte CE_ ; Write the status ; ; Disable the chip ret ;_ ; Block_Read ; ; This routine will read a block of data from the EEPROM ; ; Routines Called: Get_Data_Byte ; Input: HL = Save address pointer, ; BYTE_COUNT = number of bytes ; Output: HL = Address of next save location ; Registers used: A, HL, BYTE_COUNT ;_ ; Block_Read: mov call A, #READ ; Send reset command !E2_Command_Fix mov call mov call A, D !Put_Byte A, E !Put_Byte ; ; ; ; ; Send Send Send Send DE upper address byte EEPROM Start Address lower address byte EEPROM Start Address = EEPROM Address Blk_Rd_Loop: call mov dbnz set1 !Get_Byte [HL+], A BYTE_COUNT, $Blk_Rd_Loop CE_ ; Disable EEPROM ret ;_ ; Block_Write ; ; This routine will write a block of data to the EEPROM ; Since the EEPROM has a 32 byte page, a limit of 32 bytes of ; data can be written before the issuing of a non-volatile write ; cycle. Also, in order to avoid data wrapping on a page, care ; must be taken when writing over page boundaries. ; ; Routines Called: E2_Command_Fix, Put_Byte, Wait_EE 8 AN98.0 June 13, 2005 Application Note 98 ; Input: DE = Internal Address of EEPROM ; (where data is to be written) ; HL = Address of data to be written ; BYTE_COUNT = Number of bytes to write ; Output: None ; Registers used: AX, DE, HL, BYTE_COUNT ;_ ; Block_Write: mov call set1 A, #WREN !E2_Command_Fix CE_ ; Prepare to enable writing ; Send a WREN command ; Disable EEPROM Write_OP: mov call mov call mov call A, #WRITE !E2_Command_Fix A, D !Put_Byte A, E !Put_Byte ; Start writing ; Send upper address byte ; Send EEPROM Start Address ; Send lower address byte ; Send EEPROM Start Address ; DE = EEPROM Address Blk_Loop: mov call a, [HL+] !Put_Byte ; Get next byte ; Send it out ; HL points to next byte ; Count byte, if last one, go write ; else check for 32 byte boundary dbnz BYTE_COUNT, $Next_bit br NV_Write Next_bit: incw mov and cmp bne DE A, E A, #31 A, #0 $Blk_Loop ; Increment EEPROM address pointer ; Check for 32 byte block boundary ; Is this a new block start? ; No, keep sending NV_Write: set1 call cmp bne CE_ !Wait_EE BYTE_COUNT, 0 Block_Write ; ; ; ; Disable EEPROM Wait for any writes to complete If not all bytes are sent keep on. mov call set1 A, #WRDI !E2_Command_Fix CE_ ; Disable writes ; Disable EEPROM ; ret END Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that the Application Note or Technical Brief is current before proceeding. For information regarding Intersil Corporation and its products, see www.intersil.com 9 AN98.0 June 13, 2005