X5043 X25020 X25020-2 X24C16 - Datasheet Archive

 

Alternative: X5043 X25020 2K 256 x 8 Bit SPI Serial EEPROM with Block LockTM Protection DESCRIPTION · 2MHz clock rate

 

Recommend System Management Alternative: X5043 X5043 X25020 X25020 2K 256 x 8 Bit SPI Serial EEPROM with Block LockTM Protection DESCRIPTION · 2MHz clock rate · SPI modes (0,0 & 1,1) · 256 X 8 bits -16-byte page mode · Low power CMOS -10µA standby current -3mA active write current · 2.7V To 5.5V power supply · Block lock protection -Protect 1/4, 1/2 or all of EEPROM array · Built-in inadvertent write protection -Power-up/power-down protection circuitry -Write latch -Write protect pin · Self-timed write cycle -5ms write cycle time (typical) · High reliability -Endurance: 1,000,000 cycles per byte -Data retention: 100 years -ESD protection: 2000V on all pins · 8-lead SOIC Package The X25020 X25020 is a CMOS 2048-bit serial EEPROM, internally organized as 256 x 8. The X25020 X25020 features a serial interface and software protocol, allowing operation on a simple three-wire bus. The bus signals are a clock input (SCK) plus separate data in (SI) and data out (SO) lines. Access to the device is controlled through a chip select (CS) input, allowing any number of devices to share the same bus. du c t FEATURES ro P e The X25020 X25020 utilizes Xicor's proprietary Direct WriteTM cell, providing a minimum endurance of 1,000,000 cycles per byte and a minimum data retention of 100 years. et BLOCK DIAGRAM Write Protect Logic O CS HOLD WP X Decode Logic 256 Byte Array 4 bs ol Status Register SO SI SCK The X25020 X25020 also features two additional inputs that provide the end user with added flexibility. By asserting the HOLD input, the X25020 X25020 will ignore transitions on its inputs, thus allowing the host to service higher priority interrupts. The WP input can be used as a hardwire input to the X25020 X25020 (disabling all write attempts), thus providing a mechanism for limiting end user capability of altering the memory. Command Decode And Control Logic 4 X 128 4 4 X 128 16 Write Control and Timing Logic 16 X 128 16 8 Y Decode Data Register Direct WriteTM and Block LockTM Protection is a trademark of Xicor, Inc. REV 1.1.1 12/8/00 www.xicor.com Characteristics subject to change without notice. 1 of 13 X25020 X25020 PIN CONFIGURATION Serial Output (SO) SO is a push/pull serial data output pin. During a read cycle, data is shifted out on this pin. Data is clocked out by the falling edge of the serial clock. SOIC SO Serial Input (SI) SI is the serial data input pin. All opcodes, byte addresses, and data to be written to the memory are input on this pin. Data is latched by the rising edge of the serial clock. 2 WP VSS PIN NAMES Serial Clock (SCK) Chip Select (CS) et e When CS is HIGH, the X25020 X25020 is deselected and the SO pin is at high impedance; unless an internal write operation is underway, the X25020 X25020 will be in the standby power mode. CS LOW enables the X25020 X25020, placing it in the active power mode. It should be noted that after power-up, a HIGH to LOW transition on CS is required prior to the start of any operation. bs ol Write Protect (WP) When WP is LOW, nonvolatile writes to the X25020 X25020 are disabled, but the part otherwise functions normally. When WP is held HIGH, all functions, including nonvolatile writes operate normally. WP going LOW while CS is still LOW will interrupt a write to the X25020 X25020. If the internal write cycle has already been initiated, WP going LOW will have no affect on a write. O Hold (HOLD) HOLD is used in conjunction with the CS pin to select the device. Once the part is selected and a serial sequence is underway, HOLD may be used to pause the serial communication with the controller without resetting the serial sequence. To pause, HOLD must be brought LOW while SCK is LOW. To resume communication, HOLD is brought HIGH, again while SCK is LOW. If the pause feature is not used, HOLD should be held HIGH at all times. REV 1.1.1 12/8/00 7 X25020 X25020 VCC HOLD 3 6 SCK 4 5 SI Description CS Chip Select Input SO Serial Output SI Serial Input SCK Serial Clock Input ro Symbol P The Serial Clock controls the serial bus timing for data input and output. Opcodes, addresses, or data present on the SI pin are latched on the rising edge of the clock input, while data on the SO pin change after the falling edge of the clock input. 8 1 du c CS t PIN DESCRIPTIONS WP Write Protect Input VSS Ground VCC Supply Voltage HOLD Hold Input PRINCIPLES OF OPERATION The X25020 X25020 is a 256 x 8 EEPROM designed to interface directly with the synchronous serial peripheral interface (SPI) of many popular microcontroller families. The X25020 X25020 contains an 8-bit instruction register. It is accessed via the SI input, with data being clocked in on the rising SCK. CS must be LOW and the HOLD and WP inputs must be HIGH during the entire operation. Table 1 contains a list of the instructions and their opcodes. All instructions, addresses and data are transferred MSB first. Data input is sampled on the first rising edge of SCK after CS goes LOW. SCK is static, allowing the user to stop the clock and then resume operations. If the clock line is shared with other peripheral devices on the SPI bus, the user can assert the HOLD input to place the X25020 X25020 into a "PAUSE" condition. After releasing HOLD, the X25020 X25020 will resume operation from the point when HOLD was first asserted. www.xicor.com Characteristics subject to change without notice. 2 of 13 X25020 X25020 7 6 5 4 3 2 1 0 0 0 0 0 BP1 BP0 WEL WIP t The Write Enable Latch (WEL) bit indicates the status of the "write enable" latch. When set to a "1", the latch is set, when set to a "0", the latch is reset. du c Status Register The RDSR instruction provides access to the status register. The status register may be read at any time, even during a write cycle. The status register is formatted as follows: The Write-In-Process (WIP) bit indicates whether the X25020 X25020 is busy with a write operation. When set to a "1", a write is in progress, when set to a "0", no write is in progress. During a write, all other bits are set to "1". The Block Protect (BP0 and BP1) bits are nonvolatile and allow the user to select one of four levels of protection. The X25020 X25020 is divided into four 512-bit segments. One, two, or all four of the segments may be protected. That is, the user may read the segments but will be unable to alter (write) data within the selected segments. The partitioning is controlled as illustrated below. ro Write Enable Latch The X25020 X25020 contains a "write enable" latch. This latch must be SET before a write operation will be completed internally. The WREN instruction will set the latch and the WRDI instruction will reset the latch. This latch is automatically reset upon a power-up condition and after the completion of a byte, page, or status register write cycle. Status Register Bits BP0 Array Addresses Protected 0 0 None 0 1 $C0­$FF 0 $80­$FF 1 1 $00­$FF e P BP1 1 BP0 and BP1 are set by the WRSR instruction. WEL and WIP are read-only and automatically set by other operations. et Table 1. Instruction Set Instruction Name Instruction Format* Operation 0000 0110 Set the write enable latch (enable write operations) WRDI 0000 0100 Reset the write enable latch (disable write operations) RDSR 0000 0101 Read status register 0000 0001 Write status register 0000 0011 Read data from memory array beginning at selected address 0000 0010 Write data to memory array beginning at selected address (1 to 32 bytes) WRSR READ bs WRITE ol WREN Notes: *Instructions are shown MSB in leftmost position. Instructions are transferred MSB first. O Clock and Data Timing Data input on the SI line is latched on the rising edge of SCK. Data is output on the SO line by the falling edge of SCK. Read Sequence When reading from the EEPROM memory array, CS is first pulled LOW to select the device. The 8-bit READ instruction is transmitted to the X25020 X25020, followed by the 8-bit address. After the read opcode and address are sent, the data stored in the memory at the selected REV 1.1.1 12/8/00 address is shifted out on the SO line. The data stored in memory at the next address can be read sequentially by continuing to provide clock pulses. The address is automatically incremented to the next higher address after each byte of data is shifted out. When the highest address is reached ($FF), the address counter rolls over to address $00, allowing the read cycle to be continued indefinitely. The read operation is terminated by taking CS HIGH. Refer to the read EEPROM array operation sequence illustrated in Figure 1. www.xicor.com Characteristics subject to change without notice. 3 of 13 X25020 X25020 t Hold Operation The HOLD input should be HIGH (at VIH) under normal operation. If a data transfer is to be interrupted, HOLD can be pulled LOW to suspend the transfer until it can be resumed. The only restriction is the SCK input must be LOW when HOLD is first pulled LOW, and SCK must also be LOW when HOLD is released. The HOLD input may be tied HIGH either directly to VCC or tied to VCC through a resistor. Operational Notes The X25020 X25020 powers-up in the following state: et e P To write data to the EEPROM memory array, the user issues the WRITE instruction, followed by the address and then the data to be written. This is minimally a thirty-two clock operation. CS must go LOW and remain LOW for the duration of the operation. The host may continue to write up to 16 bytes of data to the X25020 X25020. The only restriction is that the 16 bytes must reside on the same page. If the address counter reaches the end of the page and the clock continues, the counter will "roll over" to the first address of the page and overwrite any data that may have been written. While the write is in progress following a status register or EEPROM write sequence, the status register may be read to check the WIP bit. During this time the WIP bit will be HIGH. du c Write Sequence Prior to any attempt to write data into the X25020 X25020, the "write enable" latch must first be set by issuing the WREN instruction (See Figure 3). CS is first taken LOW, then the WREN instruction is clocked into the X25020 X25020. After all eight bits of the instruction are transmitted, CS must then be taken HIGH. If the user continues the write operation without taking CS HIGH after issuing the WREN instruction, the write operation will be ignored. To write to the status register, the WRSR instruction is followed by the data to be written. Data bits 0, 1, 4, 5, 6 and 7 must be "0". Figure 6 illustrates this sequence. ro To read the status register CS line is first pulled LOW to select the device, followed by the 8-bit RDSR instruction. After the read status register opcode is sent, the contents of the status register are shifted out on the SO line. Figure 2 illustrates the read status register sequence. ­ A HIGH to LOW transition on CS is required to enter an active state and receive an instruction. ­ SO pin is high impedance. ­ The "write enable" latch is reset. Data Protection The following circuitry has been included to prevent inadvertent writes: ­ The "write enable" latch is reset upon power-up. ­ A WREN instruction must be issued to set the "write enable" latch. ­ CS must come HIGH at the proper clock count in order to start a write cycle. O bs ol For the write operation (byte or page write) to be completed, CS can only be brought HIGH after bit 0 of data byte N is clocked in. If it is brought HIGH at any other time, the write operation will not be completed. Refer to Figures 4 and 5 for a detailed illustration of the write sequences and time frames in which CS going HIGH are valid. ­ The device is in the low power standby state. REV 1.1.1 12/8/00 www.xicor.com Characteristics subject to change without notice. 4 of 13 X25020 X25020 Figure 1. Read EEPROM Array Operation Sequence CS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 t 0 Instruction du c SCK Byte Address SI 7 6 5 4 3 2 1 0 Data Out High Impedance 7 6 5 4 3 2 1 0 ro SO MSB P Figure 2. Read Status Register Operation Sequence CS 0 1 2 3 5 6 7 8 9 10 11 12 13 14 e SCK 4 Data Out High Impedance ol SI et Instruction SO 7 6 5 4 3 2 1 0 MSB O bs Figure 3. Write Enable Latch Sequence CS 0 1 2 3 4 5 6 7 SCK SI SO REV 1.1.1 12/8/00 High Impedance www.xicor.com Characteristics subject to change without notice. 5 of 13 X25020 X25020 Figure 4. Byte Write Operation Sequence CS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 t 0 Instruction Byte Address SI 7 6 5 7 8 4 9 3 Data Byte 2 1 0 High Impedance Figure 5. Page Write Operation Sequence 2 3 4 5 6 7 6 et SI 4 3 2 1 0 Byte Address 5 4 3 Data Byte 1 2 1 0 7 6 5 4 3 2 1 0 ol CS 5 10 11 12 13 14 15 16 17 18 19 20 21 22 23 e SCK Instruction 6 P CS 1 7 ro SO 0 du c SCK 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 bs SCK Data Byte 2 7 6 5 4 3 2 1 0 7 6 5 4 3 Data Byte 4 2 1 0 7 6 5 4 3 2 1 0 O SI Data Byte 3 REV 1.1.1 12/8/00 www.xicor.com Characteristics subject to change without notice. 6 of 13 X25020 X25020 Figure 6. Write Status Register Operation Sequence 0 1 2 3 4 5 6 7 8 9 7 6 10 11 12 13 14 15 Instruction Data Byte SI High Impedance 5 4 3 2 1 0 O bs ol et e P ro SO du c SCK t CS REV 1.1.1 12/8/00 www.xicor.com Characteristics subject to change without notice. 7 of 13 X25020 X25020 COMMENT Temperature under bias .­65°C to +135°C Storage temperature .­65°C to +150°C Voltage on any pin with respect to VSS . ­1V to +7V D.C. output current . 5mA Lead temperature (soldering, 10 seconds).300°C Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. du c t ABSOLUTE MAXIMUM RATINGS RECOMMENDED OPERATING CONDITIONS Min. Max. Supply Voltage Limits Commercial 0°C +70°C X25020-2 X25020-2.7 2.7 to 5.5V Industrial ­40°C +85°C ro Temperature P D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.) Limits Symbol Parameter Min. ILO 10 µA CS = VCC, VIN = VSS or VCC ­ 0.3V 10 µA VIN = VSS to VCC 10 µA VOUT = VSS to VCC VCC x 0.3 V VCC + 0.5 V 0.4 V IOL = 2mA V IOH = ­1mA Output leakage current e Input leakage current SCK = VCC x 0.1/VCC x 0.9 @ 1MHz, SO = Open et ILI mA VCC x 0.7 VCC supply current (standby) 3 VCC supply current (active) ISB Unit ­0.5 ICC Max. (1) Input LOW voltage (1) VIH Input HIGH voltage VOL Output LOW voltage VOH Output HIGH voltage ol VIL VCC ­ 0.8 Test Conditions bs POWER-UP TIMING Symbol (2) (2) tPUR Max. Unit Power-up to read operation 1 ms Power-up to write operation 5 ms Max. Unit Conditions Output capacitance (SO) 8 pF VOUT = 0V Input capacitance (SCK, SI, CS, WP, HOLD) 6 pF VIN = 0V O tPUW Parameter Min. CAPACITANCE TA = +25°C, F = 1MHZ, VCC = 5V. Symbol (2) COUT (2) CIN Test Notes: (1) VIL min. and VIH max. are for reference only and are not tested. (2) This parameter is periodically sampled and not 100% tested. REV 1.1.1 12/8/00 www.xicor.com Characteristics subject to change without notice. 8 of 13 X25020 X25020 EQUIVALENT A.C. LOAD CIRCUIT AT 5V VCC A.C. TEST CONDITIONS Input pulse levels VCC x 0.5 t 10ns Input and output timing level 2.16K VCC x 0.1 to VCC x 0.9 Input rise and fall times 5V 3.07K du c Output 100pF ro A.C. CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified) Data Input Timing Symbol Parameter fSCK Min. CS lead time CS lag time tWH Clock HIGH time tWL Clock LOW time tSU Data setup time tH Data hold time tRI Data in rise time tFI Data in Fall time 2 MHz 1000 ns 500 ns 500 ns 400 e tLAG P Cycle time et tCYC tLEAD Unit 0 Clock frequency Max. ns 400 ns 100 ns 100 ns 2 µs 2 µs HOLD setup time 200 ns HOLD hold time 200 ns tCS CS deselect time 500 ns (4) Write cycle time bs tWC ol tHD tCD 10 ms Max. Unit Data Output Timing Symbol Parameter Min. Clock frequency 1 MHz tDIS Output disable time 500 ns Output valid from clock LOW 360 ns O fSCK tV tHO (3) 0 Output hold time 0 ns tRO Output rise time 300 ns tFO(3) Output fall time 300 ns tLZ HOLD HIGH to output in low Z 100 ns tHZ HOLD LOW to output in high Z 100 ns Notes: (3) Parameter is tested on a sample basis only. (4) tWC is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile write cycle. REV 1.1.1 12/8/00 www.xicor.com Characteristics subject to change without notice. 9 of 13 X25020 X25020 Serial Output Timing CS tCYC t tV SO du c SCK tHO MSB Out tWL MSB­1 Out tDIS LSB Out ADDR LSB IN ro SI tLAG tWH tCS P Serial Input Timing CS tLEAD e tLAG et SCK tSU MSB IN tFI LSB IN High Impedance O bs SO tRI ol SI tH REV 1.1.1 12/8/00 www.xicor.com Characteristics subject to change without notice. 10 of 13 X25020 X25020 Hold Timing CS tHD tCD tCD t tHD du c SCK tHZ tLZ SO ro SI P HOLD INPUTS OUTPUTS Must be steady Will be steady May change from LOW to HIGH Will change from LOW to HIGH Will change from HIGH to LOW ol May change from HIGH to LOW e WAVEFORM et SYMBOL TABLE Changing: State Not Known Center Line is High Impedance O bs Don't Care: Changes Allowed N/A REV 1.1.1 12/8/00 www.xicor.com Characteristics subject to change without notice. 11 of 13 X25020 X25020 PACKAGING INFORMATION du c t 8-Lead Plastic, SOIC, Package Code S8 0.150 (3.80) 0.228 (5.80) 0.158 (4.00) 0.244 (6.20) Pin 1 Index 0.014 (0.35) 0.019 (0.49) P 0.188 (4.78) 0.197 (5.00) ro Pin 1 e (4X) 7° et 0.053 (1.35) 0.069 (1.75) 0.004 (0.19) 0.010 (0.25) ol 0.050 (1.27) 0.010 (0.25) X 45° 0.020 (0.50) O bs 0° - 8° 0.050"Typical 0.050" Typical 0.0075 (0.19) 0.010 (0.25) 0.250" 0.016 (0.410) 0.037 (0.937) 0.030" Typical 8 Places FOOTPRINT NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) REV 1.1.1 12/8/00 www.xicor.com Characteristics subject to change without notice. 12 of 13 X25020 X25020 Ordering Information P T -V VCC Limits 2.7V = 2.7V to 5.5V du c Device t X25020 X25020 Temperature Range Blank = Commercial = 0°C to +70°C I = Industrial = ­40°C to +85°C ro Package S = 8-Lead SOIC Part Mark Convention X Blank = 8-Lead SOIC P X25020 X25020 X LIMITED WARRANTY ol et e F = 2.7V to 5.5V, 0°C to +70°C G = 2.7V to 5.5V, ­40°C to +85°C ©Xicor, Inc. 2001 Patents Pending bs Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied. COPYRIGHTS AND TRADEMARKS O Xicor, Inc., the Xicor logo, E2POT, XDCP, XBGA, AUTOSTORE, Direct Write cell, Concurrent Read-Write, PASS, MPS, PushPOT, Block Lock, IdentiPROM, E2KEY, X24C16 X24C16, SecureFlash, and SerialFlash are all trademarks or registered trademarks of Xicor, Inc. All other brand and product names mentioned herein are used for identification purposes only, and are trademarks or registered trademarks of their respective holders. U.S. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691; 5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending. LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence. Xicor's products are not authorized for use in critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. REV 1.1.1 12/8/00 www.xicor.com Characteristics subject to change without notice. 13 of 13