WT5082 296KB 768KO 6502STACK PTS01 PTS00 PTS11 PTS10 EEP16 EEP15 EEP14 EEP13 - Datasheet Archive

 

9 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel (852) 2123 3289 Fax (852) 2123 3393 E-mail: sales@jesstech.com HomePage:

 

Suites 2202-7, 22/F, Tower 6, The Gateway, 9 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel (852) 2123 3289 Fax (852) 2123 3393 E-mail: sales@jesstech.com HomePage: http://www.jesstech.com WT5082 WT5082 V0.97 DESCRIPTION The WT5082 WT5082 is a high-performance, low-cost, CMOS 8-bit single-chip micro-controller with POCSAG decoder12KB SRAM 296KB 296KB ROM and 56x32 / 56x33 dot-matrix LCD driver embedded, which is suitable for information paging applications, especially when large number of LCD dots and large ROM and SRAM space are needed, such as Chinese character display pagers. This chip has 8-bit CPU, RAM, ROM, I/Os, two timers/counters, interrupt controller, LCD driver and watchdog timer. To be suitable for portable battery-powered applications, a power saving function is included. FEATURES u POCSAG pager code decoder ² Single crystal support 512, 1200 and 2400 baud rates ( 76.8kHz crystal ) ² Support 6 RICs addresses and 6 independent frame numbers ² Support partial address match facility for address F ( up to 260k addresses are provided ) ² 3 RF control lines ( PLL, quick charge and enable ) ² Build in data filter ( 16-times over-sampling ) and data bit clock recovery ² Interrupt 6502 CPU when there are any status change ² DMA or interrupt mode to send the received message data to CPU u 8-bit single chip Microcontroller with 56x32 / 56x33 LCD driver u 12Kbytes SRAM ( ~ 2K bits for LCD display SRAM ) , 256 Kbytes character pattern ROM , 32Kbytes program ROM and 8Kbytes ROM for test program u Wide voltage operating range from 2.5 V to 3.6 V u Built-in Ring Oscillator with maximum frequency up to 2.0 MHz u I/O port (21 pins) Input port 8 pins Input/output port 13 pins u Watchdog Timer u Operating current 0.5mA / 1MHz @ 3V ; providing standby mode and key wake-up mode ² Ring OSC OFF and 76.8KHz X'tal OSC ON: current consumption < 60 uA @ 3V 1 Suites 2202-7, 22/F, Tower 6, The Gateway, 9 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel (852) 2123 3289 Fax (852) 2123 3393 E-mail: sales@jesstech.com HomePage: http://www.jesstech.com WT5082 WT5082 V0.97 u u u u u u u u u ² Both 1Mhz OSC and 76.8KHz X'tal OSC are OFF: current consumption < 5 uA @ 3V Dual timer / counters 7-bit EPI ( external port interrupt ) for key wake-up interrupt l-bit EPI ( external port interrupt to 6502 NMI ) for battery remove detect SIO for flex decoder ( 32bit ) UART( 10 bits ) One PWM signal function 2.2V threshold automatic power on reset 2.0V low power reset Package: Chip form or 128-pin LQFP ( 14mm x 14mm x 1.4mm ) PACKAGE OUTLINE 2 Suites 2202-7, 22/F, Tower 6, The Gateway, 9 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel (852) 2123 3289 Fax (852) 2123 3393 E-mail: sales@jesstech.com HomePage: http://www.jesstech.com WT5082 WT5082 V0.97 BLOCK DIAGRAM 3 Suites 2202-7, 22/F, Tower 6, The Gateway, 9 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel (852) 2123 3289 Fax (852) 2123 3393 E-mail: sales@jesstech.com HomePage: http://www.jesstech.com WT5082 WT5082 V0.97 PIN FUNCTION ( 128-pin LQFP ) 4 Suites 2202-7, 22/F, Tower 6, The Gateway, 9 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel (852) 2123 3289 Fax (852) 2123 3393 E-mail: sales@jesstech.com HomePage: http://www.jesstech.com SEG 32 ~ SEG 55 COM 31 ~ COM 16 COM 32 BIAS 1 ~ BIAS 4 V LCD 50 ~ 73 74 ~ 89 91 ~ 94 P Output Output Output Output Input Cb Ca P14 _ EPI4 P15 _ EPI5 P20 _ LMP P21 _ SS 100 101 P22 102 I/O P23 _ ECS P24 _ ECK P25 _ EDI P26 _ EDO P27 _ RE2 103 104 105 106 107 I/O I/O I/O I/O I/O P06 _ RDY 108 I/O P01 _ RE1 109 I/O P00 _ RE 110 Output P04 _ RFDI P07 111 112 Output Input P10 _ EPI0 ~ 113 I/O P13 _ EPI3 RESETB GND XIN XOUT VDD ROSC P02 _ Ptimer0 P03 _ Ptimer1 114 - 117 Input Input P Input Output P Input I/O I/O 768KO 768KO Output TEST COM0 Input Output V PP Output Output Output Input Input I/O WT5082 WT5082 Power Source LCD segment output LCD common output LCD common output ( for ICON ) LCD bias voltage output LCD voltage supply V RO*2 LCD pumping capacitor LCD pumping capacitor EPI4 , Battery low detect EPI5 , Battery low detect General I/O or Lamp output General I/O , SS output pin for Serial I/O or UART serial output General I/O or PLL _ LE General I/O for EEPROM CS General I/O , for EEPROM CK & PLL CK General I/O for EEPROM DI & PLL DATA General I/O for EEPROM DO RF control signal 2 output ( RF enable ) or MISO input pin for Serial I/O General I/O or RDY input pin for Serial I/O ; EPI6 or UART Serial Input RF control signal 2 output ( RF enable ) or MISO input pin for Serial I/O RF control signal output or SCK output pin for SIO RF signal data input General I/O port , Input port for EPI7 or PWM signal output 4-bit input port for External interrupt and general input System reset signal input ; low active Ground Crystal input Crystal output Power source Resistor for ring oscillator General I/O port or output from ptimer0 General I/O port or output from ptimer1 76.8KHz clock output for FLEX decoder or PWM Enable control signal Test pin. High active LCD common output V0.97 APPLICATION DIAGRAM 5 Suites 2202-7, 22/F, Tower 6, The Gateway, 9 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel (852) 2123 3289 Fax (852) 2123 3393 E-mail: sales@jesstech.com HomePage: http://www.jesstech.com WT5082 WT5082 V0.97 6 Suites 2202-7, 22/F, Tower 6, The Gateway, 9 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel (852) 2123 3289 Fax (852) 2123 3393 E-mail: sales@jesstech.com HomePage: http://www.jesstech.com WT5082 WT5082 SECTION 1. MEMORY CONFIGRATION ( MEMORY MAP & INTERNAL MEMORY CONFIGRUATION ) CPU MEMORY ADDRESS FUNCTION ADDRESS SPACE ( bytes ) $0000 - $004F PORT / REGISTERS 80 $0050 - $00FF INTERNAL SRAM 176 $0100 - $01FF 6502STACK 6502STACK 256 $0200 - $2EFF SRAM 11K $2F19 - $3F18 Reserved 3K $3F19 - $3FF8 LCD Display SRAM Buffer 224 $3FF9 - $3FFF LCD Icon SRAM Buffer $4000 - $5FFF Font ROM Window1 8K $6000 - $7FFF Font ROM Window2 8K $8000 - $FFF1 PROGRAM ROM $FFFA - $FFFF INTERRUPT ECTOR 7 ~ 32K 6 Vector address Vector type $FFFA - $FFFB NMI vector $FFFC - $FFFD Reset vector $FFFE - $FFFF IRQ vector V.0.97 7 Suites 2202-7, 22/F, Tower 6, The Gateway, 9 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel (852) 2123 3289 Fax (852) 2123 3393 E-mail: sales@jesstech.com HomePage: http://www.jesstech.com WT5082 WT5082 ADDR 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH NAME Port P0 DIR P0DIR Port P0 CFG P0CFG Port P0 Data P0DAT Port P1 CFG P1CFG Port P1 Data P1DAT Port P2 Direction P2DIR Port P2 configuration P2CFG Port P2 Data P2DAT Whtchdog Timer Control WDTCTL Port Timer0 Control PT0CTL Port Timer0 Preload Data PTIME0 Port Timer0 Count value TIMER0 Port Timer1Control PT1CTL Port Timer1 Preload Data PTIME1 Port Timer1 Count value TIMER1 Cpu Halt register HALT Bit number Read Write R/W P07D P06D - - P03D P02D R/W P07C P06C - P04C P03C R/W P07 P06 - P04 R/W - - P15C R - - R/W P27D R/W P02C P01C P00C P03 P02 - - P14C P13C P12C P11C P10C P15 P14 P13 P12 P11 P10 P26D P25D P24D P23D P22D P21D P20D P27C P26C P25C P24C P23C P22C P21C P20C R/W - P26 P25 P24 P23 P22 P21 P20 R/W WEN - - - - - WCK1 WCK0 R/W EPT0 - PT0S OPT0 - PTS01 PTS01 PTS00 PTS00 W PT07 PT06 PT05 PT04 PT03 PT02 PT01 PT00 R T07 T06 T05 T04 T03 T02 T01 T00 R/W EPT1 - PT1S OPT1 - - PTS11 PTS11 PTS10 PTS10 W PT17 PT16 PT15 PT14 PT13 PT12 PT11 PT10 R T17 T16 T15 T14 T13 T12 T11 T10 W × × × × × × × × 8 Suites 2202-7, 22/F, Tower 6, The Gateway, 9 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel (852) 2123 3289 Fax (852) 2123 3393 E-mail: sales@jesstech.com HomePage: http://www.jesstech.com WT5082 WT5082 V.0.97 ADDR 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH NAME Time Base Timer Control BTCTL Time Base Timer Preload data BTIME Time Base Counter Value TIMERB RTC timer control RTCCTL RTC Hour register Hour RTC Minute register Minute RTC Minute register Second IRQ Interrupt Mask IRQMK IRQ Interrupt Status IRQSR EPI Interrupt Mask EPIMK EPI Interrupt Status EPISR Inverse EPI signal IEP1 P_decoder Interrupt Mask PDIMK P_decoder Interrupt Status PDISR Expand ROM Window0 Address ROMWinADR0 Expand ROM Window1 Address ROMWinADR1 Bit number Read Write R/W EBT - - - - - BTS1 BTS0 W BT7 BT6 BT5 BT4 BT3 BT2 BT1 BT0 R TB7 TB6 TB5 TB4 TB3 TB2 TB1 TB0 R/W - - RT11 RT10 - - RT01 RT00 R/W SET - H4 H3 H2 H1 H0 R/W - - M5 M4 M3 M2 M1 M0 R/W - - S5 S4 S3 S2 S1 S0 R/W - MRTC MSIO MRT1 MRT0 MBT MPT1 MPT0 R FEP1 FRTC FSIO FRT1 FRT0 FBT FPT1 FPT0 EEP16 EEP16 EEP15 EEP15 EEP14 EEP14 EEP13 EEP13 EEP12 EEP12 EEP11 EEP11 EEP10 EEP10 R / W EEP17 EEP17 R EP17 EP16 EP15 EP14 EP13 EP12 EP11 EP10 R/W IEP17 IEP17 IEP16 IEP16 IEP15 IEP15 IEP14 IEP14 IEP13 IEP13 IEP12 IEP12 IEP11 IEP11 IEP10 IEP10 R / W EPD17 EPD17 EPD16 EPD16 EPD15 EPD15 EPD14 EPD14 EPD13 EPD13 EPD12 EPD12 EPD11 EPD11 EPD10 EPD10 R PD17 PD16 PD15 PD14 PD13 PD12 PD11 PD10 R/W - - - W0A4 W0A3 W0A2 W0A1 W0A0 R/W - - - W1A4 W1A3 W1A2 W1A1 W1A0 9 Suites 2202-7, 22/F, Tower 6, The Gateway, 9 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel (852) 2123 3289 Fax (852) 2123 3393 E-mail: sales@jesstech.com HomePage: http://www.jesstech.com WT5082 WT5082 V.0.97 ADDR 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH NAME P_decoder Control PDCTL P_decoder Receive Data PDDR P_decoder DMA mode Address pointer ( low byte ) PDDRpH Read Write R / W OverRange LostSync ErrorFlag 0 EPDMA REON PDEOM PDON R PDD7 PDD6 PDD5 PDD4 PDD3 PDD2 PDD1 PDD0 R PDA7 PDA6 PDA5 PDA4 PDA3 PDA2 PDA1 PDA0 - - PDBA3 PDBA2 PDBA1 PDBA0 PDA9 PDA8 R/W MCL ADCL - - R/W EOM7 EOM6 EOM5 EOM4 EOM3 EOM2 EOM1 EOM0 R/W - LCDPMP LCDDC LCDI FRQS3 FRQS2 FRQS1 FRQS0 R/W SIOE - - - - - - SCKO R / W SIOB07 SIOB07 SIOB06 SIOB06 SIOB05 SIOB05 SIOB04 SIOB04 SIOB03 SIOB03 SIOB02 SIOB02 SIOB01 SIOB01 R / W SIOB15 SIOB15 SIOB14 SIOB14 SIOB13 SIOB13 SIOB12 SIOB12 SIOB11 SIOB11 SIOB10 SIOB10 SIOB9 SIOB8 R / W SIOB23 SIOB23 SIOB22 SIOB22 SIOB21 SIOB21 SIOB20 SIOB20 SIOB19 SIOB19 SIOB18 SIOB18 SIOB17 SIOB17 SIOB16 SIOB16 R / W SIOB31 SIOB31 SIOB30 SIOB30 SIOB29 SIOB29 SIOB28 SIOB28 SIOB27 SIOB27 SIOB26 SIOB26 SIOB25 SIOB25 SIOB24 SIOB24 R / W EUART - RX_FULL TX_Empty R / W EPWM - PWM_TX PDDR DMA mode Address pointer ( high byte and Base Address ) R/W MPDDRp PDDRp pointer mask MPDDRp P_decoder EOM mark PDEOM LCD Dis[play Control LCDCTL Serial I/O Control SIOCTL SIO Data Buffer 0 SIOB0 SIO Data Buffer 1 SIOB1 SIO Data Buffer 2 SIOB2 SIO Data Buffer 3 SIOB3 UART Control UARTCTL PWM Control PWMCTL PWM Data Buffer PWMB System Clock Control CKCTL Bit number ClrPadr MPDA9 MPDA8 MPDA7 MPDA6 SIOB00 SIOB00 - - - UART_TX Plndex3 Plndex2 Plndex1 Plndex0 R / W PWMB7 PWMB6 PWMB5 PWMB4 PWMB3 PWMB2 PWMB1 PWMB0 R/W PLL4 PLL3 PLL2 PLL1 PLL0 CK2 CK1 V.0.97 10 CK0 Suites 2202-7, 22/F, Tower 6, The Gateway, 9 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel (852) 2123 3289 Fax (852) 2123 3393 E-mail: sales@jesstech.com HomePage: http://www.jesstech.com ADDR 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH NAME P_DECODER CONFIGURATION PDCONF0 P_DECODER CONFIGURATION PDCONF1 P_DECODER CONFIGURATION PDCONF2 P_DECODER CONFIGURATION PDCONF3 P_DECODER CONFIGURATION PDCONF4 P_DECODER CONFIGURATION PDCONF5 P_DECODER CONFIGURATION PDCONF6 P_DECODER CONFIGURATION PDCONF7 P_DECODER CONFIGURATION PDCONF8 P_DECODER CONFIGURATION PDCONF9 P_DECODER CONFIGURATION PDCONF10 PDCONF10 P_DECODER CONFIGURATION PDCONF11 PDCONF11 P_DECODER CONFIGURATION PDCONF12 PDCONF12 P_DECODER CONFIGURATION PDCONF13 PDCONF13 P_DECODER CONFIGURATION PDCONF14 PDCONF14 P_DECODER CONFIGURATION PDCONF15 PDCONF15 WT5082 WT5082 Bit number Read Write R/W A00 A01 A02 A03 A04 A05 A06 A07 R/W A08 A09 A10 A11 A12 A13 A14 A15 R/W A16 A17 FA0 FA1 FA2 FCA1 FCA0 DSA R/W B00 B01 B02 B03 B04 B05 B06 B07 R/W B08 B09 B10 B11 B12 B13 B14 B15 R/W B16 B17 FB0 FB1 FB2 FCB1 FCB0 DSB R/W C00 C01 C02 C03 C04 C05 C06 C07 R/W C08 C09 C10 C11 C12 C13 C14 C15 R/W C16 C17 FC0 FC1 FC2 FCC1 FCC0 DSC R/W D00 D01 D02 D03 D04 D05 D06 D07 R/W D08 D09 D10 D11 D12 D13 D14 D15 R/W D16 D17 FD0 FD1 FD2 FCD1 FCD0 DSD R/W E00 E01 E02 E03 E04 E05 E06 E07 R/W E08 E09 E10 E11 E12 E13 E14 E15 R/W E16 E17 FE0 FE1 FE2 FCE1 FCE0 DSE R/W F00 F01 F02 F03 F04 F05 F06 F07 V0.97 11 Suites 2202-7, 22/F, Tower 6, The Gateway, 9 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel (852) 2123 3289 Fax (852) 2123 3393 E-mail: sales@jesstech.com HomePage: http://www.jesstech.com ADDR 40H 41H 42H 43H 44H 45H 46H 47H 48H 49H 4AH NAME P_DECODER CONFIGURATION PDCONF16 PDCONF16 P_DECODER CONFIGURATION PDCONF17 PDCONF17 P_DECODER CONFIGURATION PDCONF18 PDCONF18 P_DECODER CONFIGURATION PDCONF19 PDCONF19 P_DECODER CONFIGURATION PDCONF20 PDCONF20 P_DECODER CONFIGURATION PDCONF21 PDCONF21 P_DECODER CONFIGURATION PDCONF22 PDCONF22 P_DECODER CONFIGURATION PDCONF23 PDCONF23 P_DECODER CONFIGURATION PDCONF24 PDCONF24 P_DECODER CONFIGURATION PDCONF25 PDCONF25 P_DECODER CONFIGURATION PDCONF26 PDCONF26 4BH ~ 4EH Bit number Read Write R/W F08 F09 F10 F11 F12 F13 F14 F15 R/W F16 F17 FF0 FF1 FF2 FCF1 FCF0 DSF R/W MF0 MF1 MF2 MF3 MF4 MF5 MF6 MF7 R/W MF8 MF9 MF10 MF11 MF12 MF13 MF14 MF15 R/W MF16 MF17 ×00 ×01 ×02 ×03 ×04 ×05 R/W ×06 ×07 ×08 0 0 ×11 ×12 ×13 R/W ×14 ×15 ×16 ×17 ×18 ×19 ×20 ×21 R/W ×22 ×23 ×24 ×25 ×26 ×27 ×28 ×29 R/W ×30 ×31 ×32 ×33 ×34 1 1 1 R/W ×38 ×39 ×40 ×41 ×42 ×43 ×44 ×45 R/W ×46 ×47 ×48 ×49 ×50 ×51 ×52 ×53 Reserved 4FH WT5082 WT5082 P_Decoder Status ( for Test ) PSTAT For Test only 12 Suites 2202-7, 22/F, Tower 6, The Gateway, 9 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel (852) 2123 3289 Fax (852) 2123 3393 E-mail: sales@jesstech.com HomePage: http://www.jesstech.com WT5082 WT5082 V.0.97 SECTION 3. INPUT / OUTPUT PORTS The WT5082 WT5082 consists of three parallel ports, namely P0 , P1 and P2. And, these entire ports can be served for multiple purposes depend on the port configuration. All port are reset to input mode. SECTION 3.1 PORT P0 The Port P0 is a 7 bits input and output port. Its functions are listed below and controlled by individual register. The EPI function is enabled when it is set as input. Port P00 _ RE Output P01 _ RE1 Output P02 _ Ptimer0 I/O Function RF control signal output or SCK output pin for serial I/O RF control signal 1 output ( quick charge ) or MOSI output pin for serial I/O General output port or output from ptimer0 P03 _ Ptimer1 I/O General output port or output from ptimer1 P04 _ RFDI Input RF signal data input P06 I/O General I/O or EPI6 P07 I/O General I/O or EPI7 P0DIR ( Port P0 Direction Register ) : reset value 0xFF Address Bit no 00H / R_W 7 6 5 4 3 2 1 0 P07D P06D - - P03D P02D - - P0CFG ( Port P0 Configuration Register ) : reset value 0x00 Address Bit no 01H / R_W 7 6 5 4 3 2 1 0 P07C P06C - P04C P03C P02C P01C P00C 13 Suites 2202-7, 22/F, Tower 6, The Gateway, 9 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel (852) 2123 3289 Fax (852) 2123 3393 E-mail: sales@jesstech.com HomePage: http://www.jesstech.com WT5082 WT5082 V.0.97 P0DAT ( Port P0 Data Register ) : reset value 0x00 Address Bit no 02H / R_W 7 6 5 4 3 2 1 0 P07 P06 - P04 P03 P02 - - P00 , P01 is used for output only with RF control signal or Serial I/O. User can set SIOE to enable P00 , P01 works with Serial I/O function. SIOE P00C / P01C 0 0 1 1 0 1 0 1 Function of Port P00 / P01 RE control output with Push-pull RF control output with open drain Serial I/O output with Push-pull Serial I/O output with open drain P02 , P03 is used for input and output with general output or Ptimer output. User can set EPT0 , EPT1 to enable P02 , P03 works with Ptimer output. P02D / P03D 0 0 0 0 1 1 OPT0 / OPT1 0 0 1 1 0 0 P02C / P03C 0 1 0 1 0 1 Function of Port P02 / P03 General output with Push-pull General output with open drain Ptimer output with Push-pull Ptimer output with open drain General input without pull-up General input with pull-up P04 is input only for RF signal Input. P04C Function of Port P04 0 1 Input without pull-up Input with pull-up 14 Suites 2202-7, 22/F, Tower 6, The Gateway, 9 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel (852) 2123 3289 Fax (852) 2123 3393 E-mail: sales@jesstech.com HomePage: http://www.jesstech.com WT5082 WT5082 V.0.97 P06 , P07 is used to multi-function with general I/O and EPI input. Set EPI6 , EPI7 can make P06 , P06 works with EPI interrupt. Disable EPI6 , EPI7 , it works with a general I/O port. EPI6 / EPI7 0 0 0 0 1 1 P06D / P07D 0 0 1 1 1 1 P06C / P07C 0 1 0 1 0 1 Function of Port P06 / P07 General output with Push-pull General output with open drain General input without pull-up General input with pull-up EPI input without pull-up EPI input with pull-up 15 Suites 2202-7, 22/F, Tower 6, The Gateway, 9 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel (852) 2123 3289 Fax (852) 2123 3393 E-mail: sales@jesstech.com HomePage: http://www.jesstech.com WT5082 WT5082 V.0.97 SECTION 3.2.1 PORT P1 ( External interrupt input port ) The P10 ~ P15 is served as an External Port Interrupt Function, and its configuration can be programmed by P1CFG. P1CFG ( Port P1 configuration Register ) : reset value 0x00 Address Bit no 03H / R_W 7 6 5 4 3 2 1 0 - - P15C P14C P13C P12C P11C P10C Function of Port P10C ~ P15C Input without pull-up Input with pull-up P10C ~ P15C 0 1 P1DAT ( Port P1 data Register ) : reset value 0x00 Address Bit no 04H / R_W 7 6 5 4 3 2 1 0 - - P15 P14 P13 P12 P11 P10 P15 is also connect to NMI interrupt input when EPDI7 enable and EPI5 disable. P14 is used for Battery low detect. User can connect P14 with RF borad ALM signal, it will automatically detect ALM when RE active. 16 Suites 2202-7, 22/F, Tower 6, The Gateway, 9 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel (852) 2123 3289 Fax (852) 2123 3393 E-mail: sales@jesstech.com HomePage: http://www.jesstech.com WT5082 WT5082 V.0.97 SECTION 3.3 PORT P2 ( general input and output port ) The Port.P2 is used for general I/O. User can program it to communicate with EEPROM or Flex Decoder. Its direction can be set by P2DIR. Out can be with or without open-drain by setting PWCFG. And Input can be with or without pull-up in the same way. P2DAT ( Port Data Register ) : reset value 0x00 Address 07H / R_W Bit no 7 6 5 4 3 2 1 0 - P26 P25 P24 P23 P22 P21 P20 P2DIR ( Port P2 direction Register ) : reset value 0xFF Address 05H / R_W Bit no 7 6 5 4 3 2 1 0 P27D P26D P25D P24D P23D P22D P21D P20D P2CFG ( Port P2 configuration Register ) : reset value 0xFF Address 06H / R_W Bit no 7 6 5 4 3 2 1 0 P27C P26C P25C P24C P23C P22C P21C P20C P2Xd P2xC 0 0 1 1 0 1 0 1 Function of Port P06 / P07 Output with Push-pull Output with open drain Input without pull-up Input with pull-up 17 Suites 2202-7, 22/F, Tower 6, The Gateway, 9 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel (852) 2123 3289 Fax (852) 2123 3393 E-mail: sales@jesstech.com HomePage: http://www.jesstech.com WT5082 WT5082 V.0.97 SECTION 4. CPU AND RELATIVE MODULES The WT5082 WT5082 includes one 6502 CPU module , and this section describes some 6502 functions that relative t the WT5082 WT5082 application. SECTION 4.1 CPU HALT CONTROL HALT ( CPU HALT Control register ) : reset value 0x00 Address bit no 0FH / W 7 6 5 4 3 2 1 0 - - - - - - - - Any write operation except interrupt routine to this address will stop the clock source of the CPU module , and any interrupt call will restart the CPU clock source. SECTION 4.2 CPU CLOCK SOURCE ( ) CKCTL ( System Clock Control register ) : reset value 0x00 18 Suites 2202-7, 22/F, Tower 6, The Gateway, 9 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel (852) 2123 3289 Fax (852) 2123 3393 E-mail: sales@jesstech.com HomePage: http://www.jesstech.com Address WT5082 WT5082 2FH / R_W bit no 7 6 5 4 3 2 1 0 PLL4 PLL3 PLL2 PLL1 PLL0 CK2 CK1 CK0 Where the CKCTL register defines the clock source of the 6502 CPU module V.0.97 CPU clock sources selection ( ) CK2 CK1 0 0 0 0 1 0 0 1 1 0 CPU clock source ( ) CK0 0 1 0 1 0 fXT ( 76.8K ) fXT / 2 ( 38.4K ) fXT * 2 ( 153.6K ) fXT * 4 ( 307.2K ) fM ( up to 2M ) Before you switch CPU Clock source to fM , you must set PLL0 ~ 4 first. You can select PLL output frequency by following table. User can choose Ring OSC by select PLL4 ~ PLL0 equal to 0. And other value set to PLL4 ~ PLL0 will work with PLL. PLL output clock table PLL4 PLL3 PLL2 PLL1 PLL0 Hz 0 0 0 0 0 RingOSC 0 0 0 0 1 0 0 0 0 1 1 0 1 1 1 0 0 . 1 1 1 19 Suites 2202-7, 22/F, Tower 6, The Gateway, 9 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel (852) 2123 3289 Fax (852) 2123 3393 E-mail: sales@jesstech.com HomePage: http://www.jesstech.com 1 1 1 0 1 1 1 1 1 0 1 1 1 1 WT5082 WT5082 1 V.0.97 SECTON 4.3 CHIP RESET The CPU module can be reset from four sources, namely the external RESETB pin, the automatic 2.2 voltage power on reset module, the watchdog timer reset and the 2.0V low power reset. The RESETB pin is the only external reset source, and it is connected with a Schmidt trigger input gate to improve the noise figure by the Schmidt trigger. Whenever the RESETB pin is pulled to low, the reset operation is active until this pin is changed to high. The automatic power on reset module is an internal 2.2V voltage detector module, and it generates a power on reset pulse when the power is under the voltage threshold value. The watchdog timer reset is generated when the watchdog time threshold value is reached. The programming and the function of watchdog timer are introduced on the next section. The lowpower reset will automatically detect VDD. When VDD is under 2.0V, it will generate reset signal to chip reset. It normally works with 30. CHIP RESET SOURCE DIAGRAM 20 Suites 2202-7, 22/F, Tower 6, The Gateway, 9 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel (852) 2123 3289 Fax (852) 2123 3393 E-mail: sales@jesstech.com HomePage: http://www.jesstech.com WT5082 WT5082 V.0.97 SECTION 4.4 WATCHDOG TIMER The watchdog timer is controlled by the WEN-bit of the WDTCTL register, and its clock source is from fWTCK ( the watchdog timer clock ). Frequencies of this clock are defined by the WCK1 and WCK0 of WDTCTL register. Whenever the CPU accesses the WDTCTL register, the watchdog timer / counter will be reset to zero. WDTCTL ( Watchdog Timer Control register ) : reset value 0x00 Address 08H / R_W bit no 7 6 5 4 3 2 1 0 WEN - - - - - WCK1 WCK0 WCK1 WCK0 Watchdog timer active cycle 0 0 1 0 1 0 1 second 2 second 4 second 21 Suites 2202-7, 22/F, Tower 6, The Gateway, 9 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel (852) 2123 3289 Fax (852) 2123 3393 E-mail: sales@jesstech.com HomePage: http://www.jesstech.com 1 1 WT5082 WT5082 8 second V.0.97 SECTON 4.5 TIMER MODULE ( PTIMER 0 / 1 , TIME BASE , RTC 0 / 1 ) There are 5 timer modules in WT5082M WT5082M, namely ptimer 0, ptimer1, time base timer and the real time clock 0/1 ( RTC ). The PTIMER 0 and 1 generate the IRQ interrupt to CPU when the timer is reloaded after the counting value reaches zero. User programming the preload timer values into the PTIME0 and PTIME1 registers, and then enable these timer modules. The clock source of these two timers is selected from PTS11 PTS11, PTS10 PTS10, PTS01 PTS01 and PTS00 PTS00 of PT0CTL or PT1CTL register. Both two timers also can serve as the counter function, and the counter value can be obtained from the TIMER0 and the TIMER1 registers. PT0CTL ( PORT TIMER 0 CONTROL register ) : reset value 0x00 Address bit no 09H / R_W 7 6 5 4 3 2 1 0 EPT0 - PT0S OPT0 - - PTS01 PTS01 PTS00 PTS00 22 Suites 2202-7, 22/F, Tower 6, The Gateway, 9 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel (852) 2123 3289 Fax (852) 2123 3393 E-mail: sales@jesstech.com HomePage: http://www.jesstech.com WT5082 WT5082 PTIME0 ( PORT TIMER 0 PRELOAD DATA ) : reset value 0x00 Address bit no 0AH / W 7 6 5 4 3 2 1 0 PT07 PT06 PT05 PT04 PT03 PT02 PT01 PT00 TIMER0 ( PORT TIMER 0 COUNTER VALUE ) : reset value 0x00 Address bit no 0BH / R 7 6 5 4 3 2 1 0 T07 T06 T05 T04 T03 T02 T01 T00 TIMER0 ( PORT TIMER 0 COUNTER VALUE ) : reset value 0x00 Address bit no 0CH / R_W 7 6 5 4 3 2 1 0 EPT1 - PT1S OPT1 - - PTS11 PTS11 PTS10 PTS10 V.0.97 PTIME1 ( PORT TIMER 1 PRELOAD DATA ) : reset value 0x00 Address bit no 0DH / R 7 6 5 4 3 2 1 0 PT17 PT16 PT15 PT14 PT13 PT12 PT11 PT10 TIMER1 ( PORT TIMER 1 COUNTER VALUE ) : reset value 0x00 Address bit no 0EH / R 7 6 5 4 3 2 1 0 T17 T16 T15 T14 T13 T12 T11 T10 23 Suites 2202-7, 22/F, Tower 6, The Gateway, 9 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel (852) 2123 3289 Fax (852) 2123 3393 E-mail: sales@jesstech.com HomePage: http://www.jesstech.com WT5082 WT5082 The PTOCTL and PT1CTL registers control the port timer 0 and timer 1 for enabling or not. The PTS11 PTS11, PTS10 PTS10, PTS01 PTS01, PTS00 PTS00 data bits of PT0CTL and PT1CTL registers define the clock source of the PTIME0 and PTIME1 clock counter. The PT0S, PT1S registers define the output waveform is normal or inverse. EPT1 EPT0 Function 1 0 X X X X 1 0 Enable Port Timer 1 ( PTIME 1 ) Disable Port Timer 1 ( PTIME 1 ) Enable Port Timer 0 ( PTIME 0 ) Disable Port Timer 0 ( PTIME 0 ) When Disable Ptimer.0 and Ptimer.1, It will output High PT1S PT0S Function 1 0 X X X X 1 0 Inverse Output Waveform ( PTIME1 ) Normal Output Waveform ( PTIME1 ) Inverse Output Waveform ( PTIME0 ) Normal Output Waveform ( PTIME0 ) v.0.97 OPT1 OPT0 Function 1 0 X X X X 1 0 Enable P03 output with Ptimer1 Disable P03 output with Ptimer1 Enable P02 output with Ptimer0 Disable P02 output with Ptimer0 PTS01 PTS01 PTS00 PTS00 PTIME0 clock source ( when fp = 32.768khz & fXT = 76.8khz ) 0 0 1 0 1 0 fXT ( 76.8k ) fXT * 2 ( 153.6k ) fPTIME1 ( clock from PTIME1 ) 24 Suites 2202-7, 22/F, Tower 6, The Gateway, 9 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel (852) 2123 3289 Fax (852) 2123 3393 E-mail: sales@jesstech.com HomePage: http://www.jesstech.com 1 1 Fp / 2 7 ( 256hz ) PTS11 PTS11 PTS10 PTS10 PTIME1 clock source ( when fp = 32.768khz & fXT = 76.8khz ) 0 0 1 1 0 1 0 1 WT5082 WT5082 fXT ( 76.8k ) fXT * 2 ( 307.2k ) fp / 2 6 ( 512hz ) fp / 2 7 ( 256hz ) v.0.97 25 Suites 2202-7, 22/F, Tower 6, The Gateway, 9 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel (852) 2123 3289 Fax (852) 2123 3393 E-mail: sales@jesstech.com HomePage: http://www.jesstech.com WT5082 WT5082 v.0.97 The Time base timer , RTC timer 0, and the RTC timer 1 are controlled by the BTCTL and the RTCCTL registers. The EBT of BTCTL enables the Time base timer and the BTS1 and BTS0 bits define the clock source of the time base timer. While the reload timer value is given at the TIMERB register, the counter value of the time base timer can be obtained from the BTIME register. The RT11 and RT10 bits of the RTCCTL register define the RTC1 interrupt clock source, and the RT01 and RT00 bits define the RTC0 interrupt source. For convenience sake, we also provide Hour, Minute, and Second register to display time. User can program Hour, Minute, and Second. We suggest that user write " 0 " to the " SET " bit of the Hour register before programming. The RTC time is counting unless the " SET " bit is " 1 ". And there is an IRQ interrupt per minute to cpu in order to refresh Date, Month, and Year in system application. See more detail in Section4.6. 26 Suites 2202-7, 22/F, Tower 6, The Gateway, 9 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel (852) 2123 3289 Fax (852) 2123 3393 E-mail: sales@jesstech.com HomePage: http://www.jesstech.com WT5082 WT5082 BTCTL ( Time base timer control register ) : reset value 0x00 Address bit no 10H / R_W 7 6 5 4 3 2 1 0 EBT - - - - - BTS1 BTS0 BTIME ( Time base timer preload data ) : reset value 0x00 Address bit no 11H / W 7 6 5 4 3 2 1 0 BT7 BT6 BT5 BT4 BT3 BT2 BT1 BT0 TIMERB ( Time base counter value ) : reset value 0x00 Address bit no 12H / R 7 6 5 4 3 2 1 0 TB7 TB6 TB5 TB4 TB3 TB2 TB1 TB0 RTCCTL ( RTC timer control ) : reset value 0x00 Address bit no 13H / R_W 7 6 5 4 3 2 1 0 - - RT11 RT10 - - RT01 RT00 v.0.97 EBT BTS1 BTS0 Function / Clock source 0 1 X X X - X 0 0 1 - X 0 1 0 Time base timer is disable Time base timer is enable fp / 2 5 ( 1024hz ) fp / 2 7 ( 256hz ) fp / 2 9 ( 64hz ) 27 Suites 2202-7, 22/F, Tower 6, The Gateway, 9 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel (852) 2123 3289 Fax (852) 2123 3393 E-mail: sales@jesstech.com HomePage: http://www.jesstech.com X 1 WT5082 WT5082 fp / 2 11 ( 16hz ) 1 RT11 / RT01 RT10 / RT00 Clock source 0 0 1 1 0 1 0 1 1hz 2hz 8hz 32hz v.0.97 Hour ( RTC Hour register ) : reset value 0x00 Address bit no 14H / R_W 7 6 5 4 3 2 1 0 SET - - H4 H3 H2 H1 H0 28 Suites 2202-7, 22/F, Tower 6, The Gateway, 9 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel (852) 2123 3289 Fax (852) 2123 3393 E-mail: sales@jesstech.com HomePage: http://www.jesstech.com WT5082 WT5082 Minute ( RTC Minute register ) : reset value 0x00 Address bit no 15H / R_W 7 6 5 4 3 2 1 0 - - M5 M4 M3 M2 M1 M0 Second ( RTC Second register ) : reset value 0x00 Address bit no 16H / R_W 7 6 5 4 3 2 1 0 - - S5 S4 S3 S2 S1 S0 SECTION 4.6 INTERRUPT SOURCE The NMI interrupt source is connected with P_DECODER module, and the IRQ interrupt source is connected with the other timer & external interrupt input. SOURCE of CPU / NMI and / IRQ DIAGRAM POSCAG DECODER PDI, ( EPI5 ) interrupt NMI PDI, ( EPI5 ) interrupt IRQ ( EPI5 ) EPI0 ~ EPI5 EPI6 ~ EPI7 PTIMER 0 / 1 TIME BASE TIMER RTC 0 / 1 v.0.97 NMI & IRQ Interrupt vector address Vector Address Interrupt Source FFFAH , FFFBH NMI interrupt 29 Suites 2202-7, 22/F, Tower 6, The Gateway, 9 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel (852) 2123 3289 Fax (852) 2123 3393 E-mail: sales@jesstech.com HomePage: http://www.jesstech.com FFFCH , FFFDH Reset FFFEH , FFFFH WT5082 WT5082 IRQ Interrupt mask registers : IRQMK ( IRQ interrupt mask register ) : reset value 0x00 Address bit no 17H / R_W 7 6 5 4 3 2 1 0 - MRTC MSIO MRT1 MRT0 MBT MPT1 MPT0 EPIMK ( EPI interrupt mask register ) : reset value 0x00 Address bit no 19H / R_W 7 6 5 4 3 2 1 0 EEPI7 EEPI6 EEPI5 EEPI4 EEPI3 EEPI2 EEPI1 EEPI0 PDIMK ( P-decoder Interrupt Mask register ) : reset value 0x00 Address bit no 1CH / R_W 7 6 5 4 3 2 1 0 EPDI7 EPDI6 EPDI5 EPDI4 EPDI3 EPDI2 EPDI1 EPDI0 ( NOTE ) PDECODER interrupt connect with the NMI interrupt of CPU v.0.97 Interrupt status registers : IRQSR ( IRQ interrupt status register ) : reset value 0x00, reset after read Address 18H / R 30 Suites 2202-7, 22/F, Tower 6, The Gateway, 9 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel (852) 2123 3289 Fax (852) 2123 3393 E-mail: sales@jesstech.com HomePage: http://www.jesstech.com bit no WT5082 WT5082 6 5 4 3 2 1 0 FEPI ( NOTE ) 7 FRTC FSIO FRT1 FRT0 FBT FPT1 FPT0 Any read operation to IRQSR will clear all IRQSR data bits ( except FEPI ). FEPI will be reset when EPISR is cleared as zero. EPISR ( EPI interrupt status register ) : reset value 0x00, reset after read Address bit no 1AH / R 6 5 4 3 2 1 0 EPI7 ( NOTE ) 7 EPI6 EPI5 EPI4 EPI3 EPI2 EPI1 EPI0 Any read operation to EPISR will clear all EPISR data bits. And EPI5 is also connect to NMI when EPDI7 enable and EEPI5 disable PDISR ( P-Decoder interrupt status register ) : reset value 0x00, reset after read Address bit no 1DH / R 6 5 4 3 2 1 0 PDI7 ( NOTE ) 7 PDI6 PDI5 PDI4 PDI3 PDI2 PDI1 PDI0 Any read operation to PDISR will clear PDI0 ­ PDI7 INTERRUPT DEFINITION : IRQ Interrupt ( PTIMER 0/1, Time Base timer, EPI, RTC 0/1, Per Minute ) The CPU IRQ interrupt is generated by the EPI input (External Port Interrupt, can be used as key wakeup interrupt), time base timer, port timer 0/1, and the RTC clock interrupt. The P10-PI7 P10-PI7 pins service two basic functions: the External Port Interrupt ( EPI ) input pins and the general-purpose input pins. EPI.4 is default used for ALM and it will automatically detect battery voltage when RE active and EPI.5 is also connect to .0.97 NMI interrupt input when EEPI5 diable and EPDI7 enable. The other EPI function is enabled and a falling edge is detected at one of the enabled EPI pin input, the EPIx-bit in the EPISR register is set and if the 31 Suites 2202-7, 22/F, Tower 6, The Gateway, 9 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel (852) 2123 3289 Fax (852) 2123 3393 E-mail: sales@jesstech.com HomePage: http://www.jesstech.com WT5082 WT5082 EEPIx-bit of EPIMK register is enabled, one IRQ interrupt is generated to 6502. Each EPI input pin can be enabled or disabled by the corresponding EEPIx-bit in the EPIMK register, and the usage of the EPI function does not affect the input function of port P 1, user can get the EPI pin status from the EPISR data register. IRQSR ( IRQ interrupt status register ) , clear after read FEPI FRTC FSIIO FRT1 FRT0 FBT FPT1 FPT0 Interrupt status X X X X X X X 1 Ptimer 0 interrupt X X X X X X 1 X Ptime 1 interrupt X X X X X X X Time base timer interrupt X X X X X X X PTC 0 interrupt X X X X X X X RTC 1 interrupt X X X X X X X There are SIO interrupt X X X X X X X RTC rer Minute interrupt X X X X X X X There are EPI interrupt ( note : when FEPI is set , ref to the EPISR to get the status of EPI ) IRQMK ( IRQ interrupt mask register ) , status MRTC MSIO MRT1 MRT0 MBT MPT1 MPT0 Interrupt status X X X X X X 1 Enable Ptimer 0 interrupt X X X X X 1 X Enable Ptimer 1 interrupt X X X X 1 X X Enable Time base timer interrupt X X X 1 X X X Enable RTC 0 interrupt X X 1 X X X X Enable RTC 1 interrupt X 1 X X X X X Enable SIO interrupt X X X X X X Enable RTC / min interrupt ( note : the interrupt mask of EPI is defined at the EPIMK register ) v.0.97 EPI ( External Port Interrupt and RTC Interrupt ) 32 Suites 2202-7, 22/F, Tower 6, The Gateway, 9 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel (852) 2123 3289 Fax (852) 2123 3393 E-mail: sales@jesstech.com HomePage: http://www.jesstech.com WT5082 WT5082 The EPIMK register controls the external port interrupt function is acted or not. Set 0 to the EPIEx bit of EPIMK register disables the EPI function. The IEPI register can invert the input EPIx signal value, when the IEPIx bit is set as 0, the rising edge of the P1x / EPIx pin will generates an EPI interrupt. In the other case, the IEPIx bit is set as 1, the EPI interrupt is generated when there is a falling edge change of the P1x / EPIx pin input. Becarefully EPI.5 is also connect with NMI interrupt input when EEPI5 disable and EPDI7 enable. EPIMK ( EPI interrupt Mask register ) : reset value 0x00 Address bit no 19H / R_W 7 6 5 4 3 2 1 0 EEPI7 EEPI6 EEPI5 EEPI4 EEPI3 EEPI2 EEPI1 EEPI0 EEPI7 ­ EEPI0 EEPIx 0 1 ( External Port Interrupt Enable ) P1 x / EP x ( External Port Interrupt ) pin Disable Enable 33 Suites 2202-7, 22/F, Tower 6, The Gateway, 9 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel (852) 2123 3289 Fax (852) 2123 3393 E-mail: sales@jesstech.com HomePage: http://www.jesstech.com WT5082 WT5082 v.0.97 IEPI ( Interrupt EPI signal register ) : reset value 0x00 Address bit no 1BH / R_W 7 6 5 4 3 2 1 0 IEPI7 IEPI6 IEPI5 IEEPI4 IEPI3 IEPI2 IEPI1 IEPI0 IEPI7 ­ IEPI0 ( Invert EPI input, only for Port P1 ) IEPIx 0 1 P1x active EPI function clock edge Normal ( rising edge active ) Invert ( falling edge active ) EPISR ( EPI status register ) : reset value 0x00, reset after read Address bit no 1AH / R 7 6 5 4 3 2 1 0 EPI7 EPI6 EPI5 EEPI4 EPI3 EPI2 EPI1 EPI0 IEPI7 ­ IEPI0 ( Invert EPI input, only for Port P1 ) IEPIx 0 1 P1x active EPI function clock edge Normal ( rising edge active ) Invert ( falling edge active ) ( Note : EPI5 is connect with NMI interrupt when EEPI5 disable and EPDI7 enable. And EPI4 is work with batter low detect, it will automatically detect ALM when RE active ) 34 Suites 2202-7, 22/F, Tower 6, The Gateway, 9 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel (852) 2123 3289 Fax (852) 2123 3393 E-mail: sales@jesstech.com HomePage: http://www.jesstech.com WT5082 WT5082 v.0.97 P-DECODER Interrupt ( PDI ) The / NMI interrupt is exclusively used to service the POCSAG code decoder module ( PDI interrupt / PDECODER Interrupt ), and the interrupt is generated when there is any status change of POCSAG code decoder such as receiver address, message and out of range indicator or DMA buffer overflow. The interrupt status can be obtained from the PDISR register, and the P-DECODER based on the internal status of decoder updates this register then interrupts the CPU module when there is any status changed. This PDISR register is a read only data register, and when there is any change of the PDISR register, the PDIMK register enables or disables the interrupt operation to the CPU module. The EPDMA-bit of the PDCTL register enables the P-decoder with the CPU interface mode into the DMA mode, for more details information please refer to the " POCSAG CODE DECODER " section. PDISR ( P-DECODER & EPI Interrupt ) status PDI7 PDI6 PDI5 PDI4 PDI3 PDI2 PDI1 PDI0 X X X X X X X 1 Address ID matched X X X X X X 1 X End of message codeword receive X X X X X X X Over Range X X X X X X X Synchronize with POSCAG code X X X X X X X Send message codeword data X X X X X X X Incoming POCSAG in SC frame X X X X X X X DMA Buffer Overflow X X X X X X X External interrupt form Port15 35 Interrupt status of P-DECODER Suites 2202-7, 22/F, Tower 6, The Gateway, 9 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel (852) 2123 3289 Fax (852) 2123 3393 E-mail: sales@jesstech.com HomePage: http://www.jesstech.com WT5082 WT5082 PDIMK ( P-DECODER Interrupt Mask register ) EPDI7 EPDI6 EPDI5 EPDI4 EPDI3 EPDI2 EPDI1 EPDI0 Interrupt status of P-DECODER X X X X X X X 1 Enable PDI0 interrupt X X X X X X 1 X Enable PDI1 interrupt X X X X X X X Enable PDI2 interrupt X X X X X X X Enable PDI3 interrupt X X X X X X X Enable PDI4 interrupt X X X X X X X Enable PDI5 interrupt X X X X X X X Enable PDI6 interrupt X X X X X X X Enable PDI7 interrupt v.0.97 SECTION 5. POCSAG CODE DECODER The POCSAG code decoder ( P-DECODER ) module is fully compatible with the CCIR Radio Paging Code Number 1, it can support 512 bps, 1200bps and 2400bps data speed base on one single crystal. The WT5082 WT5082 architecture allows for the numeric, alphanumeric, and tone only pager application. SECTION 5.1 P DECODER FEATURE l l l l l l l l l l l l Fully compatible with CCIR Radio-paging Code No. 1 ( POCSAG standard ). Single crystal support 512, 1200 and 2400 baud rate ( 76.SkHz crystal ) Support 6 RIC addresses and 6 independent frame numbers. Support partial address match facility for address F ( up to 260k addresses are provided ). 3 RF power saving control lines ( PLL, quick charge, and enable ). Support alphanumeric, numeric or tone only pages application. Build in data filter ( 16-times over-sampling ) and data bit clock recovery. Interrupt 6502 CPU when there are any status change Communicate with 6502 CPU base on memory I/O map method. Provide 2-bit random error correction and 3 bits random error detection in all code words. Synchronize / over range indication. DMA or interrupt mode to send the received message data to 6502 CPU. 36 Suites 2202-7, 22/F, Tower 6, The Gateway, 9 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel (852) 2123 3289 Fax (852) 2123 3393 E-mail: sales@jesstech.com HomePage: http://www.jesstech.com WT5082 WT5082 v.0.97 PDCONFx ( P-DECODER configuration registers ) : reset value 0x00 37 Suites 2202-7, 22/F, Tower 6, The Gateway, 9 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel (852) 2123 3289 Fax (852) 2123 3393 E-mail: sales@jesstech.com HomePage: http://www.jesstech.com ADDR NAME WT5082 WT5082 Bit number Read Write 0030H 0030H PDCONF0 R/W A00 A01 A02 A03 A04 A05 A06 A07 0031H 0031H PDCONF1 R/W A08 A09 A10 A11 A12 A13 A14 A15 0032H 0032H PDCONF2 R/W A16 A17 FA0 FA1 FA2 FCA1 FCA0 DSA 0033H 0033H PDCONF3 R/W B00 B01 B02 B03 B04 B05 B06 B07 0034H 0034H PDCONF4 R/W B08 B09 B10 B11 B12 B13 B14 B15 0035H 0035H PDCONF5 R/W B16 B17 FB0 FB1 FB2 FCB1 FCB0 DSB 0036H 0036H PDCONF6 R/W C00 C01 C02 C03 C04 C05 C06 C07 0037H 0037H PDCONF7 R/W C08 C09 C10 C11 C12 C13 C14 C15 0038H 0038H PDCONF8 R/W C16 C17 FC0 FC1 FC2 FCC1 FCC0 DSC 0039H 0039H PDCONF9 R/W D00 D01 D02 D03 D04 D05 D06 D07 003AH 003AH PDCONF10 PDCONF10 R/W D08 D09 D10 D11 D12 D13 D14 D15 003BH 003BH PDCONF11 PDCONF11 R/W D16 D17 FD0 FD1 FD2 FCD1 FCD0 DSD 003CH 003CH PDCONF12 PDCONF12 R/W E00 E01 E02 E03 E04 E05 E06 E07 003DH 003DH PDCONF13 PDCONF13 R/W E08 E09 E10 E11 E12 E13 E14 E15 003EH 003EH PDCONF14 PDCONF14 R/W E16 E17 FE0 FCE1 FCE0 DSE 003FH 003FH PDCONF15 PDCONF15 R/W F00 F01 F02 F03 F04 F05 F06 F07 0040H 0040H PDCONF16 PDCONF16 R/W F08 F09 F10 F11 F12 F13 F14 F15 0041H 0041H PDCONF17 PDCONF17 R/W F16 F17 FF0 FF1 FF2 FCF1 FCF0 DSF 0042H 0042H PDCONF18 PDCONF18 R/W MF0 MF1 MF2 MF3 MF4 MF5 MF6 MF7 0043H 0043H PDCONF19 PDCONF19 R/W MF8 MF9 MF10 MF11 MF12 MF13 MF14 MF15 0044H 0044H PDCONF20 PDCONF20 R/W MF16 MF17 X00 X01 X02 X03 X04 X05 0045H 0045H PDCONF21 PDCONF21 R/W X06 X07 X08 X11 X12 X13 0046H 0046H PDCONF22 PDCONF22 R/W X14 X15 X16 X17 X18 X19 X20 X21 0047H 0047H PDCONF23 PDCONF23 R/W X22 X23 X24 X25 X26 X27 X28 X29 0048H 0048H PDCONF24 PDCONF24 R/W X30 X31 X32 X33 X34 0049H 0049H PDCONF25 PDCONF25 R/W X38 X39 X40 X41 X42 X43 X44 X45 004AH 004AH PDCONF26 PDCONF26 R/W X46 X47 X48 X49 X50 X51 X52 X53 v.0.97 SECTION 5.2 RELATIVE REGISTERS PDCTL ( P-DECODER control register ) : reset value 0x00 38 Suites 2202-7, 22/F, Tower 6, The Gateway, 9 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel (852) 2123 3289 Fax (852) 2123 3393 E-mail: sales@jesstech.com HomePage: http://www.jesstech.com Address bit no WT5082 WT5082 20H / R_W 7 OverRan ge 6 5 LostSyn ErrorFla c g 4 3 2 1 0 0 EPDMA REON PDEOM PDON EPDMA REON PDEOM PDON Ennable function X X X 1 Enable P-Decoder X X 1 X Enable P-Decoder EOM mode X X X Force RE pin ON X X X Enable P-Decoder DMA mode The following 3 bits is read only and will reset to 0 when address match : Function bit status 0 1 OverRange In POCSAG sync status LostSync Never Sync with S.C. ( OverRange = 1 ) ErrorFlag No error ( X34 = 1 ) PS. LostSync will reset after reading Lost sync with POCSAG Ever Sync with S.C. CW have error PDIMK ( P-DECODER interrupt mask register ) : reset value 0x00 Address 1CH / R_W bit no 7 6 5 4 3 2 1 0 PDIMK EPDI7 EPDI6 EPDI5 EPDI4 EPDI3 EPDI2 EPDI1 EPDI0 PDISR ( P-DECODER interrupt status register ) : reset value 0x00, reset after read Address 1DH / R bit no 7 6 5 4 3 2 1 0 PDISR PDI7 PDI6 PDI5 PDI4 PDI3 PDI2 PDI1 PDI0 v.0.97 PDDR ( P-DECODER receive data register ) : reset value 0x00 39 Suites 2202-7, 22/F, Tower 6, The Gateway, 9 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel (852) 2123 3289 Fax (852) 2123 3393 E-mail: sales@jesstech.com HomePage: http://www.jesstech.com Address WT5082 WT5082 21H / R bit no 7 6 5 4 3 2 1 0 PDDR PDD7 PDD6 PDD5 PDD4 PDD3 PDD2 PDD1 PDD0 PDDRp ( PDDR DMA mode address pointer / low byte ) : reset value 0x00 Address 22H / R bit no 7 6 5 4 3 2 1 0 PDDRp PDA7 PDA6 PDA5 PDA4 PDA3 PDA2 PDA1 PDA0 PDDRpH ( PDDR DMA mode address pointer / high byte / Base address ) : reset value 0x00 Address 23H / R_W bit no 7 6 5 4 3 2 1 0 PDDRpH - - PDBA3 PDBA2 PDBA1 PDBA0 PDA9 PDA8 Note : PDA8, PDA9 is read only , others are R/W. MPDDRp ( PDDRp mask register ) : reset value 0x00 Address 24H / R_W bit no 7 6 5 4 3 2 1 0 MPDDRp MCL ADCL - - MPDA9 MPDA8 MPDA7 MPDA6 PDEOM ( P-DECODER EOM ( End of Message ) Address mark register ) : reset value 0x00 25H / R_W bit no 7 PDEOM EOM7 6 EOM6 5 4 3 2 1 0 EOM5 EOM4 EOM3 EOM2 EOM1 EOM0 v.0.97 40 Suites 2202-7, 22/F, Tower 6, The Gateway, 9 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel (852) 2123 3289 Fax (852) 2123 3393 E-mail: sales@jesstech.com HomePage: http://www.jesstech.com ABSOLUTE MAXIMUM RATINGS ( VSS = 0 V ) SYMBO PARAMETER RATING L DC Supply Voltage VDD -0.5 ~ +3.6 Input Voltage Vin -0.5 ~ VDD + 0.5 Range Operating Tor 0 ~ +70 Temperature Storage Tstg -50 ~ +150 Temperature WT5082 WT5082 UNIT V V V0.97 POCSAG DECODER MODULE ( P-DECODER ) 41 Suites 2202-7, 22/F, Tower 6, The Gateway, 9 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel (852) 2123 3289 Fax (852) 2123 3393 E-mail: sales@jesstech.com HomePage: http://www.jesstech.com WT5082 WT5082 v.0.97 SECTION 5.3 CPU INTERFACE The CPU module configures the P-DECODER by the PDCONF0 ~ PDCONF26 PDCONF26 registers, and enables or turn on the P-DECODER by the PDON bit of PDCTL register. When there is any status changed of the P-DECODER, the P-DECODER interrupts the CPU module and sets the interrupt flag bits in the PDISR register. The received POCSAG codeword data can be obtained from the PDDR registers. After the P-DECODER is turned on, the RE1 and RE2 pins are acted as the RF power saving control output ports and the P-DEOCDER waits for the incoming POCSAG code signal from the RFDI input pin. P-DECODER interrupts CPU When the P-DECODER is turned on and enabled, the P-DECODER starts to receive the incoming POCSAG codeword data. If there is any status changed, the P-DECODER set the PDIx bits of PDISR register, and then interrupts the CPU module. Whenever any one of the RIC addresses, that set in the PDCONFx registers, are matched with the incoming POCSAG address codeword, the PDECODER interrupts the CPU module and starts to send the received codeword data by the PDDR registers. The PDIMK register is used to control the P-decoder interrupt operation, either enable or disable. PDISR ( P-DECODER ) status 42 Suites 2202-7, 22/F, Tower 6, The Gateway, 9 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel (852) 2123 3289 Fax (852) 2123 3393 E-mail: sales@jesstech.com HomePage: http://www.jesstech.com WT5082 WT5082 PDI7 PDI6 PDI5 PDI4 PDI3 PDI2 PDI1 PDI0 Interrupt status of P-DECODER X X X X X X X 1 Address ID matched X X X X X X 1 X End of message codeword receive X X X X X X X Over Range X X X X X X X Synchronize with POSCAG code X X X X X X X Send message codeword data X X X X X X X Incoming POCSAG in SC frame X X X X X X X DMA Buffer Overflow X X X X X X X Battery removed v.0.97 PDIMK ( P-DECODER Interrupt Mask register) EPDI7 EPDI6 EPDI5 EPDI4 EPDI3 EPDI2 EPDI1 EPDI0 Enable function X X X X X X X 1 Enable PDI0 interrupt X X X X X X 1 X Enable PDI1 interrupt X X X X X X X Enable PDI2 interrupt X X X X X X X Enable PDI3 interrupt X X X X X X X Enable PDI4 interrupt X X X X X X X Enable PDI5 interrupt X X X X X X X Enable PDI6 interrupt X X X X X X X Enable PDI7 interrupt Data DMA mode of P-DECODER The P-DECODER receives the incoming message codeword data of the matched RIC address, and transfers them to the CPU module by either interrupt mode or the DMA mode. In the interrupt mode, 43 Suites 2202-7, 22/F, Tower 6, The Gateway, 9 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel (852) 2123 3289 Fax (852) 2123 3393 E-mail: sales@jesstech.com HomePage: http://www.jesstech.com WT5082 WT5082 the CPU enables the PDDR active interrupt by setting the EPDI4 of the PDISR register. While CPU receives this interrupt, it can obtain the incoming message codeword data at the PDDR register. The EPDMA bit of the PDCTL register enables the P-DECODER data DMA mode. In this mode, the P-DECODER automatically transfers the incoming message codeword data into the data RAM module that addressed by the PDDR address pointer, which is read only and defined at the PDDRp & PDDRpH register. The PDDR address pointer register automatically increases by 1 after each PDDR data write operation. The 6502 CPU module can get the last data address pointer by accessing this register ( PDBAx & PDDRp & PDDRpH ). We use MPDDRp to descide one page size. PDBAx ( x = 0-3 ) in PDDRpH to indicate which page is used. Before using DMA mode, set PDBAx to an available memory address. We strongly suggest that do not set PDBAx as "0000 " ( zero page ). Page 0 PDBAx = 0000, Page 1 PDBAx = 0001, . . Page15 PDBAx = 1111, PDDR address pointer = { PDBAx, PDA9, PDA8, . . , PDA1, PDA0 } v.0.97 P-DECODER data DMA mode 44 Suites 2202-7, 22/F, Tower 6, The Gateway, 9 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel (852) 2123 3289 Fax (852) 2123 3393 E-mail: sales@jesstech.com HomePage: http://www.jesstech.com WT5082 WT5082 v.0.97 In the P DECODER data DMA mode, the memory address is defined at the PDDRp and PDDRpH register, and it can define 14-bit memory address. The MPDDRp register can mask the address output of the PDDRp and PDDRpH register, and by using the MPDDRp register the updated memory area can be limited at one sub-area of memory. If PDDRpH is being mask, PDA9 ~ PDA6 can be written to change different address. For example, when the MPPDRp equals to 0x0FH, then PDA9 ~ PDA6 can be witten. The PDDRpH register is set as 0x04H, and PDDRp register is set as 0x80H then the DMA memory address will be limited at 0480H 0480H to 04BFH 04BFH area. If PDDRp register is set as 0x40H then DMA memory address will limited at 0440H 0440H to 047FH 047FH area. If MPPDRp equals to 0x0CH, then only PDA9 and PDA8 can be written, PDA7 and PDA6 are read only. So if PDDRpH register is set as 0x04H, and PDDRp register can't be set then the DMA memory address will be limited at 0400H 0400H to 04FFH 04FFH area. User can set the MCL bit of MPDDRp to clear PDDRp and PDDRpH after each cpu reading, or set the ADCL bit of MDDRp to clear automatically PDDRp and PDDRpH when P_decoder address is matched. 45 Suites 2202-7, 22/F, Tower 6, The Gateway, 9 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel (852) 2123 3289 Fax (852) 2123 3393 E-mail: sales@jesstech.com HomePage: http://www.jesstech.com MPDAx WT5082 WT5082 Data memory address bus 0 ( PDAx is read / write ) Enable PDAx 0 ( PDAx is read only ) (note: X is between 9 ~ 6 ) 1 MPDDRp Data memory address bus 0x0F 64 0x0E 128 0x0C 256 0x08 512 0x00 1024 v.0.97 RECEIVED MESSAGE DATA FORMAT ( PDDR REGISTER ) When the incoming POCSAG address codeword matches one of the internal RICs, the P-DECODER interrupts the CPU module and stores the incoming codeword data into the PDDR register. There are 3 different formats in the PDDR register data words, the start word, the message word and the EOM (end of message) mark byte. The start word contains the matched address ID, address codeword data and the FC code. The message word contains the received message codeword data and error flag. The data format of message word can be the package data format or the direct shift format. The package data format can be 4 or 7 bits per byte, which is set by the X00 - X07, X38 - X53 of PDCONFx register. The EOM mark byte is sent while end of the message codeword. The EOM mark byte is defined at 46 Suites 2202-7, 22/F, Tower 6, The Gateway, 9 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel (852) 2123 3289 Fax (852) 2123 3393 E-mail: sales@jesstech.com HomePage: http://www.jesstech.com WT5082 WT5082 PDEOM register and is enabled when the PDEOM bit of PDCTL register is enabled. Message Word ( 2 to 5 bytes ) x N Start Word ( 3 bytes ) EOM Mark Byte ( note ) (note: EOM mark byte is enabled when the PDEOM of PDCTL register is set as 1 ) * POCSAG Address codeword Format: Bit 1 Bit2 . bit19 Bit20 Bit21 Bit22 . bit31 Bit32 0 A0, A1 . A17 FC0 FC1 CRC Code Parity ( Start word Format ): Total 3 PDDR data byte bit no PDDR ( 1 ) ID0 ID1 ID2 A0 A1 A2 A3 PDDR ( 2 ) A4 A5 A6 A7 A8 A9 A10 A11 PDDR ( 3 ) A12 A13 A14 A15 A16 A17 FC0 FC1 v.0.97 Address ID Code Bits : ( ID0, ID1, and ID2 ) ID2 ID1 ID0 Address ( RIC ) Match 0 0 0 A 0 0 1 B 47 Suites 2202-7, 22/F, Tower 6, The Gateway, 9 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel (852) 2123 3289 Fax (852) 2123 3393 E-mail: sales@jesstech.com HomePage: http://www.jesstech.com 0 1 0 C 0 1 1 D 1 0 0 E 1 0 1 WT5082 WT5082 F ( Message word format: Direct shift mode ) The FCx0/FCxl bit of PDCONFx register defines the message word whether is acted as the "direct shift" format or the "data package" format. While in the direct shift format, i.e., FCx0/FCxl equal to 1, the message word shifts out message codeword data as P-DECODER received and corrected them, and it hasn't any data package. * POCSAG message codeword format bit 1 Bit2 . bit21 Bit22 . bit31 Bit32 1 MA00 . MA19 CRC Parity Message word ( 3 PDDR data bytes ) Bit no PDDR ( 1 ) X Error MA00 MA01 MA02 MA03 PDDR ( 2 ) MA04 MA05 MA06 MA07 MA08 MA09 MA10 MA11 PDDR ( 3 ) MA12 MA13 MA14 MA15 MA16 MA17 MA18 MA19 v.0.97 ( Message word format : Data packaging mode ) Each POCSAG message codeword contain 20 bits message code, the P-DECODER divides each 4 / 7 bits into some message bytes for shift out to microprocessor. User can define different package methods by using different FC code ( FC code is given in POCSAG address codeword ), 48 Suites 2202-7, 22/F, Tower 6, The Gateway, 9 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel (852) 2123 3289 Fax (852) 2123 3393 E-mail: sales@jesstech.com HomePage: http://www.jesstech.com WT5082 WT5082 and each different address also can define different message codeword format. * Message codeword format selection in different address FCA 1 / FCB 1 / FCC 1 FCD 1 / FCE 1 / FCF 1 FCA 0 / FCB 0 / FCC 0 FCD 0 / FCE 0 / FCF 0 0 0 0 1 Data package mode ( Depend on FC ) 4 bits data package method 1 0 7 bits data package method 1 1 Direct shift Mode Data Package mode Note: Please comfirm the FCx0 equal FC0, and FCxl equal FC1 * Message Codeword data packaging method (define in X00 - X07, X38 - X53 ) While FCx0 and FCxl are equal with 0, the different address have different data package format, it depends on table. Address FC1 = 0 FC0 = 0 FC1 = 0 FC0 = 1 FC1 = 1 FC0 = 0 FC1 = 1 FC0 = 1 Data Package Method Address X00 X01 X02 X03 B X04 X05 X06 X07 C X38 X39 X40 X41 D X42 X43 X44 X45 E X46 X47 X48 X49 F X50 X51 X52 X53 4 bits 7 bits v.0.97 Example of Data Packaging Method: 7 bit and 4 bits packaging method * POCSAG message codeword Format 49 Suites 2202-7, 22/F, Tower 6, The Gateway, 9 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel (852) 2123 3289 Fax (852) 2123 3393 E-mail: sales@jesstech.com HomePage: http://www.jesstech.com bit 1 Bit32 CRC Parity CRC Parity MA00 . MA19 MB00 . MB19 1 1 * Bit22 . bit31 Bit2 . bit21 WT5082 WT5082 7 Bits Packaging Method Output Message word 1 ( 2 PDDR data bytes ) Bit no PDDR ( 1 ) MA00 MA01 MA02 MA03 MA04 MA05 MA06 Error PDDR ( 2 ) MA07 MA08 MA09 MA10 MA11 MA12 MA13 Error Message word 2 ( 3 PDDR data bytes ) Bit no PDDR ( 1 ) MA14 MA15 MA16 MA17 MA18 MA19 MB00 Error PDDR ( 2 ) MB01 MB02 MB03 MB04 MB05 MB06 MB07 Error PDDR ( 3 ) MB08 MB09 MB10 MB11 MB12 MB13 MB14 Error v.0.97 * 4 Bits Packaging Method Output Message word 1 ( 5 PDDR data bytes ) 50 Suites 2202-7, 22/F, Tower 6, The Gateway, 9 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel (852) 2123 3289 Fax (852) 2123 3393 E-mail: sales@jesstech.com HomePage: http://www.jesstech.com WT5082 WT5082 Bit no PDDR ( 1 ) MA00 MA01 MA02 MA03 0 0 0 Error PDDR ( 2 ) MA04 MA05 MA06 MA07 0 0 0 Error PDDR ( 3 ) MA08 MA09 MA10 MA11 0 0 0 Error PDDR ( 4 ) MA12 MA13 MA14 MA15 0 0 0 Error PDDR ( 5 ) MA16 MA17 MA18 MA19 0 0 0 Error Message word 2 ( 5 PDDR data bytes ) Bit no PDDR ( 1 ) MB00 MB01 MB02 MB03 0 0 0 Error PDDR ( 2 ) MB04 MB05 MB06 MB07 0 0 0 Error PDDR ( 3 ) MB08 MB09 MB10 MB11 0 0 0 Error PDDR ( 4 ) MB12 MB13 MB14 MB15 0 0 0 Error PDDR ( 5 ) MB16 MB17 MB18 MB19 0 0 0 Error ( EOM mark byte Format ) : Total 1 PDDR data byte EOM7 Bit no EOM6 EOM5 EOM4 EOM3 EOM2 EOM1 EOM0 The EOM ( End of Message ) mark data format is defined at the PDEOM register, and this byte is sent out only when the PDEOM bit of PDCTL register is set as 1. v.0.97 51 Suites 2202-7, 22/F, Tower 6, The Gateway, 9 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel (852) 2123 3289 Fax (852) 2123 3393 E-mail: sales@jesstech.com HomePage: http://www.jesstech.com WT5082 WT5082 v.0.97 52 Suites 2202-7, 22/F, Tower 6, The Gateway, 9 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel (852) 2123 3289 Fax (852) 2123 3393 E-mail: sales@jesstech.com HomePage: http://www.jesstech.com WT5082 WT5082 SECTION 5.4 CONFIGURATION REGISTERS There are total 27 configuration registers of the POCSAG code decoder, and the data bits consist of 6 RIC addresses, 6 address frame, 6 disable address ID flag, 18 address F mask bits, and 33 special function bits. The CPU module uses the memory map method to program this registers, after the PDON bit of the PDCTL register is turned on that P-DECODER depends on these data bits to start operation. ( NOTE ) The P_DECODER c0nfigurati0n registers carl be accessed ONLY when the P_DECODER module is off. (PDON=0 ) Address ID Bits Definition The P-DECODER supply 6 POCSAG RIC addresses and 6 user frames. Each frame number can be independently programmed, that is, six addresses IDs can be in a same frame location or not. User can disable any one of 6 RIC addresses by setting the Disable address ID bits. * Address ID Bits A00 ­ A17 Address A ID Bits B00 ­ B17 Address B ID Bits C00 ­ C17 Address C ID Bits D00 ­ D17 Address D ID Bits E00 ­ E17 Address E ID Bits F00 ­ F17 Address F ID Bits * Frame Number Bits FA0 ­ FA2 Frame number of Address A FB0 ­ FB2 Frame number of Address B FC0 ­ FC2 Frame number of Address C FD0 ­ FD2 Frame number of Address D 53 Suites 2202-7, 22/F, Tower 6, The Gateway, 9 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel (852) 2123 3289 Fax (852) 2123 3393 E-mail: sales@jesstech.com HomePage: http://www.jesstech.com FE0 ­ FE2 Frame number of Address E FF0 ­ FF2 WT5082 WT5082 Frame number of Address F v.0.97 ( Address Definition and POCSAG Code ) * POCSAG Address codeword Format: Bit 1 Bit2 . bit19 Bit20 Bit21 Bit22 . bit31 Bit32 0 AddressCode FC0 FC1 CRC Code Parity * The Relation between POCSAG Address-Code and the EEPROM Address-Code POCSAG Code Bit number 2 3 4 5 6 . 19 PDCONFx address bit name A00 A01 A02 A03 A04 . A17 B00 B01 B02 B03 B04 . B17 C00 C01 C02 C03 C04 . C17 D00 D01 D02 D03 D04 . D17 E00 E01 E02 E03 E04 . E17 F00 F01 F02 F03 F04 . F17 * Frame Number definition FA0 / FB0 / FC0 / FA1 / FB1 / FC1 / FA2 / FB2 / FC2 / FD0 / FE0 / FF0 / 0 FD1 / FE1 / FF1 / 0 FD2 / FE2 / FF2 / 0 Frame Number 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 4 54 0 Suites 2202-7, 22/F, Tower 6, The Gateway, 9 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel (852) 2123 3289 Fax (852) 2123 3393 E-mail: sales@jesstech.com HomePage: http://www.jesstech.com 1 0 1 5 1 1 0 6 1 1 1 WT5082 WT5082 7 v.0.97 Disable Address ID Bits ( DA / DSB / DSC / DSD / DSE / DSF ) User defines the any one of following bit to disable any address ID code. * Disable Address ID Bits 1 DSA DSB DSC DSD DSE DSF 1 1 1 1 1 Disable Address A ID Code 0 Enable Disable Address B ID Code 0 Enable Disable Address C ID Code 0 Enable Disable Address D ID Code 0 Enable Disable Address E ID Code 0 Enable Disable Address F ID Code 0 Enable Address F Mask Bits : Mask Address F RIC Pattern Match (MF0 / MF1 / MF2 / MF3 / MF4 / MF5 / MF6 / MF7 / MF8 / MF9 / MF10 / MF11 / MF12 / MF13 / MF14 / MF15 ) Normal each RIC pattern contains 18 bits, while the P-DECODER can match a sub-set of RIC in address F for a specific application. Mask Bits Address F RIC Code MF0 1 RIC Mask F0 0 RIC Mask F0 MF1 1 RIC Mask F1 0 RIC Mask F1 MF2 1 RIC Mask F2 0 RIC Mask F2 MF3 1 RIC Mask F3 0 RIC Mask F3 55 Suites 2202-7, 22/F, Tower 6, The Gateway, 9 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel (852) 2123 3289 Fax (852) 2123 3393 E-mail: sales@jesstech.com HomePage: http://www.jesstech.com MF4 1 RIC Mask F4 1 RIC Mask F5 / F6 / F7 / F8 / F9 / F10 / F11 / F12 / F13 / F14 / F15 ) 1 RIC Mask F16 MF5 - MF15 MF16 MF17 1 RIC Mask WT5082 WT5082 0 RIC Mask F4 0 RIC Mask F5 / F6 / F7 / F8 / F9 / F10 / F11 / F12 / F13 / F14 / F15 ) 0 RIC Mask F16 F17 0 RIC Mask F17 v.0.97 Output Data Format Function selection ( FCx1 / FCx0 , X00-07 X00-07 and X38-53 X38-53 ) * Message codeword format selection in different address FCA1 / FCB1 / FCC1 FCA0 / FCB0 / FCC0 FCD1 / FCE1 / FCF1 FCD0 / FCE0 / FCF0 0 0 0 1 Data package mode ( Depend on FC ) 4 bits data package method 1 0 7 bits data package method 1 1 Direct shift Mode Data Package mode * Message Codeword data packaging method ( define in X00 ­ X07 , X38 ­ X53 ) While FCx0 and FCx1 are equal with 0, the different address have different address have different data package format, it depends on table Address FC1 = 0 FC0 = 0 FC1 = 0 FC0 = 1 FC1 = 1 FC0 = 0 FC1 = 1 FC0 = 1 Address X00 X01 X02 X03 B X04 X05 X06 X07 C X38 X39 X40 X41 D X42 X43 X44 X45 E X46 X47 X48 X49 F X50 X51 X52 X53 4 bits 7 bits 56 Data Package Method Suites 2202-7, 22/F, Tower 6, The Gateway, 9 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel (852) 2123 3289 Fax (852) 2123 3393 E-mail: sales@jesstech.com HomePage: http://www.jesstech.com WT5082 WT5082 Message Error Flag Type Select ( X08 ) User uses this data bit to force the P-DECODER sends out message codeword data with bit 7 as " BCH can't recover this codeword " or " BCH Algorithm ever correct this codeword ". X08 Bit 7 of Message codeword Data Selection 0 BCH Algorithm can't recover this codeword 1 BCH Algorithm ever correct this codeword v.0.97 Disable Frame Number Match ( X11 ) Turn off the frame number match of RIC address. When the frame number match function is disabled, the P-DECODER always turns on the RF board after it synchronizes with POCSAG. It only matches the RIC addresses and it doesn't care the frame number that defined in the PDCONFx registers. X11 Frame Number Match 0 Normal 1 Disable Frame Number Match Error Correction Mode Selection ( X12 ) The P-DECODER can correct 2 bits random error or 4 bits burst error per codeword, user can select one of these, as application need. X12 Codeword error correction mode selection 0 2 Bit Random Error Correction Mode 1 4 Bit Burst Error Correction Mode RE / RE1 / RE2 active state ( X13 ) X13 Active State 57 Suites 2202-7, 22/F, Tower 6, The Gateway, 9 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel (852) 2123 3289 Fax (852) 2123 3393 E-mail: sales@jesstech.com HomePage: http://www.jesstech.com 0 High 1 WT5082 WT5082 Low Select message codeword error correct method of address ( X14 ) X14 Error Correction Method 0 2 bit random or 4 bits burst mode ( X14 ) 1 1 bit error correct and 2 bits error detection v.0.97 RE1 active width (X15 / X16 ) X15 X16 RE1 active width ( per baud rate ) 0 0 1 Bit 0 1 4 Bit 1 0 RE Preactive Width ­ 1 1 1 Active on every sync. Codeword Cycle Reverse RFDI input ( X 17 ) X17 RF ­ DI data input 0 Normal 1 Reverse Data Input Random error bits accept rate in preamble pattern ( X18 / X19 ) Define how many random bits error can be accepted in preamble pattern recognition within 32 bits. X18 X19 Accept error bits each 32 bits 0 0 4 ( N ormal ) 0 1 6 1 0 8 1 1 5 58 Suites 2202-7, 22/F, Tower 6, The Gateway, 9 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel (852) 2123 3289 Fax (852) 2123 3393 E-mail: sales@jesstech.com HomePage: http://www.jesstech.com WT5082 WT5082 Baud rate selection option bits ( X20 / X21 ) X20 X21 Connected Crystal Baud Rate 0 1 76.8k 512 1 0 76.8k 1200 1 1 76.8k 2400 v.0.97 Message codeword stop receive condition ( X22 ) X22 Stop Message Receive Condition Continue Receive Message, don't care error condition of message codeword or address codeword Stop Receive Message when 2 Continue Message Codeword error or One Address Codeword error 0 1 RE pre-active width ( X23 / X24 / X25 / X26 / X27 ) X23 X24 X25 X26 X27 Pre-active width ( per Baud Rate ) 0 0 0 0 0 1 0 0 0 0 0 1 1 0 3 0 1 1 1 0 0 0 0 . 1 0 1 0 0 0 0 1 29 1 1 1 1 1 0 59 0 . 1 1 5 . 33 35 . 0 1 61 RE2 Preactive width ( X28 / X29 / X30 / X31 / X32 / X33 ) Pre-active time of RE2 output pin 59 Suites 2202-7, 22/F, Tower 6, The Gateway, 9 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel (852) 2123 3289 Fax (852) 2123 3393 E-mail: sales@jesstech.com HomePage: http://www.jesstech.com X28 X29 X30 X31 X32 X33 Bits 0 0 0 0 0 0 don't use 0 0 0 0 0 0 0 0 0 1 . 1 0 0 . 1 0 0 . 1 2 0 4 1 WT5082 WT5082 0 0 0 0 1 1 1 1 1 0 1 1 1 1 1 0 0 1 0 0 1 1 0 0 1 0 0 1 . 1 30 0 32 1 34 1 94 0 96 1 98 1 . 126 . v.0.97 Data Output Form ( X34 ) X34 Data Output Form 0 No operation with PDDR 1 Operation PDDR with follow description When X32 = 1, data package in 4 bits, output data will become Original After transfer " 0" 0x00 0x30 " 1" 0x01 0x31 " 2" 0x02 0x32 " 3" 0x03 0x33 " 4" 0x04 0x34 " 5" 0x05 0x35 " 6" 0x06 0x36 60 Suites 2202-7, 22/F, Tower 6, The Gateway, 9 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel (852) 2123 3289 Fax (852) 2123 3393 E-mail: sales@jesstech.com HomePage: http://www.jesstech.com " 7" 0x07 0x37 " 8" 0x08 0x38 " 9" 0x09 0x39 "A" 0x0A 0x41 "B" 0x0B 0x42 "C" 0x0C 0x43 "D" 0x0D 0x44 "E" 0x0E 0x45 " " 0x0F WT5082 WT5082 0x20 No matter data package is 7 bits or 4 bits , Register PDDR bit 7 equals error flag. v.0.97 SECTION 6. LCD DRIVER The LCD driver module supports 56×33 ( with icon line ), or a maximum of 1848 dots. The bias of the LCD driver is 1/5 and the duty is 1/32 or 1/33. To obtain a good quality of LCD display, an internal charge pump voltage generator is included. LCDCTL ( LCD display control register ) : reset value 0x00 Address bit no 26H / R_W 7 - 6 LCDPM P 5 4 3 2 1 0 LCDC LCDI FRQS3 FRQS2 FRQS1 FRQS0 FRQS2 FRQS1 FRQS0 Output fo ( fXT = 76.8khz ) 0 0 0 0 fXT ( 76.8khz ) 0 0 0 1 fXT / 2 ( 38.4khz ) 0 0 1 0 fXT / 3 ( 25.6khz ) 0 0 1 1 fXT / 4 ( 19.2khz ) 0 1 0 0 fXT / 5 ( 15.36khz ) 0 1 0 1 fXT / 6 ( 12.8khz ) 0 1 1 0 fXT / 7 ( 10.97khz ) 0 1 1 1 fXT / 8 ( 9.6khz ) 1 0 0 0 fXT / 9 ( 8.53khz ) FRQS3 61 Suites 2202-7, 22/F, Tower 6, The Gateway, 9 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel (852) 2123 3289 Fax (852) 2123 3393 E-mail: sales@jesstech.com HomePage: http://www.jesstech.com WT5082 WT5082 1 0 0 1 fXT / 10 ( 7.68khz ) 1 0 1 0 fXT / 11 ( 6.98khz ) 1 0 1 1 fXT / 12 ( 6.4khz ) 1 1 0 0 fXT / 13 ( 5.9khz ) 1 1 0 1 fXT / 14 ( 5.485khz ) 1 1 1 0 fXT / 15 ( 5.12khz ) 1 1 1 1 fXT / 16 ( 4.8khz ) Note : The actual frame frequency to the LCD is fLCD , and equals to fo/4 v.0.97 LCDPMP LCDC LCDI - 0 - Disable LCD display - 1 0 Enable LCD display without icon line - 1 1 Enable LCD display with icon line 0 - - LCD voltage pumping OFF 1 - - LCD voltage pumping ON LCD Display RAM Memory Mapping 62 Function Suites 2202-7, 22/F, Tower 6, The Gateway, 9 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel (852) 2123 3289 Fax (852) 2123 3393 E-mail: sales@jesstech.com HomePage: http://www.jesstech.com WT5082 WT5082 Connecting Configurations of LCD Bias ² Voltage Doubler v.0.97 v.0.97 SECTION 7. Serial I/O Interface SOCTL ( Serial I/O control register ) : reset value 0x00 Address bit no 27H / R_W 7 6 5 4 3 2 1 0 SIOE - - - - - - SCKO When SlOE is set, the P00_RE, P01_RE1, and P27_RE2 will become the SCK, MOSI, and MISO port function. It also enables the 768KO 768KO pin to send 76.8KHz clock. User must use the P21_SS, and P06_RDY pin to recognize whether it is in sending or receiving mode when communicates with flex decoder. When it is ready, set SCKO and a 76.8kHz clock of 32bits will send out. The data in SIOB0-3 will be send synchronized with SCK by MOSI pin. And SIOB0-3 will also receive data from flex decoder at the same time by MISO pin. So wt5082 uses the same address for different register to input and output. When it is finished, it generates a IRQ interrupt to CPU by FSIO in IRQSR, user can mask this interrupt by MSIO in IRQMK. SIOB0 ( Serial I/O sending data Buffer 0 register ) : reset value 0x00 Address bit no 28H / R_W 7 6 5 4 3 2 1 0 SIOB07 SIOB07 SIOB06 SIOB06 SIOB05 SIOB05 SIOB04 SIOB04 SIOB03 SIOB03 SIOB02 SIOB02 SIOB01 SIOB01 SIOB00 SIOB00 SIOB1 ( Serial I/O sending data Buffer 1 register ) : reset value 0x00 Address 29H / R_W 63 Suites 2202-7, 22/F, Tower 6, The Gateway, 9 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel (852) 2123 3289 Fax (852) 2123 3393 E-mail: sales@jesstech.com HomePage: http://www.jesstech.com bit no WT5082 WT5082 7 6 5 4 3 2 1 0 SIOB15 SIOB15 SIOB14 SIOB14 SIOB13 SIOB13 SIOB12 SIOB12 SIOB11 SIOB11 SIOB10 SIOB10 SIOB09 SIOB09 SIOB08 SIOB08 SIOB2 ( Serial I/O sending data Buffer 2 register ) : reset value 0x00 Address bit no 2AH / R_W 7 6 5 4 3 2 1 0 SIOB23 SIOB23 SIOB22 SIOB22 SIOB21 SIOB21 SIOB20 SIOB20 SIOB19 SIOB19 SIOB18 SIOB18 SIOB17 SIOB17 SIOB16 SIOB16 SIOB3 ( Serial I/O sending data Buffer 3 register ) : reset value 0x00 Address bit no 2BH / R_W 7 6 5 4 3 2 1 0 SIOB31 SIOB31 SIOB30 SIOB30 SIOB29 SIOB29 SIOB28 SIOB28 SIOB27 SIOB27 SIOB26 SIOB26 SIOB25 SIOB25 SIOB24 SIOB24 v.0.97 SECTION 8. Expanded ROM This chip has embedded extra-large ROM, and we use virtual memory bank to access expanded ROM. The virtual memory bank is set ROMW in ADRx as high byte and 6502 address [ 12 0 ] as low byte. ROMWinADR0 use in Data Memory 0 from $4000 ~ $5FFF, ROMWinADR1 uses in Data Memory 1 from $6000 ~ $7FFF. For example, when the ROMWinADR0 equal to $06 and 6502 address equal $55AA, it will access expand rom with address $D5AA ROMWinADR0 ( Expand ROM Window0 address register ): reset value 0x00 Address 1EH / R_W 64 Suites 2202-7, 22/F, Tower 6, The Gateway, 9 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel (852) 2123 3289 Fax (852) 2123 3393 E-mail: sales@jesstech.com HomePage: http://www.jesstech.com bit no WT5082 WT5082 7 6 5 4 3 2 1 0 - - - W0A4 W0A3 W0A2 W0A1 W0A0 ROMWinADR1 (Expand ROM Windowl address register): reset value 0x00 Address bit no 1FH / R_W 7 6 5 4 3 2 1 0 - - - W1A4 W1A3 W1A2 W1A1 W1A0 Configuration of ROM 256Kbytes Character ROM 32Kbytes Program ROM v.0.97 65 Suites 2202-7, 22/F, Tower 6, The Gateway, 9 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel (852) 2123 3289 Fax (852) 2123 3393 E-mail: sales@jesstech.com HomePage: http://www.jesstech.com WT5082 WT5082 v.0.97 Section 9. UART To supply communication of PC and wt5082, UART function is supplied. Set EUART to enable UART function active, and P21 will switch as data out and P06 will switch as data in. The baud rate of UART is 9600 baud rate. The UART Data Buffer UARTD is active when EUART is enabled. When ready sending data out with UART, user must set UART_TX to start UART data out. EPI6 is used to interrupt cpu after receiving data and sending data, user can check RX_Full and TX_Empty to verify if Receive Buffer is Full or Transmit Buffer is Empty. UARTCTL (UART control register):reset value 0x00 Address bit no 2CH / R_W 7 6 5 4 3 2 1 0 EUART - RX_Full TX_Empty - - - UART_TX 66 Suites 2202-7, 22/F, Tower 6, The Gateway, 9 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel (852) 2123 3289 Fax (852) 2123 3393 E-mail: sales@jesstech.com HomePage: http://www.jesstech.com WT5082 WT5082 RX_FULL TX_EMPTY Status X 1 TX_Buffer is Empty 1 X RX Buffer is Full UARTD (Serial I/O Buffer and UART Data buffer register): reset value 0x00 Address bit no 28H / R_W 7 SIOB07 SIOB07 / UARTD 7 6 SIOB06 SIOB06 / UARTD 6 5 4 SIOB05 SIOB05 / UARTD5 SIOB04 SIOB04 / UARTD4 3 SIOB03 SIOB03 / UARTD 3 2 SIOB02 SIOB02 / UARTD 2 1 SIOB01 SIOB01 / UARTD 1 0 SIOB00 SIOB00 / UARTD0 UARTD is active only when EUART equals High v.0.97 Section 10. PWM The PWM function is control by PWMCTL register, user can set EPWM to enable PWM function internal clock and function, and switch P07 as PWM signal output, Port 768KO 768KO as output for enable control. And EPI7 is used to end of PWM transmission. PWMCTL (PWM Control register): reset value 0x00 Address bit no 2DH / R_W 7 6 5 4 3 2 1 0 EPWM - PWM_TX ClrPAdr PIndex3 PIndex2 PIndex1 PIndex0 67 Suites 2202-7, 22/F, Tower 6, The Gateway, 9 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel (852) 2123 3289 Fax (852) 2123 3393 E-mail: sales@jesstech.com HomePage: http://www.jesstech.com WT5082 WT5082 User can set EPWM to enable PWM circuit clock, The PWM function output is a 800 baud rate PWM signal. There are 16 bytes register to store pattern. When writing PWMB register once, the internal address of PWMBx will increase automatically. User can set ClrPAdr to reset internal address of PWMBx to initial address and remember initial address is 0x0F. Plndex is descided how many bytes will send out to Port P07. When PIndex equals to 0x04, It will shift data from PB4x to PB0x and LSB first. User can set PWM_TX to start sending PWM signal, and PWM_TX will reset automatically till the end of PWM signal. And Port 768KO 768KO will be preactive to high 3 bits and delay 2 bits to low till end of PWM signal. Before send user program data from PWMBx, wt5082 will send Initial PWM pattern about 4.587ms first. PWM signal timing pattern Initial PWM signal timing pattern v.0.97 PWMB ( PWM Data Buffer register ): reset value 0x00 Address bit no 2EH / R_W 7 6 PWMBx PWMBx7 6 5 PWMBx5 4 3 PWMBx PWMBx4 3 68 2 PWMBx 2 1 PWMBx 1 0 PWMBx0 Suites 2202-7, 22/F, Tower 6, The Gateway, 9 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel (852) 2123 3289 Fax (852) 2123 3393 E-mail: sales@jesstech.com HomePage: http://www.jesstech.com WT5082 WT5082 PAdr3 PAdr2 PAdr1 PAdr0 PWMB7 PWMB6 PWMB5 PWMB4 PWMB3 PWMB2 PWMB1 PWMB0 0 0 0 0 PB07 PB06 PB05 PB04 PB03 PB02 PB01 PB00 0 0 0 PB17 PB16 PB15 PB14 PB13 PB12 PB11 PB10 0 0 PB27 PB26 PB25 PB24 PB23 PB22 PB21 PB20 0 PB37 PB36 PB35 PB34 PB33 PB32 PB31 PB30 0 PB47 PB46 PB45 PB44 PB43 PB42 PB41 PB40 0 PB57 PB56 PB55 PB54 PB53 PB52 PB51 PB50 0 PB67 PB66 PB65 PB64 PB63 PB62 PB61 PB60 0 PB77 PB76 PB75 PB74 PB73 PB72 PB71 PB70 PB87 PB86 PB85 PB84 PB83 PB82 PB81 PB80 PB97 PB96 PB95 PB94 PB93 PB92 PB91 PB90 PBA7 PBA6 PBA5 PBA4 PBA3 PBA2 PBA1 PBA0 PBB7 PBB6 PBB5 PBB4 PBB3 PBB2 PBB1 PBB0 PBC7 PBC6 PBC5 PBC4 PBC3 PBC2 PBC1 PBC0 PBD7 PBD6 PBD5 PBD4 PBD3 PBD2 PBD1 PBD0 PBE7 PBE6 PBE5 PBE4 PBE3 PBE2 PBE1 PBE0 PBF7 PBF6 PBF5 PBF4 PBF3 PBF2 PBF1 PBF0 v.0.97 APPENDIX.A ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS ( VSS = 0 V ) SYMBOL RATING UNIT VDD -0.5 ~ +3.6 V Input Voltage Range Vin -0.5 ~ VDD + 0.5 V Operating Tor 0 ~ +70 PARAMETER DC Supply Voltage 69 Suites 2202-7, 22/F, Tower 6, The Gateway, 9 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel (852) 2123 3289 Fax (852) 2123 3393 E-mail: sales@jesstech.com HomePage: http://www.jesstech.com WT5082 WT5082 Temperature Storage Temperature Tstg -50 ~ +150 ELECTRICAL CHARACTERISTICS ( VSS = 0 V , Topr = 0 to 70 ) Operating Voltage SYMBO L VDD Operating Current IOP Standby Current ISTB OSC Frequency FOSC Input High Level VIH Input Low Level Output Current P0 & P2 Output Current P0 & P2 CPU Clock VIL PARAMETER Min . 2.4 Unit - Max . 3.6 - 60 uA 1MHz @ 3.0V 5 uA MH z V VDD = 3.0V V VDD = 3.0V 1.0 mA VDD = 3.0V , Voh = 2.7V 68 mA VDD = 3.0V , Vol = 0.5V MH z @ 3.0V Typ. 1.0 2.0 2.7 0.3 Ioh Iol 1.0 FCPU 0.0 3 2.0 CONDITIONS V VDD = 3.0V VDD = 3.0V V0.97 APPENDIX.B LCD DISPLAY SRAM MAPPING * LCD Display ( $3F19 ) BYTE-ROW # 1 70 Suites 2202-7, 22/F, Tower 6, The Gateway, 9 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel (852) 2123 3289 Fax (852) 2123 3393 E-mail: sales@jesstech.com HomePage: http://www.jesstech.com WT5082 WT5082 b7 b6 b5 b4 b3 b2 b1 b0 D00 ( $3F19 ) : x0y7 x0y6 x0y5 x0y4 x0y3 x0y2 x0y1 x0y0 D01 ( $3F1A ) : x1y7 x1y6 x1y5 x1y4 x1y3 x1y2 x1y1 x1y0 D02 ( $3F1B ) : x2y7 x2y6 x2y5 x2y4 x2y3 x2y2 x2y1 x2y0 D03 ( $3F1C ) : x3y7 x3y6 x3y5 x3y4 x3y3 x3y2 x3y1 x3y0 D04 ( $3F1D ) : x4y7 x4y6 x4y5 x4y4 x4y3 x4y2 x4y1 x4y0 D05 ( $3F1E ) : x5y7 x5y6 x5y5 x5y4 x5y3 x5y2 x5y1 x5y0 D06 ( $3F1F ) : x6y7 x6y6 x6y5 x6y4 x6y3 x6y2 x6y1 x6y0 D07 ( $3F20 ) : x7y7 x7y6 x7y5 x7y4 x7y3 x7y2 x7y1 x7y0 D08 ( $3F21 ) : x8y7 x8y6 x8y5 x8y4 x8y3 x8y2 x8y1 x8y0 D09 ( $3F22 ) : x9y7 x9y6 x9y5 x9y4 x9y3 x9y2 x9y1 x9y0 D0A ( $3F23 ) : x10y7 x10y6 x10y5 x10y4 x10y3 x10y2 x10y1 x10y0 D0B ( $3F24 ) : x11y7 x11y6 x11y5 x11y4 x11y3 x11y2 x11y1 x11y0 D0C ( $3F25 ) : x12y7 x12y6 x12y5 x12y4 x12y3 x12y2 x12y1 x12y0 D0D ( $3F26 ) : x13y7 x13y6 x13y5 x13y4 x13y3 x13y2 x13y1 x13y0 D0E ( $3F27 ) : x14y7 x14y6 x14y5 x14y4 x14y3 x14y2 x14y1 x14y0 D0F ( $3F28 ) : x15y7 x15y6 x15y5 x15y4 x15y3 x15y2 x15y1 x15y0 D10 ( $3F29 ) : x16y7 x16y6 x16y5 x16y4 x16y3 x16y2 x16y1 x16y0 D11 ( $3F2A ) : x17y7 x17y6 x17y5 x17y4 x17y3 x17y2 x17y1 x17y0 D12 ( $3F2B ) : x18y7 x18y6 x18y5 x18y4 x18y3 x18y2 x18y1 x18y0 D13 ( $3F2C ) : x19y7 x19y6 x19y5 x19y4 x19y3 x19y2 x19y1 x19y0 D14 ( $3F2D ) : x20y7 x20y6 x20y5 x20y4 x20y3 x20y2 x20y1 x20y0 D15 ( $3F2E ) : x21y7 x21y6 x21y5 x21y4 x21y3 x21y2 x21y1 x21y0 D16 ( $3F2F ) : x22y7 x22y6 x22y5 x22y4 x22y3 x22y2 x22y1 x22y0 D17 ( $3F30 ) : x23y7 x23y6 x23y5 x23y4 x23y3 x23y2 x23y1 x23y0 D18 ( $3F31 ) : x24y7 x24y6 x24y5 x24y4 x24y3 x24y2 x24y1 x24y0 D19 ( $3F32 ) : x25y7 x25y6 x25y5 x25y4 x25y3 x25y2 x25y1 x25y0 D1A ( $3F33 ) : x26y7 x26y6 x26y5 x26y4 x26y3 x26y2 x26y1 x26y0 D1B ( $3F34 ) : x27y7 x27y6 x27y5 x27y4 x27y3 x27y2 x27y1 x27y0 D1C ( $3F35 ) : x28y7 x28y6 x28y5 x28y4 x28y3 x28y2 x28y1 x28y0 D1D ( $3F36 ) : x29y7 x29y6 x29y5 x29y4 x29y3 x29y2 x29y1 x29y0 D1E ( $3F37 ) : x30y7 x30y6 x30y5 x30y4 x30y3 x30y2 x30y1 x30y0 D1F ( $3F38 ) : x31y7 x31y6 x31y5 x31y4 x31y3 x31y2 x31y1 x31y0 V0.97 71 Suites 2202-7, 22/F, Tower 6, The Gateway, 9 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel (852) 2123 3289 Fax (852) 2123 3393 E-mail: sales@jesstech.com HomePage: http://www.jesstech.com WT5082 WT5082 D20 ( $3F39 ) : x32y7 x32y6 x32y5 x32y4 x32y3 x32y2 x32y1 x32y0 D21 ( $3F3A ) : x33y7 x33y6 x33y5 x33y4 x33y3 x33y2 x33y1 x33y0 D22 ( $3F3B ) : x34y7 x34y6 x34y5 x34y4 x34y3 x34y2 x34y1 x34y0 D23 ( $3F3C ) : x35y7 x35y6 x35y5 x35y4 x35y3 x35y2 x35y1 x35y0 D24 ( $3F3D ) : x36y7 x36y6 x36y5 x36y4 x36y3 x36y2 x36y1 x36y0 D25 ( $3F3E ) : x37y7 x37y6 x37y5 x37y4 x37y3 x37y2 x37y1 x37y0 D26 ( $3F3F ) : x38y7 x38y6 x38y5 x38y4 x38y3 x38y2 x38y1 x38y0 D27 ( $3F40 ) : x39y7 x39y6 x39y5 x39y4 x39y3 x39y2 x39y1 x39y0 D28 ( $3F41 ) : x40y7 x40y6 x40y5 x40y4 x40y3 x40y2 x40y1 x40y0 D29 ( $3F42 ) : x41y7 x41y6 x41y5 x41y4 x41y3 x41y2 x41y1 x41y0 D2A ( $3F43 ) : x42y7 x42y6 x42y5 x42y4 x42y3 x42y2 x42y1 x42y0 D2B ( $3F44 ) : x43y7 x43y6 x43y5 x43y4 x43y3 x43y2 x43y1 x43y0 D2C ( $3F45 ) : x44y7 x44y6 x44y5 x44y4 x44y3 x44y2 x44y1 x44y0 D2D ( $3F46 ) : x45y7 x45y6 x45y5 x45y4 x45y3 x45y2 x45y1 x45y0 D2E ( $3F47 ) : x46y7 x46y6 x46y5 x46y4 x46y3 x46y2 x46y1 x46y0 D2F ( $3F48 ) : x47y7 x47y6 x47y5 x47y4 x47y3 x47y2 x47y1 x47y0 D30 ( $3F49 ) : x48y7 x48y6 x48y5 x48y4 x48y3 x48y2 x48y1 x48y0 D31 ( $3F4A ) : x49y7 x49y6 x49y5 x49y4 x49y3 x49y2 x49y1 x49y0 D32 ( $3F4B ) : x50y7 x50y6 x50y5 x50y4 x50y3 x50y2 x50y1 x50y0 D33 ( $3F4C ) : x51y7 x51y6 x51y5 x51y4 x51y3 x51y2 x51y1 x51y0 D34 ( $3F4D ) : x52y7 x52y6 x52y5 x52y4 x52y3 x52y2 x52y1 x52y0 D35 ( $3F4E ) : x53y7 x53y6 x53y5 x53y4 x53y3 x53y2 x53y1 x53y0 D36 ( $3F4F ) : x54y7 x54y6 x54y5 x54y4 x54y3 x54y2 x54y1 x54y0 D37 ( $3F50 ) : x55y7 x55y6 x55y5 x55y4 x55y3 x55y2 x55y1 x55y0 V0.97 72 Suites 2202-7, 22/F, Tower 6, The Gateway, 9 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel (852) 2123 3289 Fax (852) 2123 3393 E-mail: sales@jesstech.com HomePage: http://www.jesstech.com WT5082 WT5082 BYTE-ROW # 2 b7 b6 b5 b4 b3 b2 b1 b0 D38 ( $3F51 ) : x0y15 x0y14 x0y13 x0y12 x0y11 x0y10 x0y9 x0y8 D39 ( $3F52 ) : x1y15 x1y14 x1y13 x1y12 x1y11 x1y10 x1y9 x1y8 D3A ( $3F53 ) : x2y15 x2y14 x2y13 x2y12 x2y11 x2y10 x2y9 x2y8 D3B ( $3F54 ) : x3y15 x3y14 x3y13 x3y12 x3y11 x3y10 x3y9 x3y8 D3C ( $3F55 ) : x4y15 x4y14 x4y13 x4y12 x4y11 x4y10 x4y9 x4y8 D3D ( $3F56 ) : x5y15 x5y14 x5y13 x5y12 x5y11 x5y10 x5y9 x5y8 D3E ( $3F57 ) : x6y15 x6y14 x6y13 x6y12 x6y11 x6y10 x6y9 x6y8 D3F ( $3F58 ) : x7y15 x7y14 x7y13 x7y12 x7y11 x7y10 x7y9 x7y8 D40 ( $3F59 ) : x8y15 x8y14 x8y13 x8y12 x8y11 x8y10 x8y9 x8y8 D41 ( $3F5A ) : x9y15 x9y14 x9y13 x9y12 x9y11 x9y10 x9y9 x9y8 D42 ( $3F5B ) : x10y15 x10y14 x10y13 x10y12 x10y11 x10y10 x10y9 x10y8 D43 ( $3F5C ) : x11y15 x11y14 x11y13 x11y12 x11y11 x11y10 x11y9 x11y8 D44 ( $3F5D ) : x12y15 x12y14 x12y13 x12y12 x12y11 x12y10 x12y9 x12y8 D45 ( $3F5E ) : x13y15 x13y14 x13y13 x13y12 x13y11 x13y10 x13y9 x13y8 D46 ( $3F5F ) : x14y15 x14y14 x14y13 x14y12 x14y11 x14y10 x14y9 x14y8 D47 ( $3F60 ) : x15y15 x15y14 x15y13 x15y12 x15y11 x15y10 x15y9 x15y8 D48 ( $3F61 ) : x16y15 x16y14 x16y13 x16y12 x16y11 x16y10 x16y9 x16y8 D49 ( $3F62 ) : x17y15 x17y14 x17y13 x17y12 x17y11 x17y10 x17y9 x17y8 D4A ( $3F63 ) : x18y15 x18y14 x18y13 x18y12 x18y11 x18y10 x18y9 x18y8 D4B ( $3F64 ) : x19y15 x19y14 x19y13 x19y12 x19y11 x19y10 x19y9 x19y8 D4C ( $3F65 ) : x20y15 x20y14 x20y13 x20y12 x20y11 x20y10 x20y9 x20y8 D4D ( $3F66 ) : x21y15 x21y14 x21y13 x21y12 x21y11 x21y10 x21y9 x21y8 D4E ( $3F67 ) : x22y15 x22y14 x22y13 x22y12 x22y11 x22y10 x22y9 x22y8 D4F ( $3F68 ) : x23y15 x23y14 x23y13 x23y12 x23y11 x23y10 x23y9 x23y8 V0.97 73 Suites 2202-7, 22/F, Tower 6, The Gateway, 9 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel (852) 2123 3289 Fax (852) 2123 3393 E-mail: sales@jesstech.com HomePage: http://www.jesstech.com WT5082 WT5082 D57 ( $3F70 ) : x31y15 x31y14 x31y13 x31y12 x31y11 x31y10 x31y9 x31y8 D58 ( $3F71 ) : x32y15 x32y14 x32y13 x32y12 x32y11 x32y10 x32y9 x32y8 D59 ( $3F72 ) : x33y15 x33y14 x33y13 x33y12 x33y11 x33y10 x33y9 x33y8 D5A ( $3F73 ) : x34y15 x34y14 x34y13 x34y12 x34y11 x34y10 x34y9 x34y8 D5B ( $3F74 ) : x35y15 x35y14 x35y13 x35y12 x35y11 x35y10 x35y9 x35y8 D5C ( $3F75 ) : x36y15 x36y14 x36y13 x36y12 x36y11 x36y10 x36y9 x36y8 D5D ( $3F76 ) : x37y15 x37y14 x37y13 x37y12 x37y11 x37y10 x37y9 x37y8 D5E ( $3F77 ) : x38y15 x38y14 x38y13 x38y12 x38y11 x38y10 x38y9 x38y8 D5F ( $3F78 ) : x39y15 x39y14 x39y13 x39y12 x39y11 x39y10 x39y9 x39y8 D60 ( $3F79 ) : x40y15 x40y14 x40y13 x40y12 x40y11 x40y10 x40y9 x40y8 D61 ( $3F7A ) : x41y15 x41y14 x41y13 x41y12 x41y11 x41y10 x41y9 x41y8 D62 ( $3F7B ) : x42y15 x42y14 x42y13 x42y12 x42y11 x42y10 x42y9 x42y8 D63 ( $3F7C ) : x43y15 x43y14 x43y13 x43y12 x43y11 x43y10 x43y9 x43y8 D64 ( $3F7D ) : x44y15 x44y14 x44y13 x44y12 x44y11 x44y10 x44y9 x44y8 D65 ( $3F7E ) : x45y15 x45y14 x45y13 x45y12 x45y11 x45y10 x45y9 x45y8 D66 ( $3F7F ) : x46y15 x46y14 x46y13 x46y12 x46y11 x46y10 x46y9 x46y8 D67 ( $3F80 ) : x47y15 x47y14 x47y13 x47y12 x47y11 x47y10 x47y9 x47y8 D68 ( $3F81 ) : x48y15 x48y14 x48y13 x48y12 x48y11 x48y10 x48y9 x48y8 D69 ( $3F82 ) : x49y15 x49y14 x49y13 x49y12 x49y11 x49y10 x49y9 x49y8 D6A ( $3F83 ) : x50y15 x50y14 x50y13 x50y12 x50y11 x50y10 x50y9 x50y8 D6B ( $3F84 ) : x51y15 x51y14 x51y13 x51y12 x51y11 x51y10 x51y9 x51y8 D6C ( $3F85 ) : x52y15 x52y14 x52y13 x52y12 x52y11 x52y10 x52y9 x52y8 D6D ( $3F86 ) : x53y15 x53y14 x53y13 x53y12 x53y11 x53y10 x53y9 x53y8 D6E ( $3F87 ) : x54y15 x54y14 x54y13 x54y12 x54y11 x54y10 x54y9 x54y8 D6F ( $3F88 ) : x55y15 x55y14 x55y13 x55y12 x55y11 x55y10 x55y9 x55y8 V0.97 74 Suites 2202-7, 22/F, Tower 6, The Gateway, 9 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel (852) 2123 3289 Fax (852) 2123 3393 E-mail: sales@jesstech.com HomePage: http://www.jesstech.com WT5082 WT5082 BYTE-ROW # 3 D70 ( $3F89 ) : x0y23 x0y22 x0y21 x0y20 x0y19 x0y18 x0y17 x0y16 D71 ( $3F8A ) : x1y23 x1y22 x1y21 x1y20 x1y19 x1y18 x1y17 x1y16 D72 ( $3F8B ) : x2y23 x2y22 x2y21 x2y20 x2y19 x2y18 x2y17 x2y16 D73 ( $3F8C ) : x3y23 x3y22 x3y21 x3y20 x3y19 x3y18 x3y17 x3y16 D74 ( $3F8D ) : x4y23 x4y22 x4y21 x4y20 x4y19 x4y18 x4y17 x4y16 D75 ( $3F8E ) : x5y23 x5y22 x5y21 x5y20 x5y19 x5y18 x5y17 x5y16 D76 ( $3F8F ) : x6y23 x6y22 x6y21 x6y20 x6y19 x6y18 x6y17 x6y16 D77 ( $3F90 ) : x7y23 x7y22 x7y21 x7y20 x7y19 x7y18 x7y17 x7y16 D78 ( $3F91 ) : x8y23 x8y22 x8y21 x8y20 x8y19 x8y18 x8y17 x8y16 D79 ( $3F92 ) : x9y23 x9y22 x9y21 x9y20 x9y19 x9y18 x9y17 x9y16 D7A ( $3F93 ) : x10y23 x10y22 x10y21 x10y20 x10y19 x10y18 x10y17 x10y16 D7B ( $3F94 ) : x11y23 x11y22 x11y21 x11y20 x11y19 x11y18 x11y17 x11y16 D7C ( $3F95 ) : x12y23 x12y22 x12y21 x12y20 x12y19 x12y18 x12y17 x12y16 D7D ( $3F96 ) : x13y23 x13y22 x13y21 x13y20 x13y19 x13y18 x13y17 x13y16 D7E ( $3F97 ) : x14y23 x14y22 x14y21 x14y20 x14y19 x14y18 x14y17 x14y16 D7F ( $3F98 ) : x15y23 x15y22 x15y21 x15y20 x15y19 x15y18 x15y17 x15y16 D80 ( $3F99 ) : x16y23 x16y22 x16y21 x16y20 x16y19 x16y18 x16y17 x16y16 D81 ( $3F9A ) : x17y23 x17y22 x17y21 x17y20 x17y19 x17y18 x17y17 x17y16 D82 ( $3F9B ) : x18y23 x18y22 x18y21 x18y20 x18y19 x18y18 x18y17 x18y16 D83 ( $3F9C ) : x19y23 x19y22 x19y21 x19y20 x19y19 x19y18 x19y17 x19y16 D84 ( $3F9D ) : x20y23 x20y22 x20y21 x20y20 x20y19 x20y18 x20y17