WS7106 WS7107 WS7106CPL WS7107CPL WS7106/WS710 WS7106TEST WS7107GND 45/RC - Datasheet Archive

 

Converters WS7106 / WS7107 Features Description · Guaranteed Zero Reading for 0V Input on All Scales · True

 

3 1/2Digit LCD/LED Display A/D Converters WS7106 WS7106 / WS7107 WS7107 Features Description · Guaranteed Zero Reading for 0V Input on All Scales · True Polarity at Zero for Precise Null Detection · True Differential Input and Reference, Direct Display Drive - LCD WS7106 WS7106, LED WS7107 WS7107 · On Chip Clock and Reference · Low Noise - Less Than 15µVP-P · No Additional Active Circuits Required · Low Power Dissipation - Typically Less Than 10mW Ordering Information PART NO. TEMP. RANGE (oC) PACKAGE The WS7106 WS7106 and WS7107 WS7107 are high performance, low power, 31/2 digit A/D converters. Included are seven segment decoders, display drivers, a reference, and a clock. The WS7106 WS7106 is designed to interface with a liquid crystal display (LCD) and includes a multiplexed backplane drive; the WS 7107 will directly drive an instrument size light emitting diode (LED) display. The WS7106 WS7106 and WS 7107 bring together a combination of high accuracy, versatility, and true economy.True differential inputs and reference are useful in all systems, but give the desiger an uncommon advantage when measuring load cells, strain gauges and other bridge type transducers. Finally, the true economy of single power supply operation (WS7106 WS7106), enables a high performance panel meter to built with the addition of only 10 passive compoents and a disply. PKG. NO. WS7106CPL WS7106CPL 0 to 70 40Ld PDIP E40.6 WS7107CPL WS7107CPL 0 to70 40Ld PDIP E40.6 Pinouts WS7106CPL WS7106CPL (PDIP) WS7107CPL WS7107CPL (PDIP) V+ 1 40 OSC 1 D1 2 39 OSC 2 C1 3 38 OSC 3 B1 4 37 TEST A1 5 36 REF HI F1 6 35 REF LO G1 7 34 CREF+ E1 8 33 CREF- D2 9 32 COMMON C2 10 31 IN HI B2 11 30 IN LO A2 12 29 A-Z F2 13 28 BUFF E2 14 27 INT D3 15 26 V- B3 16 25 G2 (10' s) F3 17 24 C3 E3 18 23 A3 (1000) AB4 19 22 G3 POL 20 21 BP/GND (1' s) (10' s) (100' s) (MINUS) Wing Shing Computer Components Co., (H.K.)Ltd. Homepage: http://www.wingshing.com Tel:(852)2341 9276 Fax:(852)2797 8153 E-mail: wsccltd@hkstar.com (100' s) WS7106/WS710 WS7106/WS710 7 Absolute Maximum Ratings Thermal Information Supply Voltage Thermal Resistance (typical, Note 2) WS7106 WS7106, V+ to V-.15v WS7107 WS7107, V+ to GND.6V WS7107 WS7107, V_ to GND. .-9V Analog Input Voltage (Either Input) (Note 1)V+ to VReference Input Voltage (Either Input)V+ to VClock Input WS7106TEST WS7106TEST to V+ WS7107GND WS7107GND to V+ JA(/W) PDIP Package. . . 50 Maximum Junction Temperature. .150 Maximum Storage Temperature Range.-65 to 150 Operating Conditions Temperature Range.0 to 70 CAUTION: Stresses above those listed in "absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation Of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Notes: 1. Input voltages may exceed the supply voltages provided the input current is limited to ±100µA 2. JA Is measured with the component mounted on an evaluation PC on board in fee air. Electrical specifications (Note 3) TEST CONDITIONS PARAMETER MIN TYP MAX UNIT -000.0 ±000.0 +000.0 Digital Reading 999 999/1000 1000 Digital Reading SYSTEM PERFORMACE Zero Input Reading VIN=0.0V, FULL Scale = 200mV Ratiometric Reading VIN = VREF, VREF = 100mV Rollover Error -VIN=+VIN=200mV Difference in Reading for Equal Positive and Negative Inputs Near Full Scale -1 0.2 +1 Counts Linearity Full Scale = 200mV or Full Scale = 2V Maximum Deviation from Best Straight Line Fit (note 6) -1 0.2 +1 Counts Common Mode Rejection Ratio VCM = 1V, VIN = 0V, Full Scale = 200mv(Note 6) - 50 - V/V End Power Supply Character V+ Supply Current VIN = 0 (Does Not Include LED Current for WS7107 WS7107 - 0.5 1.8 mA End Power Supply Character V- Supply Current WS7107 WS7107 Only - 0.5 1.8 mA COMMON Pin Analog Common Voltage 25k Between Common and Positive Supply (With Respect to + Supply) 2.4 3.0 3.2 V Noise (PK-PK Value not exceeded 95% of time) VIN=0V Full Scale=200mV 15 Input Leakage Current VIN=0V 1 10 pA Analog COMMON Temperature Coefficient 25K between Common and V+ 0-70 60 75 ppm/ Scale Factor Temperature Coefficient VIN=199mV 0-70Ext. ref. 0ppm/ 60 75 ppm/ Zero Reading Drift VIN=0V-70 0.2 1 uV/ 5 6 V uVP-P DISPLAY DRIVER WS7106 WS7106 ONLY Peak-to-Peak Segment Drive Voltage Peak-to-Peak Backplane Drive Voltage V+ = to V- = 9V (Note 5) 2 4 WS7106 WS7106 / WS7107 WS7107 Electrical Specifications (Continued) (Note 1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT (Except Pins 19 and 20) 5 8 - mA Pin 19 Only 10 16 - mA Pin 20 Only 4 7 - mA DISPLAY DRIVER WS7107 WS7107 ONLY Segment Sinking Current V+ = 5V, Segment Voltage = 3V NOTES: 1. Dissipation rating assumes device is mounted with all leads soldered to printed circuit board. 3. 2. Back plane drive is in phase with segment drive for 'off' segment, 180 degrees out of phase for 'on' segment. Frequency is 20 times conversion rate. Average DC component is less than 50mV 3. Not tested, Quaranteed by design. Typical Applications and Test Circuits A3 23 G3 22 BP 21 19 AB4 20 POL C3 24 18 E3 17 F3 V- 26 G2 25 16 B3 INT 27 DISPLAY 15 D3 14 E2 A-Z 29 BUFF 28 C3 13 F2 IN HI 31 C2 R2 IN LO 30 COM 32 CREF- 33 CREF+ 34 REF LO 35 TEST 37 C5 C1 R4 REF HI 36 OSC 3 38 OSC 2 39 OSC 1 40 C4 9V R5 R1 R3 + IN - + 12 A2 11 B2 D2 9 10 C2 E1 8 5 F1 A1 4 G1 B1 3 7 C1 2 6 V+ D1 1 WS7106 WS7106 C1 = 0.1µF C2 = 0.47µF C3 = 0.22µF C4 = 100pF C5 = 0.02µF R1 = 24k R2 = 47k R3 = 100k R4 = 1k R5 = 1M DISPLAY FIGURE 1. WS 7106 TEST CIRCUIT AND TYPICAL APPLICATION WITH LCD DISPLAY COMPONENTS SELECTED FOR 200mV FULL SCALE + +5V IN INT 27 V- 26 G2 25 C3 24 A3 23 G3 22 GND 21 14 E2 15 D3 16 B3 17 F3 18 E3 19 AB4 20 POL DISPLAY BUFF 28 A-Z 29 C3 13 F2 IN HI 31 COM 32 CREF- 33 CREF+ 34 REF LO 35 C2 R2 IN LO 30 C5 C1 R4 REF HI 36 TEST 37 OSC 3 38 OSC 2 39 OSC 1 40 C4 -5V R5 R1 R3 - 12 A2 11 B2 D2 9 10 C2 E1 8 A1 5 F1 B1 4 G1 C1 3 7 D1 2 6 V+ 1 WS7107 WS7107 C1 = 0.1µF C2 = 0.47µF C3 = 0.22µF C4 = 100pF C5 = 0.02µF R1 = 24k R2 = 47k R3 = 100k R4 = 1k R5 = 1M DISPLAY FIGURE 2. WS 7107 TEST CIRCUIT AND TYPICAL APPLICATION WITH LED DISPLAY COMPONENTS SELECTED FOR 200mV FULL SCALE 3 WS7106 WS7106 / WS7107 WS7107 Design Information Summary Sheet · OSCILLATOR FREQUENCY · DISPLAY COUNT V IN COUNT = 1000 × -V REF fOSC = 0.45/RC 45/RC COSC > 50pF; ROSC > 50k fOSC (Typ) = 48kHz · CONVERSION CYCLE · OSCILLATOR PERIOD tCYC = tCL0CK x 4000 tCYC = tOSC x 16,000 when fOSC = 48kHz; tCYC = 333ms tOSC = RC/0.45 · INTEGRATION CLOCK FREQUENCY · COMMON MODE INPUT VOLTAGE fCLOCK = fOSC/4 (V- + 1V) < VlN < (V+ - 0.5V) · INTEGRATION PERIOD · AUTO-ZERO CAPACITOR tINT = 1000 x (4/fOSC) 0.01µF < CAZ < 1µF · 60/50Hz REJECTION CRITERION · REFERENCE CAPACITOR tINT/t60Hz or tlNT/t60Hz = Integer 0.1µF < CREF < 1µF · OPTIMUM INTEGRATION CURRENT · VCOM Biased between Vi and V-. IINT = 4µA · VCOM V+ - 2.8V · FULL SCALE ANALOG INPUT VOLTAGE Regulation lost when V+ to V- < 6.8V If VCOM is externally pulled down to (V+ to V-)/2, the VCOM circuit will turn off. VlNFS (Typ) = 200mV or 2V · INTEGRATE RESISTOR V INFS R INT = -I INT WS 7106 POWER SUPPLY: SINGLE 9V V+ - V- = 9V Digital supply is generated internally VGND V+ - 4.5V · INTEGRATE CAPACITOR ( t INT ) ( I INT ) C INT = -V INT · WS7106 WS7106 DISPLAY: LCD Type: Direct drive with digital logic supply amplitude. · INTEGRATOR OUTPUT VOLTAGE SWING _ · WS7107 WS7107 POWER SUPPLY: DUAL +5.0V ( t INT ) ( I INT ) V INT = -C INT V+ = +5V to GND V- = -5V to GND Digital Logic and LED driver supply V+ to GND · VINT MAXIMUM SWING: · WS7107 WS7107 DISPLAY: LED Type: Non-Multiplexed Common Anode (V- + 0.5V) < VINT < (V+ - 0.5V), VINT (Typ) = 2V Typical Integrator Amplifier Output Waveform (INT Pin) AUTO ZERO PHASE (COUNTS) 2999 - 1000 SIGNAL INTEGRATE PHASE FIXED 1000 COUNTS DE-INTEGRATE PHASE 0 - 1999 COUNTS TOTAL CONVERSION TIME = 4000 x tCLOCK = 16,000 x tOSC 4 WS7106 WS7106 / WS7107 WS7107 Detailed Description the end of this phase, the polarity of the integrated signal is determined. Analog Section De-Integrate Phase Figure 3 shows the Analog Section for the WS7106 WS7106 and WS7107 WS7107. Each measurement cycle is divided into three phases. They are (1) auto-zero (A-Z), (2) signal integrate (INT) and (3) de-integrate (DE). Auto-Zer o Phase During auto-zero three things happen. First, input high and low are disconnected from the pins and internally shorted to analog COMMON. Second, the reference capacitor is charged to the reference voltage. Third, a feedback loop is closed around the system to charge the auto-zero capacitor CAZ to compensate for offset voltages in the buffer amplifier, integrator, and comparator. Since the comparator is included in the loop, the A-Z accuracy is limited only by the noise of the system. In any case, the offset referred to the input is less than 10µV. Signal Integrate Phase During signal integrate, the auto-zero loop is opened, the internal short is removed, and the internal input high and low are connected to the external pins. The converter then integrates the differential voltage between IN HI and IN LO for a fixed time. This differential voltage can be within a wide common mode range: up to 1V from either supply. If, on the other hand, the input signal has no return with respect to the converter power supply, IN LO can be tied to analog COMMON to establish the correct common mode voltage. At STRAY The final phase is de-integrate, or reference integrate. Input low is internally connected to analog COMMON and input high is connected across the previously charged reference capacitor. Circuitry within the chip ensures that the capacitor will be connected with the correct polarity to cause the integrator output to return to zero. The time required for the output to return to zero is proportional to the input signal. Specifically the digital reading displayed is: V IN DISPLAY COUNT = 1000 - . V REF Differential Input The input can accept differential voltages anywhere within the common mode range of the input amplifier, or specifically from 0.5V below the positive supply to 1V above the negative supply. In this range, the system has a CMRR of 86dB typical. However, care must be exercised to assure the integrator output does not saturate. A worst case condition would be a large positive common mode voltage with a near full scale negative differential input voltage. The negative input signal drives the integrator positive when most of its swing has been used up by the positive common mode voltage. For these critical applications the integrator output swing can be reduced to less than the recommended 2V full scale swing with little loss of accuracy. The integrator output can swing to within 0.3V of either supply without loss of linearity. STRAY CREF RINT CREF+ REF HI 34 36 V+ REF LO 35 A-Z CREF 33 A-Z CAZ BUFFER V+ 28 1 CINT A-Z INT 29 27 INTEGRATOR - + 10µA - + - + 2.8V 31 IN HI INT DE- DE+ 6.2V INPUT HIGH A-Z A-Z DE+ 32 COMPARATOR - N + DE- COMMON INT 30 INPUT LOW A-Z AND DE(±) IN LO V- FIGURE 3. ANALOG SECTION OF WS7106 WS7106 AND WS7107 WS7107 5 TO DIGITAL SECTION WS7106 WS7106 / WS7107 WS7107 Differential Reference The reference voltage can be generated anywhere within the power supply voltage of the converter. The main source of common mode error is a roll-over voltage caused by the reference capacitor losing or gaining charge to stray capacity on its nodes. If there is a large common mode voltage, the reference capacitor can gain charge (increase voltage) when called up to de-integrate a positive signal but lose charge (decrease voltage) when called up to de-integrate a negative input signal. This difference in reference for positive or negative input voltage will give a roll-over error. However, by selecting the reference capacitor such that it is large enough in comparison to the stray capacitance, this error can be held to less than 0.5 count worst case. (See Component Value Selection.) should be since this removes the common mode voltage from the reference system. Within the lC, analog COMMON is tied to an N-Channel FET that can sink approximately 30mA of current to hold the voltage 2.8V below the positive supply (when a load is trying to pull the common line positive). However, there is only 10µA of source current, so COMMON may easily be tied to a more negative voltage thus overriding the internal reference. V+ V REF HI 6.8V ZENER REF LO Analog COMMON The limitations of the on chip reference should also be recognized, however. With the WS7107 WS7107, the internal heating which results from the LED drivers can cause some degradation in performance. Due to their higher thermal resistance, plastic parts are poorer in this respect than ceramic. The combination of reference Temperature Coefficient (TC), internal chip dissipation, and package thermal resistance can increase noise near full scale from 25µV to 80µVP-P. Also the linearity in going from a high dissipation count such as 1000 (20 segments on) to a low dissipation count such as 1111(8 segments on) can suffer by a count or more. Devices with a positive TC reference may require several counts to pull out of an over-range condition. This is because over-range is a low dissipation mode, with the three least significant digits blanked. Similarly, units with a negative TC may cycle between over-range and a non-over-range count as the die alternately heats and cools. All these problems are of course eliminated if an external reference is used. The WS 7106, with its negligible dissipation, suffers from none of these problems. In either case, an external reference can easily be added, as shown in Figure 4. Analog COMMON is also used as the input low return during auto-zero and de-integrate. If IN LO is different from analog COMMON, a common mode voltage exists in the system and is taken care of by the excellent CMRR of the converter. However, in some applications IN LO will be set at a fixed known voltage (power supply common for instance). In this application, analog COMMON should be tied to the same point, thus removing the common mode voltage from the converter. The same holds true for the reference voltage. If reference can be conveniently tied to analog COMMON, it 6 IZ WS7106 WS7106 WS7107 WS7107 This pin is included primarily to set the common mode voltage for battery operation (WS7106 WS7106) or for any system where the input signals are floating with respect to the power supply. The COMMON pin sets a voltage that is approximately 2.8V more negative than the positive supply. This is selected to give a minimum end-of-life battery voltage of about 6V. However, analog COMMON has some of the attributes of a reference voltage. When the total supply voltage is large enough to cause the zener to regulate (>7V), the COMMON voltage will have a low voltage coefficient (0.001%/V), low output impedance (15), and a temperature coefficient typically less than 80ppm/oC. V- FIGURE 4A. V+ V 6.8k 20k WS7106 WS7106 WS7107 WS7107 ICL8069 ICL8069 1.2V REFERENCE REF HI REF LO COMMON FIGURE 4B. FIGURE 4. USING AN EXTERNAL REFERENCE TEST The TEST pin serves two functions. On the WS7106 WS7106 it is coupled to the internally generated digital supply through a 500 resistor. Thus it can be used as the negative supply for externally generated segment drivers such as decimal points or any other presentation the user may want to include on the LCD display. Figures 5 and 6 show such an application. No more than a 1mA load should be applied. V+ 1M TO LCD DECIMAL POINT WS7106 WS7106 BP TEST 21 37 TO LCD BACKPLANE FIGURE 5. SIMPLE INVERTER FOR FIXED DECIMAL POINT WS7106 WS7106 / WS7107 WS7107 Digital Section The second function is a "lamp test". When TEST is pulled high (to V+) all segments will be turned on and the display should read "1888". The TEST pin will sink about 15mA under these conditions. Figures 7 and 8 show the digital section for the WS7106 WS7106 and WS7107 WS7107, respectively. In the WS7106 WS7106 , an internal digital ground is generated from a 6V Zener diode and a large P-Channel source follower. This supply is made stiff to absorb the relative large capacitive currents when the back plane (BP) voltage is switched. The BP frequency is the clock frequency divided by 800. For three readings/sec., this is a 60Hz square wave with a nominal amplitude of 5V. The segments are driven at the same frequency and amplitude and are in phase with BP when OFF, but out of phase when ON. In all cases negligible DC voltage exists across the segments. CAUTION: In the lamp test mode, the segments have a constant DC voltage (no square-wave). This may burn the LCD display if maintained for extended periods. V+ V+ BP WS7106 WS7106 TO LCD DECIMAL POINTS DECIMAL POINT SELECT Figure 8 is the Digital Section of the WS7107 WS7107. It is identical to the WS 7106 except that the regulated supply and back plane drive have been eliminated and the segment drive has been increased from 2mA to 8mA, typical for instrument size common anode LED displays. Since the 1000 output (pin 19) must sink current from two LED segments, it has twice the drive capability or 16mA. TEST CD4030 CD4030 GND In both devices, the polarity indication is "on" for negative analog inputs. If IN LO and IN HI are reversed, this indication can be reversed also, if desired. FIGURE 6. EXCLUSIVE `OR' GATE FOR DECIMAL POINT DRIVE a a f a g b e a f b b f g c e c d b g c d e c d BACKPLANE 21 LCD PHASE DRIVER 7 SEGMENT DECODE TYPICAL SEGMENT OUTPUT V+ 7 SEGMENT DECODE 7 SEGMENT DECODE ÷200 0.5mA LATCH SEGMENT OUTPUT 2mA 1000's COUNTER 100's COUNTER 10's COUNTER 1's COUNTER INTERNAL DIGITAL GROUND TO SWITCH DRIVERS FROM COMPARATOR OUTPUT 1 V+ CLOCK ÷4 LOGIC CONTROL 6.2V 500 THREE INVERTERS INTERNAL DIGITAL GROUND ONE INVERTER SHOWN FOR CLARITY TEST VTH = 1V 37 26 40 OSC 1 39 38 OSC 3 OSC 2 FIGURE 7. WS 7106 DIGITAL SECTION 7 V- WS7106 WS7106 / WS7107 WS7107 a a a f g b f b e a f b g c e c d e c d 7 SEGMENT DECODE TYPICAL SEGMENT OUTPUT V+ b g c d 7 SEGMENT DECODE 7 SEGMENT DECODE LATCH 0.5mA TO SEGMENT 1000's COUNTER 100's COUNTER 10's COUNTER 1's COUNTER 8mA TO SWITCH DRIVERS FROM COMPARATOR OUTPUT DIGITAL GROUND V+ 1 V+ CLOCK ÷4 37 LOGIC CONTROL THREE INVERTERS ONE INVERTER SHOWN FOR CLARITY 27 40 OSC 1 39 OSC 2 TEST 500 DIGITAL GROUND 38 OSC 3 FIGURE 8. WS 7107 DIGITAL SECTION System Timing INTERNAL TO PART Figure 9 shows the clocking arrangement used in the WS7106 WS7106 and WS7107 WS7107 . Two basic clocking arrangements can be used: ÷4 CLOCK ÷4 CLOCK 1. Figure 9A. An external oscillator connected to pin 40. 2. Figure 9B. An R-C oscillator using all three pins. 40 The oscillator frequency is divided by four before it clocks the decade counters. It is then further divided to form the three convert-cycle phases. These are signal integrate (1000 counts), reference de-integrate (0 to 2000 counts) and auto-zero (1000 to 3000 counts). For signals less than full scale, auto-zero gets the unused portion of reference de-integrate. This makes a complete measure cycle of 4,000 counts (16,000 clock pulses) independent of input voltage. For three readings/second, an oscillator frequency of 48kHz would be used. To achieve maximum rejection of 60Hz pickup, the signal integrate cycle should be a multiple of 60Hz. Oscillator frequencies of 240kHz, 120kHz, 80kHz, 60kHz, 48kHz, 40kHz, 331/3kHz, etc. should be selected. For 50Hz rejection, Oscillator frequencies of 200kHz, 100kHz, 662/3kHz, 50kHz, 40kHz, etc. would be suitable. Note that 40kHz (2.5 readings/second) will reject both 50Hz and 60Hz (also 400Hz and 440Hz). 39 38 GND WS7107 WS7107 TEST WS7106 WS7106 FIGURE 9A. INTERNAL TO PART 40 39 38 R C RC OSCILLATOR FIGURE 9B. FIGURE 9. CLOCK CIRCUITS 8 WS7106 WS7106 / WS7107 WS7107 Component Value Selection Reference Voltage Integrating Resistor The analog input required to generate full scale output (2000 counts) is: VlN = 2VREF. Thus, for the 200mV and 2V scale, VREF should equal 100mV and 1V, respectively. However, in many applications where the A/D is connected to a transducer, there will exist a scale factor other than unity between the input voltage and the digital reading. For instance, in a weighing system, the designer might like to have a full scale reading when the voltage from the transducer is 0.662V. Instead of dividing the input down to 200mV, the designer should use the input voltage directly and select VREF = 0.341V. Suitable values for integrating resistor and capacitor would be 1 20k and 0.22µF. This makes the system slightly quieter and also avoids a divider network on the input. The WS 7107 with ±5V supplies can accept input signals up to ±4V. Another advantage of this system occurs when a digital reading of zero is desired for VIN 0. Temperature and weighing systems with a variable fare are examples. This offset reading can be conveniently generated by connecting the voltage transducer between IN HI and COMMON and the variable (or fixed) offset voltage between COMMON and IN LO. Both the buffer amplifier and the integrator have a class A output stage with 100µA of quiescent current. They can supply 4µA of drive current with negligible nonlinearity. The integrating resistor should be large enough to remain in this very linear region over the input voltage range, but small enough that undue leakage requirements are not placed on the PC board. For 2V full scale, 470k is near optimum and similarly a 47k for a 200mV scale. Integrating Capacitor The integrating capacitor should be selected to give the maximum voltage swing that ensures tolerance buildup will not saturate the integrator swing (approximately. 0.3V from either supply). In the WS7106 WS7106 or the WS7107 WS7107, When the analog COMMON is used as a reference, a nominal +2V fullscale integrator swing is fine. For the WS7107 WS7107 with +5V supplies and analog COMMON tied to supply ground, a ±3.5V to +4V swing is nominal. For three readings/second (48kHz clock) nominal values for ClNT are 0.22µF and 0.10µF, respectively. Of course, if different oscillator frequencies are used, these values should be changed in inverse proportion to maintain the same output swing. An additional requirement of the integrating capacitor is that it must have a low dielectric absorption to prevent roll-over errors. While other types of capacitors are adequate for this application, polypropylene capacitors give undetectable errors at reasonable cost. Auto-Zero Capacitor The size of the auto-zero capacitor has some influence on the noise of the system. For 200mV full scale where noise is very important, a 0.47µF capacitor is recommended. On the 2V scale, a 0.047µF capacitor increases the speed of recovery from overload and is adequate for noise on this scale. WS7107 WS7107 Power Supplies The WS 7107 is designed to work from ±5V supplies. However, if a negative supply is not available, it can be generated from the clock output with 2 diodes, 2 capacitors, and an inexpensive lC. Figure 10 shows this application. See ICL7660 ICL7660 data sheet for an alternative. In fact, in selected applications no negative supply is required. The conditions to use a single +5V supply are: 1. The input signal can be referenced to the center of the common mode range of the converter. 2. The signal is less than ±1.5V. 3. An external reference is used. Reference Capacitor A 0.1µF capacitor gives good results in most applications. However, where a large common mode voltage exists (i.e., the REF LO pin is not at analog COMMON) and a 200mV scale is used, a larger value is required to prevent roll-over error. Generally 1µF will hold the roll-over error to 0.5 count in this instance. Oscillator Components V+ CD4009 CD4009 V+ OSC 1 IN914 IN914 OSC 2 OSC 3 For all ranges of frequency a 100k resistor is recommended and the capacitor is selected from the equation: 0.047 µF + 10 µF - WS7107 WS7107 IN914 IN914 GND V- 0.45 f = - For 48kHz Clock (3 Readings/sec), RC C = 100pF. V- = 3.3V FIGURE 10. GENERATING NEGATIVE SUPPLY FROM +5V 9 WS7106 WS7106 / WS7107 WS7107 TYPICAL APPLICATIONS The WS7106 WS7106 and WS7107 WS7107 may be used in a wide variety of configurations. The circuits which follow show some of the possibilities, and serve to illustrate the exceptional versatility of these A/D converters. Typical Applications TO PIN 1 OSC 1 40 TO PIN 1 OSC 1 40 100k OSC 2 39 OSC 2 39 OSC 3 38 TEST 37 OSC 3 38 SET VREF = 100mV 100pF TEST 37 REF HI 36 CREF 33 22k CREF 34 0.1µF CREF 33 1M A-Z 29 0.47µF A-Z 29 + 9V BUFF 28 - INT 27 V - 26 IN LO 30 - 47k A3 23 0.1µF 1M + IN 0.01µF 0.47µF - 47k INT 27 0.22µF V - 26 G2 25 C3 24 22k IN HI 31 IN 0.01µF 1k COMMON 32 + IN HI 31 BUFF 28 +5V REF LO 35 1k COMMON 32 IN LO 30 SET VREF = 100mV 100pF REF HI 36 REF LO 35 CREF 34 100k 0.22µF -5V G2 25 C3 24 TO DISPLAY A3 23 G3 22 G3 22 BP 21 TO DISPLAY GND 21 TO BACKPLANE Values shown are for 200mV full scale, 3 readings/sec., floating supply voltage (9V battery). FIGURE 11 WS7106 WS7106 USING THE INTERNAL REFERENCE Values shown are for 200mV full scale, 3 readings/sec. IN LO may be tied to either COMMON for inputs floating with respect to supplies, or GND for single ended inputs. (See discussion under Analog COMMON.) FIGURE 12. WS7107 WS7107 USING THE INTERNAL REFERENCE 10 WS7106 WS7106 / WS7107 WS7107 Typical Applications (Continued) TO PIN 1 OSC 1 40 TO PIN 1 OSC 1 40 100k OSC 2 39 OSC 2 39 OSC 3 38 TEST 37 OSC 3 38 SET VREF = 100mV 100pF TEST 37 REF HI 36 CREF 33 V+ 1k 10k 10k 1M A-Z 29 IN LO 30 - A3 23 1M + IN 0.01µF 0.47µF - 47k BUFF 28 INT 27 0.22µF V- V - 26 G2 25 C3 24 6.8V 0.1µF A-Z 29 47k INT 27 V - 26 100k IN HI 31 IN 0.01µF 0.47µF 1k COMMON 32 + IN HI 31 BUFF 28 CREF 33 1.2V (ICL8069 ICL8069) +5V REF LO 35 CREF 34 0.1µF COMMON 32 IN LO 30 SET VREF = 100mV 100pF REF HI 36 REF LO 35 CREF 34 100k 0.22µF -5V G2 25 C3 24 TO DISPLAY A3 23 G3 22 G3 22 GND 21 TO DISPLAY GND 21 IN LO is tied to supply COMMON establishing the correct common mode voltage. If COMMON is not shorted to GND, the input voltage may float with respect to the power supply and COMMON acts as a pre-regulator for the reference. If COMMON is shorted to GND, the input is single ended (referred to supply GND) and the pre-regulator is overridden. FIGURE 13. WS 7107 WITH AN EXTERNAL BAND-GAP REFERENCE (1.2V TYPE) FIGURE 14. WS 7107 WITH ZENER DIODE REFERENCE TO PIN 1 TO PIN 1 OSC 1 40 OSC 1 40 100k OSC 3 38 OSC 3 38 SET VREF = 100mV 100pF TEST 37 REF LO 35 V+ REF LO 35 CREF 33 25k 24k CREF 33 BUFF 28 1M 0.047µF IN LO 30 IN 0.01µF A-Z 29 - BUFF 28 470k A3 23 0.1µF 1.2V (ICL8069 ICL8069) 1M + IN 0.01µF 0.47µF - 47k 0.22µF G2 25 V- C3 24 G2 25 C3 24 15k INT 27 V - 26 0.22µF 10k IN HI 31 + INT 27 V - 26 +5V 1k COMMON 32 IN HI 31 A-Z 29 CREF 34 0.1µF COMMON 32 IN LO 30 SET VREF = 100mV 100pF REF HI 36 REF HI 36 CREF 34 100k OSC 2 39 OSC 2 39 TEST 37 Since low TC zeners have breakdown voltages ~ 6.8V, diode must be placed across the total supply (10V). As in the case of Figure 14, IN LO may be tied to either COMMON or GND. A3 23 TO DISPLAY TO DISPLAY G3 22 GND 21 G3 22 BP/GND 21 An external reference must be used in this application, since the voltage between V+ and V- is insufficient for correct operation of the internal reference. FIGURE 15. WS7106 WS7106 AND WS7107 WS7107; RECOMMENDED COMPONENT VALUES FOR 2V FULL SCALE FIGURE 16. WS7107 WS7107 OPERATED FROM SINGLE +5V 11 WS7106 WS7106 / WS7107 WS7107 Typical Applications (Continued) TO PIN 1 OSC 1 40 TO PIN 1 V+ OSC 1 40 100k 100k OSC 2 39 OSC 2 39 OSC 3 38 OSC 3 38 100pF TEST 37 REF HI 36 REF HI 36 REF LO 35 SCALE FACTOR ADJUST 100pF TEST 37 REF LO 35 CREF 34 CREF 34 0.1µF CREF 33 CREF 33 100k 1M 100k 220k 0.1µF 22k COMMON 32 COMMON 32 IN HI 31 IN HI 31 IN LO 30 IN LO 30 0.47µF 47k BUFF 28 0.47µF A-Z 29 A-Z 29 ZERO ADJUST 0.01µF SILICON NPN MPS 3704 OR SIMILAR 47k BUFF 28 9V INT 27 INT 27 0.22µF V - 26 V - 26 0.22µF G2 25 G2 25 C3 24 C3 24 TO DISPLAY A3 23 A3 23 G3 22 G3 22 GND 21 TO DISPLAY BP 21 TO BACKPLANE The resistor values within the bridge are determined by the desired sensitivity. A silicon diode-connected transistor has a temperature coefficient of about -2mV/oC. Calibration is achieved by placing the sensing transistor in ice water and adjusting the zeroing potentiometer for a 000.0 reading. The sensor should then be placed in boiling water and the scale-factor potentiometer adjusted for a 100.0 reading. FIGURE 17. WS 7107 MEASUREING RATIOMETRIC VALUES OF QUAD LOAD CELL FIGURE 18. WS 7106 USED AS A DIGITAL CENTIGRADE THERMOMETER V+ +5V 1 V+ 1 V+ OSC 1 40 OSC 2 39 2 D1 OSC 2 39 3 C1 OSC 3 38 3 C1 OSC 3 38 4 B1 TEST 37 4 B1 TEST 37 5 A1 REF HI 36 5 A1 REF HI 36 6 F1 TO LOGIC VCC OSC 1 40 2 D1 REF LO 35 6 F1 REF LO 35 7 G1 CREF 34 7 G1 8 E1 9 D2 TO CREF 34 LOGIC GND CREF 33 8 E1 IN HI 31 11 B2 IN LO 30 12 A2 A-Z 29 13 F2 BUFF 28 14 E2 INT 27 15 D3 V- 26 16 B3 G2 25 17 F3 C3 24 18 E3 A3 23 19 AB4 G3 22 20 POL 12k BP 21 The LM339 LM339 is required to ensure logic compatibility with heavy display loading. + - VO /RANGE CD4023 CD4023 OR 74C10 74C10 + - U /RANGE CD4023 CD4023 OR 74C10 74C10 COMMON 32 IN HI 31 11 B2 IN LO 30 12 A2 A-Z 29 13 F2 BUFF 28 14 E2 INT 27 - 15 D3 V- 26 16 B3 + U /RANGE CREF 33 9 D2 10 C2 COMMON 32 10 C2 O /RANGE TO LOGIC VCC G2 25 17 F3 C3 24 18 E3 A3 23 19 AB4 G3 22 20 POL V- BP 21 + 33k CD4077 CD4077 FIGURE 19. CIRCUIT FOR DEVELOPING UNDERRANGE AND OVERRANGE SIGNAL FROM WS7106 WS7106 OUTPUTS FIGURE 20. CIRCUIT FOR DEVELOPING UNDERRANGE AND OVERRANGE SIGNALS FROM WS7107 WS7107 OUTPUT 12 WS7106 WS7106 / WS7107 WS7107 Typical Applications (Continued) TO PIN 1 OSC 1 40 100k OSC 2 39 10µF SCALE FACTOR ADJUST (VREF = 100mV FOR AC TO RMS) OSC 3 38 TEST 37 100pF 5µF CA3140 CA3140 REF HI 36 - REF LO 35 CREF 34 CREF 33 1N914 1N914 1k 22k 470k 0.1µF 2.2M COMMON 32 10k 1µF 4.3k 0.22µF 47k 10µF + 9V - INT 27 V - 26 1µF 0.47µF A-Z 29 BUFF 28 10k 1µF IN HI 31 IN LO 30 100pF (FOR OPTIMUM BANDWIDTH) 0.22µF G2 25 C3 24 A3 23 TO DISPLAY G3 22 BP 21 100k + TO BACKPLANE Test is used as a common-mode reference level to ensure compatibility with most op amps. FIGURE 21. AC TO DC CONVERTER WITH WS7106 WS7106 +5V LED SEGMENTS DM7407 DM7407 130 ICL7107 ICL7107 130 130 FIGURE 22. DISPLAY BUFFERING FOR INCREASED DRIVE CURRENT 13 AC IN WS7106 WS7106 / WS7107 WS7107 Dual-In-Line Plastic Packages (PDIP) E40.6 (JEDEC MS-011-AC MS-011-AC ISSUE B) N 40 LEAD DUAL-IN-LINE PLASTIC PACKAGE E1 INDEX AREA 1 2 3 INCHES N/2 SYMBOL -B- MILLIMETERS MIN MAX MIN MAX NOTES A - 0.250 - 6.35 4 A1 0.015 - 0.39 - 4 A2 0.125 0.195 3.18 4.95 - B 0.014 0.022 0.356 0.558 - C L B1 0.030 0.070 0.77 1.77 8 eA C 0.008 0.015 0.204 0.381 - D 1.980 2.095 D1 0.005 - -AD E BASE PLANE A2 -C- SEATING PLANE A L D1 e B1 D1 B 0.010 (0.25) M A1 eC C A B S C eB 50.3 53.2 5 - 5 0.13 E NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982 5M-1982. 3. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). 14 0.600 0.625 15.24 15.87 6 E1 0.485 0.580 12.32 14.73 5 e 0.100 BSC 2.54 BSC - eA 0.600 BSC 15.24 BSC 6 eB - 0.700 - 17.78 7 L 0.115 0.200 2.93 5.08 4 N 40 40 9