WFP6530B WFP6540 CL-FP6530A VS240 EIO240 -66C02 -74DXX V005-531 LD240 VS113 - Datasheet Archive

 

Advanced Product Information 1. PRODUCT DESCRIPTION COG Signal Driver The WFP6530B is a 6-bit, 240-channel signal driver designed

 

WFP6530B WFP6530B Advanced Product Information 1. PRODUCT DESCRIPTION COG Signal Driver The WFP6530B WFP6530B is a 6-bit, 240-channel signal driver designed for SVGA chip-on-glass (COG) TFT-LCDs. The WFP6530B WFP6530B's minimum form factor and optimized COG layout permit the design of high-display-quality, low-power 6-bit TFT-LCD's with minimum bezel area. 240-Channel, 6-Bit Signal Driver for TFT-LCD COG Applications The WFP6530B WFP6530B silicon is Rev. K of the WFP6540 WFP6540 die. The Rev. K die has 10 additional dummy pads compared to Revs. A-H. The WFP6530B WFP6530B's internal architecture includes a resistor-string DAC with the value of the individual resistor segments weighted to reduce signal driver power dissipation by as much as 20% to 40% when compared to non-weighted resistor string DAC architectures. CL-FP6530A CL-FP6530A Signal Driver 240 CL-FP6530A CL-FP6530A Signal Driver 240 . CL-FP6530A CL-FP6530A Signal Driver 240 Data from Graphics Controller Control LCD Control ASIC Reference Amplifier Circuit . Gate Driver 800x600 262,144-Color LCD Gate Driver July 21, 1999 Rev. 0.01 © 1999 Winbond Electronics Winbond Electronics Confidentiali 1 WFP6530B WFP6530B 240-Channel 6-Bit Signal Driver for COG TFT-LCDs 2. FEATURES & BENEFITS Features Benefits · Full Color Display · · 64 gray scales per primary color 262,144 (256K) color palette · · High Speed Operation 65 MHz (3.3 V and 5.0V logic supply) · · Support for wide range of color LCD resolutions Single driver bank supports up to 1024 x 768 · · · · Minimum Form Factor 17.06 mm x 1.30 mm 70 µm output pitch 675 µm ± 25 µm chip thickness · Minimum Bezel Size · · · High Integration 240 output voltage channels Bi-directional shift register · · · Minimizes external components and circuitry 10 drivers for 800x600 color LCDs Easy re-configuration from backlit operation to overhead projector (OHP) operation · Data inversion capability enables a complete internal solution for Vcom modulation by data inversion. Allows implementation of data transition reduction schemes. · Data Inversion Feature · · · · · Low-power operation Logic Supply: 3.3 V ± 0.3 or 5.0 V ± 0.5 Analog Supply: 3.3 V ± 0.3 to 5.0 V ± 0.5 Automatic standby function · · · Extends battery-based operation Low power and EMI from 3.3 V operation Minimum dynamic-power dissipation · Excellent Output Uniformity · Output Error (max) ± 0.15 LSB · Reduces Power Dissipation 20-40% or more. Reduces dc current drive requirements of external reference amplifiers · Weighted R-String: See Figure 2-1 & Table 2-1 · 2 © 1999 Winbond Electronics Winbond Electronics Confidential July 21, 1999 Rev. 0.01 WFP6530B WFP6530B 240-Channel 6-Bit Signal Driver for COG TFT-LCDs · Rseg Value - Internal weighted R-String for low power operation (see Table 2-1 and Figure 2-1). Table 2-1: Weighted RSEG Values (ignoring bus resistance) R-Segment Proportion Value 2x 40,40,40,40,40,40,40,40 V6 ~V7 1.2x 24 X 8 V5 ~V6 1x 20 X 8 V4 ~V5 1x 20 X 8 V3 ~V4 1x 20 X 8 V2 ~V3 1x 20 X 8 V1 ~V2 1.2x 24 X 8 V0 ~V1 (V00~V07) 1.75x 40, 40 40, 40, 40, 40, 40 V7 ~ V8 (V55~V63) Proportion V8 VS57 . VS56 . VS55 40 40 40 40 40 note: Resistance between reference inputs is RString. Resistance between individual codes is RSEG. 40 40 160 1 1.2 V2 V1 192 . . 1.75 280 V0 V0 VS04 VS03 VS02 . 160 VS05 . 1 VS06 . 40 . V7 VS07 RSEG Value . V1 . . 160 . V3 VS58 RSEG Value . 1 V4 VS59 . 160 VS60 . . VS61 . 192 . 1 V5 VS62 . 320 . 1.2 V6 VS63 . 2 V7 RString Value . . V8 VS01 . VS00 40 40 40 40 40 40 40 Figure 2-1: Weighted R-String Detail July 21, 1999 Rev. 0.01 © 1999 Winbond Electronics Winbond Electronics Confidential 3 WFP6530B WFP6530B 240-Channel 6-Bit Signal Driver for COG TFT-LCDs 3. WFP6530B WFP6530B DIMENSIONS & SPECIFICATIONS 3.1. DIE DIMENSIONS Dummy Pads Alignment Mark #1 D2 D3 D4 D5 VS240 VS240, Pad #281 D1 EIO240 EIO240# Pad #1 D25 Pad #2 D24 Pad #3 D23 Pad #4 Y D02 Pad #39 D00 Pad #40 EIO1# (0,0) Pad #38 D01 17.06 mm X Pad #41 D6 Alignment Mark #2 D7 D8 D9 D10 VS1, Pad #42 Dummy Pads 1.30 mm 4 © 1999 Winbond Electronics Winbond Electronics Confidential July 21, 1999 Rev. 0.01 WFP6530B WFP6530B 240-Channel 6-Bit Signal Driver for COG TFT-LCDs 3.2. Bump Specifications 72 µm 72 µm Y 56 µm 40 µm 160 µm 120 µm Figure 3-2: Split Input Pad Bump Table 3­1. Y Figure 3-3: Output Pad Bump Dummy Bump Sizes Name Size (Y by X) µm Name Pad # Size (Y by X) µm D5,D10 282,291 50 by 50 D2,D7 285,288 100 by 40 D4,D9 283,290 50 by 70 D1,D6 286,291 60 by 100 D3,D8 · · · · Pad # 284,289 50 by 100 Bump Height: 15 µm ± 2 µm Bump Dimple: less than 2 µm (see Figure 3-5) Bump Material: Gold Bump Hardness: 30 HV ~ 80 HV, · Bump Shape: Tapered wall, 80° ± 5 angle to plane of top of die Dimple < 2 um 80° Bump Height Gold Bump Oxide Metal Pad Figure 3-5: Bump Specification Definitions 3.3. Alignment Mark Coordinates Coordinates Mark Y #1 8305.0 414.3 #2 July 21, 1999 Rev. 0.01 X -8305.0 Each mark is 50 µm by 50µm 414.3 © 1999 Winbond Electronics Winbond Electronics Confidential 5 WFP6530B WFP6530B 240-Channel 6-Bit Signal Driver for COG TFT-LCDs 3.4. DIE DIMENSIONSWaffle Pack Specification 4.000 SQ. .300 .20 x 45 CHAM. 34 Spaces at .100 ± 3.400 SQ. (.060) .100 .860 (.700) .760 Capacity = 136 die xxxx 3 SPACES AT .760 = 2.280 1 A A xxxx R .03 (4) (.20) 1 .060 x .700 (+) 5°/SIDE (140) .315 .215 + .003 SEE POCKET DETAIL (.034) .034 ± .004 (140) 3.600 - .007 SQ. .080 R.03 (4) .010A .275 (+) 5 °(INSIDE) (.215) -A- .160 3.610 SQ. 2 R.03 (TYP) .06 (+) 5°/ SIDE (TYP) SECTION A-A 1.50 1.00 (.315) POCKET DETAIL .20 (+) 45°/ SIDE (12) 1 KNOCKOUTS NOT TO EXCEED .003 PAD 3 1.50 ENGRAVING TO BE .08 CHAR. X .01 WIDE X .002 RAISED. CENTER ON C L 2 (.195) MATERIAL: ABS, Tan Static Protective ABS ChipSentry© ,Stat-PRO©400 -Build Tool to .006 IN./IN. SHRINK. (.05) ChipSentry© -66C02 -66C02 1.00 -74DXX -74DXX Stat-PRO©400 Mat. Code Mtr. & Engrvng 1.50 (8) (.075) Tolerances Unless Otherwise Specified xx [.x] xxx [.xx] 6 .01 [.3] Part No. ± .005 [.13] Material ± R .03 (TYP) © 1999 Winbond Electronics Winbond Electronics Confidential 4" CHIP TRAY - 140 rect. pockets ± xxxx ± [.xxx] .115 Description .0005 [.013] 1/2° H44-xxxx-XXXX SEE NOTE 3 Drawing No. V005-531 V005-531 DIMENSIONS IN INCHES [MILLIMETERS] July 21, 1999 Rev. 0.01 WFP6530B WFP6530B 240-Channel 6-Bit Signal Driver for COG TFT-LCDs 4. PAD INFORMATION Input Bond Pad Coordinates Pad # Signal x Coordinate (in µm) y Coordinate (in µm) 1.1 1.2 2.1 2.2 3.1 3.2 4.1 4.2 5.1 5.2 6.1 6.2 7.1 7.2 8.1 8.2 9.1 9.2 10.1 10.2 11.1 11.2 12.1 12.2 13.1 13.2 14.1 14.2 15.1 15.2 16.1 16.2 17.1 17.2 18.1 18.2 19.1 19.2 20.1 20.2 21.1 21.2 22.1 22.2 23.1 23.2 24.1 24.2 25.1 25.2 26.1 26.2 27.1 27.2 28.1 28.2 29.1 29.2 30.1 30.2 31.1 31.2 EIO240 EIO240# EIO240 EIO240# D25 D25 D24 D24 D23 D23 D22 D22 D21 D21 D20 D20 D15 D15 LD240 LD240_1 LD240 LD240_1 V0 V0 V8 V8 Reserved Reserved D14 D14 D13 D13 DCLK DCLK VDDD VDDD VDDA VDDA V7 V7 V2 V2 V5 V5 V4 V4 V3 V3 V6 V6 V1 V1 AGND AGND DGND DGND D12 D12 D11 D11 D10 D10 CLAMP# CLAMP# V8 V8 7744.00 7616.00 7424.00 7296.00 7104.00 6976.00 6784.00 6656.00 6464.00 6336.00 6144.00 6016.00 5824.00 5696.00 5504.00 5376.00 5184.00 5056.00 4544.00 4416.00 3904.00 3776.00 3584.00 3456.00 3264.00 3136.00 2944.00 2816.00 2624.00 2496.00 2304.00 2176.00 1984.00 1856.00 1344.00 1216.00 704.00 576.00 384.00 256.00 64.00 -64.00 -256.00 -384.00 -576.00 -704.00 -1216.00 -1344.00 -1856.00 -1984.00 -2176.00 -2304.00 -2496.00 -2624.00 -2816.00 -2944.00 -3136.00 -3264.00 -3456.00 -3584.00 -3776.00 -3904.00 439.30 439.30 439.30 439.30 439.30 439.30 439.30 439.30 439.30 439.30 439.30 439.30 439.30 439.30 439.30 439.30 439.30 439.30 439.30 439.30 439.30 439.30 439.30 439.30 439.30 439.30 439.30 439.30 439.30 439.30 439.30 439.30 439.30 439.30 439.30 439.30 439.30 439.30 439.30 439.30 439.30 439.30 439.30 439.30 439.30 439.30 439.30 439.30 439.30 439.30 439.30 439.30 439.30 439.30 439.30 439.30 439.30 439.30 439.30 439.30 439.30 439.30 Table 4-1: WFP6530B WFP6530B Input Bond Pad Coordinates July 21, 1999 Rev. 0.01 © 1999 Winbond Electronics Winbond Electronics Confidential 7 WFP6530B WFP6530B 240-Channel 6-Bit Signal Driver for COG TFT-LCDs Pad # Signal x Coordinate (in µm) y Coordinate (in µm) 32.1 32.2 33.1 33.1 34.1 34.2 35.1 35.2 36.1 36.2 37.1 37.2 38.1 38.2 39.1 39.2 40.1 40.2 41.1 41.2 V0 V0 DATA_INV DATA_INV LP LP D05 D05 D04 D04 D03 D03 D02 D02 D01 D01 D00 D00 EIO1# EIO1# -4416.00 -4544.00 -5056.00 -5184.00 -5376.00 -5504.00 -5696.00 -5824.00 -6016.00 -6144.00 -6336.00 -6464.00 -6656.00 -6784.00 -6976.00 -7104.00 -7296.00 -7424.00 -7616.00 -7744.00 439.30 439.30 439.30 439.30 439.30 439.30 439.30 439.30 439.30 439.30 439.30 439.30 439.30 439.30 439.30 439.30 439.30 439.30 439.30 439.30 Table 4-1: WFP6530B WFP6530B Input Bond Pad Coordinates 8 © 1999 Winbond Electronics Winbond Electronics Confidential July 21, 1999 Rev. 0.01 WFP6530B WFP6530B 240-Channel 6-Bit Signal Driver for COG TFT-LCDs 4.1. Output Bond Pad Coordinate Pad # 42 Signal VS1 X (µm) -8365.0 Y (µm) -463.4 43 VS2 -8295.0 -463.4 44 VS3 -8225.0 -463.4 45 VS4 -8155.0 -463.4 46 VS5 -8085.0 -463.4 47 VS6 -8015.0 -463.4 48 VS7 -7945.0 -463.4 49 VS8 -7875.0 -463.4 50 VS9 -7805.0 -463.4 51 VS10 -7735.0 -463.4 52 VS11 -7665.0 -463.4 53 VS12 -7595.0 -463.4 54 VS13 -7525.0 -463.4 55 VS14 -7455.0 -463.4 56 VS15 -7385.0 -463.4 57 VS16 -7315.0 -463.4 58 VS17 -7245.0 -463.4 59 VS18 -7175.0 -463.4 60 VS19 -7105.0 -463.4 61 VS20 -7035.0 -463.4 62 VS21 -6965.0 -463.4 63 VS22 -6895.0 -463.4 64 VS23 -6825.0 -463.4 65 VS24 -6755.0 -463.4 66 VS25 -6685.0 -463.4 67 VS26 -6615.0 -463.4 68 VS27 -6545.0 -463.4 69 VS28 -6475.0 -463.4 70 VS29 -6405.0 -463.4 71 VS30 -6335.0 -463.4 72 VS31 -6265.0 -463.4 73 VS32 -6195.0 -463.4 74 VS33 -6125.0 -463.4 75 VS34 -6055.0 -463.4 76 VS35 -5985.0 -463.4 77 VS36 -5915.0 -463.4 Pad # 78 Signal VS37 X (µm) -5845.0 Y (µm) -463.4 79 VS38 -5775.0 -463.4 80 VS39 -5705.0 -463.4 81 VS40 -5635.0 -463.4 82 VS41 -5565.0 -463.4 83 VS42 -5495.0 -463.4 84 VS43 -5425.0 -463.4 85 VS44 -5355.0 -463.4 86 VS45 -5285.0 -463.4 87 VS46 -5215.0 -463.4 88 VS47 -5145.0 -463.4 89 VS48 -5075.0 -463.4 90 VS49 -5005.0 -463.4 91 VS50 -4935.0 -463.4 92 VS51 -4865.0 -463.4 93 VS52 -4795.0 -463.4 94 VS53 -4725.0 -463.4 95 VS54 -4655.0 -463.4 96 VS55 -4585.0 -463.4 97 VS56 -4515.0 -463.4 98 VS57 -4445.0 -463.4 99 VS58 -4375.0 -463.4 100 VS59 -4305.0 -463.4 101 VS60 -4235.0 -463.4 102 VS61 -4165.0 -463.4 103 VS62 -4095.0 -463.4 104 VS63 -4025.0 -463.4 105 VS64 -3955.0 -463.4 106 VS65 -3885.0 -463.4 107 VS66 -3815.0 -463.4 108 VS67 -3745.0 -463.4 109 VS68 -3675.0 -463.4 110 VS69 -3605.0 -463.4 111 VS70 -3535.0 -463.4 112 VS71 -3465.0 -463.4 113 VS72 -3395.0 -463.4 114 VS73 -3325.0 -463.4 115 VS74 -3255.0 -463.4 Table 4-2: July 21, 1999 Rev. 0.01 Table 4-2: © 1999 Winbond Electronics Winbond Electronics Confidential 9 WFP6530B WFP6530B 240-Channel 6-Bit Signal Driver for COG TFT-LCDs Pad # 116 Signal VS75 X (µm) -3185.0 Y (µm) -463.4 Pad # 154 Signal VS113 VS113 X (µm) -525.0 Y (µm) -463.4 117 VS76 -3115.0 -463.4 155 VS114 VS114 -455.0 -463.4 118 VS77 -3045.0 -463.4 156 VS115 VS115 -385.0 -463.4 119 VS78 -2975.0 -463.4 157 VS116 VS116 -315.0 -463.4 120 VS79 -2905.0 -463.4 158 VS117 VS117 -245.0 -463.4 121 VS80 -2835.0 -463.4 159 VS118 VS118 -175.0 -463.4 122 VS81 -2765.0 -463.4 160 VS119 VS119 -105.0 -463.4 123 VS82 -2695.0 -463.4 161 VS120 VS120 -35.0 -463.4 124 VS83 -2625.0 -463.4 162 VS121 VS121 35.0 -463.4 125 VS84 -2555.0 -463.4 163 VS122 VS122 105.0 -463.4 126 VS85 -2485.0 -463.4 164 VS123 VS123 175.0 -463.4 127 VS86 -2415.0 -463.4 165 VS124 VS124 245.0 -463.4 128 VS87 -2345.0 -463.4 166 VS125 VS125 315.0 -463.4 129 VS88 -2275.0 -463.4 167 VS126 VS126 385.0 -463.4 130 VS89 -2205.0 -463.4 168 VS127 VS127 455.0 -463.4 131 VS90 -2135.0 -463.4 169 VS128 VS128 525.0 -463.4 132 VS91 -2065.0 -463.4 170 VS129 VS129 595.0 -463.4 133 VS92 -1995.0 -463.4 171 VS130 VS130 665.0 -463.4 134 VS93 -1925.0 -463.4 172 VS131 VS131 735.0 -463.4 135 VS94 -1855.0 -463.4 173 VS132 VS132 805.0 -463.4 136 VS95 -1785.0 -463.4 174 VS133 VS133 875.0 -463.4 137 VS96 -1715.0 -463.4 175 VS134 VS134 945.0 -463.4 138 VS97 -1645.0 -463.4 176 VS135 VS135 1015.0 -463.4 139 VS98 -1575.0 -463.4 177 VS136 VS136 1085.0 -463.4 140 VS99 -1505.0 -463.4 178 VS137 VS137 1155.0 -463.4 141 VS100 VS100 -1435.0 -463.4 179 VS138 VS138 1225.0 -463.4 142 VS101 VS101 -1365.0 -463.4 180 VS139 VS139 1295.0 -463.4 143 VS102 VS102 -1295.0 -463.4 181 VS140 VS140 1365.0 -463.4 144 VS103 VS103 -1225.0 -463.4 182 VS141 VS141 1435.0 -463.4 145 VS104 VS104 -1155.0 -463.4 183 VS142 VS142 1505.0 -463.4 146 VS105 VS105 -1085.0 -463.4 184 VS143 VS143 1575.0 -463.4 147 VS106 VS106 -1015.0 -463.4 185 VS144 VS144 1645.0 -463.4 148 VS107 VS107 -945.0 -463.4 186 VS145 VS145 1715.0 -463.4 149 VS108 VS108 -875.0 -463.4 187 VS146 VS146 1785.0 -463.4 150 VS109 VS109 -805.0 -463.4 188 VS147 VS147 1855.0 -463.4 151 VS110 VS110 -735.0 -463.4 189 VS148 VS148 1925.0 -463.4 152 VS111 VS111 -665.0 -463.4 190 VS149 VS149 1995.0 -463.4 153 VS112 VS112 -595.0 -463.4 191 VS150 VS150 2065.0 -463.4 Table 4-2: 10 Table 4-2: © 1999 Winbond Electronics Winbond Electronics Confidential July 21, 1999 Rev. 0.01 WFP6530B WFP6530B 240-Channel 6-Bit Signal Driver for COG TFT-LCDs Pad # 192 Signal VS151 VS151 X (µm) 2135.0 Y (µm) -463.4 Pad # 230 Signal VS189 VS189 X (µm) 4795.0 Y (µm) -463.4 193 VS152 VS152 2205.0 -463.4 231 VS190 VS190 4865.0 -463.4 194 VS153 VS153 2275.0 -463.4 232 VS191 VS191 4935.0 -463.4 195 VS154 VS154 2345.0 -463.4 233 VS192 VS192 5005.0 -463.4 196 VS155 VS155 2415.0 -463.4 234 VS193 VS193 5075.0 -463.4 197 VS156 VS156 2485.0 -463.4 235 VS194 VS194 5145.0 -463.4 198 VS157 VS157 2555.0 -463.4 236 VS195 VS195 5215.0 -463.4 199 VS158 VS158 2625.0 -463.4 237 VS196 VS196 5285.0 -463.4 200 VS159 VS159 2695.0 -463.4 238 VS197 VS197 5355.0 -463.4 201 VS160 VS160 2765.0 -463.4 239 VS198 VS198 5425.0 -463.4 202 VS161 VS161 2835.0 -463.4 240 VS199 VS199 5495.0 -463.4 203 VS162 VS162 2905.0 -463.4 241 VS200 VS200 5565.0 -463.4 204 VS163 VS163 2975.0 -463.4 242 VS201 VS201 5635.0 -463.4 205 VS164 VS164 3045.0 -463.4 243 VS202 VS202 5705.0 -463.4 206 VS165 VS165 3115.0 -463.4 244 VS203 VS203 5775.0 -463.4 207 VS166 VS166 3185.0 -463.4 245 VS204 VS204 5845.0 -463.4 208 VS167 VS167 3255.0 -463.4 246 VS205 VS205 5915.0 -463.4 209 VS168 VS168 3325.0 -463.4 247 VS206 VS206 5985.0 -463.4 210 VS169 VS169 3395.0 -463.4 248 VS207 VS207 6055.0 -463.4 211 VS170 VS170 3465.0 -463.4 249 VS208 VS208 6125.0 -463.4 212 VS171 VS171 3535.0 -463.4 250 VS209 VS209 6195.0 -463.4 213 VS172 VS172 3605.0 -463.4 251 VS210 VS210 6265.0 -463.4 214 VS173 VS173 3675.0 -463.4 252 VS211 VS211 6335.0 -463.4 215 VS174 VS174 3745.0 -463.4 253 VS212 VS212 6405.0 -463.4 216 VS175 VS175 3815.0 -463.4 254 VS213 VS213 6475.0 -463.4 217 VS176 VS176 3885.0 -463.4 255 VS214 VS214 6545.0 -463.4 218 VS177 VS177 3955.0 -463.4 256 VS215 VS215 6615.0 -463.4 219 VS178 VS178 4025.0 -463.4 257 VS216 VS216 6685.0 -463.4 220 VS179 VS179 4095.0 -463.4 258 VS217 VS217 6755.0 -463.4 221 VS180 VS180 4165.0 -463.4 259 VS218 VS218 6825.0 -463.4 222 VS181 VS181 4235.0 -463.4 260 VS219 VS219 6895.0 -463.4 223 VS182 VS182 4305.0 -463.4 261 VS220 VS220 6965.0 -463.4 224 VS183 VS183 4375.0 -463.4 262 VS221 VS221 7035.0 -463.4 225 VS184 VS184 4445.0 -463.4 263 VS222 VS222 7105.0 -463.4 226 VS185 VS185 4515.0 -463.4 264 VS223 VS223 7175.0 -463.4 227 VS186 VS186 4585.0 -463.4 265 VS224 VS224 7245.0 -463.4 228 VS187 VS187 4655.0 -463.4 266 VS225 VS225 7315.0 -463.4 229 VS188 VS188 4725.0 -463.4 267 VS226 VS226 7385.0 -463.4 Table 4-2: July 21, 1999 Rev. 0.01 Table 4-2: © 1999 Winbond Electronics Winbond Electronics Confidential 11 WFP6530B WFP6530B 240-Channel 6-Bit Signal Driver for COG TFT-LCDs Pad # 268 Signal VS227 VS227 X (µm) 7455.0 Y (µm) -463.4 269 VS228 VS228 7525.0 -463.4 270 VS229 VS229 7595.0 -463.4 271 VS230 VS230 7665.0 -463.4 272 VS231 VS231 7735.0 -463.4 273 VS232 VS232 7805.0 -463.4 274 VS233 VS233 7875.0 -463.4 275 VS234 VS234 7945.0 -463.4 276 VS235 VS235 8015.0 -463.4 277 VS236 VS236 8085.0 -463.4 278 VS237 VS237 8155.0 -463.4 279 VS238 VS238 8225.0 -463.4 280 VS239 VS239 8295.0 -463.4 281 VS240 VS240 8365.0 -463.4 282 D5 8367.2 -204.6 283 D4 8367.2 -34.6 284 D3 8367.2 115.4 285 D2 8330.0 309.3 286 D1 8190.0 439.3 287 D6 -8190.0 439.3 288 D7 -8330.0 309.3 289 D8 -8367.2 115.4 290 D9 -8367.2 -34.6 291 D10 -8367.2 -204.6 Table 4-2: 12 © 1999 Winbond Electronics Winbond Electronics Confidential July 21, 1999 Rev. 0.01 WFP6530B WFP6530B 240-Channel 6-Bit Signal Driver for COG TFT-LCDs 5. DETAILED PAD DESCRIPTIONS The following abbreviations are used for pad types in the following sections: (I) input; (O) output; (I/O) Input/Output, (#) active `low' signal. Name Number LD240 LD240_1 9 EIO1#, EIO240 EIO240# 41,1 Type Description I LOAD DIRECTION: Controls the direction in which the data is loaded into the Input Register: When LD240 LD240_1 = `0', data is loaded from Channel VS1 to VS240 VS240. When LD240 LD240_1 = `1', data is loaded from Channel VS240 VS240 to VS1. I/O ENABLE IN/OUT: The EIO1# and EIO240 EIO240# active `low' signals initiate the loading of data into the Input Register of the WFP6530B WFP6530B. When one of the EIOx# pads is configured as an input, the other is configured as an output, with the direction determined by the LD240 LD240_1 input (see Table 5-1). The EIOx# output pads are designed to be connected to the EIOx# input pads of adjacent devices to allow a series of drivers to operate sequentially. When a `low' is applied to the EIOx# pin configured as an input on the first device in the series, data is loaded from the three sets of 6-bit Data Inputs into the first three 6-bit Input-Register locations. On subsequent transitions of the DCLK, data continues to be loaded into the remaining 6-bit Input-Register locations. When the register is full (240 words), the EIOx# pin configured as an output goes `low', enabling the next driver. The data load sequence is summarized in Table 5-1, Figure 5-1 and Figure 5-2. Table 5-1: Input/Output Selection for EIO1# and EIO240 EIO240# LD240 LD240_1 Input EIO1#, EIO240 EIO240# Functionality Data Loading Sequence EIO240 EIO240# `0' Input Output Channel 1 to 240 `1' July 21, 1999 Rev. 0.01 EIO1# Output Input Channel 240 to 1 © 1999 Winbond Electronics Winbond Electronics Confidential 13 WFP6530B WFP6530B 240-Channel 6-Bit Signal Driver for COG TFT-LCDs D05-D D05-D 00 DCLK First Input Bus LP D25-D20 D25-D20 D15-D10 D15-D10 D05-D00 D05-D00 D25-D20 D25-D20 D 15-D 10 D05-D00 D05-D00 D25-D20 D25-D20 D15-D D15-D 10 D05-D D05-D 00 Input Bus DCLK Last D25-D20 D25-D20 D 15-D 10 D05-D00 D05-D00 . Data loaded from channel VS240 VS240 to VS1 (LD240 LD240_1 = `1') D25-D20 D25-D20 D15-D10 D15-D10 D05-D00 D05-D00 LP D25-D D25-D 20 D15-D D15-D 10 D05-D00 D05-D00 Input Reg. VS240 VS240 VS239 VS239 VS238 VS238 VS3 VS2 VS1 Storage Reg. Input Reg. First . D15-D D15-D 10 D25-D20 D25-D20 D15-D10 D15-D10 D05-D00 D05-D00 D25 -D20 D15-D D15-D 10 D05-D00 D05-D00 . D25-D20 D25-D20 Last . Data loaded from channel VS1 to VS240 VS240 (LD240 LD240_1 = `0') D25-D20 D25-D20 D15-D10 D15-D10 D05-D00 D05-D00 VS240 VS240 VS239 VS239 VS238 VS238 VS3 VS2 VS1 Storage Reg. Figure 5­1. Display Data Sampling and Output Direction DCLK D05-D D05-D 00 VS1 VS4 Upper Bank D15-D D15-D 10 VS2 VS5 D25-D D25-D 20 VS3 VS6 D25-D D25-D 20 VS240 VS240 LD240 LD240_1 = `0' VS237 VS237 Lower Bank D15-D D15-D 10 VS239 VS239 VS236 VS236 D05-D D05-D 00 VS238 VS238 VS236 VS236 LD240 LD240_1 = `1' Figure 5­2. Display Data Channel Assignment and Output Sequence 14 © 1999 Winbond Electronics Winbond Electronics Confidential July 21, 1999 Rev. 0.01 WFP6530B WFP6530B 240-Channel 6-Bit Signal Driver for COG TFT-LCDs Name Number VS1-VS240 VS1-VS240 42-282 O VOLTAGE OUTPUTS: These outputs drive all 240 pixel inputs of the LCD simultaneously after the high-to-low transition of LP. Outputs are high impedance while LP is high. D05-D00 D05-D00 D15-D10 D15-D10 D25-D20 D25-D20 35-40 I 8,13,14,27-29 2-7 DATA: The Data inputs consist of 6-bit words for each of three channels. At the falling edge of DCLK, three 6-bit words for three adjacent channels are loaded in parallel. Each data bit is represented as Dij where: i = 2-0 indicates the channel j = 5-0 indicates the significance of the bit in each word. Di5 indicates the MSB and Di0 indicates the LSB of the input word. LP 34 I Latch Pulse: When LP is asserted, the data is transferred from the Input Register into the Storage Register, and the selected analog voltages drive the LCD. Also, the EIOx# output is reset to the `high' level. DCLK 15 I DATA CLOCK: Data is loaded into the input registers on the high-to-low transition of DCLK for 2xCLK= low and on both rising and falling edges of DCLK for 2xCLK = high. CLAMP# 30 I CLAMP: The CLAMP# input controls the active pulldown devices which are present on the DCLK and D00-D D00-D 25 inputs. When the CLAMP# signal drives low, these clamp devices connect DCLK and D 00 -D 25 to the WFP6530B WFP6530B's GND through a low impedance. The CLAMP# pin should be connected to VDDD in applications where level shifting is not used (i.e. when VCOM modulation is employed). VDDD 16 I DIGITAL SUPPLY VOLTAGE: Either 3.3 V or 5.0 V should be provided on this pin to supply digital power to the device. VDDA 17 I ANALOG SUPPLY VOLTAGE: Up to 5.0 V should be provided on this pin to supply analog power to the device. V8 V7 V6 V5 V4 V3 V2 V1 V0 11,31 18 23 20 21 22 19 24 10,32 I REFERENCE ANALOG VOLTAGE INPUTS: These nine inputs are used to supply the adjustable-reference voltage inputs to the resistive-string DAC to provide the transmissivity-voltage response required for each type of LCD. Note: both V8 pads must be connected to each other and to the same potential; also, both V0 pads must be . connected to each other and to the same potential AGND 25 I ANALOG GROUND DGND 26 I DIGITAL GROUND July 21, 1999 Rev. 0.01 Type Description (Cont.) © 1999 Winbond Electronics Winbond Electronics Confidential 15 WFP6530B WFP6530B 240-Channel 6-Bit Signal Driver for COG TFT-LCDs DATA_INV 33 I DATA INVERSION: The data inversion input signal, when logic high, enables inversion of the input display data (Dij). This pad should be tied "low" if data inversion is not used. See Figure 7-1 and 7-6 for timing information for this signal. 2xCLK 12 I 2xCLK: When logic high, the 2xCLK input enables sampling of input display data (Dij) on both rising and falling edges of the DCLK input (see Figure 7-2). When logic low, input display data is sampled on the falling edge of DCLK only (see Figure 7-1). 16 © 1999 Winbond Electronics Winbond Electronics Confidential July 21, 1999 Rev. 0.01 WFP6530B WFP6530B 240-Channel 6-Bit Signal Driver for COG TFT-LCDs Table 5-2: Input Data vs. Output Voltage MSB D5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 July 21, 1999 Rev. 0.01 D4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Display Data D3 D2 D1 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 1 1 0 0 1 0 0 1 0 1 1 0 1 1 1 0 1 1 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 1 1 0 0 1 0 0 1 0 1 1 0 1 1 1 0 1 1 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 1 1 0 0 1 0 0 1 0 1 1 0 1 1 1 0 1 1 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 1 1 0 0 1 0 0 1 0 1 1 0 1 1 1 0 1 1 0 1 1 1 1 1 1 LSB D0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Refer. Voltage V0, V0 V0, V1 V0, V1 V0, V1 V0, V1 V0, V1 V0, V1 V0, V1 V1, V2 V1, V2 V1, V2 V1, V2 V1, V2 V1, V2 V1, V2 V1, V2 V2, V3 V2, V3 V2, V3 V2, V3 V2, V3 V2, V3 V2, V3 V2, V3 V3, V4 V3, V4 V3, V4 V3, V4 V3, V4 V3, V4 V3, V4 V3, V4 V4, V5 V4, V5 V4, V5 V4, V5 V4, V5 V4, V5 V4, V5 V4, V5 V5, V6 V5, V6 V5, V6 V5, V6 V5, V6 V5, V6 V5, V6 V5, V6 V6, V7 V6, V7 V6, V7 V6, V7 V6, V7 V6, V7 V6, V7 V6, V7 V7, V8 V7, V8 V7, V8 V7, V8 V7, V8 V7, V8 V7, V8 V7, V8 Output Voltage V0 V0 + 1/7 x (V1 - V0) V0 + 2/7 x (V1 - V0) V0 + 3/7 x (V1 - V0) V0 + 4/7 x (V1 - V0) V0 + 5/7 x (V1 - V0) V0 + 6/7x (V1 - V0) V1 V1 + 1/8 x (V2 - V1) V1 + 2/8 x (V2 - V1) V1 + 3/8 x (V2 - V1) V1 + 4/8 x (V2 - V1) V1 + 5/8 x (V2 - V1) V1 + 6/8 x (V2 - V1) V1 + 7/8 x (V2 - V1) V2 V2 + 1/8 x (V3 - V2) V2 + 2/8 x (V3 - V2) V2 + 3/8 x (V3 - V2) V2 + 4/8 x (V3 - V2) V2 + 5/8 x (V3 - V2) V2 + 6/8 x (V3 - V2) V2 + 7/8 x (V3 - V2) V3 V3 + 1/8 x (V4 - V3) V3 + 2/8 x (V4 - V3) V3 + 3/8 x (V4 - V3) V3 + 4/8 x (V4 - V3) V3 + 5/8 x (V4 - V3) V3 + 6/8 x (V4 - V3) V3 + 7/8 x (V4 - V3) V4 V4 + 1/8 x (V5 - V4) V4 + 2/8 x (V5 - V4) V4 + 3/8 x (V5 - V4) V4 + 4/8 x (V5 - V4) V4 + 5/8 x (V5 - V4) V4 + 6/8 x (V5 - V4) V4 + 7/8 x (V5 - V4) V5 V5 + 1/8 x (V6 - V5) V5 + 2/8 x (V6 - V5) V5 + 3/8 x (V6 - V5) V5 + 4/8 x (V6 - V5) V5 + 5/8 x (V6 - V5) V5 + 6/8 x (V6 - V5) V5 + 7/8 x (V6 - V5) V6 V6 + 1/8 x (V7 - V6) V6 x 2/8 x (V 7 - V6) V6 + 3/8 x (V7 - V6) V6 + 4/8 X (V7 - V6) V6 + 5/8 x (V7 - V6) V6 + 6/8 x (V7 - V6) V6 + 7/8 x (V7 - V6) V7 V7 + 1/8 x (V8 - V7) V7 + 2/8 x (V8 - V7) V7 + 3/8 x (V8 - V7) V7 + 4/8 x (V8 - V7) V7 +5/8 x (V8 - V7) V7 + 6/8 x (V8 - V7) V7 + 7/8 x (V8 - V7) V8 © 1999 Winbond Electronics Winbond Electronics Confidential 17 WFP6530B WFP6530B 240-Channel 6-Bit Signal Driver for COG TFT-LCDs 6. 6.1 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings Symbol Parameter Min Max Units Notes VDDD Digital Power Supply Voltage -0.3 smaller of 6.0 or VDDA Volts 1,2,4 VDDA Analog Power Supply Voltage -0.3 6.0 Volts 1,2,4 V8 - V0 Analog Reference Voltage Inputs -0.3 VDDA + 0.3 Volts 1,2 VS240-VS1 VS240-VS1 Output Voltage -0.3 VDDA + 0.3 Volts 1,2 VIN Voltage on any Digital Input -0.3 VDDD + 0.3 Volts 1,2,3 PD Operating Power Dissipation 300 mW TA Operating Temperature (Ambient Temperature under bias) -10 85 °C 1 TSTR Storage Temperature -20 85 °C 1 NOTES: 1) Stresses above those listed may cause permanent damage to system components. These are stress ratings only. Functional operation at these or any conditions above those indicat ed in the operational ratings of this specification is not implied. Exposure to absolute maxi mum rating conditions for extended periods may affect system reliability. 2) All voltages are with respect to ground (GND) unless otherwise noted. 3) For D25-D20 D25-D20, D15-D10 D15-D10, D05-D00 D05-D00, DCLK, LP, CLAMP#, EIO1#, EIO240 EIO240# and LD240 LD240_1 input pads. 4) VDDA must be greater than or equal to VDDD for proper circuit operation. For this reason, VDDA should be powered on first (or at the same time as VDDD). Also, VDDD should be powered off first, or at same time as VDDA. 18 © 1999 Winbond Electronics Winbond Electronics Confidential July 21, 1999 Rev. 0.01 WFP6530B WFP6530B 240-Channel 6-Bit Signal Driver for COG TFT-LCDs 6.2 Recommended Operating Conditions Symbol Parameter Min Typical Max Units Notes VDDD Digital Supply Voltage 3.0 4.5 3.3 5.0 3.6 5.5 Volts Volts 1 1 VDDA Analog Supply Voltage 4.5 5.0 5.5 Volts 1 TA Ambient Temperature 0 25 70 °C V8 - V0 Analog Reference Voltage 0 VDDA Volts IREF Analog Reference Current 20 mA NOTES: 1) 2) July 21, 1999 Rev. 0.01 1, 2 All voltages are with respect to ground (GND) unless otherwise noted. Case I: VDDAV8V7V6V5V4V3V2V1V0 Case II: VDDAV0V1V2V3V4V5V6V7V8 © 1999 Winbond Electronics Winbond Electronics Confidential 19 WFP6530B WFP6530B 240-Channel 6-Bit Signal Driver for COG TFT-LCDs 6.3 DC Characteristics (Preliminary data ­ subject to change) VDDA = 5 V ± 0.5 V, TA = 25° C, unless otherwise specified Symbol Parameter Min VS Analog Output Voltage VST Analog Output Transition Band VERR Analog Output Error Voltage VIH Logic Input high Voltage VIL Logic Input low Voltage VOH Logic Output high Voltage VOL Logic Output low Voltage IQR Reference Quiescent Current IDDA Analog Supply Current IDDD Digital-Supply Current (active) IDDD Digital-Supply Current (Stand-by) IIN Input Leakage Current CIN Input Capacitance RString String Resistance ROUT Typ Output Resistance V0-V1 ( at code 3) V1-V2 ( at code 11) V2-V3 ( at code 19) V3-V4 ( at code 27) V4-V5 ( at code 35) V5-V6 ( at code 43) V6-V7 ( at code 51) V7-V8 ( at code 59) NOTES: 1) 2) 20 Max Units Test Conditions Note VDDA-0.03 |V8-V0| Volts +0.15 LSB 2 Volts -0.15 Volts 3 Volts 3 0.8VDDD 0.2VDDD VDDD - 0.4 1 IOH = - 0.4 mA 4 0.4 Volts IOL = 0.4 mA 4 3.4 mA 400 µA VDDA = 5.0 V 6 3.8 6.4 7 10 mA mA VDDD = 3.3 V VDDD = 5.0 V 6 80 200 400 600 µA µA VDDD = 3.3 V VDDD = 5.0 V 7 +5 µA 0 < VIN < VDDD 5 2.8 Volts pF 395 281 239 239 239 239 281 447 24.5 18.1 15.6 15.6 15.6 15.6 18.1 28.1 k 3.1 -5 V0-V1 V1-V2 V2-V3 V3-V4 V4-V5 V5-V6 V6-V7 V7-V8 213 151 129 129 129 129 151 241 304 216 184 184 184 184 216 344 5 8 See Table 5-2 for digital code-Voltage relationship. For all codes. Error is difference between measured voltage & Table 5-2 value. © 1999 Winbond Electronics Winbond Electronics Confidential July 21, 1999 Rev. 0.01 WFP6530B WFP6530B 240-Channel 6-Bit Signal Driver for COG TFT-LCDs NOTES: cont'd 3) DCLK, LP, CLAMP#, D25-D20 D25-D20, D15-D10 D15-D10, D 05-D00 05-D00, EIO1#, EIO240 EIO240#, and LD240 LD240_1 inputs 4) 5) EIO1# and EIO240 EIO240# outputs Quiescent current between V0 and V8 with |V0-V8| = 5.0 V and all other references floating 6) fDCLK=12.5 MHz, fLP = 30 kHz, device is loading ,100% of data lines toggle each DCLK cycle 7) fDCLK=12.5 MHz, fLP = 30 kHz, device is not loading,100% of data lines toggle each DCLK cycle. 8) Effective output resistance at output with highest resistance when all outputs drive the same code. See Figure 6-5. July 21, 1999 Rev. 0.01 © 1999 Winbond Electronics Winbond Electronics Confidential 21 WFP6530B WFP6530B 240-Channel 6-Bit Signal Driver for COG TFT-LCDs 6.4 AC Characteristics (VDDD = 3.3 V ± 0.3 V) ­ (Preliminary data ­ subject to change) See Figures 7-2 and 7-3 for waveforms. Conditions: VDDA = 5.0 V ± 0.5 V, TA = 25° C Symbol Parameter Min fCLK Guaranteed DCLK frequency tCLK Typical Max Units 65 MHz DCLK period 15.4 ns t2xCLK DCLK period (2xCLK mode) 30.8 ns t1 DCLK high pulse width 6 ns t2 DCLK low pulse width 6 ns t3 DCLK, LP rise time 10 ns t4 DCLK, LP fall time 10 ns t5 Data, DATA_INV setup time to DCLK Falling Edge 4 ns t6 Data, DATA_INV hold time from DCLK Falling Edge 8 ns t7 LP high pulse width 50 ns t8 Enable-In setup time to DCLK 4 ns t9 Enable-Out low delay from DCLK t10 DCLK low LP high 50 ns t11 LP low to DCLK high 50 ns t12 Data, DATA_INV setup time to DCLK Rising Edge 4 ns t13 Data, DATA_INV hold time from DCLK Rising Edge 8 Note ns NOTES: 1) 2) 22 10 ns 2 1 CLOAD = 15 pF (See Figure 7-4) LP width should not be wider than necessary since outputs don't drive to the next value until LP is low. © 1999 Winbond Electronics Winbond Electronics Confidential July 21, 1999 Rev. 0.01 WFP6530B WFP6530B 240-Channel 6-Bit Signal Driver for COG TFT-LCDs 6.5 AC Characteristics (VDDD = 5.0 V ± 0.5 V) ­ (Preliminary data ­ subject to change) See Figures 7-2 and 7-3 for waveforms. Conditions: VDDA = 5.0 V ± 0.5 V, TA = 25° C Symbol Parameter Min fCLK Guaranteed DCLK frequency tCLK Typical Max Units 65 MHz DCLK period 15.4 ns t2xCLK DCLK period (2xLCK mode) 30.8 ns t1 DCLK high pulse width 6 ns t2 DCLK low pulse width 6 ns t3 DCLK, LP rise time 10 ns t4 DCLK, LP fall time 10 ns t5 Data, DATA_INV setup time to DCLK Falling Edge 4 ns t6 Data, DATA_INV hold time from DCLK Falling Edge 8 ns t7 LP high pulse width 40 ns t8 Enable-In setup time to DCLK 4 ns t9 Enable-Out low delay from DCLK t10 DCLK low to LP high 40 ns t11 LP low to DCLK high 40 ns t12 Data, DATA_INV setup time to DCLK Rising Edge 4 ns t13 Data, DATA_INV hold time from DCLK Rising Edge 8 Note ns NOTES: 1) 2) July 21, 1999 Rev. 0.01 10 ns 2 1 CLOAD = 15 pF (See Figure 7-4). LP width should not be wider than necessary since outputs don't drive to the next value until LP is low. © 1999 Winbond Electronics Winbond Electronics Confidential 23 WFP6530B WFP6530B 240-Channel 6-Bit Signal Driver for COG TFT-LCDs t3 t4 t1 0.8VDDD 0.2VDDD DCLK tCLK t2 0.2VDDD 0.2VDDD t5 t6 0.8VDDD D ij ,DATA_INV 0.2VDDD Figure 6-1: DCLK and Data Input Timing Relationship with 2xCLK = low t4 t3 t1 DCLK t2xCLK t2 0.8VDDD 0.8V DDD 0.2VDDD 0.2VDDD 0.2VDDD t5 t6 t12 t13 0.8VDDD Dij, DATA_INV 0.2VDDD DATAn DATAn+1 Figure 6-2: DCLK and Data Input Timing Relationship with 2xCLK = high Note: When 2xCLK = high, the first rising edge of DCLK after LP falling edge clocks in the first display data word 24 © 1999 Winbond Electronics Winbond Electronics Confidential July 21, 1999 Rev. 0.01 WFP6530B WFP6530B 240-Channel 6-Bit Signal Driver for COG TFT-LCDs t7 t3 t4 0.8VDDD LP 0.2VDDD t10 DCLK[1] t11 DCLK[80] 0.8V DDD DCLK 0.2VDDD 0.2VDDD t9 Enable Output Enable Input 0.8VDDD t8 0.2VDDD 0.2VDDD Figure 6-3: LP, DCLK, EIO1#and EIO240 EIO240# Timing Relationship Enable Out EIO1#, EIO240 EIO240# CL= 15pF Figure 6-4: Capacitive Load Test Circuit any output VS1-VS240 VS1-VS240 V ROUT CL (column capacitance) Figure 6-5: ROUT Definition July 21, 1999 Rev. 0.01 © 1999 Winbond Electronics Winbond Electronics Confidential 25 WFP6530B WFP6530B 240-Channel 6-Bit Signal Driver for COG TFT-LCDs Data ij Pads 00Hex 00Hex 00Hex 3FHex 00Hex 3FHex Data_Inv Data ij Internal LP VOUTX V0 V63 V0 Figure 6-6: Data Inversion Example Updates from Previous Version Date of Issue Page 2,4 Description Die Size Corrected 4 3 Resistor String Values in Table 2-1 & Figure 2-1 21 Voltage-Code table reflect new r-string val 30 RString,R OUT, IQR 30 Feb. 18, 1996 Bump Height Spec Corrected VERR spec and Note 2 32-34 Add t2xCLK spec for 2xCLK mode Updates from Previous Version Date of Issue Page 2,4 Description Change die size 5 Oct. 8, 1996 Change max bump hardness to 80 HV 4,5,11 Decription of additional dummy bumps D1-D14 D1-D14 25 26 Replace Figure 6-5 to show definition of ROUT. © 1999 Winbond Electronics Winbond Electronics Confidential July 21, 1999 Rev. 0.01