WE128K32-XG2TXE I/O0-31 A0-16 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 I/O16 I/O17 - Datasheet Archive

 

HI-RELIABILITY PRODUCT 128Kx32 EEPROM MODULE ADVANCED* FEATURES s Access Times of 150, 200, 250, 300ns s Packaging: · 68

 

WE128K32-XG2TXE WE128K32-XG2TXE HI-RELIABILITY PRODUCT 128Kx32 EEPROM MODULE ADVANCED* FEATURES s Access Times of 150, 200, 250, 300ns s Packaging: · 68 lead, Hermetic CQFP (G2T), 22.4mm (0.880") square, 4.57mm (0.180") high (Package 509). Designed to fit JEDEC 68 lead 0.990" CQFJ footprint (Fig. 1) s Organized as 128Kx32; User Configurable as 256Kx16 or 512Kx8 s CMOS: s s s s s s s Automatic Page Write Operation Page Write Cycle Time: 10ms Max Data Polling for End of Write Detection Hardware and Software Data Protection TTL Compatible Inputs and Outputs 5 Volt Power Supply Built-in Decoupling Caps and Multiple Ground Pins for Low Noise Operation s Weight WE128K32-XG2TXE WE128K32-XG2TXE - 8 grams typical · Radiation Tolerant with Epitaxial Layer Die s s s s Write Endurance 10,000 Cycles Data Retention Ten Years Minimum (at +25°C) Commercial, Industrial and Military Temperature Ranges Low Power CMOS FIG. 1 * This data sheet describes a product that may or may not be under development and is subject to change or cancellation without notice. TOP VIEW PIN DESCRIPTION RESET A0 A1 A2 A3 A4 A5 CS3 GND CS4 WE1 A6 A7 A8 A9 A10 VCC PIN CONFIGURATION FOR WE128K32-XG2TXE WE128K32-XG2TXE I/O0-31 I/O0-31 Data Inputs/Outputs A0-16 A0-16 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 GND I/O8 I/O9 I/O10 I/O10 I/O11 I/O11 I/O12 I/O12 I/O13 I/O13 I/O14 I/O14 I/O15 I/O15 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 I/O16 I/O16 I/O17 I/O17 I/O18 I/O18 I/O19 I/O19 I/O20 I/O20 I/O21 I/O21 I/O22 I/O22 I/O23 I/O23 GND I/O24 I/O24 I/O25 I/O25 I/O26 I/O26 I/O27 I/O27 I/O28 I/O28 I/O29 I/O29 I/O30 I/O30 I/O31 I/O31 Chip Selects OE Output Enable VCC Power Supply GND Ground 0.940" The White 68 lead G2T CQFP RESET Reset fills the same fit and function as NC Not Connected the JEDEC 68 lead CQFJ or 68 PLCC. But the G2T has the TCE and lead inspection advantage BLOCK DIAGRAM of the CQFP form. WE1 CS1 WE2 CS 2 WE3 CS3 WE 4 CS 4 RESET OE A0-16 A0-16 NC NC NC WE4 WE3 A16 CS1 OE CS2 NC WE2 A15 A14 A13 A12 A11 VCC Write Enables CS1-4 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 128K x 8 8 I/O0-7 September 1999 Rev. 3 Address Inputs WE1-4 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 1 128K x 8 8 I/O8-15 I/O8-15 128K x 8 8 I/O16-23 I/O16-23 128K x 8 8 I/O24-31 I/O24-31 White Electronic Designs Corporation · Phoenix, AZ · (602) 437-1520 WE128K32-XG2TXE WE128K32-XG2TXE ABSOLUTE MAXIMUM RATINGS Parameter Symbol TRUTH TABLE Unit -55 to +125 -65 to +150 °C VG -0.6 to +6.25 V -0.6 to +13.5 V TA Storage Temperature Signal Voltage Relative to GND CS H L L X X X °C T STG Operating Temperature Voltage on OE and A9 NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. WE X H L X H X Mode Standby Read Write Out Disable Write Inhibit Data I/O High Z Data Out Data In High Z/Data Out CAPACITANCE (TA = +25°C) Parameter Symbol Conditions Max Unit OE capacitance RECOMMENDED OPERATING CONDITIONS Parameter OE X L H H X L COE VIN = 0 V, f = 1.0 MHz 50 pF Symbol Min Max Unit WE1-4 capacitance CWE VIN = 0 V, f = 1.0 MHz 20 pF Supply Voltage V CC 4.5 5.5 V CS1-4 capacitance CCS VIN = 0 V, f = 1.0 MHz 20 pF Input High Voltage (1) V IH 2.2 V CC + 0.3 V Data I/O capacitance CI/O VI/O = 0 V, f = 1.0 MHz 20 pF Input Low Voltage (2) V IL -0.5 +0.8 V Address input capacitance CAD VIN = 0 V, f = 1.0 MHz 50 pF Operating Temp. (Mil.) TA -55 +125 °C Operating Temp. (Ind.) TA -40 +85 °C This parameter is guaranteed by design but not tested. 1. RESET VIH = Vcc -0.5V min, Vcc +1V max. 2. RESET VIL = -1.0V for pulse width 50ns. DC CHARACTERISTICS (VCC = 5.0V, VSS = 0V, TA = -55°C to +125°C) Parameter Symbol Input Leakage Current (1) Max Unit VCC = 5.5, VIN = GND to VCC Conditions ILI Min 10 µA Output Leakage Current ILOx32 CS = VIH, OE = VIH, VOUT = GND to VCC 10 µA Operating Supply Current x 32 Mode ICCx32 CS = VIL, OE = VIH, f = 5MHz 250 mA Standby Current ISB CS = VIH, OE = VIH, f = 5MHz 4.5 mA Output Low Voltage VOL IOL = 2.1mA, VCC = 4.5V 0.40 Output High Voltage VOH IOH = -400µA, VCC = 4.5V V 2.4 V NOTE: DC test conditions: VIH = VCC -0.3V, VIL = 0.3V 1. RESET ILI = 0.8mA max FIG. 2 AC TEST CIRCUIT AC TEST CONDITIONS Parameter I OL Current Source Typ Unit Input Pulse Levels 1.5V (Bipolar Supply) C eff = 50 pf I OH Current Source White Electronic Designs Corporation · Phoenix, AZ · (602) 437-1520 2 5 ns Input and Output Reference Level VZ V Input Rise and Fall D.U.T. VIL = 0, VIH = 3.0 1.5 V Output Timing Reference Level 1.5 V NOTES: V Z is programmable from -2V to +7V. I OL & IOH programmable from 0 to 16mA. Tester Impedance Z0 = 75 . V Z is typically the midpoint of VOH and V OL. I OL & IOH are adjusted to simulate a typical resistive load circuit. ATE tester includes jig capacitance. WE128K32-XG2TXE WE128K32-XG2TXE AC WRITE CHARACTERISTICS (VCC = 5.0V, VSS = 0V, TA = -55°C to +125°C) WRITE A write cycle is initiated when OE is high and a low pulse is on WE or CS with CS or WE low. The address is latched on the falling edge of CS or WE whichever occurs last. The data is latched by the rising edge of CS or WE, whichever occurs first. A byte write operation will automatically continue to completion. Write Cycle Parameter Symbol Min Max Unit 10 ms Write Cycle Time, TYP = 6ms tWC Address Set-up Time tAS 0 ns Write Pulse Width (WE or CS) tWP 250 ns Chip Select Set-up Time ns tDH 10 ns tCH 0 ns Data Set-up Time tDS 100 ns Output Enable Set-up Time tOES 0 ns Output Enable Hold Time tOEH 0 ns Byte Load Cycle tBL 1 µs Reset High Time tRES 1 µs Reset Protect Time 3 ns 150 Chip Select Hold Time The WE line transition from high to low also initiates an internal 150 µsec delay timer to permit page mode operation. Each subsequent WE transition from high to low that occurs before the completion of the 150 µsec time out will restart the timer from zero. The operation of the timer is the same as a retriggerable one-shot. 0 tAH Data Hold Time Figures 3 and 4 show the write cycle timing relationships. A write cycle begins with address application, write enable and chip select. Chip select is accomplished by placing the CS line low. Write enable consists of setting the WE line low. The write cycle begins when the last of either CS or WE goes low. tCS Address Hold Time WRITE CYCLE TIMING tRP 100 µs White Electronic Designs Corporation · Phoenix, AZ · (602) 437-1520 WE128K32-XG2TXE WE128K32-XG2TXE FIG. 3 WRITE WAVEFORMS WE CONTROLLED t WC ADDRESS t CS tCH t AH CS t BL t AS t WP WE t OEH t OES OE t DS t DH DATA IN t RP t RES RESET Vcc FIG. 4 WRITE WAVEFORMS CS CONTROLLED t WC ADDRESS t WS t WH t AH WE t BL t AS t CW CS t OEH t OES OE t DS DATA IN t RES t RP RESET Vcc White Electronic Designs Corporation · Phoenix, AZ · (602) 437-1520 4 t DH WE128K32-XG2TXE WE128K32-XG2TXE READ The WE128K32-XG2TXE WE128K32-XG2TXE stores data at the memory location determined by the address pins. When CS and OE are low and WE is high, this data is present on the outputs. When CS and OE are high, the outputs are in a high impedance state. This two line control prevents bus contention. AC READ CHARACTERISTICS (VCC = 5.0V, VSS = 0V, TA = -55°C to +125°C) Read Cycle Parameter Symbol -150 Min 150 -200 Max Min 200 -250 Max Min 250 -300 Max Min 300 Unit Max Read Cycle Time t RC Address Access Time t ACC 150 200 250 300 ns Chip Select Access Time t ACS 150 200 250 300 ns Output Hold from Add. Change, OE or CS t OH 0 Output Enable to Output Valid t OE 10 85 ns 0 75 10 0 75 10 ns 0 85 10 ns Chip Select or OE to High Z Output t DF 55 55 70 70 ns RESET Low to Output Float t DFR 350 350 350 350 ns RESET to Output Delay t RR 450 450 450 450 ns FIG. 5 READ WAVEFORMS t RC ADDRESS ADDRESS VALID CS t ACS t OE OE tDF tACC OUTPUT HIGH Z tOH OUTPUT VALID t RR t DFR RESET NOTES: OE may be delayed up to tACS - tOE after the falling edge of CS without impact on tOE or by t ACC - tOE after an address change without impact on tACC . 5 White Electronic Designs Corporation · Phoenix, AZ · (602) 437-1520 WE128K32-XG2TXE WE128K32-XG2TXE DATA POLLING The WE128K32-XG2TXE WE128K32-XG2TXE offers a data polling feature which allows a faster method of writing to the device. Figure 6 shows the timing diagram for this function. During a byte or page write cycle, an attempted read of the last byte written will result in the complement of the written data on D7 (for each chip.) Once the write cycle has been completed, true data is valid on all outputs and the next cycle may begin. Data polling may begin at any time during the write cycle. DATA POLLING CHARACTERISTICS (VCC = 5.0V, VSS = 0V, TA = -55°C to +125°C) Parameter Symbol Min Data Hold Time tDH 10 OE Hold Time tOEH 0 OE To Output Valid tOE Max Unit ns ns 55 ns FIG. 6 DATA POLLING WAVEFORMS WE CS t OEH OE I/O7 t DH t OE HIGH Z ADDRESS White Electronic Designs Corporation · Phoenix, AZ · (602) 437-1520 6 WE128K32-XG2TXE WE128K32-XG2TXE PAGE WRITE OPERATION PAGE WRITE CHARACTERISTICS (VCC = 5.0V, VSS = 0V, TA = -55°C to +125°C) The WE128K32-XG2TXE WE128K32-XG2TXE has a page write operation that allows one to 128 bytes of data to be written into the device and consecutively loads during the internal programming period. Successive bytes may be loaded in the same manner after the first data byte has been loaded. An internal timer begins a time out operation at each write cycle. If another write cycle is completed within 30µs or less, a new time out period begins. Each write cycle restarts the delay period. The write cycles can be continued as long as the interval is less than the time out period. Page Mode Write Characteristics Parameter Symbol Min Max Unit 10 ms Write Cycle Time, TYP = 6ms Address Set-up Time 0 ns tAH 150 ns Data Set-up Time tDS 100 ns Data Hold Time tDH 10 ns Write Pulse Width tWP 250 ns Byte Load Cycle Time (1) tBLC Byte Load Window (1) tBL 100 µs Data Latch Time tDL 300 ns RESET Protect Time (1) After the 30µs time out is completed, the EEPROM begins an internal write cycle. During this cycle the entire page of bytes will be written at the same time. The internal programming cycle is the same regardless of the number of bytes accessed. tAS Address Hold Time The usual procedure is to increment the least significant address lines from A0 through A6 at each write cycle. In this manner a page of up to 128 bytes can be loaded in to the EEPROM in a burst mode before beginning the relatively long interval programming cycle. tWC tRP 100 µs 1 µs RESET High Time (1) tRES 1. This parameter is guarenteed by design but not tested. 30 µs FIG. 7 PAGE WRITE WAVEFORMS CS CONTROLLED(1) ADDRESS (2) A0-16 A0-16 tAS tWP WE t BL tAH tDL t CS tCH t BLC t WC CS t OES t OEH OE tDH t DS DATA IN t RP RESET t RES Vcc NOTES: 1. t DF and t DFR are defined as the time at which the outputs achieve the open circuit conditions and are no longer driven. 7 White Electronic Designs Corporation · Phoenix, AZ · (602) 437-1520 WE128K32-XG2TXE WE128K32-XG2TXE FIG. 8 SOFTWARE DATA PROTECTION ENABLE ALGORITHM(1) LOAD DATA AA TO ADDRESS 5555 © LOAD DATA 55 TO ADDRESS 2AAA © WRITES ENABLED(2) © LOAD DATA A0 TO ADDRESS 5555 © LOAD DATA XX TO ANY ADDRESS(4) LOAD LAST BYTE TO LAST ADDRESS ENTER DATA PROTECT STATE NOTES: 1. Data Format: D7 - D0 (Hex); Address Format: A16 - A0 (Hex). 2. Write Protect state will be activated at end of write even if no other data is loaded. 3. Write Protect state will be deactivated at end of write period even if no other data is loaded. 4. 1 to 128 bytes of data may be loaded. White Electronic Designs Corporation · Phoenix, AZ · (602) 437-1520 8 WE128K32-XG2TXE WE128K32-XG2TXE SOFTWARE DATA PROTECTION FIG. 9 A software write protection feature may be enabled or disabled by the user. When shipped by White Microelectronics, the WE128K32-XG2TXE WE128K32-XG2TXE has the feature disabled. Write access to the device is unrestricted. SOFTWARE DATA PROTECTION DISABLE ALGORITHM(1) To enable software write protection, the user writes three access code bytes to three special internal locations. Once write protection has been enabled, each write to the EEPROM must use the same three byte write sequence to permit writing. After setting software data protection, any attempt to write to the device without the three-byte command sequence will start the internal write timers. No data will be written to the device, however, for the duration of tWC. The write protection feature can be disabled by a six byte write sequence of specific data to specific locations. Power transitions will not reset the software write protection. LOAD DATA AA TO ADDRESS 5555 © LOAD DATA 55 TO ADDRESS 2AAA © LOAD DATA 80 TO ADDRESS 5555 © Each 128K byte block of the EEPROM has independent write protection. One or more blocks may be enabled and the rest disabled in any combination. The software write protection guards against inadvertent writes during power transitions, or unauthorized modification using a PROM programmer. LOAD DATA AA TO ADDRESS 5555 © LOAD DATA 55 TO ADDRESS 2AAA © HARDWARE DATA PROTECTION a) Write inhibiting Holding OE low and either CS or WE high inhibits write cycles. LOAD LAST BYTE TO LAST ADDRESS b) Noise filter Pulses of