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Part : WD76C30D-JU Supplier : Western Digital Manufacturer : Bristol Electronics Stock : 135 Best Price : $15.9228 Price Each : $18.00
Part : WD76C30DJU Supplier : Western Digital Manufacturer : Chip One Exchange Stock : 12 Best Price : - Price Each : -
Part : WD76C30DJU Supplier : Western Digital Manufacturer : Chip One Exchange Stock : 12 Best Price : - Price Each : -
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WD76C30 Datasheet

Part Manufacturer Description PDF Type
WD76C30 N/A DEVICE PROVIDES THREE FUNCTIONAL GROUPS Scan
WD76C30 Western Digital It is a Peripheral Controller, Interrupt Multiplexer, and Clock Generator Scan
WD76C30LV Western Digital It is a Peripheral Controller, Interrupt Multiplexer, and Clock Generator Scan

WD76C30

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: DIFFERENCES Both the WD76C30 and WD76C30LV operate with two power supplies. The WD76C30 logic is pow ered , serial port interfaces are only supported by the WD76C30. ADVANCED INFORMATION 11/19/91 6-1 , WD76C30/L V DESCRIPTION 1.0 DESCRIPTION 1.1 WD76C30/LV FEATURES 1.2 â'¢ Two , WD76C30/LV device provides three functional groups. It is a Peripheral Controller, Interrupt Mul­ tiplexer, and Clock Generator. The low power CMOS WD76C30/LV is a single device solution which provides -
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WD76C30/L WD76C30/LV WD16C452 WD16C552 WD76C10 IRQ14
Abstract: maximum recommended data rate of 512 Kbaud. 1.3 WD76C30/LV DIFFERENCES Both the WD76C30 and WD76C30LV operate with two power supplies. The WD76C30 logic is powered by a 5.0 volt supply, while the WD76C30LV , WD76C30. ADVANCED INFORMATION 11/19/91 This Material Copyrighted By Its Respective Manufacturer 6-1 , DESCRIPTION WD76C30/L V 1.0 DESCRIPTION 1.1 WD76C30/LV FEATURES â'¢ Two fully programmable , inputs â'¢ 84-pin PLCC and PQFP packages 1.2 GENERAL The WD76C30/LV device provides three functional -
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intel 80287 D 80287-8 80287-8 WD16C450 IRQ9-12 intel 80C287 A20GT CLK287
Abstract: used to select the registers internal to the WD76C30. When Input/Output Write Strobe is asserted, data , DESCRIPTION WD76C30 1.0 1.1 DESCRIPTION FEATURES 1.2 GENERAL The WD76C30 device provides , 8-1 WD76C30 1.3 PERIPHERAL CONTROLLER DESCRIPTION (W D 16C 550 c o m p a tib le ) or a , CS2 AO · A2 FIGURE 1-1. W D76C30 BLOCK DIAGRAM 8-2 3/ 29/91 PIN DESCRIPTION WD76C30 , ASSIGNMENT 3/29/91 8-3 WD76C30 PIN DESCRIPTION PIN NUMBER 76 MNEMONIC BIDEN SIGNAL NAME -
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D16C550 80C287-10 Q-MATIC 76C30 D76C10 WD16C550 84-PIN
Abstract: only supported by the WD76C30. ADVANCED INFORMATION 11/19/91 6-1 WD76C30lLV 1.4 , WD76C30lLV DESCRIPTION 1.0 DESCRIPTION 1.1 WD76C30/LV FEATURES 1.2 · Two fully , and WD76C30LV operate with two power supplies. The WD76C30 logic is powered by a 5.0 volt supply , WD76C30, excluding the serial and parallel ports. +3.3V power supply to the WD76C30LV, excluding the , I. . WD76C30lLV TABLE OF CONTENTS Section Title 1.0 DESCRIPTION 1.1 Features -
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IR014 WD37C65 ir037 WQ76C30
Abstract: , especially those relating to "lap-top" devices. The set includes the WD76C10, the WD76C20, and the WD76C30 as , neaated. When used to enable and disable the WD76C30 48 MHz clock, CSEN acts as a strobe to a latch. When , issued as a chip select to the WD76C30 to enable the parallel port #0. 80 CSSSEB CSL Serial Port B Chip Select o CMOS chip select output decoded from CSL input lines and issued as a chip select to the WD76C30 , decoded from CSL input lines and issued as a chip select to the WD76C30 to enable the serial port A. REAL -
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nec 765 fdc LM 3771 hdd spindle motor WD7600 chn 850 7812 WD76C20/LV WD76C20LV WD90C20LV WD76C20/L WD76C20L 14MHZ
Abstract: & CSPARO stay asserted2 16H 1 0 1 1 0 48 MHz Clk Enable for WD76C30. CSL , the WD76C10, the WD76C20, and the WD76C30 as shown in Figure 1-1. Together these chips provide all , function of CSEN is neaated. When used to enable and disable the WD76C30 48 MHz clock, CSEN acts as a , select output decoded from CSL input lines and issued as a chip select to the WD76C30 to enable the , from CSL input lines and issued as a chip select to the WD76C30 to enable the serial port B. 81 -
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Abstract: ~~:) _ "' I~ I~ SD15:0 SA19:0 WD76C30 SEA, SEA, PAR, BUS INTERFACE 84 PIN POFP/PLCC , WD76C20, and the WD76C30 as shown in Figure 1-1. Together these chips provide all necessary logic to , function of CSEN is negated. When used to enable and disable the WD76C30 48 MHz clock, CSEN acts as a , select output decoded from CSL input lines and issued as a chip select to the WD76C30 to enable the , from CSL input lines and issued as a chip select to the WD76C30 to enable the serial port B. 81 -
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NEC 765A cmo 765 laptop HARD DISK CIRCUIT diagram floppy disk Stepper Motors EM- 546 stepper motor EPROM 27512
Abstract: Super I/O Configuration WD7615 with WD76C20/WD76C30 C o n fig u ra tio n , generic "Super I/O" device or w ith the WD76C20 and WD76C30 · Replaces majority of external "glue" logic , sea d d i 3042 a? h iiid c WD7615 FIGURE 1-3. WD7615 WITH WD76C20/WD76C30 -
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136-pin wd76c10a WD76C10LR 013Q3S DD13D3 A20GATE T-52-09 136-P 136-PIN
Abstract: during Suspend mode, signaling the WD76C30 to disable the 48 MHz crystal. Figure 2-6 illustrates the , function of CSEN is neaated. When used to enable and disable the WD76C30 48 MHz clock, CSEN acts as a , select to the WD76C30 to enable the parallel port #0. CMOS chip select output decoded from CSL input lines and issued as a chip select to the WD76C30 to enable the serial port B. CMOS chip select output decoded from CSL input lines and issued as a chip select to the WD76C30 to enable the serial port A. 72 -
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circuit diagram laptop motherboard plcc ide controller MC146818A D76C20 D76C2 8042CS
Abstract: CSPARO to remain low during Suspend mode, signaling the WD76C30 to disable the 48 MHz crystal. 2.2 , WD76C30 48 MHz clock, CSEN acts as a strobe to a latch. When it and DACKEN are both asserted, the TC , select output decoded from CSL input lines and issued as a chip select to the WD76C30 to enable the , lines and issued as a chip select to the WD76C30 to enable the serial port B. 81 CSSERA CSL Serial Port , the WD76C30 to enable the serial port A. Real Time Clock 58 RCLR RTC RAM Clear I A dual function -
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765 fdc FLOPPY STEPPER MOTOR diagram baling machine WD75C10 8042 PS2 WD92C32
Abstract: , WD76C30/WD7630LV â'¢ T he W D 76C 30 provides tw o serial ports system m em ory, video m em ory, and -
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80386SX D7900LV 7900L 7910L 7910X 7910LV
Abstract: are are provided. packaged in 84-pin PL C C s. WD76C30 T he W D 76C 30 provides tw o serial -
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Abstract: . Notebook Compatibles WD76C30 POWER MANAGEMENT DRIVERS 80386SX and 80286 T he W D 76C 30 -
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WD7600LP 7600L 80386S D76C-30
Abstract: inishing pow er m anagem ent capabilities. WD76C30 Laptop Compatibles P ow er M anagem en t D -
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132-P
Abstract: : '-.-, SD15:0 SA19:0 WD76C30 SER, SER, PAR, BUS INTERFACE 84 PIN POFP/PLCC irq in RAMDAC , description of this bit, refer to the WD76C30 Data Book, section 4.3 Bits 02-00 - Not used, state is ignored -
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WD76C10ALP d472 TRANSISTOR transistor d472 IT191 t2146 wd90c90 floppy disk chip WD76C1 WD76C10ALV CLK14 WD76C10AILPILV A23-A1
Abstract: "lap-top" devices. The set includes the W D 76C 10, the W D76C20ALV, and the WD76C30ALV as shown in Figure , enable and d isa ble the WD76C30ALV 48 MHz clock, CSEN acts as a strobe to a latch. When it and DACKEN , chip select to the WD76C30ALV to enable the parallel port #0. CSSERB CSL Serial Port B Chip Select , WD76C30ALV to enable the serial port B. CSSERA CSL Serial Port A Chip Select 0 TTL chip select output decoded from CSL input lines and issued as a chip select to the WD76C30ALV to enable the serial port A -
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WD76C20ALV WD76C20A 100-PIN
Abstract: SA19:0 IR015:3 irq in AT BUS SA19:0 s WD76C30 SER. SER. PAR. BUS INTERFACE 84 PIN POFP , Write Control Register. For a description of this bit, refer to the WD76C30 Data Book, section 4.3 -
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ht321 WD7910 WD7910LP WD7910/WD7910LP T-52-33-05
Abstract: ~~{~~~: I SD15:0 SA19:0 WD76C30 SER, SER, PAR, BUS INTERFACE 64 PIN POFP/PLCC IROI5:3 SD15:0 , parallel port Write Control Register. For a description of this bit, refer to the WD76C30 Data Book -
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d472 TRANSISTOR equivalent IMS T414 wd90c10 t410 TRANSISTOR SPB105 K544 WD7910IWD7910LP WD791 O/WD791
Abstract: :; SA19:0 - KEYBD CTL cs I t:~~~;:~~(~~~: I SD15:0 SA19:0 WD76C30 SER, SER, PAR, BUS , this bit, refer to the WD76C30 Data Book, section 4.3 Bits 02-00 - Not used, state is ignored -
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a872 TRANSISTOR equivalent power generation POWER COMMAND HM 1211 POWER COMMAND HM 1211 LT242 sot 23 transistor Aft 49 transistor book WD771 OIWD771 WD7710 WD7710/WD7710LP OIWD771OLP WD7710IWD7710LP
Abstract: the W D 76C 10, the W D76C20ALV, and the WD76C30ALV as shown in Figure 1-1. Together these chips , enable and d isa ble the WD76C30ALV 48 MHz clock, CSEN acts as a strobe to a latch. When it and DACKEN , Select TTL chip select output decoded from CSL input lines and issued as a chip select to the WD76C30ALV , input lines and issued as a chip select to the WD76C30ALV to enable the serial port B. CSL Serial Port A , WD76C30ALV to enable the serial port A. 80 6 CSSERB o 81 7 CSSERA 0 REAL TIME -
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57-DB3 S3V 77 CHN 535 S3V 83
Abstract: : '-.-, SD15:0 SA19:0 WD76C30 SER, SER, PAR, BUS INTERFACE 84 PIN POFP/PLCC irq in RAMDAC , description of this bit, refer to the WD76C30 Data Book, section 4.3 Bits 02-00 - Not used, state is ignored -
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