W78M32V-XBX DQ0-31 A0-22 DQ0-15 DQ16-31 A22-A0 DQ15-DQ0 A22-A20 A22-A12 - Datasheet Archive

 

W78M32V-XBX 8Mx32 Flash 3.3V Page Mode Simultaneous Read/Write Operation Multi-Chip Package FEATURES Access Times of 70, 90, 100,

 

White Electronic Designs W78M32V-XBX W78M32V-XBX 8Mx32 Flash 3.3V Page Mode Simultaneous Read/Write Operation Multi-Chip Package FEATURES Access Times of 70, 90, 100, 120ns Unlock Bypass Program command Packaging · 159 PBGA, 13x22mm ­ 1.27mm pitch · Reduces overall programming time when issuing multiple program command sequences 1,000,000 Erase/Program Cycles per sector Ready/Busy# output (RY/BY#) Page Mode · Hardware method for detecting program or erase cycle completion · Page size is 8 words: Fast page read access from random locations within the page. Hardware reset pin (RESET#) · Hardware method of resetting the internal state machine to the read mode Sector Architecture · Bank A (16Mb): 4Kw x 8 and 32 Kw x 31 WP#/ACC input pin · Bank B (48Mb): 32Kw x 96 · Write protect (WP#) function allows protection of two outermost boot sector, regardless of sector protect status · Bank C (48Mb): 32Kw x 96 · Bank D (16Mb): 4Kw x 8 and 3Kw x 31 Both top and bottom boot blocks Zero Power Operation · Acceleration (ACC) function accelerates program timing Organized as 8Mx32, user configurable as 2x8Mx16 Persistent Sector Protection Commercial, Industrial and Military Temperature Ranges 3.3 Volt for read, erase and write operations · A command sector protection method of locking combinations of individual sectors and sector groups to prevent program or erase operation within that sector Simultaneous read/write operations: Password Sector Protection or Cancellation · Data can be continuously read from one bank while executing erase/program functions in another bank · A sector protection method to lock combinations of individual sectors and sector groups to prevent program or erase operations within that sector using a user-defined 64-bit password. · Zero latency between read and write operations Erase Suspend/Resume · Suspends erase operations to allow read or programming in other sectors of same bank * This product is subject to change without notice. Data Polling and Toggle Bits · Provides a software method of detecting the status of program or erase cycles White Electronic Designs Corp. reserves the right to change products or specifications without notice. April 2006 Rev. 3 1 White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com White Electronic Designs W78M32V-XBX W78M32V-XBX FIG 1: PIN CONFIGURATION FOR W78M32V-XBX W78M32V-XBX (TOP VIEW) 1 3 4 5 6 7 8 GND A 2 GND GND VCC VIO GND GND GND PIN DESCRIPTION 9 10 VCC B VIO GND DQ25 WE2# VIO NC DNU NC VCC VIO C VCC DQ17 DQ27 DQ29 DQ31 NC NC NC NC VCC D VIO DQ24 DQ19 DQ21 DQ23 NC NC NC NC VIO E VCC DQ16 DQ26 DQ28 DQ30 NC NC NC NC VCC F GND CS2# DQ18 DQ20 DQ22 NC NC NC NC GND G GND OE# A0 A22 VCC A12 A16 A21 A20 GND H GND A2 WP#/ACC A11 GND VIO A7 A10 A15 GND A3 A6 A9 VCC GND A1 RESET# A13 GND K GND A4 A17 RY/BY# GND A14 A5 A18 A8 GND L GND NC NC NC DNU* DQ9 DQ4 WE1# A19 GND M VIO NC NC NC NC DQ1 DQ11 DQ6 DQ15 VIO N VCC NC NC NC NC DQ8 DQ3 DQ13 DQ7 VCC P VIO NC NC NC NC DQ0 DQ10 DQ5 DQ14 VIO R VCC VCC NC NC NC CS1# DQ2 DQ12 GND VCC T VIO Data Inputs/Outputs Address Inputs Write Enables Chip Selects Output Enable Hardware Reset Hardware Write Protection/Acceleration Ready/Busy Output Power Supply I/O Power Supply Ground Do Not Use Not Connected GND J DQ0-31 DQ0-31 A0-22 A0-22 WE#1-2 CS#1-2 OE# RESET# WP#/ACC RY/BY# VCC VIO GND DNU NC BLOCK DIAGRAM WE1# CS1# WE2# CS2# RY/BY# RESET# OE# A0-22 A0-22 8M X 16 8M X 16 WP#/ACC GND GND GND VIO VCC GND GND GND DQ0-15 DQ0-15 VIO DQ16-31 DQ16-31 *Ball L5 is reserved for A23 on future upgrades White Electronic Designs Corp. reserves the right to change products or specifications without notice. April 2006 Rev. 3 2 White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com White Electronic Designs W78M32V-XBX W78M32V-XBX GENERAL DESCRIPTION JEDEC 42.4 single-power-supply Flash standard. Commands are written to the command register using standard microprocessor write timing. Register contents serve as inputs to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices. The W78M32V-XBX W78M32V-XBX is a 256Mb, 3.3 volt-only Page Mode and Simultaneous Read/Write Flash memory device. The device offers fast page access times allowing high speed microprocessors to operate without wait states. To eliminate bus contention the device has separate chip enable (CS#), write enable (WE#) and output enable (OE#) controls. Simultaneous Read/Write Operation with Zero Latency. Device programming occurs by executing the program command sequence. The Unlock Bypass mode facilitates faster programming times by requiring only two write cycles to program data instead of four. Device erasure occurs by executing the erase command sequence. The Simultaneous Read/Write architecture provides simultaneous operation by dividing the memory space into 4 banks, which can be considered to be four separate memory arrays as far as certain operations are concerned. The device can improve overall system performance by allowing a host system to program or erase in one bank, then immediately and simultaneously read from another bank with zero latency (with two simultaneous operations operating at any one time). This releases the system from waiting for the completion of a program or erase operation, greatly improving system performance. The host system can detect whether a program or erase operation is complete by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device can be organized in both top and bottom sector configurations. The banks are organized as follows: Bank A B C D Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of sectors of memory. This can be achieved in-system or via programming equipment. Sectors 16 Mbit (4 Kw x 8 and 32 Kw x 31) 48 Mbit (32 Kw x 96) 48 Mbit (32 Kw x 96) 16 Mbit (4 Kw x 8 and 32 Kw x 31) The Erase Suspend/Erase Resume feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. If a read is needed from the SecSi Sector area (One Time Program area) after an erase suspend, then the user must use the proper command sequence to enter and exit this region. Page Mode Features The page size is 8 words. After initial page access is accomplished, the page mode operation provides fast read access speed of random locations within that page. The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly reduced in both these modes. Standard Flash Memory Features The device requires a 3.3 volt power supply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. The device is entirely command set compatible with the White Electronic Designs Corp. reserves the right to change products or specifications without notice. April 2006 Rev. 3 3 White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com White Electronic Designs W78M32V-XBX W78M32V-XBX DEVICE BUS OPERATIONS command. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. Table 1 lists the device bus operations, the inputs and control levels they require, and the resulting output. The following subsections describe each of these operations in further detail. This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory location. The register is a latch used to store the commands, along with the address and data information needed to execute the TABLE 1. DEVICE BUS OPERATION3 Operation Read L L H H X Addresses (A22-A0 A22-A0) AIN Write L H L H X AIN DIN VIO± 0.3 V L X X X (Note 2) X High-Z H H VIO ± 0.3 V H X X High-Z Reset X X X L X X High-Z Temporary Sector Unprotect (High Voltage X X X VID X AIN DIN Standby Output Disable CS# OE# WE# RESET# WP#/ACC DQ15-DQ0 DQ15-DQ0 DOUT Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 11.5-12.5 V, VHH = 8.5-9.5 V, X = Don't Care, SA = Sector Address, AIN = Address In, DIN = Data In, DOUT = Data Out Notes: 1. The sector protect and sector unprotect functions may also be Implemented via programming equipment. See the High Voltage Sector Protection section. 2. WP#/ACC must be high when writing to sectors 0, 1, 268, or 269. 3. For each chip Random Read (Non-Page Read) REQUIREMENTS FOR READING ARRAY DATA Address access time (tACC) is equal to the delay from stable addresses to valid output data. The chip enable access time (tCS) is the delay from the stable addresses and stable CS# to valid data at the output inputs. The output enable access time is the delay from the falling edge of the OE# to valid data at the output inputs (assuming the addresses have been stable for at least tACC­tOE time). To read array data from the outputs, the system must drive the OE# and appropriate CS# pins to VIL. CS# is the power control. OE# is the output control and gates array data to the output pins. WE# should remain at VIH. The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. Each bank remains enabled for read access until the command register contents are altered. Page Mode Read The device is capable of fast page mode read and is compatible with the page mode Mask ROM read operation. This mode provides faster read access speed for random locations within a page. Address bits A22­A3 select an 8 word page, and address bits A2­A0 select a specific word within that page. This is an asynchronous operation with the microprocessor supplying the specific word location. Refer to the AC Characteristics table for timing specifications and to Figure 11 for the timing diagram. ICC1 in the DC Characteristics table represents the active current specification for reading array data. The random or initial page access is tACC or tCS and subsequent page read accesses (as long as the locations specified by the microprocessor falls within that page) is White Electronic Designs Corp. reserves the right to change products or specifications without notice. April 2006 Rev. 3 4 White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com White Electronic Designs The device features an Unlock Bypass mode to facilitate faster programming. Once a bank enters the Unlock Bypass mode, only two write cycles are required to program a word, instead of four. The "Word Program Command Sequence" section has details on programming data to the device using both standard and Unlock Bypass command sequences. equivalent to tPACC. When CS# is deasserted (CS#=VIH), the reassertion of CS# for subsequent access has access time of tACC or tCS. Here again, CS# selects the device and OE# is the output control and should be used to gate data to the output inputs if the device is selected. Fast page mode accesses are obtained by keeping A22­A3 constant and changing A2­A0 to select the specific word within that page. An erase operation can erase one sector, multiple sectors, or the entire device. Table 4 indicates the address space that each sector occupies. A "bank address" is the address bits required to uniquely select a bank. Similarly, a "sector address" refers to the address bits required to uniquely select a sector. The "Command Definitions" section has details on erasing a sector or the entire chip, or suspending/ resuming the erase operation. TABLE 2. PAGE SELECT Word Word 0 Word 1 Word 2 Word 3 Word 4 Word 5 Word 6 Word 7 A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 I CC2 in the DC Characteristics table represents the active current specification for the write mode. The AC Characteristics section contains timing specification tables and timing diagrams for write operations. Accelerated Program Operation The device offers accelerated program operations through the ACC function. This function is primarily intended to allow faster manufacturing throughput at the factory. SIMULTANEOUS OPERATION In addition to the conventional features (read, program, erase-suspend read, and erase-suspend program), the device is capable of reading data from one bank of memory while a program or erase operation is in progress in another bank of memory (simultaneous operation). The bank can be selected by bank addresses (A22­A20) with zero latency. If the system asserts VHH on this pin, the device automatically enters the mentioned Unlock Bypass mode, temporarily unprotects any protected sectors, and uses the higher voltage on the pin to reduce the time required for program operations. The system would use a two-cycle program command sequence as required by the Unlock Bypass mode. Removing VHH from the WP#/ACC pin returns the device to normal operation. Note that VHH must not be asserted on WP#/ACC for operations other than accelerated programming, or device damage may result. In addition, the WP#/ACC pin should be raised to VCC when not in use. That is, the WP#/ACC pin should not be left floating or unconnected; inconsistent behavior of the device may result. The simultaneous operation can execute multi-function mode in the same bank. TABLE 3. BANK SELECT Bank Bank A Bank B Bank C Bank D W78M32V-XBX W78M32V-XBX A22-A20 A22-A20 000 001, 010, 011 100, 101, 110 111 Autoselect Functions If the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the internal register (which is separate from the memory array) on DQ63­DQ0. Standard read cycle timings apply in this mode. Refer to the Autoselect Mode and Autoselect Command Sequence sections for more information. WRITING COMMANDS/COMMAND SEQUENCES To write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive WE# and CS# to VIL, and OE# to VIH. White Electronic Designs Corp. reserves the right to change products or specifications without notice. April 2006 Rev. 3 5 White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com White Electronic Designs W78M32V-XBX W78M32V-XBX STANDBY MODE not within VSS±0.3 V, the standby current will be greater. When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input. The device enters the CMOS standby mode when the CS# and RESET# pins are both held at VIO ± 0.3 V. If CS# and RESET# are held at VIH, but not within VIO ± 0.3 V, the device will be in the standby mode, but the standby current will be greater. The device requires standard access time (tCS) for read access when the device is in either of these standby modes, before it is ready to read data. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory. If the device is deselected during erasure or programming, the device draws active current until the operation is completed. If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a "0" (busy) until the internal reset operation is complete, which requires a time of tREADY (during Embedded Algorithms). The system can thus monitor RY/ BY# to determine whether the reset operation is complete. If RESET# is asserted when a program or erase operation is not executing (RY/BY# pin is "1"), the reset operation is completed within a time of tREADY (not during Embedded Algorithms). The system can read data tRH after the RESET# pin returns to VIH. ICC3 in the DC Characteristics table represents the CMOS standby current specification. Refer to the AC Characteristic tables for RESET# parameters and to Figure 14 for the timing diagram. AUTOMATIC SLEEP MODE OUTPUT DISABLE MODE The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables this mode when addresses remain stable for tACC + 150 ns. The automatic sleep mode is independent of the CS#, WE#, and OE# control signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system. Note that during automatic sleep mode, OE# must be at VIH before the device reduces current to the stated sleep mode specification. ICC5 in the DC Characteristics table represents the automatic sleep mode current specification. When the OE# input is at VIH, output from the device is disabled. The output pins (except for RY/BY#) are placed in the highest Impedance state. RESET#: HARDWARE RESET PIN The RESET# pin provides a hardware method of resetting the device to reading array data. When the RESET# pin is driven low for at least a period of tRP, the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity. Current is reduced for the duration of the RESET# pulse. When RESET# is held at VSS±0.3 V, the device draws CMOS standby current (ICC4). If RESET# is held at VIL but White Electronic Designs Corp. reserves the right to change products or specifications without notice. April 2006 Rev. 3 6 White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com White Electronic Designs W78M32V-XBX W78M32V-XBX TABLE 4. SECTOR ARCHITECTURE Bank A Bank Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38 Sector Address (A22-A12 A22-A12) 00000000000 00000000001 00000000010 00000000011 00000000100 00000000101 00000000110 00000000111 00000001XXX 00000001XXX 00000010XXX 00000010XXX 00000011XXX 00000011XXX 00000100XXX 00000100XXX 00000101XXX 00000101XXX 00000110XXX 00000110XXX 00000111XXX 00000111XXX 00001000XXX 00001000XXX 00001001XXX 00001001XXX 00001010XXX 00001010XXX 00001011XXX 00001011XXX 00001100XXX 00001100XXX 00001101XXX 00001101XXX 00001110XXX 00001110XXX 00001111XXX 00001111XXX 00010000XXX 00010000XXX 00010001XXX 00010001XXX 00010010XXX 00010010XXX 00010011XXX 00010011XXX 00010100XXX 00010100XXX 00010101XXX 00010101XXX 00010110XXX 00010110XXX 00010111XXX 00010111XXX 00011000XXX 00011000XXX 00011001XXX 00011001XXX 00011010XXX 00011010XXX 00011011XXX 00011011XXX 00011100XXX 00011100XXX 00011101XXX 00011101XXX 00011110XXX 00011110XXX 00011111XXX 00011111XXX Sector Size (Kwords) 4 4 4 4 4 4 4 4 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 Address Range (x16) 000000h-000FFFh 001000h-001FFFh 002000h-002FFFh 003000h-003FFFh 004000h-004FFFh 005000h-005FFFh 006000h-006FFFh 007000h-007FFFh 008000h-00FFFFh 010000h-017FFFh 018000h-01FFFFh 020000h-027FFFh 028000h-02FFFFh 030000h-037FFFh 038000h-03FFFFh 040000h-047FFFh 048000h-04FFFFh 050000h-057FFFh 058000h-05FFFFh 060000h-067FFFh 068000h-06FFFFh 070000h-077FFFh 078000h-07FFFFh 080000h-087FFFh 088000h-08FFFFh 090000h-097FFFh 098000h-09FFFFh 0A0000h-0A7FFFh 0A8000h-0AFFFFh 0B0000h-0B7FFFh 0B8000h-0BFFFFh 0C0000h-0C7FFFh 0C8000h-0CFFFFh 0D0000h-0D7FFFh 0D8000h-0DFFFFh 0E0000h-0E7FFFh 0E8000h-0EFFFFh 0F0000h-0F7FFFh 0F8000h-0FFFFFh White Electronic Designs Corp. reserves the right to change products or specifications without notice. April 2006 Rev. 3 7 White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com White Electronic Designs W78M32V-XBX W78M32V-XBX TABLE 4. SECTOR ARCHITECTURE Bank B Bank Sector SA39 SA40 SA41 SA42 SA43 SA44 SA45 SA46 SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70 SA71 SA72 SA73 SA74 SA75 SA76 SA77 SA78 Sector Address (A22-A12 A22-A12) 00100000XXX 00100000XXX 00100001XXX 00100001XXX 00100010XXX 00100010XXX 00100011XXX 00100011XXX 00100100XXX 00100100XXX 00100101XXX 00100101XXX 00100110XXX 00100110XXX 00100111XXX 00100111XXX 00101000XXX 00101000XXX 00101001XXX 00101001XXX 00101010XXX 00101010XXX 00101011XXX 00101011XXX 00101100XXX 00101100XXX 00101101XXX 00101101XXX 00101110XXX 00101110XXX 00101111XXX 00101111XXX 00110000XXX 00110000XXX 00110001XXX 00110001XXX 00110010XXX 00110010XXX 00110011XXX 00110011XXX 00110100XXX 00110100XXX 00110101XXX 00110101XXX 00110110XXX 00110110XXX 00110111XXX 00110111XXX 00111000XXX 00111000XXX 00111001XXX 00111001XXX 00111010XXX 00111010XXX 00111011XXX 00111011XXX 00111100XXX 00111100XXX 00111101XXX 00111101XXX 00111110XXX 00111110XXX 00111111XXX 00111111XXX 01000000XXX 01000000XXX 01000001XXX 01000001XXX 01000010XXX 01000010XXX 01000011XXX 01000011XXX 01000100XXX 01000100XXX 01000101XXX 01000101XXX 01000110XXX 01000110XXX 01000111XXX 01000111XXX Sector Size (Kwords) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 Address Range (x16) 100000h­107FFFh 108000h­10FFFFh 110000h­117FFFh 118000h­11FFFFh 120000h­127FFFh 128000h­12FFFFh 130000h­137FFFh 138000h­13FFFFh 140000h­147FFFh 148000h­14FFFFh 150000h­157FFFh 158000h­15FFFFh 160000h­167FFFh 168000h­16FFFFh 170000h­177FFFh 178000h­17FFFFh 180000h­187FFFh 188000h­18FFFFh 190000h­197FFFh 198000h­19FFFFh 1A0000h­1A7FFFh 1A8000h­1AFFFFh 1B0000h­1B7FFFh 1B8000h­1BFFFFh 1C0000h­1C7FFFh 1C8000h­1CFFFFh 1D0000h­1D7FFFh 1D8000h­1DFFFFh 1E0000h­1E7FFFh 1E8000h­1EFFFFh 1F0000h­1F7FFFh 1F8000h­1FFFFFh 200000h­207FFFh 208000h­20FFFFh 210000h­217FFFh 218000h­21FFFFh 220000h­227FFFh 228000h­22FFFFh 230000h­237FFFh 238000h­23FFFFh White Electronic Designs Corp. reserves the right to change products or specifications without notice. April 2006 Rev. 3 8 White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com White Electronic Designs W78M32V-XBX W78M32V-XBX TABLE 4. SECTOR ARCHITECTURE Bank B Bank Sector SA79 SA80 SA81 SA82 SA83 SA84 SA85 SA86 SA87 SA88 SA89 SA90 SA91 SA92 SA93 SA94 SA95 SA96 SA97 SA98 SA99 SA100 SA100 SA101 SA101 SA102 SA102 SA103 SA103 SA104 SA104 SA105 SA105 SA106 SA106 SA107 SA107 SA108 SA108 SA109 SA109 SA110 SA110 SA111 SA111 SA112 SA112 SA113 SA113 SA114 SA114 SA115 SA115 SA116 SA116 SA117 SA117 SA118 SA118 Sector Address (A22-A12 A22-A12) 01001000XXX 01001000XXX 01001001XXX 01001001XXX 01001010XXX 01001010XXX 01001011XXX 01001011XXX 01001100XXX 01001100XXX 01001101XXX 01001101XXX 01001110XXX 01001110XXX 01001111XXX 01001111XXX 01010000XXX 01010000XXX 01010001XXX 01010001XXX 01010010XXX 01010010XXX 01010011XXX 01010011XXX 01010100XXX 01010100XXX 01010101XXX 01010101XXX 01010110XXX 01010110XXX 01010111XXX 01010111XXX 01011000XXX 01011000XXX 01011001XXX 01011001XXX 01011010XXX 01011010XXX 01011011XXX 01011011XXX 01011100XXX 01011100XXX 01011101XXX 01011101XXX 01011110XXX 01011110XXX 01011111XXX 01011111XXX 01100000XXX 01100000XXX 01100001XXX 01100001XXX 01100010XXX 01100010XXX 01100011XXX 01100011XXX 01100100XXX 01100100XXX 01100101XXX 01100101XXX 01100110XXX 01100110XXX 01100111XXX 01100111XXX 01101000XXX 01101000XXX 01101001XXX 01101001XXX 01101010XXX 01101010XXX 01101011XXX 01101011XXX 01101100XXX 01101100XXX 01101101XXX 01101101XXX 01101110XXX 01101110XXX 01101111XXX 01101111XXX Sector Size (Kwords) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 Address Range (x16) 240000h­247FFFh 248000h­24FFFFh 250000h­257FFFh 258000h­25FFFFh 260000h­267FFFh 268000h­26FFFFh 270000h­277FFFh 278000h­27FFFFh 280000h­287FFFh 288000h­28FFFFh 290000h­297FFFh 298000h­29FFFFh 2A0000h­2A7FFFh 2A8000h­2AFFFFh 2B0000h­2B7FFFh 2B8000h­2BFFFFh 2C0000h­2C7FFFh 2C8000h­2CFFFFh 2D0000h­2D7FFFh 2D8000h­2DFFFFh 2E0000h­2E7FFFh 2E8000h­2EFFFFh 2F0000h­2F7FFFh 2F8000h­2FFFFFh 300000h­307FFFh 308000h­30FFFFh 310000h­317FFFh 318000h­31FFFFh 320000h­327FFFh 328000h­32FFFFh 330000h­337FFFh 338000h­33FFFFh 340000h­347FFFh 348000h­34FFFFh 350000h­357FFFh 358000h­35FFFFh 360000h­367FFFh 368000h­36FFFFh 370000h­377FFFh 378000h­37FFFFh White Electronic Designs Corp. reserves the right to change products or specifications without notice. April 2006 Rev. 3 9 White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com White Electronic Designs W78M32V-XBX W78M32V-XBX TABLE 4. SECTOR ARCHITECTURE Bank C Bank B Bank Sector SA119 SA119 SA120 SA120 SA121 SA121 SA122 SA122 SA123 SA123 SA124 SA124 SA125 SA125 SA126 SA126 SA127 SA127 SA128 SA128 SA129 SA129 SA130 SA130 SA131 SA131 SA132 SA132 SA133 SA133 SA134 SA134 SA135 SA135 SA136 SA136 SA137 SA137 SA138 SA138 SA139 SA139 SA140 SA140 SA141 SA141 SA142 SA142 SA143 SA143 SA144 SA144 SA145 SA145 SA146 SA146 SA147 SA147 SA148 SA148 SA149 SA149 SA150 SA150 SA151 SA151 SA152 SA152 SA153 SA153 SA154 SA154 SA155 SA155 SA156 SA156 SA157 SA157 SA158 SA158 Sector Address (A22-A12 A22-A12) 01110000XXX 01110000XXX 01110001XXX 01110001XXX 01110010XXX 01110010XXX 01110011XXX 01110011XXX 01110100XXX 01110100XXX 01110101XXX 01110101XXX 01110110XXX 01110110XXX 01110111XXX 01110111XXX 01111000XXX 01111000XXX 01111001XXX 01111001XXX 01111010XXX 01111010XXX 01111011XXX 01111011XXX 01111100XXX 01111100XXX 01111101XXX 01111101XXX 01111110XXX 01111110XXX 01111111XXX 01111111XXX 10000000XXX 10000000XXX 10000001XXX 10000001XXX 10000010XXX 10000010XXX 10000011XXX 10000011XXX 10000100XXX 10000100XXX 10000101XXX 10000101XXX 10000110XXX 10000110XXX 10000111XXX 10000111XXX 10001000XXX 10001000XXX 10001001XXX 10001001XXX 10001010XXX 10001010XXX 10001011XXX 10001011XXX 10001100XXX 10001100XXX 10001101XXX 10001101XXX 10001110XXX 10001110XXX 10001111XXX 10001111XXX 10010000XXX 10010000XXX 10010001XXX 10010001XXX 10010010XXX 10010010XXX 10010011XXX 10010011XXX 10010100XXX 10010100XXX 10010101XXX 10010101XXX 10010110XXX 10010110XXX 10010111XXX 10010111XXX Sector Size (Kwords) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 Address Range (x16) 380000h­387FFFh 388000h­38FFFFh 390000h­397FFFh 398000h­39FFFFh 3A0000h­3A7FFFh 3A8000h­3AFFFFh 3B0000h­3B7FFFh 3B8000h­3BFFFFh 3C0000h­3C7FFFh 3C8000h­3CFFFFh 3D0000h­3D7FFFh 3D8000h­3DFFFFh 3E0000h­3E7FFFh 3E8000h­3EFFFFh 3F0000h­3F7FFFh 3F8000h­3FFFFFh 400000h­407FFFh 408000h­40FFFFh 410000h­417FFFh 418000h­41FFFFh 420000h­427FFFh 428000h­42FFFFh 430000h­437FFFh 438000h­43FFFFh 440000h­447FFFh 448000h­44FFFFh 450000h­457FFFh 458000h­45FFFFh 460000h­467FFFh 468000h­46FFFFh 470000h­477FFFh 478000h­47FFFFh 480000h­487FFFh 488000h­48FFFFh 490000h­497FFFh 498000h­49FFFFh 4A0000h­4A7FFFh 4A8000h­4AFFFFh 4B0000h­4B7FFFh 4B8000h­4BFFFFh White Electronic Designs Corp. reserves the right to change products or specifications without notice. April 2006 Rev. 3 10 White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com White Electronic Designs W78M32V-XBX W78M32V-XBX TABLE 4. SECTOR ARCHITECTURE Bank C Bank Sector SA159 SA159 SA160 SA160 SA161 SA161 SA162 SA162 SA163 SA163 SA164 SA164 SA165 SA165 SA166 SA166 SA167 SA167 SA168 SA168 SA169 SA169 SA170 SA170 SA171 SA171 SA172 SA172 SA173 SA173 SA175 SA175 SA176 SA176 SA177 SA177 SA178 SA178 SA179 SA179 SA180 SA180 SA181 SA181 SA182 SA182 SA183 SA183 SA184 SA184 SA185 SA185 SA186 SA186 SA187 SA187 SA188 SA188 SA189 SA189 SA190 SA190 SA191 SA191 SA192 SA192 SA193 SA193 SA194 SA194 SA195 SA195 SA196 SA196 SA197 SA197 SA198 SA198 Sector Address (A22-A12 A22-A12) 10011000XXX 10011000XXX 10011001XXX 10011001XXX 10011010XXX 10011010XXX 10011011XXX 10011011XXX 10011100XXX 10011100XXX 10011101XXX 10011101XXX 10011110XXX 10011110XXX 10011111XXX 10011111XXX 10100000XXX 10100000XXX 10100001XXX 10100001XXX 10100010XXX 10100010XXX 10100011XXX 10100011XXX 10100100XXX 10100100XXX 10100101XXX 10100101XXX 10100110XXX 10100110XXX 10101000XXX 10101000XXX 10101001XXX 10101001XXX 10101010XXX 10101010XXX 10101011XXX 10101011XXX 10101100XXX 10101100XXX 10101101XXX 10101101XXX 10101110XXX 10101110XXX 10101111XXX 10101111XXX 10110000XXX 10110000XXX 10110001XXX 10110001XXX 10110010XXX 10110010XXX 10110011XXX 10110011XXX 10110100XXX 10110100XXX 10110101XXX 10110101XXX 10110110XXX 10110110XXX 10110111XXX 10110111XXX 10111000XXX 10111000XXX 10111001XXX 10111001XXX 10111010XXX 10111010XXX 10111011XXX 10111011XXX 10111100XXX 10111100XXX 10111101XXX 10111101XXX 10111110XXX 10111110XXX 10111111XXX 10111111XXX Sector Size (Kwords) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 Address Range (x16) 4C0000h­4C7FFFh 4C8000h­4CFFFFh 4D0000h­4D7FFFh 4D8000h­4DFFFFh 4E0000h­4E7FFFh 4E8000h­4EFFFFh 4F0000h­4F7FFFh 4F8000h­4FFFFFh 500000h­507FFFh 508000h­50FFFFh 510000h­517FFFh 518000h­51FFFFh 520000h­527FFFh 528000h­52FFFFh 538000h­53FFFFh 540000h­547FFFh 548000h­54FFFFh 550000h­557FFFh 558000h­15FFFFh 560000h­567FFFh 568000h­56FFFFh 570000h­577FFFh 578000h­57FFFFh 580000h­587FFFh 588000h­58FFFFh 590000h­597FFFh 598000h­59FFFFh 5A0000h­5A7FFFh 5A8000h­5AFFFFh 5B0000h­5B7FFFh 5B8000h­5BFFFFh 5C0000h­5C7FFFh 5C8000h­5CFFFFh 5D0000h­5D7FFFh 5D8000h­5DFFFFh 5E0000h­5E7FFFh 5E8000h­5EFFFFh 5F0000h­5F7FFFh 5F8000h­5FFFFFh White Electronic Designs Corp. reserves the right to change products or specifications without notice. April 2006 Rev. 3 11 White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com White Electronic Designs W78M32V-XBX W78M32V-XBX TABLE 4. SECTOR ARCHITECTURE Bank C Bank Sector SA199 SA199 SA200 SA200 SA201 SA201 SA202 SA202 SA203 SA203 SA204 SA204 SA205 SA205 SA206 SA206 SA208 SA208 SA209 SA209 SA210 SA210 SA211 SA211 SA212 SA212 SA213 SA213 SA214 SA214 SA215 SA215 SA216 SA216 SA217 SA217 SA218 SA218 SA219 SA219 SA220 SA220 SA221 SA221 SA222 SA222 SA223 SA223 SA224 SA224 SA225 SA225 SA226 SA226 SA227 SA227 SA228 SA228 SA229 SA229 SA230 SA230 Sector Address (A22-A12 A22-A12) 11000000XXX 11000000XXX 11000001XXX 11000001XXX 11000010XXX 11000010XXX 11000011XXX 11000011XXX 11000100XXX 11000100XXX 11000101XXX 11000101XXX 11000110XXX 11000110XXX 11000111XXX 11000111XXX 11001001XXX 11001001XXX 11001010XXX 11001010XXX 11001011XXX 11001011XXX 11001100XXX 11001100XXX 11001101XXX 11001101XXX 11001110XXX 11001110XXX 11001111XXX 11001111XXX 11010000XXX 11010000XXX 11010001XXX 11010001XXX 11010010XXX 11010010XXX 11010011XXX 11010011XXX 11010100XXX 11010100XXX 11010101XXX 11010101XXX 11010110XXX 11010110XXX 11010111XXX 11010111XXX 11011000XXX 11011000XXX 11011001XXX 11011001XXX 11011010XXX 11011010XXX 11011011XXX 11011011XXX 11011100XXX 11011100XXX 11011101XXX 11011101XXX 11011110XXX 11011110XXX 11011111XXX 11011111XXX Sector Size (Kwords) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 Address Range (x16) 600000h­607FFFh 608000h­60FFFFh 610000h­617FFFh 618000h­61FFFFh 620000h­627FFFh 628000h­62FFFFh 630000h­637FFFh 638000h­63FFFFh 648000h­64FFFFh 650000h­657FFFh 658000h­65FFFFh 660000h­667FFFh 668000h­66FFFFh 670000h­677FFFh 678000h­67FFFFh 680000h­687FFFh 688000h­68FFFFh 690000h­697FFFh 698000h­69FFFFh 6A0000h­6A7FFFh 6A8000h­6AFFFFh 6B0000h­6B7FFFh 6B8000h­6BFFFFh 6C0000h­6C7FFFh 6C8000h­6CFFFFh 6D0000h­6D7FFFh 6D8000h­6DFFFFh 6E0000h­6E7FFFh 6E8000h­6EFFFFh 6F0000h­6F7FFFh 6F8000h­6FFFFFh White Electronic Designs Corp. reserves the right to change products or specifications without notice. April 2006 Rev. 3 12 White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com White Electronic Designs W78M32V-XBX W78M32V-XBX TABLE 4. SECTOR ARCHITECTURE Sector Sector Address (A22-A12 A22-A12) Sector Size (Kwords) SA231 SA231 11100000XXX 11100000XXX 32 700000h-707FFFh SA232 SA232 11100001XXX 11100001XXX 32 708000h-70FFFFh SA233 SA233 11100010XXX 11100010XXX 32 710000h-717FFFh SA234 SA234 11100011XXX 11100011XXX 32 718000h-71FFFFh SA235 SA235 11100100XXX 11100100XXX 32 720000h-727FFFh SA236 SA236 11100101XXX 11100101XXX 32 728000h-72FFFFh SA237 SA237 Bank Address Range (x16) 11100110XXX 11100110XXX 32 730000h-737FFFh 738000h-73FFFFh 11100111XXX 11100111XXX 32 SA239 SA239 11101000XXX 11101000XXX 32 740000h-747FFFh SA240 SA240 11101001XXX 11101001XXX 32 748000h-74FFFFh SA241 SA241 11101010XXX 11101010XXX 32 750000h-757FFFh SA242 SA242 11101011XXX 11101011XXX 32 758000h-75FFFFh SA243 SA243 11101100XXX 11101100XXX 32 760000h-767FFFh SA244 SA244 11101101XXX 11101101XXX 32 768000h-76FFFFh SA245 SA245 11101110XXX 11101110XXX 32 770000h-777FFFh SA246 SA246 11101111XXX 11101111XXX 32 778000h-77FFFFh SA247 SA247 11110000XXX 11110000XXX 32 780000h-787FFFh SA248 SA248 Bank D SA238 SA238 11110001XXX 11110001XXX 32 788000h-78FFFFh SA249 SA249 11110010XXX 11110010XXX 32 790000h-797FFFh SA250 SA250 11110011XXX 11110011XXX 32 798000h-79FFFFh SA251 SA251 11110100XXX 11110100XXX 32 7A0000h-7A7FFFh SA252 SA252 11110101XXX 11110101XXX 32 7A8000h-7AFFFFh SA253 SA253 11110110XXX 11110110XXX 32 7B0000h-7B7FFFh SA254 SA254 11110111XXX 11110111XXX 32 7B8000h-7BFFFFh SA255 SA255 11111000XXX 11111000XXX 32 7O0000h-7C7FFFh SA256 SA256 11111001XXX 11111001XXX 32 7C8000h-7CFFFFh SA257 SA257 11111010XXX 11111010XXX 32 7D0000h-7D7FFFh SA258 SA258 11111011XXX 11111011XXX 32 7D8000h-7DFFFFh SA259 SA259 11111100XXX 11111100XXX 32 7E0000h-7E7FFFh SA260 SA260 11111101XXX 11111101XXX 32 7E8000h-7EFFFFh SA261 SA261 11111110XXX 11111110XXX 32 7F0000h-7F7FFFh SA262 SA262 11111111000 4 7F8000h-7F8FFFh SA263 SA263 11111111001 4 7F9000h-7F9FFFh SA264 SA264 11111111010 4 7FA000h-7FAFFFh SA265 SA265 11111111011 4 7FB000h-7FBFFFh SA266 SA266 11111111100 4 7FO000h-7FCFFFh SA267 SA267 11111111101 4 7FD000h-7FDFFFh SA268 SA268 11111111110 4 7FE000h-7FEFFFh SA269 SA269 11111111111 4 7FF000h-7FFFFFh White Electronic Designs Corp. reserves the right to change products or specifications without notice. April 2006 Rev. 3 13 White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com White Electronic Designs TABLE 5. SecSiTM SECTOR ADDRESSES Sector Size sector protection, the sector address must appear on the appropriate highest order address bits (see Table 4). Table 6 shows the remaining address bits that are don't care. When all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on DQ7­DQ0. However, the autoselect codes can also be accessed in-system through the command register, for instances when the device is erased or programmed in a system without access to high voltage on the A9 pin. The command sequence is illustrated in Table 13. Note that if a Bank Address (BA) on address bits A22­A20 is asserted during the third write cycle of the autoselect command, the host system can read autoselect data that bank and then immediately read array data from the other bank, without exiting the autoselect mode. Address Range Device 128 words 000000h­00007Fh Factory-Locked Area 64 words 000000h-00003Fh Customer-Lockable Area 64 words W78M32V-XBX W78M32V-XBX 000040h-00007Fh AUTOSELECT MODE The autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on DQ7­DQ0 for each chip. This mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. However, the autoselect codes can also be accessed in-system through the command register. To access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in Table 13. This method does not require VID. Refer to the Autoselect Command Sequence section for more information. When using programming equipment, the autoselect mode requires VID on address pin A9. Address pins must be as shown in Table 6. In addition, when verifying TABLE 6. AUTOSELECT CODES (HIGH VOLTAGE METHOD) CS# OE# WE# Manufacturer ID: Read Cycle 1 Read Cycle 2 Read Cycle 3 Sector Protection Verification SecSi Indicator Bit (DQ7, DQ6) L L L L H H Device ID Description A22 to A12 X X A10 A9 A8 A7 A6 X X VID VID X X L L L L A5 to A4 X L A3 A2 A1 A0 L L L L L L L H DQ15 to DQ0 (each chip) 0004h 227Eh L H H H L 2220 L H H H H 2200h 0001h (protected), 0000h (unprotected) 00C0h (factory and user locked) L L H SA X VID X L L L L L H L L L H X X VID X X L X L L H H Legend: L = Logic Low = VIL, H = Logic High = VIH, BA = Bank Address, SA = Sector Address, X = Don't care. Note: The autoselect codes may also be accessed in-system via command sequences White Electronic Designs Corp. reserves the right to change products or specifications without notice. April 2006 Rev. 3 14 White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com White Electronic Designs TABLE 7. BOOT SECTOR/SECTOR BLOCK ADDRESSES FOR PROTECTION/ UNPROTECTION Sector A22-A12 A22-A12 SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8-SA10 SA8-SA10 00000000000 00000000001 00000000010 00000000011 00000000100 00000000101 00000000110 00000000111 00000001XXX 00000001XXX 00000010XXX 00000010XXX 00000011XXX 00000011XXX 000001XXXXX 000001XXXXX 000010XXXXX 000010XXXXX 000011XXXXX 000011XXXXX 000100XXXXX 000100XXXXX 000101XXXXX 000101XXXXX 000110XXXXX 000110XXXXX 000111XXXXX 000111XXXXX 001000XXXXX 001000XXXXX 001001XXXXX 001001XXXXX 001010XXXXX 001010XXXXX 001011XXXXX 001011XXXXX 001100XXXXX 001100XXXXX 001101XXXXX 001101XXXXX 001110XXXXX 001110XXXXX 001111XXXXX 001111XXXXX 010000XXXXX 010000XXXXX 010001XXXXX 010001XXXXX 010010XXXXX 010010XXXXX 010011XXXXX 010011XXXXX 010100XXXXX 010100XXXXX 010101XXXXX 010101XXXXX 010110XXXXX 010110XXXXX 010111XXXXX 010111XXXXX 011000XXXXX 011000XXXXX 011001XXXXX 011001XXXXX 011010XXXXX 011010XXXXX 011011XXXXX 011011XXXXX 011100XXXXX 011100XXXXX 011101XXXXX 011101XXXXX 011110XXXXX 011110XXXXX SA11-SA14 SA11-SA14 SA15-SA18 SA15-SA18 SA19-SA22 SA19-SA22 SA23-SA26 SA23-SA26 SA27-SA30 SA27-SA30 SA31-SA34 SA31-SA34 SA35-SA38 SA35-SA38 SA39-SA42 SA39-SA42 SA43-SA46 SA43-SA46 SA47-SA50 SA47-SA50 SA51-SA54 SA51-SA54 SA55-SA58 SA55-SA58 SA59-SA62 SA59-SA62 SA63-SA66 SA63-SA66 SA67-SA70 SA67-SA70 SA71-SA74 SA71-SA74 SA75-SA78 SA75-SA78 SA79-SA82 SA79-SA82 SA83-SA86 SA83-SA86 SA87-SA90 SA87-SA90 SA91-SA94 SA91-SA94 SA95-SA98 SA95-SA98 SA99-SA102 SA99-SA102 SA103-SA106 SA103-SA106 SA107-SA110 SA107-SA110 SA111-SA114 SA111-SA114 SA115-SA118 SA115-SA118 SA119-SA122 SA119-SA122 SA123-SA126 SA123-SA126 SA127-SA130 SA127-SA130 W78M32V-XBX W78M32V-XBX Sector SA131-SA134 SA131-SA134 SA135-SA138 SA135-SA138 SA139-SA142 SA139-SA142 SA143-SA146 SA143-SA146 SA147-SA150 SA147-SA150 SA151-SA154 SA151-SA154 SA155-SA158 SA155-SA158 SA159-SA162 SA159-SA162 SA163-SA166 SA163-SA166 SA167-SA170 SA167-SA170 SA171-SA174 SA171-SA174 SA175-SA178 SA175-SA178 SA179-SA182 SA179-SA182 SA183-SA186 SA183-SA186 SA187-SA190 SA187-SA190 SA191-SA194 SA191-SA194 SA195-SA198 SA195-SA198 SA199-SA202 SA199-SA202 SA203-SA206 SA203-SA206 SA207-SA210 SA207-SA210 SA211-SA214 SA211-SA214 SA215-SA218 SA215-SA218 SA219-SA222 SA219-SA222 SA223-SA226 SA223-SA226 SA227-SA230 SA227-SA230 SA231-SA234 SA231-SA234 SA235-SA238 SA235-SA238 SA239-SA242 SA239-SA242 SA243-SA246 SA243-SA246 SA247-SA250 SA247-SA250 SA251-SA254 SA251-SA254 SA255-SA258 SA255-SA258 SA259-SA261 SA259-SA261 Sector/ Sector Block Size 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 96 (3x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords A22-A12 A22-A12 011111XXXXX 011111XXXXX 100000XXXXX 100000XXXXX 100001XXXXX 100001XXXXX 100010XXXXX 100010XXXXX 100011XXXXX 100011XXXXX 100100XXXXX 100100XXXXX 100101XXXXX 100101XXXXX 100110XXXXX 100110XXXXX 100111XXXXX 100111XXXXX 101000XXXXX 101000XXXXX 101001XXXXX 101001XXXXX 101010XXXXX 101010XXXXX 101011XXXXX 101011XXXXX 101100XXXXX 101100XXXXX 101101XXXXX 101101XXXXX 101110XXXXX 101110XXXXX 101111XXXXX 101111XXXXX 110000XXXXX 110000XXXXX 110001XXXXX 110001XXXXX 110010XXXXX 110010XXXXX 110011XXXXX 110011XXXXX 110100XXXXX 110100XXXXX 110101XXXXX 110101XXXXX 110110XXXXX 110110XXXXX 110111XXXXX 110111XXXXX 111000XXXXX 111000XXXXX 111001XXXXX 111001XXXXX 111010XXXXX 111010XXXXX 111011XXXXX 111011XXXXX 111100XXXXX 111100XXXXX 111101XXXXX 111101XXXXX 111110XXXXX 111110XXXXX 11111100XXX 11111100XXX 11111101XXX 11111101XXX 11111110XXX 11111110XXX 11111111000 11111111001 11111111010 11111111011 11111111100 11111111101 11111111110 11111111111 SA262 SA262 SA263 SA263 SA264 SA264 SA265 SA265 SA266 SA266 SA267 SA267 SA268 SA268 SA269 SA269 Sector/ Sector Block Size 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 96 (3x32) Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords White Electronic Designs Corp. reserves the right to change products or specifications without notice. April 2006 Rev. 3 15 White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com White Electronic Designs W78M32V-XBX W78M32V-XBX SECTOR PROTECTION protection states: The device features several levels of sector protection, which can disable both the program and erase operations in certain sectors or sector groups: Persistently Locked-The sector is protected and cannot be changed. Persistent Sector Protection Dynamically Locked-The sector is protected and can be changed by a simple command. A command sector protection method that replaces the old 12 V controlled protection method. Unlocked-The sector is unprotected and can be changed by a simple command. Password Sector Protection To achieve these states, three types of "bits" are used: A highly sophisticated protection method that requires a password before changes to certain sectors or sector groups are permitted Persistent Protection Bit (PPB) A single Persistent (non-volatile) Protection Bit is assigned to a maximum four sectors (see the sector address tables for specific sector protection groupings). All 4 Kword bootblock sectors have individual sector Persistent Protection Bits (PPBs) for greater flexibility. Each PPB is individually modifiable through the PPB Write Command. WP# Hardware Protection A write protect pin that can prevent program or erase operations in sectors 0, 1, 268, and 269. The WP# Hardware Protection feature is always available, independent of the software managed protection method chosen. The device erases all PPBs in parallel. If any PPB requires erasure, the device must be instructed to preprogram all of the sector PPBs prior to PPB erasure. Otherwise, a previously erased sector PPBs can potentially be overerased. The flash device does not have a built-in means of preventing sector PPBs over-erasure. Selecting a Sector Protection Mode All parts default to operate in the Persistent Sector Protection mode. The user must then choose if the Persistent or Password Protection method is most desirable. There are two one-time programmable non-volatile bits that define which sector protection method will be used. If the Persistent Sector Protection method is desired, programming the Persistent Sector Protection Mode Locking Bit permanently sets the device to the Persistent Sector Protection mode. If the Password Sector Protection method is desired, programming the Password Mode Locking Bit permanently sets the device to the Password Sector Protection mode. It is not possible to switch between the two protection modes once a locking bit has been set. One of the two modes must be selected when the device is first programmed. This prevents a program or virus from later setting the Password Mode Locking Bit, which would cause an unexpected shift from the default Persistent Sector Protection Mode into the Password Protection Mode. Persistent Protection Bit Lock (PPB Lock) The Persistent Protection Bit Lock (PPB Lock) is a global volatile bit. When set to "1", the PPBs cannot be changed. When cleared ("0"), the PPBs are changeable. There is only one PPB Lock bit per device. The PPB Lock is cleared after power-up or hardware reset. There is no command sequence to unlock the PPB Lock. Dynamic Protection Bit (DYB) A volatile protection bit is assigned for each sector. After power-up or hardware reset, the contents of all DYBs is "0". Each DYB is individually modifiable through the DYB Write Command. When the parts are first shipped, the PPBs are cleared, the DYBs are cleared, and PPB Lock is defaulted to power up in the cleared state ­ meaning the PPBs are changeable. The device is shipped with all sectors unprotected. When the device is first powered on the DYBs power up cleared (sectors not protected). The Protection State for each sector is determined by the logical OR of the PPB and the DYB related to that sector. For the sectors that have the PPBs cleared, the DYBs control whether or not the sector is protected or unprotected. By issuing the DYB Write It is possible to determine whether a sector is protected or unprotected. See Autoselect Mode for details. PERSISTENT SECTOR PROTECTION The Persistent Sector Protection method replaces the 12 V controlled protection method in previous WEDC flash devices. This new method provides three different sector White Electronic Designs Corp. reserves the right to change products or specifications without notice. April 2006 Rev. 3 16 White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com White Electronic Designs W78M32V-XBX W78M32V-XBX bit set command early in the boot code, and protect the boot code by holding WP#/ACC = VIL. command sequences, the DYBs will be set or cleared, thus placing each sector in the protected or unprotected state. These are the so-called Dynamic Locked or Unlocked states. They are called dynamic states because it is very easy to switch back and forth between the protected and unprotected conditions. This allows software to easily protect sectors against inadvertent changes yet does not prevent the easy removal of protection when changes are needed. The DYBs maybe set or cleared as often as needed. TABLE 8. SECTOR PROTECTION SCHEMES DYB 0 0 1 0 1 1 0 1 1 The PPB Lock bit adds an additional level of protection. Once all PPBs are programmed to the desired settings, the PPB Lock may be set to "1". Setting the PPB Lock disables all program and erase commands to the non-volatile PPBs. In effect, the PPB Lock Bit locks the PPBs into their current state. The only way to clear the PPB Lock is to go through a power cycle. System boot code can determine if any changes to the PPB are needed; for example, to allow new system code to be downloaded. If no changes are needed then the boot code can set the PPB Lock to disable any further changes to the PPBs during system operation. 0 PPB LOCK 0 0 The PPBs allow for a more static, and difficult to change, level of protection. The PPBs retain their state across power cycles because they are non-volatile. Individual PPBs are set with a command but must all be cleared as a group through a complex sequence of program and erasing commands. The PPBs are also limited to 100 erase cycles. PPB 1 0 1 1 0 1 0 0 0 1 1 1 SECTOR STATE Unprotected - PPB and DYB are changeable Unprotected - PPB not changeable, DYB is changeable Protected - PPB and DYB are changeable Protected - PPB not changeable, DYB is changeable Table 8 contains all possible combinations of the DYB, PPB, and PPB lock relating to the status of the sector In summary, if the PPB is set, and the PPB lock is set, the sector is protected and the protection can not be removed until the next power cycle clears the PPB lock. If the PPB is cleared, the sector can be dynamically locked or unlocked. The DYB then controls whether or not the sector is protected or unprotected. The WP#/ACC write protect pin adds a final level of hardware protection to sectors 0, 1, 268, and 269. When this pin is low it is not possible to change the contents of these sectors. These sectors generally hold system boot code. The WP#/ACC pin can prevent any changes to the boot code that could override the choices made while setting up sector protection during system initialization. If the user attempts to program or erase a protected sector, the device ignores the command and returns to read mode. A program command to a protected sector enables status polling for approximately 1 µs beforethe device returns to read mode without having modified the contents of the protected sector. An erase command to a protected sector enables status polling for approximately 50 µs after which the device returns to read mode without having erased the protected sector. It is possible to have sectors that have been persistently locked, and sectors that are left in the dynamic state. The sectors in the dynamic state are all unprotected. If there is a need to protect some of them, a simple DYB Write command sequence is all that is necessary. The DYB write command for the dynamic sectors switch the DYBs to signify protected and unprotected, respectively. If there is a need to change the status of the persistently locked sectors, a few more steps are required. First, the PPB Lock bit must be disabled by either putting the device through a power-cycle, or hardware reset. The PPBs can then be changed to reflect the desired settings. Setting the PPB lock bit once again will lock the PPBs, and the device operates normally again. The programming of the DYB, PPB, and PPB lock for a given sect or can be ver i f ied by writing a DYB/PPB/PPB lock verify command to the device. Persistent Sector Protection Mode Locking Bit Like the password mode locking bit, a Persistent Sector Protection mode locking bit exists to guarantee that the device remain in software sector protection. Once set, the Persistent Sector Protection locking bit prevents programming of the password protection mode locking bit. This guarantees that a hacker could not place the device in password protection mode. The best protection is achieved by executing the PPB lock White Electronic Designs Corp. reserves the right to change products or specifications without notice. April 2006 Rev. 3 17 White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com White Electronic Designs W78M32V-XBX W78M32V-XBX Both of these objectives are important, and if not carefully considered, may lead to unrecoverable errors. The user must be sure that the Password Protection method is desired when setting the Password Mode Locking Bit. More importantly, the user must be sure that the password is correct when the Password Mode Locking Bit is set. Due to the fact that read operations are disabled, there is no means to verify what the password is afterwards. If the password is lost after setting the Password Mode Locking Bit, there will be no way to clear the PPB Lock bit. PASSWORD PROTECTION MODE The Password Sector Protection Mode method allows an even higher level of security than the Persistent Sector Protection Mode. There are two main differences between the Persistent Sector Protection and the Password Sector Protection Mode: When the device is first powered on, or comes out of a reset cycle, the PPB Lock bit set to the locked state, rather than cleared to the unlocked state. The only means to clear the PPB Lock bit is by writing a unique 64-bit Password to the device. The Password Mode Locking Bit, once set, prevents reading the 64-bit password on the DQ bus and further password programming. The Password Mode Locking Bit is not erasable. Once Password Mode Locking Bit is programmed, the Persistent Sector Protection Locking Bit is disabled from programming, guaranteeing that no changes to the protection scheme are allowed. The Password Sector Protection method is otherwise identical to the Persistent Sector Protection method. A 64-bit password is the only additional tool utilized in this method. Once the Password Mode Locking Bit is set, the password is permanently set with no means to read, program, or erase it. The password is used to clear the PPB Lock bit. The Password Unlock command must be written to the flash, along with a password. The flash device internally compares the given password with the pre-programmed password. If they match, the PPB Lock bit is cleared, and the PPBs can be altered. If they do not match, the flash device does nothing. There is a built-in 2 µs delay for each "password check." This delay is intended to thwart any efforts to run a program that tries all possible combinations in order to crack the password. 64-bit Password The 64-bit Password is located in its own memory space and is accessible through the use of the Password Program and Verify commands (see "Password Verify Command"). The password function works in conjunction with the Password Mode Locking Bit, which when set, prevents the Password Verify command from reading the contents of the password on the pins of the device. WRITE PROTECT (WP#) The Write Protect feature provides a hardware method of protecting sectors 0, 1, 268, and 269 without using VID. This function is provided by the WP# pin and overrides the previously discussed High Voltage Sector Protection method. Password and Password Mode Locking Bit In order to select the Password sector protection scheme, the customer must first program the password. The password may be correlated to the unique Electronic Serial Number (ESN) of the particular flash device. Each ESN is different for every flash device; therefore each password should be different for every flash device. While programming in the password region, the customer may perform Password Verify operations. If the system asserts VIL on the WP#/ACC pin, the device disables program and erase functions in the two outermost 4 Kword sectors on both ends of the flash array independent of whether it was previously protected or unprotected. If the system asserts VIH on the WP#/ACC pin, the device reverts to whether sectors 0, 1, 268, and 269 were last set to be protected or unprotected. That is, sector protection or unprotection for these sectors depends on whether they were last protected or unprotected using the method described in High Voltage Sector Protection. Once the desired password is programmed in, the customer must then set the Password Mode Locking Bit. This operation achieves two objectives: 1. Permanently sets the device to operate using the Password Protection Mode. It is not possible to reverse this function. Note that the WP#/ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result. 2. Disables all further commands to the password region. All program, and read operations are ignored. White Electronic Designs Corp. reserves the right to change products or specifications without notice. April 2006 Rev. 3 18 White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com White Electronic Designs W78M32V-XBX W78M32V-XBX Persistent Protection Bit Lock HIGH VOLTAGE SECTOR PROTECTION The Persistent Protection Bit (PPB) Lock is a volatile bit that reflects the state of the Password Mode Locking Bit after power-up reset. If the Password Mode Lock Bit is also set after a hardware reset (RESET# asserted) or a power-up reset, the ONLY means for clearing the PPB Lock Bit in Password Protection Mode is to issue the Password Unlock command. Successful execution of the Password Unlock command clears the PPB Lock Bit, allowing for sector PPBs modifications. Asserting RESET#, taking the device through a power-on reset, or issuing the PPB Lock Bit Set command sets the PPB Lock Bit to a "1" when the Password Mode Lock Bit is not set. Sector protection and unprotection may also be implemented using programming equipment. The procedure requires high voltage (VID) to be placed on the RESET# pin. Refer to Figure 2 for details on this procedure. Note that for sector unprotect, all unprotected sectors must first be protected prior to the first sector write cycle. If the Password Mode Locking Bit is not set, including Persistent Protection Mode, the PPB Lock Bit is cleared after power-up or hardware reset. The PPB Lock Bit is set by issuing the PPB Lock Bit Set command. Once set the only means for clearing the PPB Lock Bit is by issuing a hardware or power-up reset. The Password Unlock command is ignored in Persistent Protection Mode. White Electronic Designs Corp. reserves the right to change products or specifications without notice. April 2006 Rev. 3 19 White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com White Electronic Designs W78M32V-XBX W78M32V-XBX FIGURE 2. IN-SYSTEM SECTOR PROTECTION/SECTOR UNPROTECTION ALGORITHMS START START Protect all sectors: The indicated portion of the sector protect algorithm must be performed for all unprotected sectors prior to issuing the first sector unprotect address PLSCNT = 1 RESET# = V ID Wait 4 µs Temporary Sector Unprotect Mode No PLSCNT = 1 RESET# = V Wait 4 µs First Write Cycle = 60h? First Write Cycle = 60h? No Temporary Sector Unprotect Mode Yes Yes Set up sector address No Sector Protect: Write 60h to sector address with A7-A0 = 00000010 All sectors protected? Yes Set up first sector address Sector Unprotect: Write 60h to sector address with A7-A0 = 01000010 Wait 100 µs Increment PLSCNT ID Verify Sector Protect: Write 40h to sector address with A7-A0 = 00000010 Reset PLSCNT = 1 Wait 1.2 ms Read from sector address with A7-A0 = 00000010 Verify Sector Unprotect: Write 40h to sector address with A7-A0 = 00000010 Increment PLSCNT No No PLSCNT = 25? Yes No Yes Remove V ID from RESET# Yes PLSCNT = 1000? Protect another sector? No Write reset command Remove V ID from RESET# Remove V ID from RESET# Write reset command Write reset command Sector Protect complete Set up next sector address No Data = 00h? Yes Yes Sector Protect complete Device failed Read from sector address with A7-A0 = 00000010 Data = 01h? Last sector verified? No Yes Remove V ID from RESET# Sector Unprotect complete Write reset command Sector Protect Algorithm Device failed Sector Unprotect complete Sector Unprotect Algorithm White Electronic Designs Corp. reserves the right to change products or specifications without notice. April 2006 Rev. 3 20 White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com White Electronic Designs W78M32V-XBX W78M32V-XBX SecSi sector is divided into 64 factory-lockable words that can be programmed and locked by the user. The SecSi sector is located at addresses 000000h-00007Fh in both Persistent Protection mode and Password Protection mode. It uses indicator bits (DQ6, DQ7) to indicate the factorylocked and user-locked status of the part. TEMPORARY SECTOR UNPROTECT This feature allows temporary unprotection of previously protected sectors to change data in-system. The Sector Unprotect mode is activated by setting the RESET# pin to VID. During this mode, formerly protected sectors can be programmed or erased by selecting the sector addresses. Once VID is removed from the RESET# pin, all the previously protected sectors are protected again. Figure 3 shows the algorithm, and Figure 24 shows the timing diagrams, for this feature. While PPB lock is set, the device cannot enter the Temporary Sector Unprotection Mode. The system accesses the SecSi Sector through a command sequence (see "Enter SecSiTM Sector/Exit SecSi Sector Command Sequence"). After the sysem has written the Enter SecSi Sector command sequence, it may read the SecSi Sector by using the addresses normally occupied by the boot sectors. This mode of operation continues until the system issues the Exit SecSi Sector command sequence, or until power is removed from the device. On power-up, or following a hardware reset, the device reverts to sending commands to the normal address space. Note that the ACC function and unlock bypass modes are not available when the SecSi Sector is enabled. FIGURE 3. TEMPORARY SECTOR UNPROTECT OPERATION START Factory-Locked Area (64 words) The factory-locked area of the SecSi Sector (000000h00003Fh) is locked when the part is shipped, whether or not the area was programmed at the factory. The SecSi Sector Factory-locked Indicator Bit (DQ7) is permanently set to a "1". RESET# = VID (Note 1) Perform Erase or Program Operations User-Lockable Area (64 words) The user-lockable area of the SecSi Sector (000040h00007Eh) is shipped unprotected, which allows the user to program and optionally lock the area as appropriate for the application. The SecSi Sector User-locked Indicator Bit (DQ6) is shipped as "0" and can be permanently locked to "1" by issuing the SecSi Protection Bit Program Command. The SecSi Sector can be read any number of times, but can be programmed and locked only once. Note that the accelerated programming (ACC) and unlock bypass functions are not available when programming the SecSi Sector. RESET# = VIH Temporary Sector Unprotect Completed (Note 2) Notes: 1. All protected sectors unprotected (If WP#/ACC = VIL, sectors 0, 1, 268, 269 will remain protected). 2. All previously protected sectors are protected once again The User-lockable SecSi Sector area can be protected using one of the following procedures: Follow the SecSi Sector protection Agorithm as shown in Figure 4. This allows in-system protection of the SecSi Sector without raising any device pin to a high voltage. Note that this method is only appliacable to the SecSi Sector. SecSiTM (SECURED SILICON) SECTOR FLASH MEMORY REGION The SecSi (Secured Silicon) Sector feature provides a Flash memory region that enables permanent part identification through an Electronic Serial Number (ESN) The 128-word To verify the protect/unprotect status of the SecSi Sector, follow the algorithm shown in Figure 5. White Electronic Designs Corp. reserves the right to change products or specifications without notice. April 2006 Rev. 3 21 White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com White Electronic Designs W78M32V-XBX W78M32V-XBX FIGURE 4. SECSI SECTOR PROTECTION ALGORITHM START SecSiTM Sector Entry Write AAh to address 555h Write 55h to address 2AAh Write 88h to a address 555h SecSi Sector Entry SecSi Sector Protection Entry Write AAh to address 555h Write 55h to address 2AAh Write 60h to a address 555h PLSCNT = 1 Protect SecSi Sector: write 68h to sector address with A7-A0 = 00011010 Time out 256 µs Increment PLSCNT SecSi Sector Protection Verify SecSi Sector: write 48h to sector address with A7-A0 = 00011010 Read from sector address with A7-A0 = 00011010 No No PLSCNT = 25? Data = 01h? Yes Yes Device Failed SecSi Sector Protection Completed SecSi Sector Exit Write 555h/AAh Write 2AAh/55Ah Write SA0+555h/90h Write XXXh/00h SecSi Secto r Exit White Electronic Designs Corp. reserves the right to change products or specifications without notice. April 2006 Rev. 3 22 White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com White Electronic Designs program/erase circuits are disabled, and the device resets to the read mode. Subsequent writes are ignored until VCC is greater than VLKO. The system must provide the proper signals to the control pins to prevent unintentional writes when VCC is greater than VLKO. Once the SecSi Sector is locked and verified, the system must write the Exit SecSi Sector Region command sequence to return to reading and writing the remainder of the array. The SecSi Sector lock must be used with caution since, once locked, there is no procedure available for unlocking the SecSi Sector area and none of the bits in the SecSi Sector memory space can be modified in any way. Write Pulse "Glitch" Protection Noise pulses of less than 3 ns (typical) on OE#, CS#, or WE# do not initiate a write cycle. FIGURE 5. SecSi SECTOR PROTECT VERIFY Logical Inhibit Write cycles are inhibited by holding any one of OE# = VIL, CS# = VIH or WE# = VIH. To initiate a write cycle, CS# and WE# must be a logical zero while OE# is a logical one. START RESET# = VIH or VID Wait 1 µs Write 60h to any address Write 40h to SecSi Sector address with A6 = 0, A1 = 1, A0 = 0 Read from SecSi Sector address with A6 = 0, A1 = 1, A0 = 0 W78M32V-XBX W78M32V-XBX If data = 00h, SecSi Sector is unprotected. If data = 01h, SecSi Sector is protected. Power-Up Write Inhibit If WE# = CS# = VIL and OE# = VIH during power up, the device does not accept commands on the rising edge of WE#. The internal state machine is automatically reset to the read mode on power-up. Remove VIH or VID from RESET# COMMON FLASH MEMORY INTERFACE (CFI) Write reset command The Common Flash Interface (CFI) specification outlines device and host system software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. Software support can then be device-independent, JEDEC ID-independent, and forward- and backward-compatible for the specified flash device families. Flash vendors can standardize their existing interfaces for long-term compatibility. SecSi Sector Protect Verify complete This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to address 55h, any time the device is ready to read array data. The system can read CFI information at the addresses given in Tables 9­12. To terminate reading CFI data, the system must write the reset command. The CFI Query mode is not accessible when the device is executing an Embedded Program or embedded Erase algorithm. SecSi Sector Protection Bits The SecSi Sector Protection Bits prevent programming of the SecSi Sector memory area. Once set, the SecSi Sector memory area contents are non-modifiable. Hardware Data Protection The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes. In addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during VCC power-up and power-down transitions, or from system noise. The system can also write the CFI query command when the device is in the autoselect mode. The device enters the CFI query mode, and the system can read CFI data at the addresses given in Tables 9­12. The system must write the reset command to return the device to reading array data. Low VCC Write Inhibit When VCC is less than VLKO, the device does not accept any write cycles. This protects data during VCC power-up and power-down. The command register and all internal White Electronic Designs Corp. reserves the right to change products or specifications without notice. April 2006 Rev. 3 23 White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com White Electronic Designs W78M32V-XBX W78M32V-XBX TABLE 9. CFI QUERY IDENTIFICATION STRING Addresses 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah Data 0051h 0052h 0059h 0002h 0000h 0040h 0000h 0000h 0000h 0000h 0000h Description Query Unique ASCII string "QRY" Primary OEM Command Set Address for Primary Extended Table Alternate OEM Command Set (00h = none exists) Address for Alternate OEM Extended Table (00H = none exists) TABLE 10. SYSTEM INTERFACE STRING Addresses 1Bh Data 0027h 1Ch 0036h 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h 0000h 0000h 0004h 0000h 0009h 0000h 0005h 0000h 0004h 0000h Description VCC Min. (write/erase) D7-D4: volt, D3-D0: 100 millivolt VCC Max. (write/erase) D7-D4: volt, D3-D0: 100 millivolt VPP Min. voltage (00h = no VPP pin present) VPP Max. voltage (00h = no VPP pin present) Typical timeout per single byte/word write 2N µs Typical timeout for Min. size buffer write 2N µs (00h = not supported) Typical timeout per individual block erase 2N ms Typical timeout for full chip erase 2N ms (00h = not supported) Max. timeout for byte/word write 2N times typical Max. timeout for buffer write 2N times typical Max. timeout per individual block erase 2N times typical Max. timeout for full chip erase 2N times typical (00h = not supported) White Electronic Designs Corp. reserves the right to change products or specifications without notice. April 2006 Rev. 3 24 White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com White Electronic Designs W78M32V-XBX W78M32V-XBX TABLE 11. DEVICE GEOMETRY DEFINITION Addresses 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch Data 0018h 0001h 0000h 0000h 0000h 0003h 0007h 0000h 0020h 0000h 00FDh 0000h 0000h 0001h 0007h 0000h 0020h 0000h 0000h 0000h 0000h 0000h Description Device Size = 2N byte Flash Device Interface description Max. munber of byte in multi-byte write = 2N (00h = not supported) Number of Erase Block Region within device Erase Block Region 1 Information Erase Block Region 2 information Erase Block Region 3 Information Erase Block Region 4 Information White Electronic Designs Corp. reserves the right to change products or specifications without notice. April 2006 Rev. 3 25 White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com White Electronic Designs W78M32V-XBX W78M32V-XBX TABLE 12. PRIMARY VENDOR-SPECIFIC EXTENDED QUERY Addresses 40h 41h 42h 43h 44h 45h Data 0050h 0052h 0049h 0031h 0033h 000Ch 46h 0002h 47h 0001h 48h 0001h 49h 0007h 4Ah 00E7h 4Bh 0000h 4Ch 0002h 4Dh 0085h 4Eh 0095h 4Fh 0001h 50h 0001h 57h 0004h 58h 0027h 59h 0060h 5Ah 0060h 5Bh 0027h Description Query-unique ASCII String "PRI" Major version number, ASCII (reflects modifications to the silicon) Minor version number, ASCII (reflects modifications to the CFI table) Address Sensitive Unlock (Bits 1-0) 0 = Required, 1 = Not Required Silicon Revision Number (Bits 7-2) Erase Suspend 0 = Not Supported, 1 = To Read Only, 2 = To Read & Write Sector Protect 0 = Not Supported, X = Number of sectors in per group Sector Temporary Unprotect 00 = Not Supported, 01 = Supported Sector Protect/Unprotect scheme 01 = 29F040 29F040 mode, 02 = 29F016 29F016 mode, 03 = 29F400 29F400, 04 = 29LV800 29LV800 mode Simultaneous Operation 00 = Not Supported, X = Number of Sectors excluding Bank 1 Burst Mode Type 00 = Not Supported, 01 = Supported Page Mode Type 00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page ACC (Acceleration) Supply Minimum 00h = Not Supported, D7-D4; Volt, D3-D0: 100 mV ACC (Acceleration) Supply Maximum 00h = Not Supported, D7-D4; Volt, D3-D0: 100 mV Top/Bottom Boot Sector Flag 00h = Uniform Device, 02h = Bottom Boot Device, 03 = Top Boot Device, 04h = Both Top and Bottom Program Suspend 0 = Not supported, 1 = Supported Bank Organization 00 = Data at 4Ah is zero, X = Number of Banks Bank 1 Region Information X = Number of Sectors in Bank 1 Bank 2 Region Information X = Number of Sectors in Bank 2 Bank 3 Region Information X = Number of Sectors in Bank 3 Bank 4 Region Information X = Number of Sectors in Bank 4 White Electronic Designs Corp. reserves the right to change products or specifications without notice. April 2006 Rev. 3 26 White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com White Electronic Designs W78M32V-XBX W78M32V-XBX COMMAND DEFINITIONS ignores reset commands until the operation is complete. Writing specific address and data commands or sequences into the command register initiates device operations. Table 13 defines the valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. A reset command is then required to return the device to reading array data. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the bank to which the system was writing to the read mode. If the program command sequence is written to a bank that is in the Erase Suspend mode, writing the reset command returns that bank to the erase-suspendread mode. Once programming begins, however, the device ignores reset commands until the operation is complete. All addresses are latched on the falling edge of WE# or CS#, whichever happens later. All data is latched on the rising edge of WE# or CS#, whichever happens first. Refer to the AC Characteristic section for timing diagrams. The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to the read mode. If a bank entered the autoselect mode while in the Erase Suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. Reading Array Data The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. Each bank is ready to read array data after completing an Embedded Program or Embedded Erase algorithm. If DQ5 goes high during a program or erase operation, writing the reset command returns the banks to the read mode (or erase-suspend-read mode if that bank was in Erase Suspend). After the device accepts an Erase Suspend command, the corresponding bank enters the erase-suspend- read mode, after which the system can read data from any non-erasesuspended sector within the same bank. The system can read array data using the standard read timing, except that if it reads at an address within erase-suspended sectors, the device outputs status data. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See the Erase Suspend/Erase Resume Commands section for more information. Autoselect Command Sequence The autoselect command sequence allows the host system to access the manufacturer and device codes, and determine whether or not a sector is protected. The autoselect command sequence may be written to an address within a bank that is either in the read or erasesuspend-read mode. The autoselect command may not be written while the device is actively programming or erasing in the other bank. The autoselect command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle that contains the bank address and the autoselect command. The bank then enters the autoselect mode. The system may read any number of autoselect codes without reinitiating the command sequence. The system must issue the reset command to return a bank to the read (or erase-suspend-read) mode if DQ5 goes high during an active program or erase operation, or if the bank is in the autoselect mode. See the next section, Reset Command, for more information. See also Requirements for Reading Array Data in the Device Bus Operations section for more information. The AC Characteristic table provides the read parameters, and Figure 11 shows the timing diagram. Table 13 shows the address and data requirements. To determine sector protection information, the system must write to the appropriate bank address (BA) and sector address (SA). Table 4 shows the address range and bank number associated with each sector. Reset Command Writing the reset command resets the banks to the read or erase-suspend-read mode. Address bits are don't cares for this command. The system must write the reset command to return to the read mode (or erase-suspend-read mode if the bank was previously in Erase Suspend). The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the bank to which the system was writing to the read mode. Once erasure begins, however, the device Enter SecSiTM Sector/Exit SecSi Sector Command Sequence The SecSi Sector region provides a secured data area containing a random, eight word electronic serial number White Electronic Designs Corp. reserves the right to change products or specifications without notice. April 2006 Rev. 3 27 White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com White Electronic Designs W78M32V-XBX W78M32V-XBX (ESN). The system can access the SecSi Sector region by issuing the three-cycle Enter SecSi Sector command sequence. The device continues to access the SecSi Sector region until the system issues the four-cycle Exit SecSi Sector command sequence. The Exit SecSi Sector command sequence returns the device to normal operation. The SecSi Sector is not accessible when the device is executing an Embedded Program or embedded Erase algorithm. Table 13 shows the address and data requirements for both command sequences. See also "SecSiTM (Secured Silicon) Sector Flash Memory Region" for further information. Note that the ACC function and unlock bypass modes are not available when the SecSi Sector is enabled. data to a bank faster than using the standard program command sequence. The unlock bypass command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the unlock bypass command, 20h. That bank then enters the unlock bypass mode. A two-cycle unlock bypass program command sequence is all that is required to program in this mode. The first cycle in this sequence contains the unlock bypass program command, A0h; the second cycle contains the program address and data. Additional data is programmed in the same manner. This mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total programming time. Table 13 shows the requirements for the command sequence. Word Program Command Sequence During the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset commands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command sequence. (See Table 14) Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further controls or timings. The device automatically provides internally generated program pulses and verifies the programmed cell margin. Table 13 shows the address and data requirements for the program command sequence. Note that the SecSi Sector, autoselect, and CFI functions are unavailable when a [program/erase] operation is in progress. The device offers accelerated program operations through the WP#/ACC pin. When the system asserts VHH on the WP# ACC pin, the device automatically enters the Unlock Bypass mode. The system may then write the two-cycle Unlock Bypass program command sequence. The device uses the higher voltage on the WP#/ACC pin to accelerate the operation. Note that the WP#/ACC pin must not be at VHH any operation other than accelerated programming, or device damage may result. In addition, the WP#/ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result. When the Embedded Program algorithm is complete, that bank then returns to the read mode and addresses are no longer latched. The system can determine the status of the program operation by using DQ7, DQ6, or RY/BY#. Refer to the Write Operation Status section for information on these status bits. Figure 6 illustrates the algorithm for the program operation. Refer to the Erase and Program Operations table in the AC Characteristics section for parameters, and Figure 16 for timing diagrams. Any commands written to the device during the Embedded Program Algorithm are ignored. Note that a hardware reset immediately terminates the program operation. The program command sequence should be reinitiated once that bank has returned to the read mode, to ensure data integrity. Chip Erase Command Sequence Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the Embedded Erase algorithm. The device Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from "0" back to a "1." Attempting to do so may cause that bank to set DQ5 = 1, or cause the DQ7 and DQ6 status bits to indicate the operation was successful. However, a succeeding read will show that the data is still "0." Only erase operations can convert a "0" to a "1." Unlock Bypass Command Sequence The unlock bypass feature allows the system to program White Electronic Designs Corp. reserves the right to change products or specifications without notice. April 2006 Rev. 3 28 White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com White Electronic Designs W78M32V-XBX W78M32V-XBX is in progress. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the chip erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. FIGURE 6. PROGRAM OPERATION START Figure 7 illustrates the algorithm for the erase operation. Refer to the Erase and Program Operations tables in the AC Characteristics section for parameters, and Figure 17 section for timing diagrams. Write Program Command Sequence Sector Erase Command Sequence Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock cycles are written, and are then followed by the address of the sector to be erased, and the sector erase command. Table 13 shows the address and data requirements for the sector erase command sequence. Data Poll from System Embedded Program algorithm in progress Verify Data? No The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically programs and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. Yes Increment Address No Last Address? After the command sequence is written, a sector erase timeout of 50 µs occurs. During the time-out period, additional sector addresses and sector erase commands may be written. Loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. The time between these additional cycles must be less than 50 µs, otherwise erasure may begin. Any sector erase address and command following the exceeded timeout may or may not be accepted. It is recommended that processor interrupts be disabled during this time to ensure all commands are accepted. The interrupts can be reenabled after the last Sector Erase command is written. Any command other than Sector Erase or Erase Suspend during the time-out period resets that bank to the read mode. The system must rewrite the command sequence and any additional addresses and commands. Note that SecSi Sector, autoselect, and CFI functions are unavailable when a [program/erase] operation is in progress. Yes Programming Completed does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. Table 13 shows the address and data requirements for the chip erase command sequence. When the Embedded Erase algorithm is complete, that bank returns to the read mode and addresses are no longer latched. The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. Refer to the Write Operation Status section for information on these status bits. The system can monitor DQ3 to determine if the sector erase timer has timed out (See the section on DQ3: Sector Erase Timer). The time-out begins from the rising edge of the final WE# pulse in the command sequence. Any commands written during the chip erase operation are ignored. Note that SecSi Sector, autoselect, and CFI functions are unavailable when a [program/erase] operation When the Embedded Erase algorithm is complete, the bank returns to reading array data and addresses are no longer White Electronic Designs Corp. reserves the right to change products or specifications without notice. April 2006 Rev. 3 29 White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com White Electronic Designs latched. Note that while the Embedded Erase operation is in progress, the system can read data from the non-erasing bank. The system can determine the status of the erase operation by reading DQ7, DQ6, DQ2, or RY/BY# in the erasing bank. Refer to the Write Operation Status section for information on these status bits. ERASE SUSPEND/ERASE RESUME COMMANDS The Erase Suspend command, B0h, allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. The bank address is required when writing this command. This command is valid only during the sector erase operation, including the 80 µs time-out period during the sector erase command sequence. Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands are ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the sector erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. The Erase Suspend command is ignored if written during the chip erase operation or Embedded Program algorithm. When the Erase Suspend command is written during the sector erase operation, the device requires a maximum of 20 µs to suspend the erase operation. However, when the Erase Suspend command is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation. Addresses are "don't-cares" when writing the Erase suspend command. Figure 7 illustrates the algorithm for the erase operation. Refer to the Erase and Program Operations tables in the AC Characteristics section for parameters, and Figure 17 section for timing diagrams. After the erase operation has been suspended, the bank enters the erase-suspend-read mode. The system can read data from or program data to any sector not selected for erasure. (The device "erase suspends" all sectors selected for erasure.) Reading at any address within erase-suspended sectors produces status information on DQ7­DQ0. The system can use DQ7, or DQ6 and DQ2 together, to determine if a sector is actively erasing or is erase-suspended. Refer to the Write Operation Status section for information on these status bits. FIGURE 7. ERASE OPERATION START Write Erase Command Sequence (Notes 1, 2) Data Poll to Erasing Bank from System No W78M32V-XBX W78M32V-XBX After an erase-suspended program operation is complete, the bank returns to the erase-suspend-read mode. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard Word Program operation. Refer to the Write Operation Status section for more information. Embedded Erase algorithm in progress In the erase-suspend-read mode, the system can also issue the autoselect command sequence. The device allows reading autoselect codes even at addresses within erasing sectors, since the codes are not stored in the memory array. When the device exits the autoselect mode, the device reverts to the Erase Suspend mode, and is ready for another valid operation. Refer to the Autoselect Mode and Autoselect Command Sequence sections for details. Data = FFh? Yes Erasure Completed To resume the sector erase operation, the system must write the Erase Resume command (address bits are don't care). The bank address of the erase-suspended bank is required when writing this command. Further writes of the Resume Notes: 1. See Table 13 for erase command sequence. 2. See the section on DQ3 for information on the sector erase timer. White Electronic Designs Corp. reserves the right to change products or specifications without notice. April 2006 Rev. 3 30 White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com White Electronic Designs W78M32V-XBX W78M32V-XBX command are ignored. Another Erase Suspend command can be written after the chip has resumed erasing. PASSWORD PROTECTION MODE LOCKING BIT PROGRAM COMMAND PASSWORD PROGRAM COMMAND The Password Protection Mode Locking Bit Program Command programs the Password Protection Mode Locking Bit, which prevents further verifies or updates to the Password. Once programmed, the Password Protection Mode Locking Bit cannot be erased! If the password Protection Mode Locking Bit is verified as program without margin, the Password Protection Mode Locking Bit Program command can be executed to improve the program margin. Once the Password Protection Mode Locking Bit is programmed, the Persistent Sector Protection Locking Bit program circuitry is disabled, thereby forcing the device to remain in the Password Protection mode. Exiting the Mode Locking Bit Program command is accomplished by writing the Read/Reset command. The Password Program Command permits programming the password that is used as part of the hardware protection scheme. The actual password is 64-bits long. Four Password Program commands are required to program the password. The system must enter the unlock cycle, password program command (38h) and the program address/data for each portion of the password when programming. There are no provisions for entering the 2-cycle unlock cycle, the password program command, and all the password data. There is no special addressing order required for programming the password. Also, when the password is undergoing programming, Simultaneous Operation is disabled. Read operations to any memory location will return the programming status. Once programming is complete, the user must issue a Read/Reset command to return the device to normal operation. Once the Password is written and verified, the Password Mode Locking Bit must be set in order to prevent verification. The Password Program Command is only capable of programming "0"s. Programming a "1" after a cell is programmed as a "0" results in a time-out by the Embedded Program AlgorithmTM with the cell remaining as a "0". The password is all ones when shipped from the factory. All 64-bit password combinations are valid as a password. PERSISTENT SECTOR PROTECTION MODE LOCKING BIT PROGRAM COMMAND The Persistent Sector Protection Mode Locking Bit Program Command programs the Persistent Sector Protection Mode Locking Bit, which prevents the Password Mode Locking Bit from ever being programmed. If the Persistent Sector Protection Mode Locking Bit is verified as programmed without margin, the Persistent Sector Protection Mode Locking Bit Program Command should be reissued to improve program margin. By disabling the program circuitry of the Password Mode Locking Bit, the device is forced to remain in the Persistent Sector Protection mode of operation, once this bit is set. Exiting the Persistent Protection Mode Locking Bit Program command is accomplished by writing the Read/Reset command. PASSWORD VERIFY COMMAND The Password Verify Command is used to verify the Password. The Password is verifiable only when the Password Mode Locking Bit is not programmed. If the Password Mode Locking Bit is programmed and the user attempts to verify the Password, the device will always drive all F's onto the DQ data bus. SecSi SECTOR PROTECTION BIT PROGRAM COMMAND The Password Verify command is permitted if the SecSi sector is enabled. Also, the device will not operate in Simultaneous Operation when the Password Verify command is executed. Only the password is returned regardless of the bank address. The lower two address bits (A1-A0) are valid during the Password Verify. Writing the Read/Reset command returns the device back to normal operation. The SecSi Sector Protection Bit Program Command programs the SecSi Sector Protection Bit, which prevents the SecSi sector memory from being cleared. If the SecSi Sector Protection Bit is verified as programmed without margin, the SecSi Sector Protection Bit Program Command should be reissued to improve program margin. Exiting the VCC-level SecSi Sector Protection Bit Program Command is accomplished by writing the Read/Reset command. White Electronic Designs Corp. reserves the right to change products or specifications without notice. April 2006 Rev. 3 31 White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com White Electronic Designs W78M32V-XBX W78M32V-XBX PPB LOCK BIT SET COMMAND PPB PROGRAM COMMAND The PPB Lock Bit Set command is used to set the PPB Lock bit if it is cleared either at reset or if the Password Unlock command was successfully executed. There is no PPB Lock Bit Clear command. The PPB Program command is used to program, or set, a given PPB. Each PPB is individually programmed (but is bulk erased with the other PPBs). The specific sector address (A22­A12) are written at the same time as the program command 60h with A6 = 0. If the PPB Lock Bit is set and the corresponding PPB is set for the sector, the PPB Program command will not execute and the command will time-out without programming the PPB. Once the PPB Lock Bit is set, it cannot be cleared unless the device is taken through a power-on clear or the Password Unlock command is executed. Upon setting the PPB Lock Bit, the PPBs are latched into the DYBs. If the Password Mode Locking Bit is set, the PPB Lock Bit status is reflected as set, even after a power-on reset cycle. Exiting the PPB Lock Bit Set command is accomplished by writing the Read/ Reset command (only in the Persistent Protection Mode). After programming a PPB, two additional cycles are needed to determine whether the PPB has been programmed with margin. If the PPB has been programmed without margin, the program command should be reissued to improve the program margin. Also note that the total number of PPB program/erase cycles is limited to 100 cycles. Cycling the PPBs beyond 100 cycles is not guaranteed. DYB WRITE COMMAND The DYB Write command is used to set or clear a DYB for a given sector. The high order address bits The PPB Program command does not follow the Embedded Program algorithm. (A22­A12) are issued at the same time as the code 01h or 00h on DQ7-DQ0. All other DQ data bus pins are ignored during the data write cycle. The DYBs are modifiable at any time, regardless of the state of the PPB or PPB Lock Bit. The DYBs are cleared at power-up or hardware reset. Exiting the DYB Write command is accomplished by writing the Read/Reset command. ALL PPB ERASE COMMAND The All PPB Erase command is used to erase all PPBs in bulk. There is no means for individually erasing a specific PPB. Unlike the PPB program, no specific sector address is required. However, when the PPB erase command is written all Sector PPBs are erased in parallel. If the PPB Lock Bit is set the ALL PPB Erase command will not execute and the command will time-out without erasing the PPBs. After erasing the PPBs, two additional cycles are needed to determine whether the PPB has been erased with margin. If the PPBs has been erased without margin, the erase command should be reissued to improve the program margin. PASSWORD UNLOCK COMMAND The Password Unlock command is used to clear the PPB Lock Bit so that the PPBs can be unlocked for modification, thereby allowing the PPBs to become accessible for modification. The exact password must be entered in order for the unlocking function to occur. This command cannot be issued any faster than 2 µs at a time to prevent a hacker from running through all 64-bit combinations in an attempt to correctly match a password. If the command is issued before the 2 µs execution window for each portion of the unlock, the command will be ignored. It is the responsibility of the user to preprogram all PPBs prior to issuing the All PPB Erase command. If the user attempts to erase a cleared PPB, over-erasure may occur making it difficult to program the PPB at a later time. Also note that the total number of PPB program/erase cycles is limited to 100 cycles. Cycling the PPBs beyond 100 cycles is not guaranteed. Once the Password Unlock command is entered, the RY/BY# indicates that the device is busy. Approximately 1 µs is required for each portion of the unlock. Once the first portion of the password unlock completes (RY/BY# is not low or DQ6 does not toggle when read), the next part of the password is written. The system must thus monitor RY/BY# or the status bits to confirm when to write the next portion of the password. Seven cycles are required to successfully clear the PPB Lock Bit. White Electronic Designs Corp. reserves the right to change products or specifications without notice. April 2006 Rev. 3 32 White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com White Electronic Designs W78M32V-XBX W78M32V-XBX DYB WRITE COMMAND PPB STATUS COMMAND The DYB Write command is used for setting the DYB, which is a volatile bit that is cleared at reset. There is one DYB per sector. If the PPB is set, the sector is protected regardless of the value of the DYB. If the PPB is cleared, setting the DYB to a 1 protects the sector from programs or erases. Since this is a volatile bit, removing power or resetting the device will clear the DYBs. The bank address is latched when the command is written. The programming of the PPB for a given sector can be verified by writing a PPB status verify command to the device. PPB LOCK BIT STATUS COMMAND The programming of the PPB Lock Bit for a given sector can be verified by writing a PPB Lock Bit status verify command to the device. PPB LOCK BIT SET COMMAND SECTOR PROTECTION STATUS COMMAND The PPB Lock Bit set command is used for setting the DYB, which is a volatile bit that is cleared at reset. There is one DYB per sector. If the PPB is set, the sector is protected regardless of the value of the DYB. If the PPB is cleared, setting the DYB to a 1 protects the sector from programs or erases. Since this is a volatile bit, removing power or resetting the device will clear the DYBs. The bank address is la