W6692 AD31-AD0 AD31-0 AD31-AD24 PEB2091 100PPM IO0-IO10 441/Q AR8/10 AI8/10 - Datasheet Archive
PCI ISDN S/T-CONTROLLER Table of Contents1. GENERAL DESCRIPTION. 5 2.
W6692 W6692 PCI ISDN S/T-CONTROLLER Table of Contents1. GENERAL DESCRIPTION. 5 2. FEATURES. 5 3. PIN CONFIGURATION . 6 4. PIN DESCRIPTION. 6 5. SYSTEM DIAGRAM AND APPLICATIONS. 9 6. BLOCK DIAGRAM . 10 7. FUNCTIONAL DESCRIPTIONS. 11 7.1 Main Block Functions.11 7.2 Layer 1 Functions Descriptions .12 7.2.1 S/T Interface Transmitter/Receiver .12 7.2.2 Receiver Clock Recovery And Timing Generation .15 7.2.3 Layer 1 Activation/Deactivation .16 184.108.40.206 States Descriptions and Command/Indication Codes. 16 220.127.116.11 State Transition Diagrams . 18 7.2.4 D Channel Access Control.21 7.2.5 Frame Alignment .21 18.104.22.168 FAinfA_1fr. 22 22.214.171.124 FAinfB_1fr. 22 126.96.36.199 FAinfD_1fr . 22 188.8.131.52 FAinfA_kfr. 23 184.108.40.206 FAinfB_kfr. 24 220.127.116.11 FAinfD_kfr . 24 18.104.22.168 Faregain. 24 7.2.6 Multiframe Synchronization .25 7.2.7 Test Functions .26 7.3 Serial Interface Bus .27 7.4 B Channel Switching.28 7.5 PCM Port.28 7.6 D Channel HDLC Controller.28 7.6.1 D Channel Message Transfer Modes .30 7.6.2 Reception of Frames in D Channel .30 7.6.3 Transmission of Frames in D Channel.31 -1- Publication Release Date: October 1998 Revision A1 W6692 W6692 7.7 B Channel HDLC Controller.32 7.7.1 Reception of Frames in B Channel .32 7.7.2 Transmission of Frames in B Channel.33 7.8 GCI Mode Serial Interface Bus .34 7.8.1 GCI Mode C/I Channel Handling .35 7.8.2 GCI Mode Monitor Channel Handling .35 7.9 PCI Interface Circuit.36 7.9.1 PCI Slave Mode And Configuration Serial EEPROM.36 7.9.2 Cascade Structure of Interrupt Sources .39 7.10 Peripheral Control.41 8. REGISTER DESCRIPTIONS . 42 8.1 Chip Control and D_ch HDLC controller .42 8.1.1 D_ch receive FIFO D_RFIFO Read Address 00H .44 8.1.2 D_ch transmit FIFO D_XFIFO Write Address 04H.44 8.1.3 D_ch command register D_CMDR Write Address 08H .44 8.1.4 D_ch Mode Register D_MODE Read/Write Address 0CH .45 8.1.5 D_ch Timer Register D_TIMR Read/Write Address 10H .46 8.1.6 Interrupt Status Register ISTA Read_clear Address 14H.46 8.1.7 Interrupt Mask Register IMASK R/W Address 18H.48 8.1.8 D_ch Extended Interrupt Register D_EXIR Read_clear Address 1CH.48 8.1.9 D_ch Extended Interrupt Mask Register D_EXIM Read/Write Address 20H.49 8.1.10 D_ch Status Register D_STAR Read Address 24H .49 8.1.11 D_ch Receive Status Register D_RSTA Read Address 28H .50 8.1.12 D_ch SAPI Address Mask D_SAM Read/Write Address 2CH .50 8.1.13 D_ch SAPI1 Register D_SAP1 Read/Write Address 30H .50 8.1.14 D_ch SAPI2 Register D_SAP2 Read/Write Address 34H .51 8.1.15 D_ch TEI Address Mask D_TAM Read/Write Address 38H .51 8.1.16 D_ch TEI1 Register D_TEI1 Read/Write Address 3CH.51 8.1.17 D_ch TEI2 Register D_TEI2 Read/Write Address 40H .51 8.1.18 D_ch Receive Frame Byte Count High D_RBCH Read Address 44H.52 8.1.19 D_ch Receive Frame Byte Count Low D_RBCL Read Address 48H .52 8.1.20 Timer 2 TIMR2 Write Address 4CH .52 8.1.21 Layer 1_Ready Code L1_RC Read/Write Address 50H .53 8.1.22 D_ch Control Register D_CTL Read/Write Address 54H .53 8.1.23 Command/Indication Receive Register CIR Read Address 58H .54 8.1.24 Command/Indication Transmit Register CIX Write Address 5CH .55 -2- W6692 W6692 8.1.25 S/Q Channel Receive Register SQR Read Address 60H .55 8.1.26 S/Q Channel Transmit Register SQX Write Address 64H.56 8.1.27 Peripheral Control Register PCTL Read/Write Address 68H.56 8.1.28 Monitor Receive Channel MOR Read Address 6CH .57 8.1.29 Monitor Transmit Channel MOX Read/Write Address 70H .58 8.1.30 Monitor Channel Status Register MOSR Read_clear Address 74H.58 8.1.31 Monitor Channel Control Register MOCR 8.1.32 GCI Mode Control Register GCR Read/Write Read/Write Address 78H .58 Address 7CH .59 8.1.33 Peripheral Address Register XADDR Read/Write Address F4H.60 8.1.34 Peripheral Data Register XDATA Read/Write Address F8H.61 8.1.35 Serial EEPROM Control Register EPCTL Write Address 68H .62 8.2 B1 HDLC controler .62 8.2.1 B1_ch receive FIFO B1_RFIFO Read Address 80H .63 8.2.2 B1_ch transmit FIFO B1_XFIFO Write Address 84H .63 8.2.3 B1_ch command register B1_CMDR Write Address 88H .63 8.2.4 B1_ch Mode Register B1_MODE Read/Write Address 8CH.64 8.2.5 B1_ch Extended Interrupt Register B1_EXIR Read_clear Address 90H.66 8.2.6 B1_ch Extended Interrupt Mask Register 8.2.7 B1_ch Status Register B1_STAR B1_EXIM Read/Write Address 94H .66 Read Address 98H.66 8.2.8 B1_ch Address Mask Register 1 B1_ADM1 Read/Write Address 9CH.67 8.2.9 B1_ch Address Mask Register 2 B1_ADM2 Read/Write Address A0H.67 8.2.10 B1_ch Address Register 1 B1_ADR1 Read/Write Address A4H .68 8.2.11 B1_ch Address Register 2 B1_ADR2 Read/Write Address A8H .68 8.2.12 B1_ch Receive Frame Byte Count Low B1_RBCL Read Address ACH.68 8.2.13 B1_ch Receive Frame Byte Count High B1_RBCH Read Address B0H .68 8.3 B2 HDLC controller.69 8.4 PCI Configuration Register .70 8.4.1 Device/Vendor ID Register Read Address 00 H .71 8.4.2 Status/Command Register Read/Write Address 04H .71 8.4.3 Class Code/Revision ID Register Read Address 08H .73 8.4.4 Header Type/Latency Timer Register Read Address 0CH .74 8.4.5 Base Address Register 0 Read/Write Address 10H.74 8.4.6 Base Address Register 1 Read/Write Address 14H.76 8.4.7 Subsystem/Subsystem Vendor ID Register Read Address 2CH .76 8.4.8 Interrupt Line Register Read/Write Address 3CH .77 -3- Publication Release Date: October 1998 Revision A1 W6692 W6692 9. ELECTRICAL CHARACTERISTICS. 77 9.1 Absolute Maximum Rating .77 9.2 Power Supply .78 9.3 DC Characteristics.78 9.4 Preliminary Switching Characteristics .80 9.4.1 PCM Interface Timing .80 9.4.2 Serial EEPROM Timing.81 9.4.3 Peripheral Interface Timing .82 9.5 AC Timing Test Conditions .83 10. PACKAGE DIMENSIONS . 83 -4- W6692 W6692 1. GENERAL DESCRIPTION The Winbond's single chip PCI bus ISDN S/T interface controller (W6692 W6692) is an all-in-one device suitable for ISDN Internet access. Three HDLC controllers are incorporated in the chip, one for D channel and the other two for B channels. These HDLC controllers facilitate efficient access to signalling and data services. The PCM codec interface provides voice service or other services. The built in PCI 2.1 interface circuit makes glueless design for PCI bus add-on card application. 2. FEATURES · Full duplex 2B + D S/T-interface transceiver compatible with ITU-T I.430 Recommendation - Four wire operation - Received clock recovery - Layer 1 activation/deactivation procedures - D channel access control - Supports multiframe synchronization · Supports LAPD protocol - Flag generation/recognition - Bit stuffing (zero insertion/deletion) - Frame Check Sequence (FCS) generation/check - Maskable address recognition - FIFO buffer (2 × 128 bytes) · Two B channel HDLC controllers - Maskable address recognition - Bit rate options: 56 or 64 kbps - Transparent (HDLC mode) or extended transparent mode (clear channel) - FIFO buffer (2 × 128 bytes) per B channel · Two PCM codec interfaces for speech and POTS application · Various B channel switching capabilities · GCI interface for connection with U transceiver · Built in PCI 2.1 slave mode circuit · Serial EEPROM interface for PCI configuration · Timer, interrupt input, IO/microprocessor interface for POTS or other peripheral control · +5 volt power supply · Advanced CMOS technology · Low power consumption · Packaged in 100-pin QFP -5- Publication Release Date: October 1998 Revision A1 W6692 W6692 3. PIN CONFIGURATION I OI I 1 OO 098 I / / / EE NX XX P P E T WR A S S P A R DL D D S # B BE I O K RST# VSSD VDDD CLK AD31 AD30 AD29 VSSB VDDB AD28 AD27 AD26 AD25 AD24 C/BE3# IDSEL AD23 AD22 AD21 AD20 P DV V P P F E P D F D OS D R T C C C S I US D X X K S L CN TD D D D 1 PT X PF E T V VT B C S R S DA C K T S S DL K 2 P T D D2 X T ASS L XX 1 2 1 X I N T I N 1 X I N T I N 0 V D D A 81 8 7 7 7 7 7 7 7 7 7 7 6 6 6 6 6 6 6 6 6 6 5 5 5 5 5 5 5 5 5 50 82 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 49 83 48 84 47 46 85 86 45 W6692 W6692 87 44 88 43 ISDN-PCI 89 42 90 41 91 40 39 92 93 38 94 37 95 36 96 35 97 34 98 33 99 32 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 31 100 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 I I I I V O O OO S 01 23 S / / / / B X X XX A A AA D D DD 01 23 VA DD D1 B9 AA AC DD D/ 11 1B 87 6E 2 # FI TD RRR E ADDV MY Y S E# # E # L # V S S D VSP DTE D OR DPR ## TP OA UR T 2 SR2 SR1 VSSA AD0 AD1 AD2 AD3 VDDB VSSB AD4 AD5 AD6 AD7 C/BE0# AD8 AD9 AD10 AD11 VDDB VSSB CAAA I I I I A / D D D OO OO D B1 1 1 4 5 6 7 1 E5 4 3 / / / / 2 XX XX 1 AA AA # DD DD 45 6 7 Figure 3.1 4. PIN DESCRIPTION Table 4.1 W6692 W6692 pin descriptions Notation: The suffix "#" indicates an active LOW signal. PIN NAME PIN NO. TYPE FUNCTIONS PCI BUS AD31-AD0 AD31-AD0 C/BE3#-C/BE0# 85, 86, 87, 90, 91, 92, 93, 94, 97, 98, 99, 100, 7, 8, 9, 10, 23, 24, 25, 30, 33, 34, 35, 36, 38, 39, 40, 41, 44, 45, 46, 47 I/O Address and Data are multiplexed on the same PCI pins. During the address phase, AD31-0 AD31-0 contain a 32-bit physical address. During the data phase, AD7-AD0 contain the least significant byte and AD31-AD24 AD31-AD24 contain the most significant byte. 95, 11, 22, 37 I Bus command and Byte Enables are multiplexed on the same PCI pins. During the address phase of a transaction, C/BE3#-C/BE0# define the bus command. During data phase, C/BE3#-C/BE0# are used as Byte Enable. -6- W6692 W6692 Pin Description, contiuned PIN NAME PIN NO. TYPE FUNCTIONS PAR 21 I/O Parity is even parity across AD31-AD0 AD31-AD0 and C/BE3#C/BE0#. FRAME# 12 I FRAME# is asserted to indicate a bus transaction is beginning. PCI BUS TRDY# 14 O Target Ready indicates W6692 W6692 is able to complete the current data phase of the transaction. IRDY# 13 I Initiator Ready indicates the bus masters ability to complete the current data phase of the transaction. STOP# 18 O Stop indicates W6692 W6692 is requesting the master to stop the current transaction. DEVSEL# 15 O Device Select indicates W6692 W6692 has decoded its address as the target of the current access. IDSEL 96 I Initialization Device Select is used as chip select during configuration read and write transactions. PERR# 19 O Parity Error is only for the reporting of data parity errors. CLK 84 I PCI Clock. All other PCI signals, except RST#, INTA# are sampled on the rising edge of CLK. RST# 81 I PCI Reset. RST# may be asynchronous to CLK when asserted or deasserted. INTA# 80 O Interrupt. This is level sensitive, active LOW and open drain output. DCL 72 I GCI Bus Data Clock of the frequency: 1.536 MHz. FSC 71 I GCI Bus Frame Synchronization Clock: 8 KHz. DIN 70 I GCI Bus Data Port 0 (ex: must be connectted to Siemens PEB2091 PEB2091's DOUT pin). DOUT 69 O GCI Bus Data Port 1 (ex: must be connectted to Siemens PEB2091 PEB2091's DIN pin) GCI BUS PCM BUS PFCK1 64 O PCM port 1 frame synchronization signal, with 8 KHz repetition rate and 8 bit pulse width. PFCK2 62 O PCM port 2 frame synchronization signal, with 8 KHz repetition rate and 8 bit pulse width. PBCK 63 O PCM bit synchronization clock of 1.536 MHz. PTXD 65 O PCM transmit data output. A maximum of two channels with 64 Kbit/s data rate can be multiplexed on this signal. -7- Publication Release Date: October 1998 Revision A1 W6692 W6692 Pin Description, contiuned PIN NAME PRXD PIN NO. TYPE 66 I FUNCTIONS PCM receive data input. A maximum of two channels with 64 Kbit/s data rate can be multiplexed on this signal. ISDN SIGNALS AND EXTERNAL CRYSTAL SR1 49 I S/T bus receiver input (negative). SR2 50 I S/T bus receiver input (positive). SX1 54 O S/T bus transmitter output (positive). SX2 55 O S/T bus transmitter output (negative). XTAL1 56 I Crystal or Oscillator clock input. The clock frequency: 7.68 MHz ±100PPM 100PPM. XTAL2 57 O Crystal clock output. Left unconnected when using oscillator. EXTERNAL EEPROM INTERFACE EPCS 73 O Serial EEPROM chip select (active HIGH). EPSK 74 O Serial EEPROM data clock (clock frequency < 250 KHz). EPSDI 76 I Serial EEPROM data input (must be connected to external EEPROM's data output). EPSDO 75 O Serial EEPROM data output (must be connected to external EEPROM's data input). FUNCTIONAL TEST TESTP 61 I Used to enable normal operation (1) or enter test mode (0). TRST 60 O If terminal equipment function is enabled, the reset pulse width is: - 125 uS when generated by the watchdog timer. - 16 mS when generated by exchange awake indication code change. PERIPHERAL CONTROL TOUT2 20 O Timer 2 output. A square wave with 50% duty cycle, 2- 126 mS period can be generated. XINTIN0 52 I A level change (either direction) will generate a maskable interrupt on the PCI bus interrupt request pin INTA#. XINTIN1 53 I A level change (either direction) will generate a maskable interrupt on the PCI bus interrupt request pin INTA#. -8- W6692 W6692 Pin Description, contiuned PIN NAME PIN NO. TYPE FUNCTIONS 79, 78, 77, 29, 28, 27, 26, 4, 3, 2, 1 I/O When confiured as simple IO mode (PCTL: XMODE = 0), these pins can read/write data from/to peripheral components. The pin directions are selected via register. 29, 28, 27, 26, 4, 3, 2, 1 I/O When configured as microprocessor mode (PCTL: XMODE = 1), address and data are multiplexed on these pins. XALE 77 O When configured as microprocessor mode (PCTL: XMODE = 1), this is the Address Latch Enable output. XRDB 78 O When configured as microprocessor mode (PCTL: XMODE = 1), this is the read pulse. XWRB 79 O When configured as microprocessor mode (PCTL: XMODE = 1), this is the write pulse. IO0-IO10 IO0-IO10 XAD7-XAD0 POWER AND GROUND VDDD 17, 58, 67, 83 I Digital Power Supply (5V ±5%). VDDA 51 I Analog Power Supply (5V ±5%). VDDB 6, 32, 43, 89 I PCI Bus Power Supply. VSSD 16, 59, 68, 82 I Digital Ground. VSSA 48 I Analog Ground. VSSB 5, 31, 42, 88 I PCI Bus Ground. 5. SYSTEM DIAGRAM AND APPLICATIONS Typical applications include: - PCI passive S-card for data only service - PCI passive S-card with one handset/POTS connection - PCI passive S-card with two POTS connections The all-in-one characteristic of W6692 W6692 makes it excellent for ISDN Internet-access passive card applications. The booming home PC market and powerful CPU capability make it possible to make a very low-cost ISDN Internet access card by using CPU's computing power and user friendly PCI interface. W6692 W6692 is designed for this type of scenario. W6692 W6692 integrates three HDLC controllers in the chip and interfaces to PCI bus directly. In addition, W6692 W6692 provides peripheral control circuits for PCM CODEC and POTS interface. In the first and second applications, the all-in-one feature of W6692 W6692 makes glue circuit unnecessary. In the third application, only a few TTL-like glue circuits are needed for the two POTS interface control. -9- Publication Release Date: October 1998 Revision A1 W6692 W6692 NT EEPROM 4-wire S/T Transformer Module Protection Circuit W6692 W6692 PCI S-Controller Phone POTS Circuit x2 PCM Codec x2 Fax Figure 5.1 ISDN Internet passive S-card with two pots connections 6. BLOCK DIAGRAM The block diagram of W6692 W6692 is shown in Figure 6.1 B2 2B+D 4-wire S/T Line Transceiver & AMI/BIN Conversion B1 Serial Interface Bus (SIB) D B-channel Switching Crystal/Oscillator (7.68 MHz) POTS circuit GCI Circuit D HDLC Controller B1 HDLC Controller B2 HDLC Controller FIFO 2B+D GCI Bus FIFO FIFO DPLL and Timing Generator PCI Interface Circuit Peripheral Control PCI Bus Figure 6.1 W6692 W6692 Functional Block Diagram - 10 - PCM Port PCM CODEC W6692 W6692 7. FUNCTIONAL DESCRIPTIONS 7.1 Main Block Functions The functional block diagram of W6692 W6692 is shown in Figure 6.1. The main function blocks are: - - - - - - - - - Layer 1 function according to ITU-T I.430 Serial Interface Bus (SIB) B channel switching supports GCI bus interface PCM port (x 2) D channel HDLC controller B channel HDLC controllers (x 2) PCI interface circuit Peripheral control The layer 1 function includes: - - - - - - - S/T bus transmitter/receiver Timing recovery using Digital Phase Locked Loop (DPLL) circuit Layer 1 activation/deactivation D channel access control Frame alignment Multiframe synchronization Test functions The serial interface bus performs the multiplexing/demultiplexing of D and 2B channels. The B channel switching determines the connection between layer1/GCI, layer 2 and PCM. The GCI circuit is used to connect a U transceiver. In this case, the layer 1 function of S/T interface is disabled. After power up or reset, the GCI circuit is disabled and the S/T layer 1 function is enabled. The PCM port provides two 64 kbps clear channels to connect to PCM codec chips. The D channel HDLC controller performs the LAPD (Link Access Procedure on the D channel) protocol according to ITU-T I.441/Q 441/Q.921 recommendation. There are two independent B channel HDLC controllers. They can be used to support HDLC-like protocols such as Internet PPP. The PCI interface circuit implements PCI specification revision 2.1 slave mode function. The peripheral control block is used to control other peripheral devices such as CODEC, POTS, LEDs or device with microprocessor interface. - 11 - Publication Release Date: October 1998 Revision A1 W6692 W6692 7.2 Layer 1 Functions Descriptions The layer 1 functions includes: - Transmitter/Receiver which conform to the electrical specifications of ITU-T I.430 - Receiver clock recovery and timing generation - Output phase delay (deviation) compensation - Layer 1 activation/deactivation procedures - D channel access control - Frame alignment - Multiframe synchronization - Test functions 7.2.1 S/T Interface Transmitter/Receiver According to ITU-T I.430, pseudo-ternary code with 100% pulse width is used in both directions of transmission on the S/T interface. The binary "1" is represented by no line signal (zero volt), whereas a binary "0" is represented by a positive or negative pulse. Data transmissions on the S/T interface are arranged as frame structures. The frame is 250 µs long and consists of 48 bits, which corresponds to a 192 kbit/s line rate. Each frame carries two octets of B1 channel, two octets of B2 channel and four D channel bits. Therefore, the 2B+D data rate is 144 kbit/s. The frame structure is shown in Figure 7.1. The frame begin is marked by a framing bit, which is followed by a DC balancing bit. The first binary "0" following the framing bit balancing bit is of the same polarity as the framing bit balancing bit, and subsequent binary zeros must alternate in polarity. - 12 - W6692 W6692 48 bits in 250 µs NT TE D L F L B1B1B1B1B1B1B1B1 E D A FAN B2B2B2B2B2B2B2B2 E D MB1B1B1B1B1B1B1B1 E D S B2B2B2B2B2B2B2B2 E 0 1 0 2 bits TE NT D L F L B1B1B1B1B1B1B1B1 L D L FA L B2B2B2B2B2B2B2B2 L D L B1B1B1B1B1B1B1B1 L D L B2B2B2B2B2B2B2B2 L D L F L 0 1 0 F = Framing bit L = DC balancing bit D = D channel bit E = D channel echo bit FA = Auxiliary framing bit or Q-bit N = Bit set to a binary value N=FA B1 = Bit within B channel 1 B2 = Bit within B channel 2 A = Bit used for activation S = Bit used for S channel M = Multiframe bit Figure 7.1 Frame structure at s/t interface There are three wiring configurations according to I.430: point-to-point, short passive bus and extended pass bus. They are shown in Figure 7.2. - 13 - Publication Release Date: October 1998 Revision A1 W6692 W6692 W669 TE 1000 m TR TR NT TR NT TR NT (a) Point-to-point configuration 100~200 m TR 10m W669 W669 . TE1 TE8 (b) Short passive bus configuration 100~200 m 50m TR 10m W669 TE1 . W669 TE8 (c) Extended passive bus configuration TR: Terminating Figure 7.2 W6692 W6692 wiring configuration in te applications The transmitter and receiver are implemented by differential circuits to increase signal to noise ratio (SNR). The nominal differential line pulse amplitude at 100 termination is 750 mV, zero to peak. Transformers with 2:1 turn ration are needed at transmitter and receiver for voltage level translation and DC isolation. To meet the electrical characteristic requirements in I.430, some additional circuits are needed. At the transmitter side, the external resistors (18 to 33 ) are used to adjust the output pulse amplitude and to meet the transmitter active impedance ( 20 when transmitting binary zeros). At the receiver side, the 1.8 k resistors protect the device inputs, while the 10 k resistors (1.8 k +8.2 k) limit the peak current in impedance tests. The diode bridge is used for overvoltage protection. - 14 - W6692 W6692 18-33 2:1 SX1 GND 100 VDD 18-33 SX2 Figure 7.3 External transmitter circuitry 8.2 K 1.8 K 2:1 SR1 VDD GND 100 8.2 K 1.8 K SR2 Figure 7.4 External receiver circuitry After hardware reset, the receiver may enter power down state to save power. In thist state, the internal clocks are turned off, but the analog level detector is still active to detect signal coming from the S interface. The power down state is left either by non-INFO 0 signal from S interface or C/I command from micro-processor. 7.2.2 Receiver Clock Recovery And Timing Generation A Digital Phase Locked Loop (DPLL) circuit is used to derive the receive clock from the received data stream. This DPLL uses a 7.68 MHz clock as reference. According to I.430, the transmit clock is normally delayed by 2 bit time from the receive clock. The "total phase deviation input to output" is 7% to +15% of a bit period. In some cases, delay compensation may be needed to meet this requirement (see OPS1-0 bits in D_CTL register). - 15 - Publication Release Date: October 1998 Revision A1 W6692 W6692 Table 7.1 Output phase delay compensation table OPS1 OPS0 EFFECT 0 0 No phase delay compensation 0 1 Phase delay compensation 260 nS 1 0 Phase delay compensation 520 nS 1 1 Phase delay compensation 1040 nS W6692 W6692 does not need RC filter on receiver side, therefore zero delay compensation is selected normally. This is the default setting. The PCM output clocks (PFCK1-2, PBCK) are synchronous to the S-interface timing. 7.2.3 Layer 1 Activation/Deactivation The layer 1 activation/deactivation procedures are implemented by a finite state machine. The state transitions are triggered by signals received at S interface or commands issued from micro-processor. The state outputs signals to S interface and indication to micro-processor. The CIX register is used by micro-processor to issue command, and the CIR register is used by micro-processor to receive indication. Some commands are used for special purposes. They are "layer 1 reset", "analog loopback", "send continuous zeros" and "send single zero". 22.214.171.124 States Descriptions and Command/Indication Codes F3 Deactivated without clock This is the "deactivated" state of ITU-T I.430. The receive line awake unit is active except during a hardware reset pulse. After reset, once the indication "1111" has been read out, internal clocks will turn off and stay at this state if INFO 0 is received on the S line. The turn off time is approximate 93 mS. The command ECK must be issued to activate the clocks. F3 Deactivated with clock This state is identical to "F3 Deactivated without clock" except the internal clocks are enabled. The state is entered by a ECK command. The clocks are enabled approximately 0.5 mS to 4 mS after the ECK command, depending on the crystal capacitances. (It is about 0.5 mS for 12 to 33 pF capacitance). F3 Awaiting Deactivation The W6692 W6692 enters this state after receiving INFO 0 (in states F5 to F8) for 16 mS (64 frames). This time constant prevents spurious effect on S interface. Any non-INFO 0 signal on the S interface causes transition to "F5 Identifying Input" state. If this transition does not occur in a specific time (500-1000 mS), the micro-processor may issue DRC or ECK command to deactivate layer 1. F4 Awaiting Signal This state is reached when an activate request command has been received. In this state, the layer 1 transmits INFO1 and INFO 0 is received from the S interface. The software starts timer T3 of I.430 - 16 - W6692 W6692 when issuing activate request command. The software deactivates layer 1 if no signal other than INFO 0 has been received on S interface before expiration of T3. F5 Identifying Input After the receipt of any non-INFO 0 signal from NT, the W6692 W6692 ceases to transmit INFO 1 and awaits identification of INFO 2 or INFO 4. This state is reached at most 50 µS after a signal different from INFO 0 is present at the receiver of the S interface. F6 Synchronized When W6692 W6692 receives an activation signal (INFO 2), it responds with INFO 3 and waits for normal frames (INFO 4). This state is reached at most 6 mS after an INFO 2 arrives at the S interface (in case the clocks were disabled in "F3 Deactivated without clock"). F7 Activated This is the normal active state with the layer 1 protocol activated in both directions. From state "F6 Synchronized" , state F7 is reached at most 0.5 mS after reception of INFO 4. From state "F3 Deactivated without clock" with the clocks disabled, state F7 is reached at most 6 mS after the W6692 W6692 is directly activated by INFO 4. F8 Lost Framing This is the state where the W6692 W6692 has lost frame synchronization and is awaiting resynchronization by INFO 2 or INFO 4 or deactivation by INFO 0. Special States: Analog Loop Initiated On Enable Analog Loop command, INFO 3 is sent by the line transmitter internally to the line receiver (INFO 0 is sent to the line). The receiver is not yet synchronized. Analog Loop Activated The receiver is synchronized on INFO 3 which is looped back internally from the transmitter. The indication 'TI" or "ATI" is sent depending on whether or not a signal different from INFO 0 is detected on the S interface. Send Continuous Pulses A 96 KHz continuous pulse with alternating polarities is sent. Send Single Pulses A 2 KHz isolated pulse with alternating polarities is sent. Layer 1 Reset A layer 1 reset command forces the transmission of INFO 0 and disables the S line awake detector. Thus activation from NT is not possible. There is no indication in reset state. The reset state can be left only with ECK command. - 17 - Publication Release Date: October 1998 Revision A1 W6692 W6692 Table 7.2 Layer 1 command codes COMMAND SYM. CODE DESCRIPTION Enable clock ECK 0000 Enable internal clocks Layer 1 reset RST 0001 Layer 1 reset Send continuous pulses SCP 0100 Send continuous pulses at 96 KHz Send single pulses SSP 0010 Send isolated pulses at 2 KHz Activate request at priority 8 AR8 1000 Activate layer 1 and set D channel priority level to 8 Activate request at priority 10 AR10 1001 Activate layer 1 and set D channel priority to 10 Enable analog loopback EAL 1010 Enable analog loopback Deactivate layer 1 DRC 1111 Deactivate layer 1 and disable internal clocks Table 7.3 Layer 1 indication codes INDICATION SYM. Clock Enabled Deactivate request downstream CE DRD Level detected Activate request downstream LD ARD CODE DESCRIPTIONS 0111 Internal clocks are enabled 0000 Deactivation request by S interface, i.e INFO 0 received 0100 Signal received, receiver not synchronous 1000 INFO 2 received Test indication TI Awake test indication ATI 1011 Level detected during test function Activate indication with priority class 1 AI8 1100 INFO 4 received, D channel priority is 8 or 9 Activate indication with priority class 2 AI10 1101 INFO 4 received, D channel priority is 10 or 11 Clock disabled CD 1010 Analog loopback activated or continuous zeros or single zeros transmitted 1111 Layer 1 deactivated, internal clocks are disabled 126.96.36.199 State Transition Diagrams The followings are the state transition diagrams which implement the activation/deactivation state matrix in I.430 (TABLE 5/I.430). The "command" and "s receive" entries in each state octagon keeps the state, the "indication" and "s transmit" entries in each state octagon are the state outputs. For example, at "F3 Deactivated with clock" state, the layer 1 will stay at this state if the command is "ECK" and the INFO 0 is received on S interface. At this state, it provides "CE" indication to the micro-processor and transmits INFO 0 on S interface. A "AR8/10 AR8/10" command causes transition to F4 and non-INFO 0 signal causes transition to F5. Note that the command code writtern by the microprocessor in CIX register and indication code written by layer 1 in CIR register are transmitted repeatedly until a new code is written. - 18 - W6692 W6692 F4 Await. Signal AR8/10 AR8/10 CE DRC ECK i0 i1 F3 Deact w/o AR8/1 3) ^i0 DRC CD 3) F5 Ident. Input ^i0 i0 i4 1) ^RST any LD 2) i0 ECK i0 DRC F3 Deact with AR8/10 AR8/10 i2 Lost Framing i0 ECK 3) CE ^i0 F6 i0 i0 1) ^RST i0 ARD i2 ECK i3 DRC i4 F3 Await. Deact. i2 3) ^i0 AR8/10 AR8/10 DRD F7 Activated i0 AR8/10 AR8/10 AI8/10 AI8/10 i4 i3 Notation: Lost Framing i4 F8 Lost i2 1) ^RST any i0 i0 2) State LD i0 com s receive i0 Ind s trans. Notes: 1. "^RST" means "NOT layer 1 reset command". 2. "Any" means any signal other than i0, which has not yet been determined. 3. "^i0" means any signal other than i0. Figure 7.5 layer 1 activation/deactivation state diagram - normal mode - 19 - Publication Release Date: October 1998 Revision A1 W6692 W6692 Ana. Loop Init. Reset EAL RST RST 2) None Ignored EAL 5) Ignored i0 Y CE i3 ECK 5) 5) i3 ^i3 Ana. Loop Act. 2) EAL Send Cont. TI/ATI 5) Ignored SCP SCP i3 TI Ignored ic 3) 2) Y Notation: Send Sing. State SSP SSP TI Ignored is com s receive 4) Ind s trans. 2) Y Notes: 1. RST can be issued at any state, while SCP, SCZ and EAL can be issued only at F3 or F7. 2. Y is one of the commands : ECK, DRC, RST. 3. Continuous pulses at 96 KHz. 4. Isolated pulses at 2 KHz. 5. The INFO 3 is transmitted internally only. Figure 7.6 layer 1 activation/deactivation state diagram - SPECIAL mode - 20 - Y W6692 W6692 7.2.4 D Channel Access Control The D channel access control includes collision detection and priority management. The collision detection is always enabled. The priority management procedure as specified in ITU-T I.430 is fully implemented in W6692 W6692. A collision is detected if the transmitted D bit and the received echo bit do not match. When this occurs, D channel transmission is immediately stopped and the echo channel is monitored to attempt the next D channel access. The layer 1 module uses an internal signal to inform layer 2 module of the collision condition (DRDY bit goes inactive in D_STAR register). There are two priority classes: class 1 and class 2. Within each class, there are normal and lower priority levels. Table 7.4 D priority classes NORMAL LEVEL LOWER LEVEL Priority class 1 8 9 Priority class 2 10 11 The selection of priority class is via the AR8/AR10 AR8/AR10 command. The following table summarizes the commands/indications used for setting the priority classes: Table 7.5 D Priority commands/indications COMMAND SYM. CODE REMARKS Activate request, set priority 8 AR8 1000 Activation command, set D channel priority to 8 Activate request, set priority 10 AR10 1001 Activation command, set D channel priority to 10 INDICATION ABBR. REMARKS Activate indication with priority 8 AI8 1100 Info 4 received, D channel priority is 8 or 9 Activate indication with priority 10 AI10 1101 Info 4 received, D channel priority is 10 or 11 7.2.5 Frame Alignment The following sections describe the behavior of W6692 W6692 in respect to the CTS-2 conformance test procedures for frame alignment. Please refer to ETSI-TM3 Appendix B1 for detailed descriptions. - 21 - Publication Release Date: October 1998 Revision A1 W6692 W6692 188.8.131.52 FAinfA_1fr This test checks if TE does not lose frame alignment on receipt of one bad frame. The pattern for the bad frame is defined as IX_96 KHz. This pattern consists of alternating pulses at 96 KHz during the whole frame. Info 4 Info 4 Info 4 IX_96 KHz Info 3 Info 3 Info 3 Device Settings Result W6692 W6692 None Info 3 Pass 184.108.40.206 FAinfB_1fr This test checks if TE does not lose frame alignment on receipt of one IX_I4noflag frame which has no framing and balancing bit. The following figure indicates one possible IX_I4noflag waveform. Info 4 Info 4 Info 4 I4_BASIC IX_I4noflag Info 3 Info 3 Info 3 Device Settings Result W6692 W6692 None Info 3 Pass 220.127.116.11 FAinfD_1fr This test checks if TE does not lose frame alignment on receipt of one IX-I4viol16 frame. The IX_I4viol16 frame remains at binary "1" until the first B2 bit which is bit position 16. The pulse sequences are: Framing bit, balancing bit, B2 bit, M bit, S bit, balancing bit. The TE should reflect the received FA bit (FA = "1") in the transmitted frame. - 22 - W6692 W6692 IX_I4viol16 Info 4 Info 4 Info 4 FA = 1 Info 3 Info 3 Info 3 I3_BASIC with FA = 1 Device Settings Result W6692 W6692 None Pass 18.104.22.168 FAinfA_kfr This is to test the number k of IX_96 KHz frames necessary for loss of frame alignment. Info 4 Info 4 IX_96kHz Info 3 Info 3 IX_96kHz IX_96kHz Info 3 I3_SFAL Device Settings Result W6692 W6692 k=2 Info 0 Pass - 23 - Publication Release Date: October 1998 Revision A1 W6692 W6692 22.214.171.124 FAinfB_kfr This is to test the number k of IX_I4noflag frames necessary for loss of frame alignment. Info 4 Info 4 I4-BASIC Info 3 Info 3 IX_I4noflag IX_I4noflag IX_I4noflag Info 3 I3_SFAL Device Settings Result W6692 W6692 k=2 Info 0 Pass 126.96.36.199 FAinfD_kfr This is to test the number k of IX_I4noflag frames necessary for loss of frame alignment. Info 4 Info 4 FA = 1 Info 3 Info 3 Info 3 with FA =1 I3_SFAL Device Settings Result W6692 W6692 k=2 Info 0 Pass 188.8.131.52 Faregain This is to test the number m of good frames necessary for regain of frame alignment. The TE regains frame alignment at m+1 frame. - 24 - W6692 W6692 The W6692 W6692 achieves synchronization after 5 frames, i.e m = 4. 1 Info X 2 3 4 5 6 7 Info 4 Info 4 Info 4 Info 4 Info 4 Info 4 Info 4 Info 3 Info 3 Info 3 I3_SFL Device Settings Result W6692 W6692 m=4 Pass 7.2.6 Multiframe Synchronization As specified by ITU-T I.430, the Q bit is transmitted from TE to NT in the position normally occupied by the auxiliary framing bit (FA) in one frame out of 5, whereas the S bit is transmitted from NT to TE. The S and Q bit positions and multiframe structure are shown in Table 7.6. The functions provided by W6692 W6692 are: - Multiframe synchronization: Synchronization is achived when the M bit pattern has been correctly received during 20 consecutive frames starting from frame number 1. Note: Criterion for multiframe synchronization is not defined in I.430 Recommendation. - S bits receive and detect: When synchronization is achieved, the four received S bits in frames 1, 6, 11, 16 are stored as S1 to S4 in the SQR register respectively. A change in the recived four bits (S1-4) is indicated by an interrupt (ISC in D_EXIR register and SCC in CIR register). - Multiframe synchronization monitoring: Multiframe synchronization is constantly monitored. The synchronization state is indicated by the MSYN bit in the SQR register. - Q bits transmit and FA mirroring: When multiframe synchronization is achived, the four bits Q1-4 stored in the SQXR register are transmitted as the four Q bits (FA-bit position) in frames 1, 6, 11 and 16. Otherwise the FA bit transmitted is a mirror of the received FA-bit. At loss of synchronization, the mirroring is resumed at the next FA-bit. - The multiframe synchronization can be disabled by setting MFD bit in the D_MODE register. - According to I.430 Recommendation, the S/Q channel can be used as operation and maintenance signalling channel. At transmitter, a S/Q code for a message shall be repeated at least six times or as many as necessary to obtain the desired response. At receiver, a message shall be considered received only when the proper codes is received three consecutive times. - 25 - Publication Release Date: October 1998 Revision A1 W6692 W6692 Table 7.6 Multiframe structure in S/T interface Frame Number NT-to-TE FA-bit position NT-to-TE M bit NT-to-TE S bit TE-to-NT FA-bit position 1 ONE ONE S1 Q1 2 ZERO ZERO ZERO ZERO 3 ZERO ZERO ZERO ZERO 4 ZERO ZERO ZERO ZERO 5 ZERO ZERO ZERO ZERO 6 ONE ZERO S2 Q2 7 ZERO ZERO ZERO ZERO 8 ZERO ZERO ZERO ZERO 9 ZERO ZERO ZERO ZERO 10 ZERO ZERO ZERO ZERO 11 ONE ZERO S3 Q3 12 ZERO ZERO ZERO ZERO 13 ZERO ZERO ZERO ZERO 14 ZERO ZERO ZERO ZERO 15 ZERO ZERO ZERO ZERO 16 ONE ZERO S4 Q4 17 ZERO ZERO ZERO ZERO 18 ZERO ZERO ZERO ZERO 19 ZERO ZERO ZERO ZERO 20 ZERO ZERO ZERO ZERO 1 ONE ONE S1 Q1 2 ZERO ZERO ZERO ZERO etc. 7.2.7 Test Functions The W6692 W6692 provides loop and test functions as follows: - digital loop via DLP bit in D_MODE register: In the layer 2 block, the transmitted 2B+D data are internally looped (from HDLC transmitter to HDLC receiver), and in the PCM ports, the transmitted B channels are internally looped (from PCM inputs to PCM outputs). The clock timings are generated internally and are independent of the S bus timing. This loop function is used for test of PCM and higher layer functions, excluding layer 1. After hardware reset, W6692 W6692 will power down if S bus is not connected or if there is no signal on the S bus. In this case, the C/I command ECK must be issued to power up the chip. - 26 - W6692 W6692 Test Functions, continued - analog loop via the C/I command EAL: The analog S interface transmitter is internally connected to the S interface receiver. When the receiver has synchronized itself to the internal INFO 3 signal, the message "Test Indication" or "Awake Test Indication" is delivered to the CIR register. No signal is transmitted over the S interface. In this mode, the S interface awake detector is enabled. Therefore if a level (INFO 2/ INFO 4) is detected on the S interface, this will be reported by the "Awake Test Indication (ATI)" indication. - remote loopback via RLP bit in D_MODE register: The digital 2B data received from the S interface receiver is loopbacked to the S interface transmitter. The D channel is not looped. When RLP is enabled, layer 1 D channel is connected to HDLC port and DLP cannot be enabled. - transmission of special test signals via layer 1 command: * Send Single Pulses (SSP): To send isolated single pulses of alternating polarity, with pulse width of one bit time, 250 µS apart, with a repetition frequency of 2 KHz. * Send Continuous Pulses (SCP): To send continuous pulses of alternating polarity, with pulse width of bit time. The repetition frequency is 96 KHz. 250 us (a) Single pulses (b) Continuous pulses Figure 7.7 SSP and SCP test signals 7.3 Serial Interface Bus The 192 kbps S/T interface signal consists of two B channels (64 kbps each), one D channel (16 kbps) and other control signals. The multiplexing/demultiplexing functions are carried out in the Serial Interface Bus (SIB) block. In addition, the B1 and B2 channels can be individually set to carry 64 kbps or 56 kbps traffic. - 27 - Publication Release Date: October 1998 Revision A1 W6692 W6692 7.4 B Channel Switching Each B channel in S/T bus or U transceiver can be individually programmed to connect to one of the three data ports: B channel HDLC controller, PCM port 1 or PCM port 2. In addition, the PCM ports can be programmed to connect to the B channel HDLC controller for voice recording/ retrieving from main memory in answering machine applications. In this case, only extended transparent mode can be used. The switching matrix is controlled by PXC bit in PCTL register and BSW1-0 bits in B1_MODE and B2_MODE registers as follows: A special mode is provided (BSW1-0 = 11B) in which case the PCM port can receive data from layer 1 and the HDLC receiver can receive data from PCM port simultaneously. B1 01 layer 1 0 PCM1 /GCI 00 10 1 HDLC 1 B2 01 layer 1 PCM2 /GCI 00 0 10 HDLC BSW1-0 bits PXC bit 7.5 PCM Port There are two PCM ports in W6692 W6692. Each PCM port can connect to a PCM codec filter chip. These two PCM ports share the same signals except for the frame synchronization clocks. The frame synchronization clocks (PFCK1-2) are 8 KHz and the bit synchronization clock (PBCK) is 1.536 MHz. The bit data rate is 64 kbps per port. 7.6 D Channel HDLC Controller There are two HDLC protocols that are used for ISDN layer 2 functions: LAPD and LAPB. Their frame formats are shown below. - 28 - W6692 W6692 LAPB modulo 8: flag address control information Control field bits 7 flag (0 or N octets) (1 octet) (1octet) (1octet) FCS (2 octets) (1 octet) 6 5 4 3 2 1 0 I frame N(R) P S frame N(R) P/F S S 0 1 P/F M M 1 1 U frame M M M N(S) 0 LAPB modulo 128: flag address control information FCS flag (1 octet) (1octet) (1 or 2 octets) (0 or N octets) (2 octets) (1 octet) 1st octet Control field bits 7 6 5 I frame 4 2nd octet 3 2 1 0 N(S) S frame X X X U frame M M M P/F X 7 6 5 4 3 2 1 0 0 N(R) P N(R) P/F S S 0 1 M M 1 1 LAPD: modulo 128 only flag address control FCS flag (2 octets) (1 octet) (2 octets) information (0 or N octets) (2 octets) (1 octet) 1st octet Control field bits 7 6 5 I frame 4 3 2nd octet 2 1 N(S) S frame 0 U frame M M M P/F 0 0 0 0 7 6 5 4 3 2 1 0 0 N(R) P/F N(R) P/F S S 0 1 M M 1 1 - 29 - Publication Release Date: October 1998 Revision A1 W6692 W6692 7.6.1 D Channel Message Transfer Modes The D channel HDLC controller operates in transparent mode. Chracteristics: - Receive frame address recognition - Address comparison maskable bit-by-bit - Flag generation / deletion - Zero bit insertion/ deletion - Frame Check Sequence (FCS) generation/ check with CRC_ITU-T 16 12 5 Note. The LAPD protocol uses the CRC_ITU-T for Frame Check Sequence. The polynominal is X + X + X + 1. For address recognition, the W6692 W6692 provides four programmable registers for individual SAPI TEI values, SAP1-2 and TEI1-2, plus two fixed values for group SAPI and TEI, SAPG and TEIG. SAPG equals FEH or FCH which corresponds to SAPI = 63 for layer management procedure. TEIG equals FFH which corresponds to TEI = 127 for automatic TEI assignment procedure. address combinations are: - SAP1 + TEI1 - SAP1 + FFH - SAP2 + TEI2 - SAP2 + FFH - FEH (FCH) + TEI1 - FEH (FCH) + TEI2 - and The The The FEH (FCH) + FFH The receive frame address comparisons can be disabled (masked) per bit basis with the D_SAM and D_TAM registers, but comparisons with the SAPG or TEIG cannot be disabled. 7.6.2 Reception of Frames in D Channel A 128-byte FIFO is provided in the receive direction. The data movement between receive FIFO and micro-processor is handled by interrupts. There are two interrupt sources: Receive Message Ready (D_RMR) and Receive Message End (D_RME). The D_RMR interrupt indicates that at least 64 bytes of data have been received and the message/ frame is not ended. Upon D_RMR interrupt, the micro-processor reads out 64 bytes of data from the FIFO. The D_RME interrupt indicates the last segment of a message or a message with length 64 bytes has been received. The length of data is less than or equal to 64 and is specified in the D_RBCL register. If the length of the last segment of message is 64, only D_RME interrupt is generated and the RBC50 RBC50 bits in D_RBCL register are 000000B 000000B. - 30 - W6692 W6692 The data between the opening flag and the CRC field are stored in D_RFIFO. For LAPD frame, this includes the address field, control field and information field. When a D_RMR or D_RME interrupt is generated, the micro-processor must read out the data from D_RFIFO and issues the Receive Message Acknowledgement command (D_CMDR: RACK bit) to explicitly acknowledge the interrupt. The micro-processor must handle the interrupt before more than 64 bytes of data are received. This corresponds to a maximum micro-processor reaction time of 32 mS at 16 kbps data rate. If the micro-processor is late in handling the interrupt, the incoming additional bytes will result in a "data overflow" interrupt and status bit. 7.6.3 Transmission of Frames in D Channel A 128-byte FIFO is provided in the transmit direction. If the transmit FIFO is ready (which is indicated by a D_XFR interrupt ), the micro-processor can write up to 64 bytes of data into the FIFO and use the XMS command bit to start frame transmission. The HDLC transmitter sends the opening flag first and then sends the data in the transmit FIFO. The micro-processor must write the address, control and information field of a frame into the transmit FIFO. Every time no more than 64 bytes of data are left in the transmit FIFO, the transmitter generates a D_XFR interrupt to request another block of data. The micro-processor can then write further data to the transmit FIFO and enables the subsequent transmission by issuing an XMS command. If the data written to the FIFO is the last segment of a frame, the micro-processor issues the XME (Transmit Message End) and XMS command bits to finish the frame transmission. The transmitter then transmits the data in the FIFO and appends CRC and closing flag. If the micro-processor fails to respond the D_XFR interrupt within a given time (32 mS), a data underrun condition will occur. The W6692 W6692 will automatically reset the transmitter and send inter frame time fill pattern (all 1's) on D channel. The micro-processor is informed about this condition via an XDUN (Transmit Data Underrun) interrupt in D_EXIR register. The microprocessor must wait until transmit FIFO ready (via XFR interrupt ), re-write data, and issue XMS command to re-transmit the data. It is possible to abort a frame by issuing a D_CMDR: XRST (D channel Transmitter Reset) command. The XRST command resets the transmitter and causes a transmit FIFO ready condition. After the micro-processor has issued the XME command, the successful termination of transmission is indicated by an D_XFR interrupt. The inter-frame time fill pattern must be all 1's, according to ITU-T I.430. Collisions which occur on the D channel of S interface will cause an D_EXIR: XCOL interrupt. A XRST (Transmitter Reset) command must be issued and software must wait until transmit FIFO ready (via XFR interrupt), re-write data, and issue XMS command to re-transmit the data. - 31 - Publication Release Date: October 1998 Revision A1 W6692 W6692 7.7 B Channel HDLC Controller There are two B channel HDLC controllers. Each B channel HDLC controller provides two operation modes: - Transparent mode characteristics: * 2 byte address field * Receive address comparison maskable bit-by-bit * Data between opening flag and CRC (not included) stored in receive FIFO * Flag generation/ deletion * Frame Check Sequence generation/ check with CRC_ITU-T polynominal * Zero bit insertion/ deletion - Extended transparent mode characteristics: * All data transmitted/ received without modification * No address comparison * No flag generation/ detection * No FCS generation/ check * No bit stuffing For PCM-HDLC connection, only extended transparent mode can be selected. The data rate in B channel can be set at 64 kbps or 56 kbps by the B1_MODE (B2_MODE): SW56 bit. 7.7.1 Reception of Frames in B Channel A 128-byte FIFO is provided in the receive direction. The receive FIFO threshold can be set at 64 or 96 bytes by the Bn_MODE register. If the number of received data reaches the threshold, a Receive Message Ready (RMR) interrupt will be generated. The operations for reception of frames differ in each mode: Transparent mode : The received frame address is compared with the contents in receive address registers. In addition, the comparisons can be selectively masked bit-by-bit via address mask registers. Comparison is disabled when the corresponding mask bit is "1". In addition, flag recognition, CRC check and zero bit deletion are also performed. The result of CRC check is indicated in Bn_STAR:CRCE bit. The data between opening flag and CRC field (not included) is stored in receive FIFO. Two interrupts are used for the reception of data. The RMR interrupt in Bn_EXIR register indicates at least a threshold block of data have been put in the receive FIFO. The RME interrupt in Bn_EXIR register indicates the end of frame has been received. The micro-processor can read out a threshold length of data from receive FIFO at RMR interrupt, or all the data in receive FIFO at RME interrupt. At each RMR/ RME interrupt, micro-processor must issue a Receive Message Acknowledgement(RACK) command to explicitly acknowledge the interrupt. - 32 - W6692 W6692 The micro-processor reaction time for RMR/ RME interrupt depends on the FIFO threshold setting and B channel data rate. For example, it is 8 mS if the FIFO threshold is 64 and the B channel data rate is 64 kbps. If the micro-processor is late in handling the interrupt, the incoming additional bytes will result in a "data overflow" interrupt and status bit. Extended transparent mode: In this mode, all data received are stored in the receive FIFO without any modification. Every time up to a threshold length of data has been stored in the FIFO, a Bn_RMR interrupt is generated. In this mode, there is no RME interrupt. The micro-processor must react to the RMR interrupt in time, otherwise a "data overflow" interrupt and status bit will be generated. 7.7.2 Transmission of Frames in B Channel A 128-byte FIFO is provided in the transmit direction. The FIFO threshold can be set at 64 or 96 bytes. The transmitter and receiver use the same FIFO threshold setting. The transmit operations differ in both modes: Transparent mode : In this mode, the following functions are performed by the transmitter automatically: - Flag generation - CRC generation - Zero bit insertion The fields such as address, control and information are provided by the micro-processor and are stored in transmit FIFO. To start the frame transmission, the micro-processor issues a XMS (Transmit Message Start) command. The transmitter requests another block of data via XFR interrupt when more than a threshold length of vacancies are left in the FIFO.The micro-processor then writes up to a threshold length of data into the FIFO and activates the subsequent transmission of the frame by a XMS command too. The micro-processor indicates the end of the frame transmission by issuing XME (Transmit Message End) and XMS commands at the same time. The transmitter then transmits all the data left in the transmit FIFO and appends the CRC and closing flag. After this, a XFR interrupt is generated. The inter-frame time fill pattern can be programmed to 1's or flags. During the frame transmission, the micro-processor reaction time for the XFR interrupt depends on the FIFO threshold setting and B channel data rate. For example, it is 8 mS if the FIFO threshold is 64 and the B channel data rate is 64 kbps. If the micro-processor fails to responds within the given reaction time, the transmit FIFO will be underrun. In this case, the W6692 W6692 will automatically reset the transmitter and send the inter frame time fill pattern on B channel. The micro-processor is informed about this via a Transmit Data Underrun interrupt (XDUN bit in Bn_EXIR register). The microprocessor must wait until transmit FIFO ready (via XFR interrupt), re-write data, and issue XMS command to re-transmit the data. The micro-processor can abort a frame transmission by issuing a Transmitter Reset command (XRES bit in Bn_CMDR register). The XRES command resets the transmitter and sends inter frame time fill pattern on B channel. It also results in a transmit pool ready condition. - 33 - Publication Release Date: October 1998 Revision A1 W6692 W6692 Extended transparent mode: All the data in the transmit FIFO are transmitted without any modification, i.e. no flags and CRCs are inserted, and no bit stuffing is performed. Transmission is started by a XMS command. The transmitter requests another block of data via XFR interrupt when more than a threshold length of vacancies are left in the FIFO. The micro-processor reacts to this condition by writing up to a threshold length of data into the transmit FIFO and issues a XMS command to continue the message transmission. The micro-processor reaction time depends on the FIFO threshold setting and B channel data rate. For example, it is 8 mS if the FIFO threshold is 64 and the B channel data rate is 64 kbps. If the micro-processor fails to respond within the given reaction time, the transmit FIFO will hold no data to transmit. In this case, the W6692 W6692 will automatically reset the transmitter and send the inter frame time fill pattern on B channel. The micro-processor is informed about this via a Transmit Data Underrun interrupt (XDUN bit in Bn_EXIR register). The microprocessor must wait until transmit FIFO ready (via XFR interrupt), re-write data, and issue XMS command to re-transmit the data. 7.8 GCI Mode Serial Interface Bus The GCI is a generalization and enchancement of the general purpose serial interface bus. The GCI bus offers capacity for the transfer of maintenance information. In terminal applications, the GCI constitute a powerful backplane bus offering sophisticated control capabilities for peripheral modules. The channel structure of the GCI mode is depicted below: Channel Structure of the W6692 W6692 GCI Mode: B1 B2 B1 Mon D C I NULL NULL B2 st 1 Octet Monitor 2 nd Octet D MR C/I rd 3 Octet th 4 Octet Figure 7.8 GCI Mode Channel Structure The first two octets constitute the two 64 Kbps B channels. The third octet is the Monitor channel. It is used for the exchange of data between the W6692 W6692 and the other attached device using the GCI Monitor channel protocol. The fourth octet (control channel) contains: two bits for the 16 Kbps D channel, a 4-bit C/I channel (Command/Indication channel), and 2-bit MR and MX for supporting the Monitor channel handshaking protocol. - 34 - MX W6692 W6692 The W6692 W6692 GCI Mode Signals are: DIN/DOUT : 768 Kbps DCL : 1.536 MHz input FSC : 8 KHz input 7.8.1 GCI Mode C/I Channel Handling The Command/Indication channel carries real-time status information between the W6692 W6692 and another device connected to the GCI bus interface. One C/I channel conveys the commands and indications between a layer 1 device and layer 2 device. This C/I channel is access via register CIR (in receive direction, layer 1 to layer 2) and register CIX (in transmit direction, layer 2 to layer 1). The C/I code is 4-bit long. · In the receive direction, the code from layer 1 is continuously monitored, with an interrupt being generated anytime a change occurs. A new code must be found in two consecutive GCI frames to be consided valid and to trigger a C/I code change interrupt status (double last look criterion). · In the transmit direction, the code written in CIX is continuously transmitted in the channel. 7.8.2 GCI Mode Monitor Channel Handling The Monitor channel protocol is a handshake protocol used for high speed information exchange between the W6692 W6692 and other devices. In the W6692 W6692 GCI mode only one Monitor channel is available. The Monitor channel is necessary for: · programming and controlling devices attached to the GCI interface. · data exchange between two microprocessor systems attached to two different devices on one GCI backplane. Use of the Monitor channel avoids the necessity of a dedicated serial communication path between two systems. The Monitor channel operates on an asynchronous basis. While data transfers on the bus take place synchronized to frame sync, the flow of data is controlled by a handshake procedure using the Monitor Channel Receiver (MOR) and Monitor Channel Transmit (MOX) bits. When data is placed into the Monitor channel and the MX bit is activated. This data will be transmitted repeatedly once per 8 KHz frame until the transfer is acknowledged via the MR bit. The microprocessor may either enforce a 1 (idle state) in MR, MX by setting the control bit MRC or MXC (MOCR register) to 0, or enable the control of these bits internally by the W6692 W6692 according to the Monitor channel protocol. Thus, before a data exchange can begin, the control bit MRC, or MXC should be set to 1 by the microprocessor. The relevant status bits are: · for the reception of Monitor data: MDR (Monitor Channel Data Received) MER (Monitor Channel End of Reception) · for the transmission of Monitor data: MDA (Monitor Channel Data Acknowledged) MAB (Monitor Channel Data Abort) About the status bit MAC (Monitor Channel Transmit Active) indicates whether a transmission is progress. - 35 - Publication Release Date: October 1998 Revision A1 W6692 W6692 · if set MAC = 0, the previous transmission has been terminated. Before starting a transmission, the microprocessor should verify that the transmitter is inactive. · if set MAC = 1, after having written data into the Monitor Transmit Channel (MOX) register, the microprocessor sets this bit to 1. This enables the MX bit to go active (0), indicating the presence of valid Monitor data (contents of MOX) in the corresponding frame. The receiing device stores the Monitor byte in its MOR (Monitor Receive Register) and generates a MDR (Monitor Channel Data Receive) interrupt status. Alerted by the MDR interrupt, the microprocessor reads the MOR register. When it is ready to accept data, it sets the MR control bit MRC to 1 to enable the receiver to store succeeding Monitor channel bytes and acknowledge them according to the Monitor channel protocol. In addition, it enables other Monitor channel interrupts by setting Monitor Channel Interrupt Enable to 1. The first Monitor channel byte is acknowledged by the receiving device setting the MR bit to 0. This causes a MDA (Monitor Channel Data Acknowledge) interrupt status at the transmitter. A new Monitor channel data byte can now be written by the microprocessor in MOX register. The MX bit is still in the active (0) state. The transmitter indicates a new byte in the Monitor channel by returning the MX bit active after sending it once in the inactive state. The receiver stores the Monitor channel byte in MOR register and generates a new MDR interrupt status. When the microprocessor has read the MOR register , the receiver acknowledges the data by returning the MR bit active after sending it once in the inactive state. This in turn causes the transmitter to generate a MDA interrupt status. This MDA interrupt write data MDR interrupt read data MDA interrupt handshake procedure is repeated as long as the transmitter has data to send. When the last byte has been acknowledged by the receiver (MDA interrupt status), the microprocessor sets the Monitor channel Transmit Control bit MXC to 0. This enforces an inactive (1) state in the MX bit. Two frames of MX inactive signifies the end of a message. Thus, a MER (Monitor channel End of Reception) interrupt status is generated by the receiver when the MX is received in the inactive state in two consecutive frames. As a result, the microprocessor sets the MR control bit MRC to 0, which in turn enforces an inactive state in the MR bit. This marks the end of the transmittion, making the MAC (Monitor channel Active) bit return to 0. During a transmission process, it is possible for the receiver to ask a transmission to be aborted by sending an inactive MR bit value in two consecutive frames. This is effected by the microprocessor writing the MR control bit MRC to 0. An aborted transmission is indicated by a MAB (Monitor Channel Data Abort) interrupt status at the transmitter. 7.9 PCI Interface Circuit 7.9.1 PCI Slave Mode And Configuration Serial EEPROM W6692 W6692 implements slave (target) mode function which meets PCI local bus specification revision 2.1. All the signals are 5V, 33 MHz compatible. A signle function, type 00h configuration header is implemented for control of the internal ISDN device and external peripheral device(s). Memory mode and/or IO mode can be used for W6692 W6692's register access. After power on reset, W6692 W6692 starts to read configuration data from serial EEPROM port. The first word read is Vendor ID, if it equals FFFFH, default configuration data is used, otherwise, the configuration data stored in serial EEPROM is used. The default configuration data is as follows: - 36 - W6692 W6692 Vendor ID : 1050H 1050H (Winbond's ID) Device ID : 6692H 6692H Class Code : 02 80 00H Revision ID : 00H Subsystem Vendor ID : FFFFH Subsystem ID : FFFFH Memory Base Address Register : Enabled and Implemented at 10H IO Base Address Register : Enabled and Implemented at 14H A 9346/93C46 9346/93C46 type serial EEPROM is used for configuration data storage. The format is as follows: ADDRESS 15 8 7 0 0 15 Vendor ID 0 1 15 Device ID 0 2 7 Interface Code 0 7 Revision ID 0 3 7 Base Class Code 0 7 Subclass Code 0 4 15 Subsystem Vendor ID 0 5 15 Subsystem ID 0 6 15 Address Register Control 0 Address Register Control: 15 14 13 MEN IEN PRE 12 0 not used Figure 7.9 Serial eeprom data format Important Note: In all PC platforms, burst mode is used very often for memory access. Because W6692 W6692 does not support burst mode, it is recommended not to use memory access for W6692 W6692's internal registers and data. - 37 - Publication Release Date: October 1998 Revision A1 W6692 W6692 The Address Register Control determines the Address Registers implementation. Bit 13 is the prefetchable bit in Memory Base Address register. MEN IEN LOCATION 10H 1 1 Memory Base Address Reg. IO Base Address Reg. Yes 1 0 Memory Base Address Reg. Not Implemented Yes 0 1 IO Base Address Reg. Not Implemented No 0 0 Not Implemented Not Implemented No Memory Base Address Reg. IO Base Address Reg. EEPROM empty LOCATION 14H PRE USED PRE = 1 In all cases, Memory Base Address register allocates 4096 byte spaces and IO Base Address register allocates 256 byte space. W6692 W6692 provides one register for on-board programming of the serial EEPROM. This register called EPCTL register is at offset address FCH. The format is: 7 3 1 0 EN Reserved 2 SK CS SDO The data written at bits 2-0 are directly output on pins EPSK, EPCS and EPSDO if EN = 1. The outputs are disabled if EN = 0. EN bit does not affect the power on configuration read. For example, to generate the following waveform, the write data sequence is: SEQUENCE EN SK CS SDO 1 1 0 0 0 2 1 1 1 1 3 1 0 1 1 4 1 1 1 0 5 1 0 1 0 EPCS EPSK EPSDO - 38 - W6692 W6692 7.9.2 Cascade Structure of Interrupt Sources The W6692 W6692 uses cascade structure to record the causes of various interrupts. The interrupt structure is shown in Figure 7.10. A read of the ISTA register clears all the interrupts except D_EXI, B1_EXI and B2_EXI bits. These three bits are cleared if their corresponding extended interrupt registers are cleard. B1_EXI bit is cleared by reading the B1_EXIR register and B2_EXI bit is cleared by reading the B2_EXIR register. Reading of B1_EXIR or B2_EXIR register clears all the bits in it. The B1_EXIM and B2_EXIM registers mask the corresponding bits in the B1_EXIR and B2_EXIR registers. To clear the D_EXI bit, all the bits in D_EXIR must first be cleared. A read of the D_EXIR register clears all the bits except the ISC bit. The ISC bit is cleared by a read of CIR and SQR registers. An ISC interrupt may originate from - a change in the received indication code (ICC bit in CIR register) or - a change in the received S code (SCC bit in CIR register). The ICC interrupt can not be disabled while the SCC interrupt can be disbled by clearing the SCIE bit in SQX register. Bits SCC and ICC are cleared by a read of SQR and CIR. D_EXIM register masks the corresponding bits in D_EXIR register. If the D_EXIM: ISC bit is set to one, it masks the ICC and SCC interrupts. The ICC or SCC bit is set whenever a new code is loaded in CIR or SQR. But if the previous register content has not been read out in case of a code change, the new code will not be loaded. The code registers are buffered with a FIFO size of two. Thus if several consecutive code changes are detected, only the first and the last code is obtained at the first and second register read, respectively. - 39 - Publication Release Date: October 1998 Revision A1 W6692 W6692 IRQ pin D RM D RME D XFR XINT1 XINT0 D EXI B1 EXI B2 EXI RMR RME RDOV XFR XDUN XFR XDUN B1_EXIM B1_EXIR RMR RME RDOV RMR RME RDOV XFR XDUN XFR XDUN B2 EXIM D RMR D RME D XFR XINT1 XINT0 D EXI B1 EXI B2 EXI IMASK RMR RME RDOV B2_EXIR ISTA RDOV XDUN XCOL TIN2 MOC ISC TEXP WEXP D_EXIM RDOV XDUN XCOL TIN2 MOC ISC TEXP WEXP SCC ICC D_EXIR SCIE Q1 Q2 Q3 Q4 CODR3 CODR2 CODR1 CODR0 SQX Figure 7.10 W6692 W6692 interrupt structure - 40 - CIR XIND1 XIND0 MSYN SCIE S1 S2 S3 S4 SQR W6692 W6692 7.10 Peripheral Control In PCI card with POTS application, the peripheral devices such as CODEC, DTMF and SLIC can be directly controlled by W6692 W6692, therefore preclude the need for another PCI controller chip. The peripheral control function includes timer, interrupt inputs and programmable IOs or microprocessor interface. There are two timers implemented in W6692 W6692: D_TIMR and TIMR2. D_TIMR is a long period timer whcich can be used to control the 1 sec, 2 sec ON/OFF of ring tone. While TIMR2 is a short period timer which can be used to generate the tens hertz of ring signal. ADDRESS INTERRUPT STATUS INTERRUPT MASK OUTPUT PIN PERIOD CYCLIC D_TIMR 10H DEXIR: TEXP DEXIM: TEXP No (0.6) x 2.048 s +(1.32) x 64 mS Yes (CNT = 7) TIMR2 4CH DEXIR: TIN2 DEXIM: TIN2 TOUT2 (1.63) mS Yes (TMD = 1) TOUT2 toggles when TIMR2 counts down to zero. For example, if the timer period is 1 mS, then the period of TOUT2 is 2 mS. There are two interrupt input pins: XINTIN0, XINTIN1. Whenever signal level changes (eith rising or falling), a maskable interrupt is generated which in turn will make an interrupt request on PCI bus if it is unmasked. The interrupt status bits are ISTA: XINT0, ISTA: XINT1. The mask bits are IMASK: XINT0, IMASK: XINT1. In addition, the signal level can be read at bits SQR: XIND0, SQR; XIND1. These pins can be used for monitor of SLIC hook state and/or DTMF data valid status. The IO interface can be programmed as simple IO (PCTL: XMODE = 0) or 8-bit microprocessor interface (PCTL: XMODE = 1). As simple IOs, the directions of the 11 pins are selected via OE5-0 bits in PCTL register and the read/write data accessed via XADDR and XDATA registers. As output, the register data is output on the pin, as input, the current level of pin is read in. In this mode, a maximum of 11 IO ports are supported. If programmed as 8-bit microprocessor mode, an 8-bit multiplexed bus is used to control peripheral deveces. The address and data are multiplexed on XAD7-0. XALE is used for address latch and XRDB, XWRB are used for read/write strobe. To access peripheral device, first write the desired address in XADDR register and then read/write data at XDATA register. In this mode, a maximum of 256 byte ports can be supported by adding some glue TTLs on board. - 41 - Publication Release Date: October 1998 Revision A1 W6692 W6692 8. REGISTER DESCRIPTIONS 8.1 Chip Control and D_ch HDLC controller Table 8.1 Register address map: Chip Control and D channel HDLC SECTION 8.1.1 8.1.2 8.1.3 8.1.4 8.1.5 8.1.6 8.1.7 8.1.8 8.1.9 8.1.10 8.1.11 8.1.12 8.1.13 8.1.14 8.1.15 8.1.16 8.1.17 8.1.18 8.1.19 8.1.20 8.1.21 8.1.22 8.1.23 8.1.24 8.1.25 8.1.26 8.1.27 8.1.28 8.1.29 8.1.30 8.1.31 8.1.32 8.1.33 8.1.34 8.1.35 OFFSET 00 04 08 0C 10 14 18 1C 20 24 28 2C 30 34 38 3C 40 44 48 4C 50 54 58 5C 60 64 68 6C 70 74 78 7C F4 F8 FC ACCESS R W W R/W R/W R_clear R/W R_clear R/W R R R/W R/W R/W R/W R/W R/W R R W R/W R/W R W R W R/W R R/W R R/W R/W R/W R/W W REGISTER NAME D_RFIFO D_XFIFO D_CMDR D_MODE D_TIMR ISTA IMASK D_EXIR D_EXIM D_STAR D_RSTA D_SAM D_SAP1 D_SAP2 D_TAM D_TEI1 D_TEI2 D_RBCH D_RBCL TIMR2 L1_RC D_CTL CIR CIX SQR SQX PCTL MOR MOX MOSR MOCR GCR XADDR XDATA EPCTL - 42 - DESCRIPTION D channel receive FIFO D channel transmit FIFO D channel command register D channel mode control D channel timer control Interrupt status register Interrupt mask register D channel extended interrupt D channel extended interrupt mask D channel status register D channel receive status D channel address mask 1 D channel individual SAPI 1 D channel individual SAPI 2 D channel address mask 2 D channel individual TEI 1 D channel individual TEI 2 D channel receive frame byte count high D channel receive frame byte count low Timer 2 GCI layer 1 ready code D channel control register Command/Indication receive Command/Indication transmit S/Q channel receive register S/Q channel transmit register Peripheral control register Monitor receive channel Monitor transmit channel Monitor channel status register Monitor channel control register GCI mode control register Peripheral address register Peripheral data register Serial EEPROM control W6692 W6692 Table 8.2 Register summary: Chip Control and D channel HDLC OFFSET R/W NAME 00 R W 6 5 4 3 2 1 0 D_RFIFO 04 7 D_XFIFO 08 W D_CMDR RACK RRST STT XMS XME XRST 0C R/W D_MODE MMS RACT TMS TEE MFD DLP RLP 10 R/W D_TIMR CNT1 VAL4 VAL3 VAL2 VAL1 VAL0 CNT2 CNT0 14 R_clr ISTA D_RMR D_RME D_XFR XINT1 XINT0 D_EXI B1_EXI B2_EXI 18 R/W D_RMR D_RME D_XFR XINT1 XINT0 D_EXI B1_EXI B2_EXI 1C R_clr D_EXIR RDOV XDUN XCOL TIN2 MOC ISC TEXP WEXP XDUN MOC ISC TEXP WEXP IMASK 20 R/W D_EXIM RDOV 24 R D_STAR XDOW 28 R D_RSTA XCOL TIN2 XBZ DRDY RDOV CRCE RMB 2C R/W D_SAM SAM7 SAM6 SAM5 SAM4 SAM3 SAM2 SAM1 SAM0 30 R/W D_SAP1 SA17 SA16 SA15 SA14 SA13 SA12 SA11 SA10 34 R/W D_SAP2 SA27 SA26 SA25 SA24 SA23 SA22 SA21 SA20 38 R/W D_TAM TAM7 TAM6 TAM5 TAM4 TAM3 TAM2 TAM1 TAM0 3C R/W D_TEI1 TA17 TA16 TA15 TA14 TA13 TA12 TA11 TA10 40 R/W D_TEI2 TA27 TA26 TA25 TA24 TA23 TA22 TA21 TA20 44 R D_RBCH VN1 VN0 LOV RBC12 RBC12 RBC11 RBC11 RBC10 RBC10 RBC9 RBC8 48 R D_RBCL RBC7 RBC6 RBC5 RBC4 RBC3 RBC2 RBC1 RBC0 TMD 0 TCN5 TCN4 4C W TIMR2 50 R/W L1_RC 54 R/W D_CTL WTT1 WTT2 58 R CIR SCC ICC 5C W CIX 60 R SQR 64 W SQX 68 R/W PCTL 6C R R/W RC0 TPS OPS1 OPS0 CODR3 CODR2 CODR1 CODR0 CODX2 CODX1 CODX0 SRST S1 S2 S3 S4 Q1 Q2 Q3 Q4 OE2 OE1 OE0 XMODE PXC MER MDA MAB MRIE OE3 SCIE MDR OE4 MSYN MRC MXIE MXC GRLP SPU PD GE MOX 74 TCN0 MOR 70 TCN1 RC1 SCIE OE5 XIND0 TCN2 RC2 CODX3 XIND1 TCN3 RC3 R_clr MOSR 78 R/W MOCR 7C R/W GCR MAC F4 R/W XADDR XA7/IO7 XA6/IO6 XA5/IO5 XA4/IO4 XA3/IO3 XA2/IO2 F8 R/W XDATA XD7 FC W EPCTL TLP XD6 XD5 XD4 XA1/IO1 XA0/IO0 XD2/IO10 XD2/IO10 XD1/IO9 XD0/IO8 EN - 43 - XD3 SK CS SDO Publication Release Date: October 1998 Revision A1 W6692 W6692 8.1.1 D_ch receive FIFO D_RFIFO Read Address 00H The D_RFIFO has a length of 128 bytes. After a D_RMR interrupt, exactly 64 bytes are available. After a D_RME interrupt, the number of bytes available equals RBC5-0 bits in the D_RBCL register. 8.1.2 D_ch transmit FIFO D_XFIFO Write Address 04H The D_XFIFO has a length of 128 bytes. After an D_XFR interrupt, up to 64 bytes of data can be written into this FIFO for transmission. At the first time, up to 128 bytes of data can be written. 8.1.3 D_ch command register D_CMDR Write Address 08H Value after reset: 00H 7 6 RACK RRST RACK 5 4 3 STT 2 XMS 1 0 XME XRST Receive Acknowledge After a D_RMR or D_RME interrupt, the processor must read out the data in D_RFIFO and then sets this bit to acknowledge the interrupt. RRST Receiver Reset Setting this bit resets the D_ch HDLC receiver and clears the D_RFIFO data. STT Start Timer The D_ch hardware timer is started when this bit is set to one. The timer is stopped when it expires or by a write of the D_TIMR register. Note that the timer must be in external mode. XMS Transmit Message Start/Continue Setting this bit will start or continue the transmission of a frame. The opening flag is automatically added by the HDLC controller. XME Transmit Message End Setting this bit indicates the end of frame transmission. The D_ch HDLC controller automatically appends the CRC and the closing flag after the data transmission. Note: If the frame 64 bytes, XME plus XMS commands must be issued at the same time. XRST Transmitter Reset Setting this bit resets the D_ch HDLC transmitter and clears the D_XFIFO. The transmitter will send inter frame time fill pattern (which is 1's) immediately. This command also results in a transmit FIFO ready condition. - 44 - W6692 W6692 8.1.4 D_ch Mode Register D_MODE Read/Write Address 0CH Value after reset: 00H 7 6 MMS RACT MMS 5 4 3 2 1 0 TMS TEE MFD DLP RLP Message Mode Setting Determines the message transfer mode of the D_ch HDLC controller: MMS MODE ADDRESS BYTES FIRST BYTE ADDRESS COMPARISON WITH: SECOND BYTE ADDRESS COMPARISON WITH: 0 Transparent mode 2 D_SAP1, D_SAP2, SAPG D_TEI1, D_TEI2, TEIG Notes: 1. D_SAP1, D_SAP2: two programmable address values for the first received address byte; SAPG = fixed value FC/FEH. D_TEI1, D_TEI2 : two programmable address values for the second received address byte; TEIG = fixed value FFH. 2: The first byte address comparison can be masked by D_SAM register, and the second byte address comparison can be masked by D_TAM register. But the comparisons with SAPG and TEIG cannot be disabled. RACT Receiver Active Setting this bit activates the D_ch HDLC receiver. This bit can be read. The receiver must be in active state in order to receive data. TMS Timer Mode Setting Sets the operating mode of the D_ch timer. In the external mode (TMS = 0), the timer is controlled by the processor. It is started by setting the STT bit in D_CMDR and is stopped by a write of the D_TIMR register or when it expires. When the timer expires, a maskable D_EXP interrupt is generated. In the internal mode (TMS = 1), the timer is used for internal test purposes. It should not be selected for normal chip operation. TEE Terminal Equipment Function Enable The terminal equipment function is enabled when this bit is "1". The supported functions are: - Watchdog timer, enabled when TEE = 1 and D_CTL: TPS =1 - Exchange awake, enabled when TEE = 1 and D_CTL: TPS =0 When the watchdog timer has been enabled, the micro-processor has to program the WTT1, 2 bits in a specified manner within 1024 mS to reset and restart the timer. Otherwise, the timer will expire in 1024 mS and a WEXP interrupt together with a 125 µS reset pulse on TRST pin is generated. The exchange awake condition is initiated by C/I code change condition. A 16 mS reset pulse on TRST pin is generated. Switching TPS bit will reset the watchdog timer. The TEE bit is cleared only by a hardware reset. - 45 - Publication Release Date: October 1998 Revision A1 W6692 W6692 MFD Multiframe Disable This bit is used to enable or disable the multiframe structure on S/T interface: 0 : Multiframe is enabled 1 : Multiframe is disabled DLP Digital Loopback Setting this bit activates the digital loopback function. The transmitted digital 2B+D channels are looped to the received 2B+D channels. Note that after hardware reset, the internal clocks will turn off if the S bus is not connected or if there is no signal on the S bus. In this case, the C/I command ECK must be issued to enable loopback function. RLP Remote Loopback Setting this bit to "1" activates the remote loopback function. The received 2B channels from the S interface are looped to the transmitted 2B channels of S interface. The D channel is not looped in this loopback function. 8.1.5 D_ch Timer Register D_TIMR Read/Write Address 10H Value after reset: FFH 7 6 5 4 3 2 1 0 CNT2 CNT1 CNT0 VAL4 VAL3 VAL2 VAL1 VAL0 CNT together with VAL determine the time period T2 after which a TEXP interrupt will be generated: T2 = CNT * 2.048 s + T1 with T1 = (VAL +1) * 0.064 s The timer is started by setting the STT bit in D_CMDR and will be stopped when a TEXP interrupt is generated or the D_TIMR register is written. Note: If CNT is set to 7, a TEXP interrupt is generated periodically at every expiration of T1. This register can be read only after the timer has been started. The read value indicates the timer's current count value. In case layer 1 is not activated, a C/I command "ECK" must be issued in addition to the STT command to start the timer. 8.1.6 Interrupt Status Register ISTA Read_clear Address 14H Value after reset: 00H 7 6 5 D_RMR D_RME D_XFR D_RMR 4 3 2 1 0 D_EXI B1_EXI B2_EXI D_ch Receive Message Ready A 64-byte data is available in the D_RFIFO. The frame is not complete yet. - 46 - W6692 W6692 D_RME D_ch Receive Message End The last part of a frame with length > 64 bytes or a whole frame with length 64 bytes has been received. The whole frame length is obtained from D_RBCH + D_RBCL registers. The length of data in the D_RFIFO equals: Data length = RBC5-0 if RBC5-0 0 Data length = 64 if RBC5-0 =0 D_XFR D_ch Transmit FIFO Ready This bit indicates that the transmit FIFO is ready to accept data. Up to 64 bytes of data can be written into the D_XFIFO. An D_XFR interrupt is generated in the following cases: - after an XMS command, when 64 bytes of XFIFO is empty - after an XMS together with an XME command is issued, when the whole frame has been transmitted - after hardware reset XINT1 XINTIN1 Interrupt This bit indicates that level change occurs at XINTIN1 pin. Both positive and negative edges will cause an interrupt. XINT0 XINTIN1 Interrupt This bit indicates that level change occurs at XINTIN0 pin. Both positive and negative edges will cause an interrupt. D_EXI D_ch Extended Interrupt This bit indicates that at least one interrupt bit has been set in D_EXIR register. B1_EXI B1_ch Extended Interrupt This bit indicates that at least one interrupt bit has been set in B1_EXIR register. B2_EXI B2_ch Extended Interrupt This bit indicates that at least one interrupt bit has been set in B2_EXIR register. Note: A read of the ISTA register clears all bits except D_EXI, B1_EXI and B2_EXI bits. D_EXI bit is cleared when all bits in D_EXIR register are cleared, B1_EXI bit is cleared by reading B1_EXI register and B2_EXI bit is cleared by reading B2_EXIR register. - 47 - Publication Release Date: October 1998 Revision A1 W6692 W6692 8.1.7 Interrupt Mask Register IMASK R/W Address 18H Value after reset: FFH 7 6 5 4 3 2 1 0 D_RMR D_RME D_XFR XINT1 XINT0 D_EXI B1_EXI B2_EXI Setting the bit to "1" masks the corresponding interrupt source in ISTA register. Masked interrupt status bits are read as zero. They are internally stored and pending until the mask bits are zero. Setting the D_EXI, B1_EXI or B2_EXI bit to "1" masks all the interrupts in D_EXIR, B1_EXIR or B2_EXIR register, respectively. 8.1.8 D_ch Extended Interrupt Register D_EXIR Read_clear Address 1CH Value after reset: 00H 7 6 5 RDOV XDUN XCOL RDOV 4 3 2 1 0 MOC ISC TEXP WEXP Receive Data Overflow Frame overflow (too many short frames) or data overflow occurs in the receive FIFO. In data overflow, the incoming data will overwrite the data in the receive FIFO. If RDOV interrupt occurs, software has to reset the receiver and discard the data received. XDUN Transmit Data Underrun This interrupt indicates the D_XFIFO has run out of data. In this case, the W6692 W6692 will automatically reset the transmitter and send the inter frame time fill pattern (all 1's) on D channel. The microprocessor must wait until transmit FIFO ready (via XFR interrupt), re-write data, and issue XMS command to re-transmit the data. XCOL Transmit Collision This bit indicates a collision on the S-bus has been detected. A XRST command must be issued and software must wait until transmit FIFO ready (via XFR interrupt), re-write data, and issue XMS command to re-transmit the data. TIN2 Timer 2 Expiration This bit is set when Timer 2 counts down to zero. MOC Monitor Channel Status Change A change in the GCI mode Monitor Channel Status Register (MOSR) has occurred. A new Monitor channel byte is stored in the MOR register. ISC Indication or S Channel Change A change in the layer 1 indication code or multiframe S channel has been detected. The actual value can be read from CIR or SQR registers. - 48 - W6692 W6692 TEXP D_ch Timer Expiration Expiration occurs in the D_ch timer. The timer must be in external mode. WEXP Watchdog Timer Expiration Expiration occurs in the watch dog timer. A reset pulse with 125 µS pulse width is also generated on the TRST pin. See D_CTL register for watch dog timer control. 8.1.9 D_ch Extended Interrupt Mask Register D_EXIM Read/Write Address 20H Value after reset: FFH 7 6 5 4 3 2 1 0 RDOV XDUN XCOL TIN2 MOC ISC TEXP WEXP Setting the bit to "1" masks the corresponding interrupt source in D_EXIR register. Masked interrupt status bits are read as zero. They are internally stored and pending until the mask bits are zero. All the interrupts in D_EXIR will be masked if the IMASK: D_EXI bit is set to "1". 8.1.10 D_ch Status Register D_STAR Read Address 24H Value after reset: 0XH 7 6 XDOW XDOW 5 4 XBZ 3 2 1 0 DRDY Transmit Data Overwritten At least one byte of data has been overwritten in the D_XFIFO. This bit is set by data overwritten condition and is cleared only by XRST command. XBZ Transmitter Busy This bit indicates the D_HDLC transmitter is busy. The XBZ bit is active from the transmission of opening flag to the transmission of closing flag. DRDY D Channel Ready This bit indicates the status of layer 1 D channel. 0: The layer 1 D channel is not ready. No transmission is allowed. 1: The layer 1 D channel is ready. Layer 2 can transmit data to layer 1. - 49 - Publication Release Date: October 1998 Revision A1 W6692 W6692 8.1.11 D_ch Receive Status Register D_RSTA Read Address 28H Value after reset: 20H 7 6 4 RDOV RDOV 5 CRCE 3 2 1 0 RMB Receive Data Overflow A "1" indicates that the D_RFIFO is overflow. The incoming data will overwrite data in the receive FIFO. The data overflow condition will set both the status and interrupt bits. It is recommended that software must read the RDOV bit after reading data from D_RFIFO at RMR or RME interrupt. The software must abort the data and issue a RRST command to reset the receiver if RDOV = 1. The frame overflow condition will not set this bit. CRCE CRC Error This bit indicates the result of frame CRC check: 0: CRC correct 1: CRC error RMB Receive Message Aborted A "1" means that a sequence of seven 1's was received and the frame is aborted. Software must issue RRST command to reset the receiver. Note: Normally D_RSTA register should be read by the micro-processor after a D_RME interrupt. The contents of D_RSTA are valid only after a D_RME interrupt and remain valid until the frame is acknowledged via a RACK bit. 8.1.12 D_ch SAPI Address Mask D_SAM Read/Write Address 2CH Value after reset: 00H 7 6 5 4 3 2 1 0 SAM7 SAM6 SAM5 SAM4 SAM3 SAM2 SAM1 SAM0 This register masks(disables) the first byte address comparison of the incoming frame. If the mask bit is "1" the corresponding bit comparisons with D_SAP1, D_SAP2 are disabled. Comparison with SAPG is always performed. Note: For the LAPD frame, the least significant two bits are the C/R bit and EA = 0 bit. It is suggested that the comparison with C/R bit be masked. EA = 0 for two octet address frame e.g LAPD, EA = 1 for one octet address frame. 8.1.13 D_ch SAPI1 Register D_SAP1 Read/Write Address 30H Value after reset: 00H 7 6 5 4 3 2 1 0 SA17 SA16 SA15 SA14 SA13 SA12 SA11 SA10 This register contains the first choice of the first byte address of received frame. For LAPD frame, SA17 - SA12 is the SAPI value, SA11 is C/R bit and SA10 is zero. - 50 - W6692 W6692 8.1.14 D_ch SAPI2 Register D_SAP2 Read/Write Address 34H Value after reset: 00H 7 6 5 4 3 2 1 0 SA27 SA26 SA25 SA24 SA23 SA22 SA21 SA20 This register contains the second choice of the first byte address of received frame. For LAPD frame, SA27 - SA22 is the SAPI value, SA21 is C/R bit and SA20 is zero. 8.1.15 D_ch TEI Address Mask D_TAM Read/Write Address 38H Value after reset: 00H 7 6 5 4 3 2 1 0 TAM7 TAM6 TAM5 TAM4 TAM3 TAM2 TAM1 TAM0 This register masks(disables) the second byte address comparison of the incoming frame. If the mask bit is "1" the corresponding bit comparisons with D_TEI1, D_TEI2 are disabled. Comparison with TEIG is always performed. Note: For the LAPD frame, the least significant bit is the EA = 1 bit. 8.1.16 D_ch TEI1 Register D_TEI1 Read/Write Address 3CH Value after reset: 00H 7 6 5 4 3 2 1 0 TA17 TA16 TA15 TA14 TA13 TA12 TA11 TA10 TA17 - TA10 This