W5300 -W5300 100LQFP 14X14 128KB BIT16EN W5100 10/100M OSC25I VCC343 TMS01R - Datasheet Archive

 

High-Performance Internet Connectivity Solution W5300 Version 1.2.3 W5300 © 2008 WIZnet Co., Inc. All Rights Reserved. For

 

High-performance Internet Connectivity Solution High-Performance Internet Connectivity Solution W5300 W5300 Version 1.2.3 W5300 W5300 © 2008 WIZnet Co., Inc. All Rights Reserved. For more information, visit our website at http://www.wiznet.co.kr © Copyright 2008 WIZnet Co., Inc. All rights reserved. 1 High-performance Internet Connectivity Solution Document History Information Version Date Descriptions Ver. 1.0.0 Mar. 11, 2008 Release with W5300 W5300 launching Ver. 1.1.0 May. 15, 2008 Correct a number of typing errors 4.4 SOCKET Register >> Sn_DPORTR R/W à WO, Modify the description, Refer to P.77 4.4 SOCKET Register >> Sn_MSSR In the MSS Table, Modified the PPPoE MSS value of MACRAW(1502 à 1514), Refer to P.79 5.2.1.1 TCP SERVER >> ESTABLISHED : Receiving process W5300 W5300 At the phase, Modified the example code Replace `SEND' with `SEND_KEEP'. Refer to P.93~94 5.2.4 MACRAW >> Receiving process At the phase, Modified the free size and CRC Free size 1526 à 1528, CRC(2) à CRC(4), Refer to P.111 Ver. 1.1.1 July 4, 2008 Correct a number of typing errors Add PIN "BRDYn" description to "1.3 Host Interface signal" 5.2.1.1 TCP SERVER >> ESTABLISHED : Receiving process At the phase, Modified the example code Replace `SEND_KEEP' with `SEND'. Refer to P.93~94 Ver 1.2 Dec. 30, 2008 1. PIN Description Add to `8' Symbol 1.2 Configuration Signals Modify ADDR type (ID à I), No Internal Pulled-down Modify DATA[15:0] type (IO à IO8) 6.2. Indirect Address Mode ADDR[9:0] has no internal pulled-down resister. So, ADDR[9:3] should be connected to ground for using indirect address mode. © Copyright 2008 WIZnet Co., Inc. All rights reserved. 2 High-performance Internet Connectivity Solution Modify the description & figures. Ver 1.2.1 Jan. 22, 2009 Modify the Figure 2. Ferrite Bead 0.1uF à 1uH Ver 1.2.2 Feb. 16, 2009 1.7 Clock Signals. Delete XTLP/XTLN Pin Type 7. Electrical Specifications - DC Characteristics : Modify the Test Condition of VOH, VOL : VOH - Min (2.0(2.4), Delete Typical and Max value : VOL ­ Delete Min and Typical value V1.2.3 Feb.11, 2010 Figure 2 -W5300 -W5300 Power Supply Signal schematic W5300 W5300 © Copyright 2008 WIZnet Co., Inc. All rights reserved. 3 High-performance Internet Connectivity Solution WIZnet's online Technical Support If you have something to ask about WIZnet Products, write down your question on Q&A Board of `Support' menu in WIZnet website (www.wiznet.co.kr). WIZnet Engineer will give an answer as soon as possible. Click W5300 W5300 © Copyright 2008 WIZnet Co., Inc. All rights reserved. 4 High-performance Internet Connectivity Solution W5300 W5300 W5300 W5300 is a 0.18 µm CMOS technology single chip into which 10/100 Ethernet controller, MAC, and TCP/IP are integrated. W5300 W5300 is designed for Internet embedded applications where easy implementation, stability, high performance, and effective cost are required. W5300 W5300's target application is the embedded internet solution requiring high performance such as multi-media streaming service. Comparing to existing WIZnet chip solution, W5300 W5300 has been improved in memory and data process. W5300 W5300 is the most appropriate to the products of IPTV, IP-STB and DTV transferring multi-media data with high-capacity. The Internet connectivity can be implemented easily and quickly only with single chip having TCP/IP protocol and 10/100 Ethernet MAC & PHY. High-Performance Hardware TCP/IP single chip solutions WIZnet retains the technology of full hardware logic of communication protocols such as TCP, W5300 W5300 UDP, IPv4, ICMP, IGMP, ARP and PPPoE. In order to provide high-performing data communication, the data communication memory is extended to 128Kbyte and 16bit bus interface is supported in W5300 W5300. Users can utilize independent 8 hardware SOCKETs for highspeed data communication. More flexible memory allocation for various applications The memory for data communication can be allocated to each SOCKET in the range of 0~64Kbytes. It is more flexible for users to utilize the memory according to their application. Users can develop more efficient system by concentrating on the application of high performance. Easy to implements for beginners W5300 W5300 supports BUS interface as the host interface. By using direct and indirect access methods, W5300 W5300 can easily interfaced to the host as like SRAM memory. The data communication memory of W5300 W5300 can be accessed through TX/RX FIFO registers that exist in each SOCKET. With these features, even beginners can implement Internet connectivity by using W5300 W5300. © Copyright 2008 WIZnet Co., Inc. All rights reserved. 5 High-performance Internet Connectivity Solution Target Applications The W5300 W5300 is well-suited for many embedded applications, including: - Home Network Devices: Set-Top Boxes, PVRs, Digital Media Adapters - Serial-to-Ethernet: Access Controls, LED displays, etc. - Parallel-to-Ethernet: POS / Mini Printers, Copiers - USB-to-Ethernet: Storage Devices, Network Printers - GPIO-to-Ethernet: Home Network Sensors - Security Systems: DVRs, Network Cameras, Kiosks - Factory and Building Automation - Medical Monitoring Equipment - Embedded Servers Features Supports hardwired TCP/IP protocols : TCP,UDP,ICMP,IPv4,ARP,IGMPv2,PPPoE,Ethernet - Supports 8 independent SOCKETs simultaneously - High network performance : Up to 50Mbps - Supports hybrid TCP/IP stack(software and hardware TCP/IP stack) - Supports PPPoE connection (with PAP/CHAP Authentication mode) - IP Fragmentation is not supported - Internal 128Kbytes memory for data communication(Internal TX/RX memory) - More flexible allocation internal TX/RX memory according to application throughput - Supports memory-to-memory DMA (only 16bit Data bus width & slave mode) - Embedded 10BaseT/100BaseTX Ethernet PHY - Supports auto negotiation (Full-duplex and half duplex) - Supports auto MDI/MDIX(Crossover) - Supports network Indicator LEDs (TX, RX, Full/Half duplex, Collision, Link, Speed) - Supports a external PHY instead of the internal PHY - Supports 16/8 bit data bus width - Supports 2 host interface mode(Direct address mode & Indirect address mode) - External 25MHz operation frequency (For internal PLL logic, period=40ns) - Internal 150MHz core operation frequency (PLL_CLK, period=about 6.67ns) - Network operation frequency (NIC_CLK : 25MHz(100BaseTX) or 2.5MHz(10BaseT) - 3.3V operation with 5V I/O signal tolerance - Embedded power regulator for 1.8V core operation - 0.18 µm CMOS technology - 100LQFP 100LQFP 14X14 14X14 Lead-Free Package © Copyright 2008 WIZnet Co., Inc. All rights reserved. W5300 W5300 - 6 High-performance Internet Connectivity Solution Block Diagram Host Host Host Bus Interface Host Interface Manager 150MHz 25MHz Register Manager PLL PPPoE 3.3V 1.8V Power Regulator ARP IGMP V1/V2 IP W5300 W5300 ICMP Memory Manager UDP TCP 128KB 128KB TX/RX DPRAM TCP/IP Core 802.3 Ethernet MAC + - MII Manager (CSMA/CD) Ethernet PHY External MII 3rd Party Media Interface Transformer Ethernet PHY RJ45 © Copyright 2008 WIZnet Co., Inc. All rights reserved. 7 High-performance Internet Connectivity Solution PLL(Phase-Locked Loop) It creates a 150MHz clock signal by multiplying 25MHz clock source by six. The 150MHz clock is used for operating internal blocks such as TCP/IP core block, `Host Interface Manager' and `Register Manager'. PLL is locked-in after reset and it supplies a stable clock. Power Regulator With 3.3V power input, the power regulator creates 1.8V/150mA power. This power regulator supplies the power for core operation of W5300 W5300. It is not required to add other power regulators, but recommended to add a capacitor for more stable 1.8V power supplying. Host Interface Manager It detects host bus signal, and manages read/write operations of the host according to data bus width or host interface mode. W5300 W5300 Register Manager It manages Mode register, COMMON Register, and SOCKET Register. Memory Manager It manages internal data memory of 128KBytes ­ TX/RX memory allocated in each SOCKET by the host. The host can access the memory only through TX/RX FIFO Register of each SOCKET. 128KB 128KB TX/RX DPRAM It is the 128KByte memory for data communication and composed of 16 DPRAM(Dual-Port RAM) of 8KBytes. It is allocated flexibly to each SOCKET by the host. MII(Media Independent Interface) Manager rd It manages MII interface. MII interface can be switched to internal PHY or external PHY(3 party PHY) according to the configuration of TEST_MODE[3:0]. Internal Ethernet PHY W5300 W5300 includes 10BaseT/100BaseTX Ethernet PHY. Internal PHY supports half-duplex/full duplex, auto-negotiation and auto MDI/MDIX. It also supports 6 network indicator LED output such as Link status, speed and duplex. TCP/IP Core TCP/IP Core is the fully hardwired logic based on network protocol processing technology of WIZnet. © Copyright 2008 WIZnet Co., Inc. All rights reserved. 8 High-performance Internet Connectivity Solution - 802.3 Ethernet MAC(Media Access Control) It controls Ethernet access of CSMA/CD(Carrier Sense Multiple Access with Collision Detect). It is the protocol technology based on a 48-bit source/destination MAC address. It th also allows the host to control MAC layer through its 0 SOCKET. So, it is possible to implement software TCP/IP stack together with hardware TCP/IP stack. - PPPoE(Point-To-Point Protocol over Ethernet) It is the protocol technology to use PPP service at the Ethernet. It encapsulates the payload(data) part of Ethernet frame as the PPP frame and transmits it. When receiving, it de-capsulates the PPP frame. PPPoE supports PPP communication with PPPoE server and PAP/CHAP authentication methods. - ARP(Address Resolution Protocol) ARP is the MAC address resolution protocol by using IP address. It transmits the ARPreply to the ARP-request from the peer. It also sends ARP-request to find the MAC address of the peer and processes the ARP-reply to the request. IP(Internet Protocol) W5300 W5300 - IP is the protocol technology to support data communication at the IP layer. IP fragmentation is not supported. It is not possible to receive the fragmented packets. Except for TCP or UDP, all protocol number is supported. In case of TCP or UDP, use the hardwired stack. - ICMP(Internet Control Message Protocol) It receives the ICMP packets such as the fragment MTU, unreachable destination, and notifies the host. After receiving Ping-request ICMP packet, it transmits Ping-reply ICMP packet. It supports maximum 119 Byte as Ping-request size. If the size is over 119Bytes, it is not supported. - IGMPv1/v2(Internet Group Management Protocol version 1/2) It processes IGMP such as IGMP Join/Leave, Report at the UDP multicasting mode. Only version 1 and 2 of IGMP logic is supported. When using upper version of IGMP, it should be manually implemented by using IP layer. - UDP(User Datagram Protocol) It is the protocol technology to support data communication at the UDP layer. It supports user datagram such as unicast, multicast, and broadcast. - TCP(Transmission Control Protocol) It is the protocol technology to support data communication at the TCP layer. It supports "TCP SERVER" and "TCP CLIENT" communication. W5300 W5300 internally processes all protocol communication without intervention of the host. W5300 W5300 is based on TOE(TCP/IP Offload Engine) that can maximize the host performance by reducing the host overhead in processing TCP/IP stack. © Copyright 2008 WIZnet Co., Inc. All rights reserved. 9 High-performance Internet Connectivity Solution Table of Contents 1. PIN Description . 12 1.1 PIN Layout . 12 1.2 Configuration Signals . 13 1.3 Host Interface Signals . 14 1.4 Media Interface Signals. 16 1.5 MII interface signal for external PHY . 17 1.6 Network Indicator LED Signals . 19 1.7 Clock Signals . 19 1.8 Power Supply Signals . 20 2. System Memory Map . 22 3. W5300 W5300 Registers . 24 W5300 W5300 3.1 Mode Register . 25 3.2 Indirect Mode Registers . 25 3.3 COMMON registers . 25 3.4 SOCKET registers . 29 4. Register Description . 45 4.1 Mode Register . 46 4.2 Indirect Mode Registers . 49 4.3 COMMON Registers . 50 4.4 SOCKET Registers . 66 5. Functional Description . 88 5.1 Initialization . 88 5.2 Data Communication . 90 5.2.1 TCP . 90 5.2.2 UDP. 100 5.2.3 IPRAW . 107 5.2.4 MACRAW . 109 6. External Interface . 115 6.1 Direct Address Mode . 115 6.1.1 16 Bit Data Bus Width . 115 6.1.2 8 Bit Data Bus Width . 115 6.2 Indirect Address Mode . 116 6.2.1 16 Bit Data Bus Width . 116 6.2.2 8 Bit Data Bus Width . 116 © Copyright 2008 WIZnet Co., Inc. All rights reserved. 10 High-performance Internet Connectivity Solution 6.3 Internal PHY Mode . 117 6.4 External PHY Mode . 118 7. Electrical Specifications . 119 8. IR Reflow Temperature Profile (Lead-Free) . 123 9. Package Descriptions . 124 List of Figures Fig 1. PIN Layout . 12 Fig 2. Power Design . 21 Fig 3. Memory Map . 23 Fig 4. `BRDYn' Timing . 65 Fig 5. SOCKETn Status Transition . 77 Fig 6. Access to Internal TX Memory . 86 W5300 W5300 Fig 7. Access to Internal RX Memory . 87 Fig 8. Allocation Internal TX/RX memory of SOCKETn . 89 Fig 9. "TCP SERVER" & "TCP CLIENT" . 90 Fig 10. "TCP SERVER" Operation Flow . 91 Fig 11. The received TCP data format. 93 Fig 12. "TCP CLIENT" Operation Flow . 99 Fig 13. UDP Operation Flow . 100 Fig 14. The received UDP data format . 101 Fig 15. IPRAW Operation Flow . 107 Fig 16. The received IPRAW data format . 108 Fig 17. MACRAW Operation Flow . 109 Fig 18. The received MACRAW data format . 110 Fig 19. Internal PHY & LED Signals . 117 Fig 20. External PHY Interface with MII . 118 © Copyright 2008 WIZnet Co., Inc. All rights reserved. 11 High-performance Internet Connectivity Solution 1. PIN Description Typ Description e Type Description I Input D Internal pulled-down with 75K resistor O Output with driving current 2mA M Multi-function IO Input/Output (Bidirectional) H Active high U Internal pulled-up with 75K resistor L Active low O8 Output with driving current 8mA IUL : Input PIN with 75K pull-up resistor. Active low OM : Multi-functional Output PIN 1.1 PIN Layout W5300 W5300 Fig 1. PIN Layout © Copyright 2008 WIZnet Co., Inc. All rights reserved. 12 High-performance Internet Connectivity Solution 1.2 Configuration Signals Symbol Type TEST_MODE[3:0] ID Description W5300 W5300 mode select It configures PHY mode and factory test mode of W5300 W5300. TEST_MODE Description 3 2 1 0 0 0 0 0 Internal PHY Mode (Normal Operation) 0 0 0 1 External PHY Mode with Crystal clock 0 0 1 0 External PHY Mode with Oscillator clock Others Reserved (Factory Test Mode) At the external PHY mode, Clock input pin is changed by clock OP_MODE[2:0] ID W5300 W5300 source. Refer to "1.7 Clock Signals". Internal PHY operation control mode It configures the operation mode of internal PHY. OP_MODE Description 2 1 0 0 0 0 Normal Operation Mode, Recommended Auto-negotiation enable with all capabilities 0 0 1 Auto-negotiation with 100 BASE-TX FDX/HDX ability 0 1 0 Auto-negotiation with 10 BASE-T FDX/HDX ability 0 1 1 Reserved 1 0 0 Manual selection of 100 BASE-TX FDX 1 0 1 Manual selection of 100 BASE-TX HDX 1 1 0 Manual selection of 10 BASE-T FDX 1 1 1 Manual selection of 10 BASE-T HDX cf> FDX : Full-duplex, HDX : Half-duplex The setting value is latched after hardware reset. © Copyright 2008 WIZnet Co., Inc. All rights reserved. 13 High-performance Internet Connectivity Solution 1.3 Host Interface Signals Symbol Type /RESET IL Description RESET Hardware Reset Signal. It initializes W5300 W5300. RESET should be held at least 2us after low assert, and wait for at least 10ms after high de-assert in order for PLL logic to be stable. Refer to RESET timing of "7 Electrical Specification" W5300 W5300 does not support Power-On-Reset. Therefore, it should be manually designed in the target system. BIT16EN BIT16EN IU 16/8 BIT DATA BUS SELECT High : 16 bit data bus Low : 8 bit data bus W5300 W5300 It determinates data bus width of W5300 W5300. th At reset time, it is latched in 15 Bit(`BW')of Mode register(MR). After reset, its change is ignored. It means data bus width can't be changed after reset. When using 8 bit data bus, it should be connected to ground. ADDR9-0 I ADDRESS System address bus. These are selected by host interface mode and data bus width of W5300 W5300. When using 16 bit data bus, ADDR0 is internally ignored. Refer to "6.External Interface". DATA[15:8] IO DATA System high data bus. These are used for read/write operation of W5300 W5300 register. In case of using 8 bit data bus, These are driven as High-Z. DATA[7:0] IO8 DATA System low data bus. These are used for read/write operation of W5300 W5300 register. /CS IL CHIP SELECT Chip select signal. © Copyright 2008 WIZnet Co., Inc. All rights reserved. 14 High-performance Internet Connectivity Solution Host selects W5300 W5300 at the W5300 W5300 read/write operation. When /CS is de-asserted high, DATA[15:0] are driven as High-Z. /WR IL WRITE ENABLE Write enable signal. Host writes W5300 W5300 register addressed by ADDR[9:0] to DATA[15:0]. DATA[15:0] are latched in the W5300 W5300 register according to the configuration of the Write-data-fetch-timing. th Refer to 13-11 bit(WDF[2:0] of MR). /RD IL READ ENABLE Read enable signal. Host reads W5300 W5300 register addressed by ADDR[9:0] through /INT OL W5300 W5300 DATA[15:0]. INTERRUPT Interrupt Request Signal. It is asserted low when interrupt(connected, disconnected, data received, data sent or timeout) occurs on operating. When interrupt service is completed by host and Interrupt register(IR) is cleared by host, it is de-asserted high. Refer to IR, Interrupt Mask Register(IMR), SOCKETn Interrupt Register(Sn_IR), SOCKETn Interrupt Mask Register(Sn_IMR). BRDY[3:0] O Buffer Ready Indicator These PIN are configured with SOCKET number, memory Type, and buffer depth by user. When TX free or RX received size of the specified SOCKET is same or greater than the configured buffer depth, these PIN signals asserts high or low. Refer to Pn_BRDYR & Pn_DPTHR in "4.3 COMMON Registers". © Copyright 2008 WIZnet Co., Inc. All rights reserved. 15 High-performance Internet Connectivity Solution 1.4 Media Interface Signals Media(10Mbps/100Mbps) interface signals are used in internal PHY mode (TEST_Mode[3:0] = "0000"). Refer to "1.2 Configuration Signals". Symbol Type RXIP I Description RXIP/RXIN Signal Pair Differential receive Input signal pair. RXIN I Receive data from the media. This signal pair needs 2 termination resistors 50(±1%) and 1 capacitor 0.1uF for better impedance matching, and this resistor/capacitor pair is located near magnetic(transformer). If not used, connect to ground. TXOP O TXOP/TXON Signal Pair Differential transmit output signal pair. O W5300 W5300 TXON Transmits data to the media. This signal pair needs 2 termination resistors 50 (±1%) and 1 capacitor 0.1uF for better impedance matching, and this resistor/capacitor pair should be located near W5300 W5300. If not used, just let them float. RSET_BG O Off-chip Resistor This pin should be pulled-down with 12.3 ±1% resistor. For the better performance, 1. Make the length of RXIP/RXIN signal pair (RX) same if possible. 2. Make the length of TXOP/TXON signal pail (TX) same if possible. 3. Locate the RXIP and RXIN signal as near as possible. 4. Locate the TXOP and TXON signal as near as possible. 5. Locate the RX and TX signal pairs far from noisy signals such as bias resistor or crystal. For the detailed information refer to "W5100 W5100 Layout Guide.pdf" © Copyright 2008 WIZnet Co., Inc. All rights reserved. 16 High-performance Internet Connectivity Solution 1.5 MII interface signal for external PHY MII interface signals are for interfacing to external PHY instead of the internal PHY of W5300 W5300. These signals can be used at the external PHY mode (TEST_Mode[3:0] = "0001" or "0010"). Refer to "1.2 Configuration Signals". At the internal PHY mode, just let them float because the pins except for multi-function pins are internal pulled-down. Symbol Type Description /TXLED(MII_TXEN) OMH Transmit Act LED / Transmit Enable This signal indicates the presence of transmit packet on the MII_TXD[3:0]. It is asserted high when the first nibble data of transmit packet is valid on MII_TXD[3:0] and is de-asserted low after the last nibble data of transmit packet is clocked out on /RXLED(MII_TXD3) OM W5300 W5300 MII_TXD[3:0]. /RXLED,/COLLED,/LEDFDX,/SPDLED / Transmit data output /COLLED(MII_TXD2) The transmit packet is synchronized with MII_TXC clock and /FDXLED(MII_TXD1) output to external PHY in nibble unit. /SPDLED(MII_TXD0) MII_TXC MII_TXD3 is the Most Significant Bit (MSB). ID Transmit Clock Input It is a continuous transmit clock from the external PHY. It is 25MHz at the 100BaseTX and 2.5MHz at the 10 BaseT. Transmit clock is used as timing reference of MII_TXD[3:0] and used for network operation clock (NIC_CLK). Rising Edge Sensitive. MII_CRS IDH Carrier Sense It is signal to notify the link traffic of the media. If carrier of media is not idle (carrier present), it is asserted high. MII_COL IDH Collision Detect When collision is detected on the media, it is asserted high. It is valid at the half-duplex and ignored at the full-duplex. Asynchronous signal. © Copyright 2008 WIZnet Co., Inc. All rights reserved. 17 ID High-performance Internet Connectivity Solution MII_RXD3 Receive Data Input MII_RXD2 When MII_RXDV is high, the received packet is synchronized MII_RXD1 with MII_RXC and inputs in nibble unit. MII_RXD0 MII_RXDV MII_RXD3 is MSB. ID Receive Data Valid This signal indicates the presence of received packet from MII_RXD[3:0]. It is asserted high when the first nibble data of the received packet is valid on MII_RXD[3:0] and is de-asserted low after the last nibble data of receive packet clocked in on MII_RXD[3:0]. It is valid when MII_RXC is at rising edge. ID Receive Clock Input W5300 W5300 MII_RXC It is continuous receive clock from the external PHY. It is 25MHz at the 100Base TX and 2.5MHz at the 10BaseT. Receive clock is used for timing reference of MII_RXD[3:0] and MII_RXDV. Rising Edge Sensitive. /FDX IDL Full-Duplex Select 0 : Full-duplex 1 : Half-duplex It is input signal from PHY that indicates link status of external PHY. Most of PHYs support auto-negotiation and notifies the result to network indicator LED or other signals. It can be connected to those signals and also it can be configurable manually by connecting high or low. Recommend for the better performance. 1. MII interface signal line length should not be more than 25cm if possible. 2. The length of MII_TXD[3:0] should be same if possible. 3. The length of MII_RXD[3:0] should be same if possible. 4. The length of MII_TXC should not be longer than MII_TXD[3:0] signal line by 2.5cm. 5. The length of MII_RXC should not be longer than MII_RXD[3:0] signal line by 2.5cm. © Copyright 2008 WIZnet Co., Inc. All rights reserved. 18 High-performance Internet Connectivity Solution 1.6 Network Indicator LED Signals The signals except for LINKLED, are used as multi-function PIN according to the configuration of TEST_MODE[3:0]. When using those signals as network indicator signals, internal PHY mode(TEST_MODE[3:0]="0000") should be configured. Symbol Type LINKLED OL Description Link LED It indicates the link status of media(10/100M 10/100M). /TXLED(MII_TXEN) OML Transmit activity LED/Transmit Enable It notifies the output of transmit data through TXOP/TXON (Transmit Activity). /RXLED(MII_TXD3) OML Receive activity LED/Transmit Data W5300 W5300 It notifies the input of receive data from RXIP/RXIN (Receive Activity) cf> By binding /TXLED and /RXLED signals with `AND' gate, it can be used for network activity LED. /COLLED(MII_TXD2) OML Collision LED/Transmit Data It notifies when collisions occur. It is valid at half-duplex, and is ignored at full-duplex. /FDXLED(MII_TXD1) OML Full duplex LED/Transmit Data It outputs low at the full-duplex and outputs high at the halfduplex according to auto-negotiation or manual configuration of OP_MODE[2:0]. /SPDLED(MII_TXD0) OML Link speed LED/Transmit Data It is asserted low at the 100Mbps and high at the 10Mbps according to auto-negotiation or manual configuration of OP_MODE[2:0]. 1.7 Clock Signals For the clock source of W5300 W5300, either a crystal or an oscillator may be used. 25MHz frequency from the clock source is created to 150MHz frequency using internal PLL logic. This 150MHz © Copyright 2008 WIZnet Co., Inc. All rights reserved. 19 High-performance Internet Connectivity Solution frequency is used for PLL_CLK(Period 6.67ns) and W5300 W5300 core operation clock. Symbol Type XTLP Description 25MHz crystal input/output 25MHz parallel-resonant crystal is used with matching capacitor for internal oscillator stabilization. Refer to "Clock Characteristic" of "7.Electrical Specifications" XTLN These can be used for internal PHY mode(TEST_MODE[3:0]="0000") or external PHY mode with crystal clock (TEST_MODE[3:0]="0001"). When using oscillator at the internal PHY mode, be sure to use 1.8V level oscillator and connect only to XTLP. And let be float XTLN. OSC25I OSC25I I 25MHz Oscillator input It is used only in external PHY mode with oscillator clock W5300 W5300 (TEST_MODE[3:0]="0010"). In order to prevent the leakage current, be sure to keep XTLP high and float XTLN, and use 1.8v level oscillator. 1.8 Power Supply Signals Symbol Type VCC3A3 Power Description 3.3V power supply for Analog part Be sure to connect 10uF tantalum capacitor between VCC343 VCC343 and GNDA in order to prevent power compensation. VCC3V3 Power 3.3V power supply for Digital part Between each VCC and GND, 0.1uF decoupling capacitor can be selectively connected. VCC3V3 can be separated to 1uH ferrite bead and connected to VCC3A3. VCC1A8 Power 1.8V power supply for Analog part Be sure to connect a 10uF tantalum capacitor and 0.1uF capacitor between VCC1A8 and GNDA for core power noise filtering. VCC1V8 Power 1.8V power supply for Digital part Between each VCC and GND, 0.1uF decoupling capacitor can be selectively connected. GNDA Ground Analog ground Make analogue ground plane as wide as possible when designing the PCB layout. GND Ground Digital ground Make digital ground plane as wide as possible when designing the © Copyright 2008 WIZnet Co., Inc. All rights reserved. 20 High-performance Internet Connectivity Solution PCB layout. 1V8O O 1.8V regulator output voltage 1.8V/150mA power created by internal power regulator, is used for core operation power (VCC1A8, VCC1V8). Be sure to connect 3.3uF tantalum capacitor between 1V8O and GND for output frequency compensation, and selectively connect 0.1uF capacitor for high frequency noise decoupling. 1V8O is connected to VCC1V8, separated to 1uH ferrite bead and connected to VCC1A8. 1V8O is the power for W5300 W5300 core operation. It should not be connected to the power of other devices. 3.3V Power Source VCC3A3 VCC3V3 VCC3V3 W5300 W5300 Ferrite Bead 1uH 0.1uF 10uF 0.1uF Ferrite Bead 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 10uF 1uH VCC1V8 VCC1A8 VCC1V8 Ferrite Bead 1V8O 1uH 0.1uF 3.3uF 10uF Ferrite Bead 10uF 0.1uF 0.1uF 1uH Fig 2. Power Design Recommend for power design. 1. Locate decoupling capacitor as close as possible to W5300 W5300. 2. Use ground plane as wide as possible. 3. If ground plane width is adequate, having a separate analog ground plane and digital ground plane is good practice. If ground plane is not wide, design analog and digital ground planes as a single ground plane, rather than separate them. © Copyright 2008 WIZnet Co., Inc. All rights reserved. 21 High-performance Internet Connectivity Solution 2. System Memory Map According to the host interface, W5300 W5300 supports direct address mode and indirect address mode. The direct address mode is that the target host system can directly access W5300 W5300 registers after mapping the registers to T.M.S(Target host system Memory-mapped I/O Space). Direct address mode memory map is composed of Mode register(MR), COMMON registers, and SOCKET registers. Those registers are mapped in T.M.S sequentially increasing by 2bytes from the BA(Base Address) of T.M.S. Using the mapping address, the target host system can directly access MR, COMMON registers and SOCKET registers. To use the direct address mode, total 0x400 bytes are required for memory space. In indirect address mode, target host system indirectly accesses COMMON registers and SOCKET registers by using IDM_AR(Indirect Mode Address Register) and IDM_DR(Indirect W5300 W5300 Mode Data Register) which are just only directly mapped in T.M.S together with MR. Indirect address mode memory map is composed of direct accessible MR, IDM_AR, IDM_DR and indirect accessible COMMON & SOCKET registers. Only MR, IDM_AR and IDM_DR are mapped in T.M.S sequentially increasing by 2Bytes from BA of T.M.S, but COMMON & SOCKET registers are not mapped in T.M.S because those register can be accessed indirectly using IDM_AR & IDM_DR. To use the indirect address mode, just 0x06 bytes are required for memory space. When target host system access Interrupt register(IR) of COMMON registers at the indirect address mode, it is processed as below: Host Write : Set IDM_AR to 0x0002, IR address (IDM_AR = 0x0002) Set IDM_DR to 0xFFFF (IDM_DR = 0xFFFF) Host Read : Set IDM_AR to 0x0002, IR address (IDM_AR = 0x0002) Read IDM_DR and save as Value (Value = IDM_DR) th The host interface mode of W5300 W5300 is decided according to the value of `IND' bit (0 bit) of MR. MR(0) = `0' => Direct address mode MR(0) = `1' => Indirect address mode The memory map of each address mode is as below: © Copyright 2008 WIZnet Co., Inc. All rights reserved. 22 BA + 0x0FE BA + 0x100 MR (Mode Reg) IR (Interrupt Reg) IMR (Interrupt Mask Reg) . . IDR (ID Reg) Reserved Target Host System BA + 0x1FE BA + 0x200 S0_MR (SOCKET0 Mode Reg) MemoryMapped I/O BA + 0x240 S1_MR BA + 0x280 S2_MR BA + 0x2C0 S3_MR BA + 0x300 S4_MR BA + 0x340 S5_MR BA + 0x380 S6_MR BA + 0x3C0 BA + 0x3FF High-performance Internet Connectivity Solution BA + 0x000 BA + 0x002 BA + 0x004 S7_MR Space (T.M.S) Mode Register Common Registers SOCKET Registers W5300 W5300 Direct Address Mode (MR(0) = `0') BA BA + 0x002 BA + 0x004 MR IDM_AR IDM_DR 0x000 0x002 0x004 Reserved IR IMR 0x0FE 0x100 0x1FE 0x200 IDR Reserved 0x240 S1_MR 0x280 S2_MR MemoryMapped 0x2C0 S3_MR Space 0x300 S4_MR (W.M.S) 0x340 S5_MR 0x380 S6_MR 0x3C0 0x3FF T.M.S S7_MR . S0_MR W5300 W5300 Internal Indirect Address Mode (MR(0) = `1') Fig 3. Memory Map © Copyright 2008 WIZnet Co., Inc. All rights reserved. 23 High-performance Internet Connectivity Solution 3. W5300 W5300 Registers W5300 W5300 register is composed of MR(to decide direct or indirect address mode), IDM_AR & IDM_DR(only used at the indirect address mode) and COMMON registers and SOCKET registers. MR, IDM_AR, and IDM_DR register are mapped in T.M.S. COMMON & SOCKET registers are mapped in T.M.S or W.M.S (W5300 W5300 internal Memory Space) according to address mode. All W5300 W5300 registers are 1Byte, 2Bytes, 4Bytes or 6Bytes. According to data bus width of target host system, the access is processed ­ 2bytes address offset at the 16bit data bus and 1 byte address offset at the 8bit data bus. When mapping W5300 W5300 registers in T.M.S, the physical T.M.S address of W5300 W5300 register is calculated as below. = Base Address of T.M.S + Address offset of W5300 W5300 Reg W5300 W5300 Physical Address of W5300 W5300 Reg The byte ordering of W5300 W5300 registers is big-endian ­ low address byte is used as the most significant byte. [Register Notation] MR : MR register MR0 : Low address register of MR (Address offset - 0x000 ), Most significant byte MR1 : High address register of MR (Address offset ­ 0x001), Least significant byte th th MR(15:5) : 11 bit (from 15 bit to 5 bit of MR register) th th MR(0) : 0 bit of MR register, 0 bit of MR1 th th MR(13) : 13 bit of MR register, 5 bit of MR0 th MR0(7) : 15 bit of MR register, Most significant bit of MR0 MR(DWB) : MR DWB bit (DWB : Bit Symbol) SHAR : Source Hardware Address Register ST SHAR0 : 1 address register of SHAR (Address offset ­ 0x008) nd SHAR1 : 2 address register of SHAR (Address offset ­ 0x009) rd SHAR2 : 3 address register of SHAR (Address offset ­ 0x00A) th SHAR3 : 4 address register of SHAR (Address offset ­ 0x00B) th SHAR4 : 5 Address register of SHAR (Address offset ­ 0x00C) th SHAR5 : 6 address register of SHAR (Address offset ­ 0x00D) © Copyright 2008 WIZnet Co., Inc. All rights reserved. 24 High-performance Internet Connectivity Solution 3.1 Mode Register Address offset Symbol Description 16Bit 8Bit 16Bit 8Bit 0x000 0x000 MR0 MR Mode Register 0x001 MR1 3.2 Indirect Mode Registers Address offset Symbol Description 16Bit 8Bit 16Bit 0x002 0x002 8Bit IDM_AR0 IDM_AR 0x003 0x004 0x004 Indirect Mode Address Register IDM_AR1 IDM_DR0 IDM_DR 0x005 Indirect Mode Data Register IDM_DR1 W5300 W5300 3.3 COMMON registers Address offset Symbol Description 16Bit 8Bit 16Bit 0x002 0x002 8Bit IR0 IR 0x003 0x004 0x004 Interrupt Register IR1 IMR0 IMR 0x005 Interrupt Mask Register IRM1 0x006 Reserved 0x006 0x007 0x008 0x008 SHAR0 0x009 0x00A Source Hardware Address Register SHAR SHAR1 0x00A SHAR2 SHAR2 0x00B 0x00C SHAR3 0x00C SHAR4 SHAR4 0x00D 0x00E SHAR5 0x00E Reserved 0x00F 0x010 0x010 GAR0 Gateway Address Register GAR 0x011 0x12 GAR1 0x012 GAR2 GAR2 0x013 GAR3 © Copyright 2008 WIZnet Co., Inc. All rights reserved. 25 High-performance Internet Connectivity Solution Address offset Symbol Description 16Bit 8Bit 16Bit 0x014 0x014 8Bit SUBR0 Subnet Mask Register SUBR 0x015 SUBR1 0x016 0x016 SUBR2 SUBR2 0x017 SUBR3 0x018 0x018 SIPR0 Source IP Address Register SIPR 0x019 SIPR1 0x01A 0x01A SIPR2 SIPR2 0x01B SIPR3 0x01C 0x01C RTR0 Retransmission Timeout-value Register RTR 0x01D RTR1 0x01E 0x01E RCR0 Reserved RCR1 Retransmission Retry-count Register RCR 0x01F TMSR0 Transmit Memory Size Register of SOCKET0 TMSR1 Transmit Memory Size Register of SOCKET1 TMSR2 Transmit Memory Size Register of SOCKET2 TMSR3 Transmit Memory Size Register of SOCKET3 TMSR4 Transmit Memory Size Register of SOCKET4 TMSR5 Transmit Memory Size Register of SOCKET5 TMSR6 Transmit Memory Size Register of SOCKET7 TMSR7 Transmit Memory Size Register of SOCKET 8 RMSR0 Receive Memory Size Register of SOCKET0 RMSR1 Receive Memory Size Register of SOCKET1 RMSR2 Receive Memory Size Register of SOCKET2 RMSR3 Receive Memory Size Register of SOCKET3 RMSR4 Receive Memory Size Register of SOCKET4 RMSR5 Receive Memory Size Register of SOCKET5 RMSR6 Receive Memory Size Register of SOCKET6 RMSR7 W5300 W5300 0x020 0x020 Receive Memory Size Register of SOCKET7 TMS01R TMS01R 0x021 0x022 0x022 TMS23R TMS23R 0x023 0x024 0x24 TMS45R TMS45R 0x025 0x026 0x26 TMS67R TMS67R 0x027 0x028 0x028 RMS01R RMS01R 0x029 0x02A 0x02A RMS23R RMS23R 0x02B 0x02C 0x02C RMS45R RMS45R 0x02D 0x02E 0x02E RMS67R RMS67R 0x02F 0x030 0x030 MTYPER0 Memory Block Type Register MTYPER 0x031 MTYPER1 0x032 0x032 PATR0 PPPoE Authentication Register PATR 0x033 PATR1 © Copyright 2008 WIZnet Co., Inc. All rights reserved. 26 High-performance Internet Connectivity Solution Address offset Symbol Description 16Bit 8Bit 16Bit 8Bit 0x034 Reserved 0x034 0x035 0x036 0x036 PTIMER0 Reserved PTIMER1 PPP LCP Request Time Register PTIMER 0x037 0x038 0x038 PMAGICR0 PMAGICR 0x039 PMAGICR1 0x03A PPP LCP Magic Number Register Reserved 0x03A 0x03B 0x03C 0x03C PSIDR0 PPP Session ID Register PSIDR 0x03D PSIDR1 0x03E Reserved 0x03E 0x03F PDHAR0 W5300 W5300 0x040 0x040 PPP Destination Hardware Address Register PDHAR 0x041 PDHAR1 0x042 0x042 PDHAR2 PDHAR2 0x043 PDHAR3 0x044 0x044 PDHAR4 PDHAR4 0x045 PDHAR5 0x046 Reserved 0x046 0x047 0x048 0x048 UIPR0 Unreachable IP Address Register UIPR 0x049 UIPR1 0x04A 0x04A UIPR2 UIPR2 0x04B UIPR3 0x04C 0x04C UPORT0 Unreachable Port Number Register UPORTR 0x04D UPORT1 0x04E 0x04E FMTUR0 Fragment MTU Register FMTUR 0x04F 0x050 FMTUR1 Reserved 0x050 0x051 : : 0x05E Reserved 0x5E 0x060 © Copyright 2008 WIZnet Co., Inc. All rights reserved. 27 High-performance Internet Connectivity Solution Address offset Symbol Description 16Bit 8Bit 16Bit 0x060 0x060 8Bit P0_BRDYR0 Reserved P0_BRDYR1 PIN "BRDY0" Configure Register P0_BRDYR 0x061 0x062 0x062 P0_BDPTHR0 PIN "BRDY0" Buffer Depth Register P0_BDPTHR 0x063 P0_BDPTHR1 0x064 0x064 P1_BRDYR0 Reserved P1_BRDYR1 PIN "BRDY1" Configure Register P1_BRDYR 0x065 0x066 0x066 P1_BDPTHR0 PIN "BRDY1" Buffer Depth Register P1_BDPTHR 0x067 P1_BDPTHR1 0x068 0x068 P1_BRDYR0 Reserved P2_BRDYR1 PIN "BRDY2" Configure Register P2_BRDYR 0x069 0x06A P2_BDPTHR0 PIN "BRDY2" Buffer Depth Register P2_BDPTHR 0x06B P2_BDPTHR1 0x06C 0x06C W5300 W5300 0x06A P3_BRDYR0 Reserved P3_BRDYR1 PIN "BRDY3" Configure Register P3_BRDYR 0x06D 0x06E 0x06E P3_BDPTHR0 PIN "BRDY3" Buffer Depth Register P3_BDPTHR 0x06F P3_BDPTHR1 0x070 Reserved 0x070 0x071 : : 0x0FC Reserved 0xFC 0x0FD 0x0FE 0xFE IDR0 W5300 W5300 ID Register IDR 0x0FF IDR1 © Copyright 2008 WIZnet Co., Inc. All rights reserved. 28 High-performance Internet Connectivity Solution 3.4 SOCKET registers Address offset Symbol Description 16Bit 8Bit 16Bit 0x200 0x200 8Bit S0_MR0 SOCKET0 Mode Register S0_MR 0x201 S0_MR1 0x202 0x202 S0_CR0 Reserved S0_CR1 SOCKET0 Command Register S0_IMR0 Reserved S0_IMR1 SOCKET0 Interrupt Mask Register S0_CR 0x203 0x204 0x204 S0_IMR 0x205 0x206 0x206 S0_IR0 Reserved S0_IR1 SOCKET0 Interrupt Register S0_IR 0x207 0x208 0x208 S0_SSR0 Reserved S0_SSR1 SOCKET0 SOCKET Status Register S0_SSR 0x209 S0_PORTR0 W5300 W5300 0x20A 0x20A SOCKET0 Source Port Register S0_PORTR 0x20B S0_PORTR1 0x20C 0x20C S0_DHAR0 SOCKET0 Destination Hardware S0_DHAR1 Address Register S0_DHAR 0x20D 0x20E 0x20E S0_DHAR2 S0_DHAR2 0x20F S0_DHAR3 0x210 0x210 S0_DHAR4 S0_DHAR4 0x211 S0_DHAR5 0x212 0x212 S0_DPORTR0 SOCKET0 Destination Port Register S0_DPORTR 0x213 S0_DPORTR1 0x214 0x214 S0_DIPR0 SOCKET0 Destination IP Address S0_DIPR1 Register S0_DIPR 0x215 0x216 0x216 S0_DIPR2 S0_DIPR2 0x217 S0_DIPR3 0x218 0x218 S0_MSSR0 SOCKET0 Maximum Segment Size S0_MSSR1 Register S0_MSSR 0x219 0x21A 0x21A S0_KPALVTR SOCKET0 Keep Alive Time Register S0_PROTOR SOCKET0 Protocol Number Register S0_PORTOR 0x21B 0x21C 0x21C S0_TOSR0 Reserved S0_TOSR1 SOCKET0 TOS Register S0_TTLR0 Reserved S0_TTLR1 SOCKET0 TTL Register S0_TOSR 0x21D 0x21E 0x21E S0_TTLR 0x21F © Copyright 2008 WIZnet Co., Inc. All rights reserved. 29 High-performance Internet Connectivity Solution Address offset Symbol Description 16Bit 8Bit 16Bit 0x220 0x220 8Bit S0_TX_WRSR0 Reserved S0_TX_WRSR1 SOCKET0 TX Write Size Register S0_TX_WRSR 0x221 0x222 0x222 S0_TX_WRSR2 S0_TX_WRSR2 0x223 S0_TX_WRSR3 0x224 0x224 S0_TX_FSR0 Reserved S0_TX_FSR1 SOCKET0 TX Free Size Register S0_TX_FSR 0x225 0x226 0x226 S0_TX_FSR2 S0_TX_FSR2 0x227 S0_TX_FSR3 0x228 0x228 S0_RX_RSR0 Reserved S0_RX_RSR1 SOCKET0 RX Receive Size Register S0_RX_RSR 0x229 0x22A S0_RX_RSR2 S0_RX_RSR2 0x22B S0_RX_RSR3 0x22C 0x22C W5300 W5300 0x22A S0_FRAGR0 Reserved S0_FRAGR1 SOCKET0 FLAG Register S0_FRAGR 0x22D 0x22E 0x22E S0_TX_FIFOR0 SOCKET0 TX FIFO Register S0_TX_FIFOR 0x22F S0_TX_FIFOR1 0x230 0x230 S0_RX_FIFOR0 SOCKET0 RX FIFO Register S0_RX_FIFOR 0x231 S0_RX_FIFOR1 0x232 Reserved 0x232 0x233 : : : : 0x23E Reserved 0x23E 0x23F © Copyright 2008 WIZnet Co., Inc. All rights reserved. 30 High-performance Internet Connectivity Solution Address offset Symbol Description 16Bit 8Bit 16Bit 0x240 0x240 8Bit S1_MR0 SOCKET1 Mode Register S1_MR 0x241 S1_MR1 0x242 0x242 S1_CR0 Reserved S1_CR1 SOCKET1 Command Register S1_IMR0 Reserved S1_IMR1 SOCKET1 Interrupt Mask Register S1_CR 0x243 0x244 0x244 S1_IMR 0x245 0x246 0x246 S1_IR0 Reserved S1_IR1 SOCKET1 Interrupt Register S1_IR 0x247 0x248 0x248 S1_SSR0 Reserved S1_SSR1 SOCKET1 SOCKET Status Register S1_SSR 0x249 0x24A S1_PORTR0 SOCKET1 Source Port Register S1_PORTR 0x24B S1_PORTR1 0x24C 0x24C S1_DHAR0 SOCKET1 Destination Hardware S1_DHAR1 Address Register S1_DHAR 0x24D 0x24E 0x24E W5300 W5300 0x24A S1_DHAR2 S1_DHAR2 0x24F S1_DHAR3 0x250 0x250 S1_DHAR4 S1_DHAR4 0x251 S1_DHAR5 0x252 0x252 S1_DPORTR0 SOCKET1 Destination Port Register S1_DPORTR 0x253 S1_DPORTR1 0x254 0x254 S1_DIPR0 SOCKET1 Destination IP Address S1_DIPR1 Register S1_DIPR 0x255 0x256 0x256 S1_DIPR2 S1_DIPR2 0x257 S1_DIPR3 0x258 0x258 S1_MSSR0 SOCKET1 Maximum Segment Size S1_MSSR1 Register S1_MSSR 0x259 0x25A 0x25A S1_KPALVTR SOCKET1 Keep Alive Time Register S1_PROTOR SOCKET1 Protocol Number Register S1_PORTOR 0x25B 0x25C 0x25C S1_TOSR0 Reserved S1_TOSR1 SOCKET1 TOS Register S1_TTLR0 Reserved S1_TTLR1 SOCKET1 TTL Register S1_TOSR 0x25D 0x25E 0x25E S1_TTLR 0x25F © Copyright 2008 WIZnet Co., Inc. All rights reserved. 31 High-performance Internet Connectivity Solution Address offset Symbol Description 16Bit 8Bit 16Bit 0x260 0x260 8Bit S1_TX_WRSR0 Reserved S1_TX_WRSR1 SOCKET1 TX Write Size Register S1_TX_WRSR 0x261 0x262 0x262 S1_TX_WRSR2 S1_TX_WRSR2 0x263 S1_TX_WRSR3 0x264 0x264 S1_TX_FSR0 Reserved S1_TX_FSR1 SOCKET1 TX Free Size Register S1_TX_FSR 0x265 0x266 0x266 S1_TX_FSR2 S1_TX_FSR2 0x267 S1_TX_FSR3 0x268 0x268 S1_RX_RSR0 Reserved S1_RX_RSR1 SOCKET1 RX Receive Size Register S1_RX_RSR 0x269 0x26A S1_RX_RSR2 S1_RX_RSR2 0x26B S1_RX_RSR3 0x26C 0x26C W5300 W5300 0x26A S1_FRAGR0 Reserved S1_FRAGR1 SOCKET1 IP FLAG Field Register S1_FRAGR 0x26D 0x26E 0x26E S1_TX_FIFOR0 SOCKET1 TX FIFO Register S1_TX_FIFOR 0x26F S1_TX_FIFOR1 0x270 0x270 S1_RX_FIFOR0 SOCKET1 RX FIFO Register S1_RX_FIFOR 0x271 S1_RX_FIFOR1 0x272 Reserved 0x272 0x273 : : : : 0x27E Reserved 0x27E 0x27F © Copyright 2008 WIZnet Co., Inc. All rights reserved. 32 High-performance Internet Connectivity Solution Address offset Symbol Description 16Bit 8Bit 16Bit 0x280 0x280 8Bit S2_MR0 SOCKET2 Mode Register S2_MR 0x281 S2_MR1 0x282 0x282 S2_CR0 Reserved S2_CR1 SOCKET2 Command Register S2_IMR0 Reserved S2_IMR1 SOCKET2 Interrupt Mask Register S2_CR 0x283 0x284 0x284 S2_IMR 0x285 0x286 0x286 S2_IR0 Reserved S2_IR1 SOCKET2 Interrupt Register S2_IR 0x287 0x288 0x288 S2_SSR0 Reserved S2_SSR1 SOCKET2 SOCKET Status Register S2_SSR 0x289 0x28A S2_PORTR0 SOCKET2 Source Port Register S2_PORTR 0x28B S2_PORTR1 0x28C 0x28C S2_DHAR0 SOCKET2 Destination Hardware S2_DHAR1 Address Register S2_DHAR 0x28D 0x28E 0x28E W5300 W5300 0x28A S2_DHAR2 S2_DHAR2 0x28F S2_DHAR3 0x290 0x290 S2_DHAR4 S2_DHAR4 0x291 S2_DHAR5 0x292 0x292 S2_DPORTR0 SOCKET2 Destination Port Register S2_DPORTR 0x293 S2_DPORTR1 0x294 0x294 S2_DIPR0 SOCKET2 Destination IP Address S2_DIPR1 Register S2_DIPR 0x295 0x296 0x296 S2_DIPR2 S2_DIPR2 0x297 S2_DIPR3 0x298 0x298 S2_MSSR0 SOCKET2 Maximum Segment Size S2_MSSR1 Register S2_MSSR 0x299 0x29A 0x29A S2_KPALVTR SOCKET2 Keep Alive Time Register S2_PROTOR SOCKET2 Protocol Number Register S2_PORTOR 0x29B 0x29C 0x29C S2_TOSR0 Reserved S2_TOSR1 SOCKET2 TOS Register S2_TTLR0 Reserved S2_TTLR1 SOCKET2 TTL Register S2_TOSR 0x29D 0x29E 0x29E S2_TTLR 0x29F © Copyright 2008 WIZnet Co., Inc. All rights reserved. 33 High-performance Internet Connectivity Solution Address offset Symbol Description 16Bit 8Bit 16Bit 0x2A0 0x2A0 8Bit S2_TX_WRSR0 Reserved S2_TX_WRSR1 SOCKET2 TX Write Size Register S2_TX_WRSR 0x2A1 0x2A2 0x2A2 S2_TX_WRSR2 S2_TX_WRSR2 0x2A3 S2_TX_WRSR3 0x2A4 0x2A4 S2_TX_FSR0 Reserved S2_TX_FSR1 SOCKET2 TX Free Size Register S2_TX_FSR 0x2A5 0x2A6 0x2A6 S2_TX_FSR2 S2_TX_FSR2 0x2A7 S2_TX_FSR3 0x2A8 0x2A8 S2_RX_RSR0 Reserved S2_RX_RSR1 SOCKET2 RX Receive Size Register S2_RX_RSR 0x2A9 0x2AA S2_RX_RSR2 S2_RX_RSR2 0x2AB S2_RX_RSR3 0x2AC 0x2AC W5300 W5300 0x2AA S2_FRAGR0 Reserved S2_FRAGR1 SOCKET2 IP FLAG Field Register S2_FRAGR 0x2AD 0x2AE 0x2AE S2_TX_FIFOR0 SOCKET2 TX FIFO Register S2_TX_FIFOR 0x2AF S2_TX_FIFOR1 0x2B0 0x2B0 S2_RX_FIFOR0 SOCKET2 RX FIFO Register S2_RX_FIFOR 0x2B1 S2_RX_FIFOR1 0x2B2 Reserved 0x2B2 0x2B3 : : : : 0x2BE Reserved 0x2BE 0x2BF © Copyright 2008 WIZnet Co., Inc. All rights reserved. 34 High-performance Internet Connectivity Solution Address offset Symbol Description 16Bit 8Bit 16Bit 0x2C0 0x2C0 8Bit S3_MR0 SOCKET3 Mode Register S3_MR 0x2C1 S3_MR1 0x2C2 0x2C2 S3_CR0 Reserved S3_CR1 SOCKET3 Command Register S3_IMR0 Reserved S3_IMR1 SOCKET3 Interrupt Mask Register S3_CR 0x2C3 0x2C4 0x2C4 S3_IMR 0x2C5 0x2C6 0x2C6 S3_IR0 Reserved S3_IR1 SOCKET3 Interrupt Register S3_IR 0x2C7 0x2C8 0x2C8 S3_SSR0 Reserved S3_SSR1 SOCKET3 SOCKET Status Register S3_SSR 0x2C9 0x2CA S3_PORTR0 SOCKET3 Source Port Register S3_PORTR 0x2CB S3_PORTR1 0x2CC 0x2CC S3_DHAR0 SOCKET3 Destination Hardware S3_DHAR1 Address Register S3_DHAR 0x2CD 0x2CE 0x2CE W5300 W5300 0x2CA S3_DHAR2 S3_DHAR2 0x2CF S3_DHAR3 0x2D0 0x2D0 S3_DHAR4 S3_DHAR4 0x2D1 S3_DHAR5 0x2D2 0x2D2 S3_DPORTR0 SOCKET3 Destination Port Register S3_DPORTR 0x2D3 S3_DPORTR1 0x2D4 0x2D4 S3_DIPR0 SOCKET3 Destination IP Address S3_DIPR1 Register S3_DIPR 0x2D5 0x2D6 0x2D6 S3_DIPR2 S3_DIPR2 0x2D7 S3_DIPR3 0x2D8 0x2D8 S3_MSSR0 SOCKET3 Maximum Segment Size S3_MSSR1 Register S3_MSSR 0x2D9 0x2DA 0x2DA S3_KPALVTR SOCKET3 Keep Alive Time Register S3_PROTOR SOCKET3 Protocol Number Register S3_PORTOR 0x2DB 0x2DC 0x2DC S3_TOSR0 Reserved S3_TOSR1 SOCKET3 TOS Register S3_TTLR0 Reserved S3_TTLR1 SOCKET3 TTL Register S3_TOSR 0x2DD 0x2DE 0x2DE S3_TTLR 0x2DF © Copyright 2008 WIZnet Co., Inc. All rights reserved. 35 High-performance Internet Connectivity Solution Address offset Symbol Description 16Bit 8Bit 16Bit 0x2E0 0x2E0 8Bit S3_TX_WRSR0 Reserved S3_TX_WRSR1 SOCKET3 TX Write Size Register S3_TX_WRSR 0x2E1 0x2E2 0x2E2 S3_TX_WRSR2 S3_TX_WRSR2 0x2E3 S3_TX_WRSR3 0x2E4 0x2E4 S3_TX_FSR0 Reserved S3_TX_FSR1 SOCKET3 TX Free Size Register S3_TX_FSR 0x2E5 0x2E6 0x2E6 S3_TX_FSR2 S3_TX_FSR2 0x2E7 S3_TX_FSR3 0x2E8 0x2E8 S3_RX_RSR0 Reserved S3_RX_RSR1 SOCKET3 RX Receive Size Register S3_RX_RSR 0x2E9 0x2EA S3_RX_RSR2 S3_RX_RSR2 0x2EB S3_RX_RSR3 0x2EC 0x2EC W5300 W5300 0x2EA S3_FRAGR0 Reserved S3_FRAGR1 SOCKET3 IP FLAG Field Register S3_FRAGR 0x2ED 0x2EE 0x2EE S3_TX_FIFOR0 SOCKET3 TX FIFO Register S3_TX_FIFOR 0x2EF S3_TX_FIFOR1 0x2F0 0x2F0 S3_RX_FIFOR0 SOCKET3 RX FIFO Register S3_RX_FIFOR 0x2F1 S3_RX_FIFOR1 0x2F2 Reserved 0x2F2 0x2F3 : : : : 0x2FE Reserved 0x2FE 0x2FF © Copyright 2008 WIZnet Co., Inc. All rights reserved. 36 High-performance Internet Connectivity Solution Address offset Symbol Description 16Bit 8Bit 16Bit 0x300 0x300 8Bit S4_MR0 SOCKET4 Mode Register S4_MR 0x301 S4_MR1 0x302 0x302 S4_CR0 Reserved S4_CR1 SOCKET4 Command Register S4_IMR0 Reserved S4_IMR1 SOCKET4 Interrupt Mask Register S4_CR 0x303 0x304 0x304 S4_IMR 0x305 0x306 0x306 S4_IR0 Reserved S4_IR1 SOCKET4 Interrupt Register S4_IR 0x307 0x308 0x308 S4_SSR0 Reserved S4_SSR1 SOCKET4 SOCKET Status Register S4_SSR 0x309 0x30A S4_PORTR0 SOCKET4 Source Port Register S4_PORTR 0x30B S4_PORTR1 0x30C 0x30C S4_DHAR0 SOCKET4 Destination Hardware S4_DHAR1 Address Register S4_DHAR 0x30D 0x30E 0x30E W5300 W5300 0x30A S4_DHAR2 S4_DHAR2 0x30F S4_DHAR3 0x310 0x310 S4_DHAR4 S4_DHAR4 0x311 S4_DHAR5 0x312 0x312 S4_DPORTR0 SOCKET4 Destination Port Register S4_DPORTR 0x313 S4_DPORTR1 0x314 0x314 S4_DIPR0 SOCKET4 Destination IP Address S4_DIPR1 Register S4_DIPR 0x315 0x316 0x316 S4_DIPR2 S4_DIPR2 0x317 S4_DIPR3 0x318 0x318 S4_MSSR0 SOCKET4 Maximum Segment Size S4_MSSR1 Register S4_MSSR 0x319 0x31A 0x31A S4_KPALVTR SOCKET4 Keep Alive Time Register S4_PROTOR SOCKET4 Protocol Number Register S4_PORTOR 0x31B 0x31C 0x31C S4_TOSR0 Reserved S4_TOSR1 SOCKET4 TOS Register S4_TTLR0 Reserved S4_TTLR1 SOCKET4 TTL Register S4_TOSR 0x31D 0x31E 0x31E S4_TTLR 0x31F © Copyright 2008 WIZnet Co., Inc. All rights reserved. 37 High-performance Internet Connectivity Solution Address offset Symbol Description 16Bit 8Bit 16Bit 0x320 0x320 8Bit S4_TX_WRSR0 Reserved S4_TX_WRSR1 SOCKET4 TX Write Size Register S4_TX_WRSR 0x321 0x322 0x322 S4_TX_WRSR2 S4_TX_WRSR2 0x323 S4_TX_WRSR3 0x324 0x324 S4_TX_FSR0 Reserved S4_TX_FSR1 SOCKET4 TX Free Size Register S4_TX_FSR 0x325 0x326 0x326 S4_TX_FSR2 S4_TX_FSR2 0x327 S4_TX_FSR3 0x328 0x328 S4_RX_RSR0 Reserved S4_RX_RSR1 SOCKET4 RX Receive Size Register S4_RX_RSR 0x329 0x32A S4_RX_RSR2 S4_RX_RSR2 0x32B S4_RX_RSR3 0x32C 0x32C W5300 W5300 0x32A S4_FRAGR0 Reserved S4_FRAGR1 SOCKET4 IP FLAG Field Register S4_FRAGR 0x32D 0x32E 0x32E S4_TX_FIFOR0 SOCKET4 TX FIFO Register S4_TX_FIFOR 0x32F S4_TX_FIFOR1 0x330 0x330 S4_RX_FIFOR0 SOCKET4 RX FIFO Register S4_RX_FIFOR 0x331 S4_RX_FIFOR1 0x332 Reserved 0x332 0x333 : : : : 0x33E Reserved 0x33E 0x33F © Copyright 2008 WIZnet Co., Inc. All rights reserved. 38 High-performance Internet Connectivity Solution Address offset Symbol Description 16Bit 8Bit 16Bit 0x340 0x340 8Bit S5_MR0 SOCKET5 Mode Register S5_MR 0x341 S5_MR1 0x342 0x342 S5_CR0 Reserved S5_CR1 SOCKET5 Command Register S5_IMR0 Reserved S5_IMR1 SOCKET5 Interrupt Mask Register S5_CR 0x343 0x344 0x344 S5_IMR 0x345 0x346 0x346 S5_IR0 Reserved S5_IR1 SOCKET5 Interrupt Register S5_IR 0x347 0x348 0x348 S5_SSR0 Reserved S5_SSR1 SOCKET5 SOCKET Status Register S5_SSR 0x349 0x34A S5_PORTR0 SOCKET5 Source Port Register S5_PORTR 0x34B S5_PORTR1 0x34C 0x34C S5_DHAR0 SOCKET5 Destination Hardware S5_DHAR1 Address Register S5_DHAR 0x34D 0x34E 0x34E W5300 W5300 0x34A S5_DHAR2 S5_DHAR2 0x34F S5_DHAR3 0x350 0x350 S5_DHAR4 S5_DHAR4 0x351 S5_DHAR5 0x352 0x352 S5_DPORTR0 SOCKET5 Destination Port Register S5_DPORTR 0x353 S5_DPORTR1 0x354 0x354 S5_DIPR0 SOCKET5 Destination IP Address S5_DIPR1 Register S5_DIPR 0x355 0x356 0x356 S5_DIPR2 S5_DIPR2 0x357 S5_DIPR3 0x358 0x358 S5_MSSR0 SOCKET5 Maximum Segment Size S5_MSSR1 Register S5_MSSR 0x359 0x35A 0x35A S5_KPALVTR SOCKET5 Keep Alive Time Register S5_PROTOR SOCKET5 Protocol Number Register S5_PORTOR 0x35B 0x35C 0x35C S5_TOSR0 Reserved S5_TOSR1 SOCKET5 TOS Register S5_TTLR0 Reserved S5_TTLR1 SOCKET5 TTL Register S5_TOSR 0x35D 0x35E 0x35E S5_TTLR 0x35F © Copyright 2008 WIZnet Co., Inc. All rights reserved. 39 High-performance Internet Connectivity Solution Address offset Symbol Description 16Bit 8Bit 16Bit 0x360 0x360 8Bit S5_TX_WRSR0 Reserved S5_TX_WRSR1 SOCKET5 TX Write Size Register S5_TX_WRSR 0x361 0x362 0x362 S5_TX_WRSR2 S5_TX_WRSR2 0x363 S5_TX_WRSR3 0x364 0x364 S5_TX_FSR0 Reserved S5_TX_FSR1 SOCKET5 TX Free Size Register S5_TX_FSR 0x365 0x366 0x366 S5_TX_FSR2 S5_TX_FSR2 0x367 S5_TX_FSR3 0x368 0x368 S5_RX_RSR0 Reserved S5_RX_RSR1 SOCKET5 RX Receive Size Register S5_RX_RSR 0x369 0x36A S5_RX_RSR2 S5_RX_RSR2 0x36B S5_RX_RSR3 0x36C 0x36C W5300 W5300 0x36A S5_FRAGR0 Reserved S5_FRAGR1 SOCKET5 IP FLAG Field Register S5_FRAGR 0x36D 0x36E 0x36E S5_TX_FIFOR0 SOCKET5 TX FIFO Register S5_TX_FIFOR 0x36F S5_TX_FIFOR1 0x370 0x370 S5_RX_FIFOR0 SOCKET5 RX FIFO Register S5_RX_FIFOR 0x371 S5_RX_FIFOR1 0x372 Reserved 0x372 0x373 : : : : 0x37E Reserved 0x37E 0x37F © Copyright 2008 WIZnet Co., Inc. All rights reserved. 40 High-performance Internet Connectivity Solution Address offset Symbol Description 16Bit 8Bit 16Bit 0x380 0x380 8Bit S6_MR0 SOCKET6 Mode Register S6_MR 0x381 S6_MR1 0x382 0x382 S6_CR0 Reserved S6_CR1 SOCKET6 Command Register S6_IMR0 Reserved S6_IMR1 SOCKET6 Interrupt Mask Register S6_CR 0x383 0x384 0x384 S6_IMR 0x385 0x386 0x386 S6_IR0 Reserved S6_IR1 SOCKET6 Interrupt Register S6_IR 0x387 0x388 0x388 S6_SSR0 Reserved S6_SSR1 SOCKET6 SOCKET Status Register S6_SSR 0x389 0x38A S6_PORTR0 SOCKET6 Source Port Register S6_PORTR 0x38B S6_PORTR1 0x38C 0x38C S6_DHAR0 SOCKET6 Destination Hardware S6_DHAR1 Address Register S6_DHAR 0x38D 0x38E 0x38E W5300 W5300 0x38A S6_DHAR2 S6_DHAR2 0x38F S6_DHAR3 0x390 0x390 S6_DHAR4 S6_DHAR4 0x391 S6_DHAR5 0x392 0x392 S6_DPORTR0 SOCKET6 Destination Port Register S6_DPORTR 0x393 S6_DPORTR1 0x394 0x394 S6_DIPR0 SOCKET6 Destination IP Address S6_DIPR1 Register S6_DIPR 0x395 0x396 0x396 S6_DIPR2 S6_DIPR2 0x397 S6_DIPR3 0x398 0x398 S6_MSSR0 SOCKET6 Maximum Segment Size S6_MSSR1 Register S6_MSSR 0x399 0x39A 0x39A S6_KPALVTR SOCKET6 Keep Alive Time Register S6_PROTOR SOCKET6 Protocol Number Register S6_PORTOR 0x39B 0x39C 0x39C S6_TOSR0 Reserved S6_TOSR1 SOCKET6 TOS Register S6_TTLR0 Reserved S6_TTLR1 SOCKET6 TTL Register S6_TOSR 0x39D 0x39E 0x39E S6_TTLR 0x39F © Copyright 2008 WIZnet Co., Inc. All rights reserved. 41 High-performance Internet Connectivity Solution Address offset Symbol Description 16Bit 8Bit 16Bit 0x3A0 0x3A0 8Bit S6_TX_WRSR0 Reserved S6_TX_WRSR1 SOCKET6 TX Write Size Register S6_TX_WRSR 0x3A1 0x3A2 0x3A2 S6_TX_WRSR2 S6_TX_WRSR2 0x3A3 S6_TX_WRSR3 0x3A4 0x3A4 S6_TX_FSR0 Reserved S6_TX_FSR1 SOCKET6 TX Free Size Register S6_TX_FSR 0x3A5 0x3A6 0x3A6 S6_TX_FSR2 S6_TX_FSR2 0x3A7 S6_TX_FSR3 0x3A8 0x3A8 S6_RX_RSR0 Reserved S6_RX_RSR1 SOCKET6 RX Receive Size Register S6_RX_RSR 0x3A9 0x3AA S6_RX_RSR2 S6_RX_RSR2 0x3AB S6_RX_RSR3 0x3AC 0x3AC W5300 W5300 0x3AA S6_FRAGR0 Reserved S6_FRAGR1 SOCKET6 IP FLAG Field Register S6_FRAGR 0x3AD 0x3AE 0x3AE S6_TX_FIFOR0 SOCKET6 TX FIFO Register S6_TX_FIFOR 0x3AF S6_TX_FIFOR1 0x3B0 0x3B0 S6_RX_FIFOR0 SOCKET6 RX FIFO Register S6_RX_FIFOR 0x3B1 S6_RX_FIFOR1 0x3B2 Reserved 0x3B2 0x3B3 : : : : 0x3BE Reserved 0x3BE 0x3BF © Copyright 2008 WIZnet Co., Inc. All rights reserved. 42 High-performance Internet Connectivity Solution Address offset Symbol Description 16Bit 8Bit 16Bit 0x3C0 0x3C0 8Bit S7_MR0 SOCKET7 Mode Register S7_MR 0x3C1 S7_MR1 0x3C2 0x3C2 S7_CR0 Reserved S7_CR1 SOCKET7 Command Register S7_IMR0 Reserved S7_IMR1 SOCKET7 Interrupt Mask Register S7_CR 0x3C3 0x3C4 0x3C4 S7_IMR 0x3C5 0x3C6 0x3C6 S7_IR0 Reserved S7_IR1 SOCKET7 Interrupt Register S7_IR 0x3C7 0x3C8 0x3C8 S7_SSR0 Reserved S7_SSR1 SOCKET7 SOCKET Status Register S7_SSR 0x3C9 0x3CA S7_PORTR0 SOCKET7 Source Port Register S7_PORTR 0x3CB S7_PORTR1 0x3CC 0x3CC S7_DHAR0 SOCKET7 Destination Hardware S7_DHAR1 Address Register S7_DHAR 0x3CD 0x3CE 0x3CE W5300 W5300 0x3CA S7_DHAR2 S7_DHAR2 0x3CF S7_DHAR3 0x3D0 0x3D0 S7_DHAR4 S7_DHAR4 0x3D1 S7_DHAR5 0x3D2 0x3D2 S7_DPORTR0 SOCKET7 Destination Port Register S7_DPORTR 0x3D3 S7_DPORTR1 0x3D4 0x3D4 S7_DIPR0 SOCKET7 Destination IP Address S7_DIPR1 Register S7_DIPR 0x3D5 0x3D6 0x3D6 S7_DIPR2 S7_DIPR2 0x3D7 S7_DIPR3 0x3D8 0x3D8 S7_MSSR0 SOCKET7 Maximum Segment Size S7_MSSR1 Register S7_MSSR 0x3D9 0x3DA 0x3DA S7_KPALVTR SOCKET7 Keep Alive Time Register S7_PROTOR SOCKET7 Protocol Number Register S7_PORTOR 0x3DB 0x3DC 0x3DC S7_TOSR0 Reserved S7_TOSR1 SOCKET7 TOS Register S7_TTLR0 Reserved S7_TTLR1 SOCKET7 TTL Register S7_TOSR 0x3DD 0x3DE 0x3DE S7_TTLR 0x3DF © Copyright 2008 WIZnet Co., Inc. All rights reserved. 43 High-performance Internet Connectivity Solution Address offset Symbol Description 16Bit 8Bit 16Bit 0x3E0 0x3E0 8Bit S7_TX_WRSR0 Reserved S7_TX_WRSR1 SOCKET7 TX Write Size Register S7_TX_WRSR 0x3E1 0x3E2 0x3E2 S7_TX_WRSR2 S7_TX_WRSR2 0x3E3 S7_TX_WRSR3 0x3E4 0x3E4 S7_TX_FSR0 Reserved S7_TX_FSR1 SOCKET7 TX Free Size Register S7_TX_FSR 0x3E5 0x3E6 0x3E6 S7_TX_FSR2 S7_TX_FSR2 0x3E7 S7_TX_FSR3 0x3E8 0x3E8 S7_RX_RSR0 Reserved S7_RX_RSR1 SOCKET7 RX Receive Size Register S7_RX_RSR 0x3E9 0x3EA S7_RX_RSR2 S7_RX_RSR2 0x3EB S7_RX_RSR3 0x3EC 0x3EC W5300 W5300 0x3EA S7_FRAGR0 Reserved S7_FRAGR1 SOCKET7 IP FLAG Field Register S7_FRAGR 0x3ED 0x3EE 0x3EE S7_TX_FIFOR0 SOCKET7 TX FIFO Register S7_TX_FIFOR 0x3EF S7_TX_FIFOR1 0x3F0 0x3F0 S7_RX_FIFOR0 SOCKET7 RX FIFO Register S7_RX_FIFOR 0x3F1 S7_RX_FIFOR1 0x3F2 Reserved 0x3F2 0x3F3 : : : : 0x3FE Reserved 0x3FE 0x3FF © Copyright 2008 WIZnet Co., Inc. All rights reserved. 44 High-performance Internet Connectivity Solution 4. Register Description [Notation] 1. Symbol(Name)[R/W,RO,WO][AO1/AO2][Reset] Symbol : Register Symbol Name : Register Name R/W : Read/Write RO : Read Only WO : Write Only AO1 : Physical Address of W5300 W5300 reg. in T.M.S (For Direct address mode) AO2 : Address Offset of W5300 W5300 reg. in W.M.S (For Indirect address mode) Reset : Reset value For convenience, we assume the Base Address(BA) of T.M.S is 0x08000, and BA of the Physical Address of W5300 W5300 Register is 0x08000. W5300 W5300 2. Pn_ : Buffer Ready PIN n("BRDYn") register prefix Pn_BRDYR(BRDYn Configure register, 0