W49F002/B/U/N 1K/10K W49F002 W49F002B W49F002U W49F002N 07FFF 05FFF 03FFF 3C000

256K × 8 CMOS FLASH MEMORY GENERAL DESCRIPTION The W49F002/B/U/N is a 2-megabit, 5-volt only CMOS flash memory organized as

Preliminary W49F002/B/U/N W49F002/B/U/N 256K × 8 CMOS FLASH MEMORY GENERAL DESCRIPTION The W49F002/B/U/N W49F002/B/U/N is a 2-megabit, 5-volt only CMOS flash memory organized as 256K × 8 bits. The device can be programmed and erased in-system with a standard 5V power supply. A 12-volt VPP is not required. The unique cell architecture of the W49F002/B/U/N W49F002/B/U/N results in fast program/erase operations with extremely low current consumption (compared to other comparable 5-volt flash memory products). The device can also be programmed and erased using standard EPROM programmers. FEATURES · · Single 5-volt operations: - 5-volt Read - 5-volt Erase - 5-volt Program · · Automatic program and erase timing with internal VPP generation End of program or erase detection - Toggle bit - Data polling Fast Program operation: - Byte-by-Byte programming: 50 µS (max.) · Latched address and data · Fast Erase operation: 100 mS (typ.) · TTL compatible I/O · Fast Read access time: 70/120 nS · JEDEC standard byte-wide pinouts · Endurance: 1K/10K 1K/10K cycles (typ.) · Available packages: 32-pin DIP and 32-pin · Ten-year data retention · Hardware data protection · One 16K byte Boot Block with Lockout protection · Two 8K byte Parameter Blocks · Two Main Memory Blocks (96K, 128K) Bytes TSOP and 32-pin-PLCC · · Low power consumption - Active current: 25 mA (typ.) - Standby current: 20 µA (typ.) -1- This document has four part numbers: W49F002 W49F002 - Bottom Boot Block with Reset Pin. W49F002B W49F002B - Bottom Boot Block without Reset Pin W49F002U W49F002U - Top Boot Block with Reset Pin. W49F002N W49F002N - Top Boot Block without Reset Pin. Publication Release Date: June 1999 Revision A1 Preliminary W49F002/B/U/N W49F002/B/U/N PIN CONFIGURATIONS *RESET/NC BLOCK DIAGRAM 32 1 VDD VSS CE OE WE RESET VDD A16 2 31 WE A15 3 30 A12 4 29 5 28 A13 A6 6 27 A8 A5 7 A4 8 26 A9 25 32-pin DIP A11 MAIN MEMORY BLOCK2 128K BYTES . A17 9 24 OE A2 10 23 DECODER A10 A1 11 22 CE A0 12 21 DQ7 DQ0 13 20 DQ6 DQ1 14 19 DQ5 DQ2 15 18 DQ4 GND 16 17 DQ3 A 1 5 A 1 6 * / R E S E T / N C 4 3 2 BOOT BLOCK 16K BYTES W49F002 W49F002(B) CE OE WE RESET A 1 7 5 29 6 28 A13 27 A8 26 A9 25 A11 A0 A5 7 A4 8 A3 9 A2 10 24 OE A1 11 23 A10 A0 12 22 CE DQ0 13 21 DQ7 32-pin PLCC . DECODER . A17 14 15 16 17 18 19 20 W49F002U W49F002U(N) D D G Q Q N 1 2 D A16 A15 A12 A7 A6 A5 A4 D Q 3 D Q 4 D Q 5 08000 07FFF 07FFF 06000 05FFF 05FFF 04000 03FFF 03FFF 00000 BOOT BLOCK 16K BYTES PARAMETER BLOCK1 8K BYTES PARAMETER BLOCK2 8K BYTES MAIN MEMORY BLOCK1 96K BYTES MAIN MEMORY BLOCK2 128K BYTES DQ0 . . DQ7 3FFFF 3C000 3C000 3BFFF 3A000 3A000 39FFF 39FFF 38000 37FFF 37FFF 20000 1FFFF 00000 D Q 6 1 2 32 31 30 3 4 5 8 9 10 OUTPUT BUFFER CONTROL A14 A6 * RESET/NC 20000 1FFFF 1 32 31 30 V / D W D E A7 6 7 MAIN MEMORY BLOCK1 96K BYTES PARAMETER BLOCK2 8K BYTES PARAMETER BLOCK1 8K BYTES 3FFFF VDD VSS A 1 2 WE V DD . . DQ7 A0 . A3 A11 A9 A8 A13 A14 A17 DQ0 A17 A14 A7 OUTPUT BUFFER CONTROL 29 28 27 32-pin TSOP 11 12 26 25 24 23 22 21 20 19 PIN DESCRIPTION OE A10 SYMBOL CE DQ7 DQ6 DQ5 DQ4 DQ3 GND DQ2 DQ1 DQ0 A0 A1 A2 A3 PIN NAME RESET Reset A0-A17 A0-A17 Address Inputs DQ0-DQ7 Data Inputs/Outputs 14 15 16 18 17 CE Chip Enable OE Output Enable WE 13 Write Enable VDD Power Supply GND *Note: This pin is a NC on the W29F002B/N W29F002B/N Ground NC -2- No Connection Preliminary W49F002/B/U/N W49F002/B/U/N FUNCTIONAL DESCRIPTION Read Mode The read operation of the W49F002/B/U/N W49F002/B/U/N is controlled by CE and OE, both of which have to be low for the host to obtain data from the outputs. CE is used for device selection. When CE is high, the chip is de-selected and only standby power will be consumed. OE is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either CE or OE is high. Refer to the timing waveforms for further details. Reset Operation The reset input pin can be used in some application. When RESET pin is at high state, the device is in normal operation mode. When RESET pin is at low state, it will halts the device and all outputs are at high impedance state. As the high state re-asserted to the RESET pin, the device will return to read or standby mode, it depends on the control signals. When the system drives the RESET pin low for at least a period of 500 nS, the device immediately terminates any operation in progress duration of the RESET pulse. The other function for RESET pin is temporary reset the boot block. By applying the 12V to RESET pin, the boot block can be reprogrammed even though the boot block lockout function is enabled. Boot Block Operation There is one 16K-byte boot block in this device, which can be used to store boot code. It is located in the first 16K bytes of the memory with the address range from 0000(hex) to 3FFF(hex) for the W49F002 W49F002(B) while in the last 16K bytes with the address range of the boot block is 3C000 3C000(hex) to 3FFFF(hex) for the W49F002U W49F002U(N). See Command Code sequence for Boot Block Lockout Enable for the specific code. Once this feature is set the data for the designated block cannot be erased or programmed (programming lockout); other memory locations can be changed with the regular programming method. Once the boot block programming lockout feature is activated, the chip erase function can no longer erase the boot block. There is one condition that the lockout feature can be overridden. Just apply 12V to RESET pin, the lockout feature will temporarily be inactivated and the block can be erased/programmed. Once the RESET pin return to TTL level, the lockout feature will be activated again. In order to detect whether the boot block feature is set on the 16K-bytes block, users can perform software command code sequence: enter the product identification mode (see Command Codes for Identification/Boot Block Lockout Detection for specific code), and then read from address "0002 (hex)". If the DQ0 of output data is "1," the boot block programming lockout feature is activated; if the DQ0 of output data is "0 ," the lockout feature is inactivated and the block can be erased/programmed. To return to normal operation, perform a three-byte command code sequence (or an alternate singlebyte command) to exit the identification mode. For the specific code, see Command Code for Identification/Boot Block Lockout Detection. Chip Erase Operation The chip-erase mode can be initiated by a six-byte command code sequence. After the command loading cycle, the device enters the internal chip erase mode, which is automatically timed and will be -3- Publication Release Date: June 1999 Revision A1 Preliminary W49F002/B/U/N W49F002/B/U/N completed as fast as 100 mS (typical). The host system is not required to provide any control or timing during this operation. The entire memory array will be erased to FF hex. by the chip erase operation if the boot block programming lockout feature is not activated. Once the boot block lockout feature is activated, the whole chip erase function will erase the two main memory blocks and the two parameter blocks but not the boot block. The device will automatically return to normal read mode after the erase operation. Data polling and/or Toggle Bits can be used to detect end of erase cycle. Sector Erase Operation There are four sectors: two main memory blocks and two parameters blocks which can be erased individually by initiating a six-byte command code sequence. Sector address is latched on the falling edge of WE signal in the sixth cycle while the data input "30(hex)" is latched at the rising edge of WE in this cycle. After the command loading cycle, the device enters the internal sector erase mode, which is automatically timed and will be completed as fast as 100 mS (typical). The host system does not require to provide any control or timing during this operation. The device will automatically return to normal read mode after the erase operation. Data polling and/or Toggle Bits can be used to detect the end of erase cycle. When different sector address is loaded in the sixth cycle for sector erase command, the correspondent sectors will be erased automatically. For example, when the sector address is set to be 01000(hex) for W49F002B W49F002B during the sector erase command, then nothing will happen and the device will go back to read mode after 100nS. For detail sector address vs corresponding multiple sectors to be erased information, please refer to the Table of Command Definition. Program Operation The W49F002/B/U/N W49F002/B/U/N is programmed on a byte-by-byte basis. Program operation can only change logical data "1" to logical data "0". The erase operation (changed entire data in two main memory blocks and two parameter blocks and/or boot block from "0" to "1") is needed before programming. The program operation is initiated by a 4-byte command code sequence (see Command Codes for Byte Programming). The device will internally enter the program operation immediately after the byteprogram command is entered. The internal program timer will automatically time-out (50 µS max. TBP). Once completed, the device returns to normal read mode. Data polling and/or Toggle Bits can be used to detect end of program cycle. Hardware Data Protection The integrity of the data stored in the W49F002/B/U/N W49F002/B/U/N is also hardware protected in the following ways: (1) Noise/Glitch Protection: A WE pulse of less than 15 nS in duration will not initiate a write cycle. (2) VDD Power Up/Down Detection: The programming operation is inhibited when VDD is less than 2.5V typical. (3) Write Inhibit Mode: Forcing OE low, CE high, or WE high will inhibit the write operation. This prevents inadvertent writes during power-up or power-down periods. (4) VDD power-on delay: When VDD has reached its sense level, the device will automatically time-out 5 mS before any write (erase/program) operation. Data Polling (DQ7)- Write Status Detection The W49F002/B/U/N W49F002/B/U/N includes a data polling feature to indicate the end of a program or erase cycle. When the W49F002/B/U/N W49F002/B/U/N is in the internal program or erase cycle, any attempt to read DQ7 of the last byte loaded will receive the complement of the true data. Once the program or erase cycle is -4- Preliminary W49F002/B/U/N W49F002/B/U/N completed, DQ7 will show the true data. Note that DQ7 will show logical "0" during the erase cycle, and become logical "1" or true data when the erase cycle has been completed. Toggle Bit (DQ6)- Write Status Detection In addition to data polling, the W49F002/B/U/N W49F002/B/U/N provides another method for determining the end of a program cycle. During the internal program or erase cycle, any consecutive attempts to read DQ6 will produce alternating 0's and 1's. When the program or erase cycle is completed, this toggling between 0's and 1's will stop. The device is then ready for the next operation. Product Identification The product ID operation outputs the manufacturer code and device code. Programming equipment automatically matches the device with its proper erase and programming algorithms. The manufacturer and device codes can be accessed by software or hardware operation. In the software access mode, a three-byte (or JEDEC 3-byte) command sequence can be used to access the product ID. A read from address 0000H 0000H outputs the manufacturer code DA(hex). A read from address 0001H 0001H outputs the device code 25(hex) for the W49F002/B W49F002/B and 0B(hex) for the W49F002U/N W49F002U/N. The product ID operation can be terminated by a three-byte command code sequence or an alternate one-byte command code sequence (see Command Definition table). In the hardware access mode, access to the product ID is activated by forcing CE and OE low, WE high, and raising A9 to 12 volts. TABLE OF OPERATING MODES Operating Mode Selection (VHH = 12V ± 5%) MODE PINS ADDRESS DQ. RESET CE OE WE Read VIH VIL VIL VIH AIN Dout Write VIH VIL VIH VIL AIN Din Standby VIH VIH X X X High Z Write Inhibit VIH X VIL X X High Z/DOUT VIH X X VIH X High Z/DOUT Output Disable VIH X VIH X X High Z Reset Mode VIL X X X X High Z Product ID VIH VIL VIL VIH A0 = VIL; A1-A17 A1-A17 = VIL; A9 = VHH Manufacturer Code DA (Hex) VIH VIL VIL VIH A0 = VIH; A1-A17 A1-A17 = VIL; A9 = VHH Device Code 25 (Hex) for the W49F002/B W49F002/B Device Code 0B (Hex) for the W49F002U/N W49F002U/N -5- Publication Release Date: June 1999 Revision A1 Preliminary W49F002/B/U/N W49F002/B/U/N TABLE OF COMMAND DEFINITION(1) NO. OF COMMAND DESCRIPTION 1ST CYCLE 2ND CYCLE 3RD CYCLE 4TH CYCLE 5TH CYCLE 6TH CYCLE Cycles Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Read Chip Erase Sector Erase Byte Program Boot Block Lockout Product ID Entry Product ID Exit (2) 1 6 6 4 6 3 3 AIN DOUT 5555 AA 5555 AA 5555 AA 5555 AA 5555 AA 5555 AA Product ID Exit (2) 1 XXXX F0 2AAA 2AAA 2AAA 2AAA 2AAA 2AAA 55 55 55 55 55 55 5555 5555 5555 5555 5555 5555 Notes: 1. Address Format: A14-A0 A14-A0 (Hex); Data Format: DQ7-DQ0 (Hex) 2. Either one of the two Product ID Exit commands can be used. 3. SA means: Sector Address (For the W49F002 W49F002(B) If SA is within 00000 to 03FFF 03FFF (Boot Block address range) Nothing will happen and the device will go back to read mode after 100nS. If SA is within 04000 to 05FFF 05FFF (Parameter Block1 address range) This command will erase PB1. If SA is within 06000 to 07FFF 07FFF (Parameter Block2 address range) This command will erase PB2. If SA is within 08000 to 1FFFF (Main Memory Block1 address range) This command will erase MMB1, PB1 and PB2. If SA is within 20000 to 3FFFF (Main Memory Block2 address range) This command will erase MMB2. (For the W49F002U W49F002U(N) If SA is within 3C000 3C000 to 3FFFF (Boot Block address range) Nothing will happen and the device will go back to read mode after 100nS. If SA is within 3A000 3A000 to 3BFFF (Parameter Block1 address range) This command will erase PB1. If SA is within 38000 to 39FFF 39FFF (Parameter Block2 address range) This command will erase PB2. If SA is within 20000 to 37FFF 37FFF (Main Memory Block1 address range) This commend will erase MMB1, PB1 and PB2. If SA is within 00000 to 1FFFF (Main Memory Block2 address range) This commend will erase MMB2. -6- 80 80 A0 80 90 F0 5555 5555 AIN 5555 AA 2AAA 55 AA 2AAA 55 DIN AA 2AAA 55 5555 10 SA(3) 30 5555 40 Preliminary W49F002/B/U/N W49F002/B/U/N Command Codes for Byte Program COMMAND SEQUENCE ADDRESS DATA 0 Write 5555H 5555H AAH 1 Write 2AAAH 55H 2 Write 5555H 5555H A0H 3 Write Programmed-address Programmed-data Byte Program Flow Chart Byte Program Command Flow Load data AA to address 5555 Load data 55 to address 2AAA Load data A0 to address 5555 Load data Din to programmedaddress Pause 50 µS Exit Notes for software program code: Data Format: DQ7-DQ0 (Hex) Address Format: A14-A0 A14-A0 (Hex) -7- Publication Release Date: June 1999 Revision A1 Preliminary W49F002/B/U/N W49F002/B/U/N Command Codes for Chip Erase BYTE SEQUENCE ADDRESS 1 Write 5555H 5555H AAH 2 Write 2AAAH 55H 3 Write 5555H 5555H 80H 4 Write 5555H 5555H AAH 5 Write 2AAAH 55H 6 Write 5555H 5555H 10H Chip Erase Acquisition Flow Load data AA to address 5555 Load data 55 to address 2AAA Load data 80 to address 5555 Load data AA to address 5555 Load data 55 to address 2AAA Load data 10 to address 5555 Pause 1 Sec. Exit Notes for chip erase: Data Format: DQ7-DQ0 (Hex) Address Format: A14-A0 A14-A0 (Hex) -8- DATA Preliminary W49F002/B/U/N W49F002/B/U/N Command Codes for Sector Erase BYTE SEQUENCE ADDRESS DATA 1 Write 5555H 5555H AAH 2 Write 2AAAH 55H 3 Write 5555H 5555H 80H 4 Write 5555H 5555H AAH 5 Write 2AAAH 55H 6 Write SA* 30H Sector Erase Acquisition Flow Load data AA to address 5555 Load data 55 to address 2AAA Load data 80 to address 5555 Load data AA to address 5555 Load data 55 to address 2AAA Load data 30 to address SA* Pause 1 Sec. Exit Notes for chip erase: Data Format: DQ7-DQ0 (Hex) Address Format: A14-A0 A14-A0 (Hex) SA : For details, see the page 6 . -9- Publication Release Date: June 1999 Revision A1 Preliminary W49F002/B/U/N W49F002/B/U/N Command Codes for Product Identification and Boot Block Lockout Detection BYTE SEQUENCE SOFTWARE PRODUCT IDENTIFICATION/BOOT BLOCK LOCKOUT DETECTION EXIT (7) ALTERNATE PRODUCT (6) IDENTIFICATION/BOOT BLOCK LOCKOUT DETECTION ENTRY ADDRESS DATA ADDRESS DATA 1 Write 5555 AA 5555H 5555H AAH 2 Write 2AAA 55 2AAAH 55H 3 Write 5555 90 5555H 5555H F0H Pause 10 µS Pause 10 µS Software Product Identification and Boot Block Lockout Detection Acquisition Flow Product Identification Entry (1) Load data AA to address 5555 Product Identification and Boot Block Lockout Detection Mode (3) Product Identification Exit(7) Load data AA to address 5555 (2) Load data 55 to address 2AAA Read address = 0000 data = DA Load data 90 to address 5555 Read address = 0001 data = 25-W49F002/B 25-W49F002/B data = 0B-W49F002U/N 0B-W49F002U/N Pause 10 µS Read address = 0002 data =in DQ0= "1" / "0" (2) (4) Load data 55 to address 2AAA Load data F0 to address 5555 Pause 10 µS (5) Normal Mode Notes for software product identification/boot block lockout detection: (1) Data Format: DQ7-DQ0 (Hex); Address Format: A14-A0 A14-A0 (Hex) (2) A1-A17 A1-A17 = VIL; manufacture code is read for A0 = VIL; device code is read for A0 = VIH. (3) The device does not remain in identification and boot block lockout detection mode if power down. (4) If the output data in DQ0= " 1 " the boot block programming lockout feature is activated; if the output data in DQ0= " 0 ," the lockout feature is inactivated and the boot block can be programmed. (5) The device returns to standard operation mode. (6) Optional 1-byte cycle (write F0 hex at XXXX address) can be used to exit the product identification/boot block lockout detection. - 10 - Preliminary W49F002/B/U/N W49F002/B/U/N Command Codes for Boot Block Lockout Enable BYTE SEQUENCE BOOT BLOCK LOCKOUT FEATURE SET Address Data 1 Write 5555H 5555H AAH 2 Write 2AAAH 55H 3 Write 5555H 5555H 80H 4 Write 5555H 5555H AAH 5 Write 2AAAH 55H 6 Write 5555H 5555H 40H Pause 1 Sec. Boot Block Lockout Enable Acquisition Flow Boot Block Lockout Feature Set Flow Load data AA to address 5555 Load data 55 to address 2AAA Load data 80 to address 5555 Load data AA to address 5555 Load data 55 to address 2AAA Load data 40 to address 5555 Pause 1 Sec. Exit Notes for boot block lockout enable: Data Format: DQ7-DQ0 (Hex) Address Format: A14-A0 A14-A0 (Hex) - 11 - Publication Release Date: June 1999 Revision A1 Preliminary W49F002/B/U/N W49F002/B/U/N DC CHARACTERISTICS Absolute Maximum Ratings PARAMETER RATING UNIT -0.5 to +7.0 V 0 to +70 °C -65 to +150 °C D.C. Voltage on Any Pin to Ground Potential except OE -0.5 to VDD +1.0 V Transient Voltage (