W25P222A MO-136 MO-108 A0-A15 I/O1-I/O32 I/O9-I/O16 I/O17-I/O24 I/O25-I/O32 - Datasheet Archive

 

64K × 32 BURST PIPELINED HIGH-SPEED CMOS STATIC RAM GENERAL DESCRIPTION The W25P222A is a high-speed, low-power,

 

Preliminary W25P222A W25P222A 64K × 32 BURST PIPELINED HIGH-SPEED CMOS STATIC RAM GENERAL DESCRIPTION The W25P222A W25P222A is a high-speed, low-power, synchronous-burst pipelined CMOS static RAM organized as 65,536 × 32 bits that operates on a single 3.3-volt power supply. A built-in two-bit burst address counter supports both PentiumTM burst mode and linear burst mode. The mode to be executed is controlled by the LBO pin. Pipelining or non-pipelining of the data outputs is controlled by the FT pin. A snooze mode reduces power dissipation. The W25P222A W25P222A supports both 2T/2T mode and 2T/1T mode, which can be selected by pin 42. The default mode is 2T/1T, with pin 42 low. To switch to 2T/2T mode, bias pin 42 to VDDQ. The state of pin 42 should not be changed after power up. The 2T/2T mode will sustain one cycle of valid data output in a burst read cycle when the device is deselected by CE2/ CE3 . This mode supports 3-1-1-11-1-1-1 in a two-bank, back-to-back burst read cycle. On the other hand, the 2T/1T mode disables data output within one cycle in a burst read cycle when the device is deselected by CE2/ CE3 . In this mode, the device supports only 3-1-1-1-2-1-1-1 in a two-bank, back-to-back burst read cycle. FEATURES · · · · · · · Synchronous operation High-speed access time: 4/4.5 nS (max.) Single +3.3V power supply Individual byte write capability 3.3V LVTTL compatible I/O Clock-controlled and registered input Asynchronous output enable · · · · · Pipelined/non-pipelined data output capability Supports snooze mode (low-power state) Internal burst counter supports Intel burst mode & linear burst mode Supports both 2T/2T & 2T/1T mode Packaged in 100-pin QFP or TQFP BLOCK DIAGRAM A(15:0) INPUT REGISTER 64K X 32 CORE ARRAY CLK CE(3:1) GW BWE BW(4:1) OE CONTROL LOGIC DATA I/O REGISTER REGISTER I/O(32:1) ADSC ADSP ADV LBO FT ZZ MS -1- Publication Release Date: August 1997 Revision A1 Preliminary W25P222A W25P222A PIN CONFIGURATION / / / C C B B A A E E W W 6 7 1 2 4 3 NC I/O 17 I/O 18 VDDQ VSSQ I/O 19 I/O 20 I/O 21 I/O 22 VSSQ VDDQ I/O 23 I/O 24 /FT VDD NC VSS I/O 25 I/O 26 VDDQ VSSQ I/O 27 I/O 28 I/O 29 I/O 30 VSSQ VDDQ I/O 31 I/O 32 NC / B W 2 / B W 1 / C V V C / E D S L G 3 D S K W / B / W O E E / A D S C / A D S P / A D A A V 8 9 1 9 9 9 9 9 9 9 9 9 9 8 8 8 8 8 8 8 8 8 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 80 79 2 0 78 3 77 4 76 5 75 6 74 7 73 8 72 9 71 10 11 70 12 69 68 13 14 67 66 15 65 16 17 64 63 18 62 19 61 20 60 21 59 22 58 23 24 57 56 25 55 26 54 27 28 53 52 29 30 3 3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 4 4 5 51 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 100-pin TQFP MO-136 MO-136 QFP MO-108 MO-108 / A A A A A A N N V V M N A A A A A A N L 5 4 3 2 1 0 C C S D S C 1 1 1 1 1 1 C B S D 0 1 2 3 4 5 O -2- NC I/O 16 I/O 15 VDDQ VSSQ I/O 14 I/O 13 I/O 12 I/O 11 VSSQ VDDQ I/O 10 I/O 9 VSS NC VDD ZZ I/O 8 I/O 7 VDDQ VSSQ I/O 6 I/O 5 I/O 4 I/O 3 VSSQ VDDQ I/O 2 I/O 1 NC Preliminary W25P222A W25P222A PIN DESCRIPTION SYMBOL TYPE DESCRIPTION Input, Synchronous Host Address I/O, Synchronous Data Inputs/Outputs Input, Clock Processor Host Bus Clock CE1 , CE2, CE3 Input, Synchronous Chip Enables GW Input, Synchronous Global Write BWE Input, Synchronous Byte Write Enable from Cache Controller BW1 - BW4 Input, Synchronous Host Bus Byte Enables used with BWE OE Input, Asynchronous Output Enable Input ADV Input, Synchronous Internal Burst Address Counter Advance ADSC Input, Synchronous Address Status from chip set ADSP Input, Synchronous Address Status from CPU ZZ Input, Asynchronous Snooze Pin for Low-power State, internally pulled low FT Input, Static Connected to VSSQ: Device operates in flow-through (non-pipelined) mode. A0-A15 A0-A15 I/O1-I/O32 I/O1-I/O32 CLK Connected to VDDQ or unconnected: Device operates in piplined mode. LBO Input, Static Lower Address Burst Order Connected to VSSQ: Device operates in linear mode. Connected to VDDQ or unconnected: Device is in nonlinear mode. MS Input, Static Mode Select for 2T/2T or 2T/1T When unconnected or pulled low, device is in 2T/1T mode; if pulled high (VDDQ), device enters 2T/2T mode. VDDQ I/O Power Supply VSSQ I/O Ground VDD Power Supply VSS Ground NC No Connection -3- Publication Release Date: August 1997 Revision A1 Preliminary W25P222A W25P222A TRUTH TABLE ADDRESS USED CE1 CE2 CE3 ADSP ADSC ADV OE DATA WRITE* Unselected No 1 X X X 0 X X Hi-Z X Unselected No 0 X 1 0 X X X Hi-Z X Unselected No 0 0 X 0 X X X Hi-Z X Unselected No 0 X 1 1 0 X X Hi-Z X CYCLE Unselected No 0 0 X 1 0 X X Hi-Z X Begin Read External 0 1 0 0 X X X Hi-Z X Begin Read External 0 1 0 1 0 X X Hi-Z Read Continue Read Next X X X 1 1 0 1 Hi-Z Read Continue Read Next X X X 1 1 0 0 D-Out Read Continue Read Next 1 X X X 1 0 1 Hi-Z Read Continue Read Next 1 X X X 1 0 0 D-Out Read Suspend Read Current X X X 1 1 1 1 Hi-Z Read Suspend Read Current X X X 1 1 1 0 D-Out Read Suspend Read Current 1 X X X 1 1 1 Hi-Z Read Suspend Read Current 1 X X X 1 1 0 D-Out Read Begin Write Current X X X 1 1 1 X Hi-Z Write Begin Write Current 1 X X X 1 1 X Hi-Z Write Begin Write External 0 1 0 1 0 X X Hi-Z Write Continue Write Next X X X 1 1 0 X Hi-Z Write Continue Write Next 1 X X X 1 0 X Hi-Z Write Suspend Write Current X X X 1 1 1 X Hi-Z Write Suspend Write Current 1 X X X 1 1 X Hi-Z Write Notes: 1. For a detailed definition of read/write, see the Write Table below. 2. An "X" means don't care, "1" means logic high, and "0" means logic low. 3. The OE pin enables the data output but is not synchronous with the clock. All signals of the SRAM are sampled synchronous to the bus clock except for the OE pin. 4. On a write cycle that follows a read cycle, OE must be inactive prior to the start of the write cycle to allow write data to set the SRAM. OE must also disable the output buffer prior to the end of a write cycle to ensure the SRAM data hold timings are met. -4- up Preliminary W25P222A W25P222A FUNCTIONAL DESCRIPTION The W25P222A W25P222A is a synchronous-burst pipelined SRAM designed for use in high-end personal computers. It supports two burst address sequences for IntelTM systems and linear mode, which can be controlled by the LBO pin. The burst cycles are initiated by ADSP or ADSC and the burst counter is incremented whenever ADV is sampled low. The device can also be switched to nonpipelined mode if necessary. Burst Address Sequence INTEL SYSTEM (LBO = VDDQ) LINEAR MODE (LBO = VSSQ) A[1:0] A[1:0] A[1:0] A[1:0] A[1:0] A[1:0] A[1:0] A[1:0] External Start Address 00 01 10 11 00 01 10 11 Second Address 01 00 11 10 01 10 11 00 Third Address 10 11 00 01 10 11 00 01 Fourth Address 11 10 01 00 11 00 01 10 The device supports several types of write mode operations. BWE and BW [4:1] support individual byte writes. The BE [7:0] signals can be directly connected to the SRAM BW [4:1]. The GW signal is used to override the byte enable signals and allows the cache controller to write all bytes to the SRAM, no matter what the byte write enable signals are. The various write modes are indicated in the Write Table below. Note that in pipelined mode, the byte write enable signals are not latched by the SRAM with addresses but with data. In pipelined mode, the cache controller must ensure the SRAM latches both data and valid byte enable signals from the processor. WRITE TABLE READ/WRITE FUNCTION GW BWE BW4 BW3 BW2 BW1 Read 1 1 X X X X Read 1 0 1 1 1 1 Write byte 1 I/O1-I/O8 1 0 1 1 1 0 Write byte 2 I/O9-I/O16 I/O9-I/O16 1 0 1 1 0 1 Write byte 2, byte 1 1 0 1 1 0 0 Write byte 3 I/O17-I/O24 I/O17-I/O24 1 0 1 0 1 1 Write byte 3, byte 1 1 0 1 0 1 0 Write byte 3, byte 2 1 0 1 0 0 1 Write byte 3, byte 2, byte 1 1 0 1 0 0 0 Write byte 4 I/O25-I/O32 I/O25-I/O32 1 0 0 1 1 1 Write byte 4, byte 1 1 0 0 1 1 0 -5- Publication Release Date: August 1997 Revision A1 Preliminary W25P222A W25P222A Write Table, continued READ/WRITE FUNCTION GW BWE BW4 BW3 BW2 BW1 Write byte 4, byte 2 1 0 0 1 0 1 Write byte 4, byte 2, byte 1 1 0 0 1 0 0 Write byte 4, byte 3 1 0 0 0 1 1 Write byte 4, byte 3, byte 1 1 0 0 0 1 0 Write byte 4, byte 3, byte 2 1 0 0 0 0 1 Write all bytes I/O1-I/O32 I/O1-I/O32 1 0 0 0 0 0 Write all bytes I/O1-I/O32 I/O1-I/O32 0 X X X X X The ZZ state is a low-power state in which the device consumes less power than in the unselected mode. Enabling the ZZ pin for a fixed period of time will force the SRAM into the ZZ state. Pulling the ZZ pin low for a set period of time will wake up the SRAM again. While the SRAM is in ZZ mode, data retention is guaranteed, but the chip will not monitor any input signal except for the ZZ pin. In the unselected mode, on the other hand, all the input signals are monitored. ABSOLUTE MAXIMUM RATINGS PARAMETER RATING UNIT Core Supply Voltage to Vss -0.5 to 4.6 V I/O Supply Voltage to Vss -0.5 to 4.6 V VSSQ -0.5 to VDDQ +0.5 V 1.0 W -65 to 150 °C 0 to +70 °C Input/Output to VSSQ Potential Allowable Power Dissipation Storage Temperaure Operating Temperature Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device. -6- Preliminary W25P222A W25P222A OPERATING CHARACTERISTICS (VDD/VDDQ = 3.15V to 3.6V, VSS/VSSQ = 0V, TA = 0 to 70° C) PARAMETER SYM. TEST CONDITIONS MIN. TYP . MAX. UNIT Input Low Voltage VIL - -0.5 - +0.8 V Input High Voltage VIH - +2.0 - VDD +0.3 V Input Leakage Current ILI VIN = VSSQ to VDDQ -10 - +10 µA Output Leakage Current ILO VI/O = VSSQ to VDDQ, and data I/O pins in high-Z state defined in truth table -10 - + 10 µA Output Low Voltage VOL IOL = +8.0 mA - - 0.4 V Output High Voltage VOH IOH = -4.0 mA 2.4 - - V Operating Current IDD TCYC min., I/O = 0 mA - - 250 mA Standby Current ISB Unselected mode defined in truth table, VIN, VIO = VIH (min.) /VIL (max.) TCYC min. - - 80 mA ZZ Mode Current IZZ ZZ mode, TCYC min. - - 5 mA Note: Typical characteristics are measured at VDD = 3.3V, TA = 25° C. CAPACITANCE (VDD = 3.3V, TA = 25° C, f = 1 MHz) PARAMETER SYM. CONDITIONS MAX. UNIT Input Capacitance CIN VIN = 0V 6 pF Input/Output Capacitance CI/O VOUT = 0V 8 pF Note: These parameters are sampled but not 100% tested. AC TEST CONDITIONS PARAMETER CONDITIONS Input Pulse Levels 0V to 3V Input Rise and Fall Times 2 nS Input and Output Timing Reference Level 1.5V Output Load CL = 30 pF, IOH/IOL = -4 mA/8 mA -7- Publication Release Date: August 1997 Revision A1 Preliminary W25P222A W25P222A AC TEST LOADS AND WAVEFORM R1 320 ohm RL = 50 ohm 3.3V VL = 1.5V OUTPUT 5 pF OUTPUT 30 pF Including Jig and Scope Zo = 50 ohm Including Jig and Scope R2 350 ohm (For TKHZ, TKLZ, TOHZ, TOLZ, measurement) 3.0V 90% 90% 10% 10% 0V 2 nS 2 nS AC TIMING CHARACTERISTICS (VDD/VDDQ = 3.15V to 3.6V, VSS/VSSQ = 0V, TA = 0 to 70° C, all timings measured in pipelined mode) PARAMETER SYM. W25P222A-4 W25P222A-4 W25P222A-4A W25P222A-4A MIN. MAX. MIN. UNIT MAX. Add. Setup Time TAS 2.0 - 2.0 - nS Add. Hold Time TAH 1.0 - 1.0 - nS Write Data Setup Time TDS 2.0 - 2.0 - nS Write Data Hold Time TDH 1.0 - 1.0 - nS ADV Setup Time TADVS 2.0 - 2.0 - nS ADV Hold Time TADVH 1.0 - 1.0 - nS ADSP Setup Time TADSS 2.0 - 2.0 - nS ADSP Hold Time TADSH 1.0 - 1.0 - nS ADSC Setup Time TADCS 2.0 - 2.0 - nS ADSC Hold Time TADCH 1.0 - 1.0 - nS CE1 , CE2, CE3 Setup Time TCES 2.0 - 2.0 - nS CE1 , CE2, CE3 Hold Time TCEH 1.0 - 1.0 - nS GW , BWE X Setup Time TWS 2.0 - 2.0 - nS GW , BWE X Hold Time TWH 1.0 - 1.0 - nS -8- NOTES Preliminary W25P222A W25P222A AC Timing Characteristics, continued PARAMETER SYM. W25P222A-4 W25P222A-4 W25P222A-4A W25P222A-4A MIN. MAX. MIN. UNIT NOTES MAX. Clock Cycle Time TCYC 7.5 - 10 - nS Clock High Pulsh Width TKH 3.0 - 4 - nS Clock Low Pulse Width TKL 3.0 - 4 - nS Clock to Output Valid TKQ - 4 - 4.5 nS Clock to Output High-Z TKHZ 1.5 7.5 1.5 10 nS 1 Clock to Output Low-Z TKLZ 0 - 0 - nS 1 Clock to Output Invalid TKX 1.5 - 1.5 - nS 1 Output Enable to Output Valid TOE - 4 - 4.5 nS Output Enable to Output High-Z TOHZ - 4 - 4.5 nS 1 Output Enable to Output Low-Z TOLZ 0 - 0 - nS 1 Output Enable to Output Invalid TOX 0 - 0 - nS ZZ Standby Time TZZS - 100 - 100 nS 2 ZZ Recover Time TZZR 100 - 100 - nS 3 Notes: 1. These parameters are sampled but not 100% tested 2. In the ZZ mode, the SRAM will enter a low-power state. In this mode, data retention is guaranteed and the clock is active. 3. ADSC and ADSP should not be accessed for at least 100 nS after chip leaves ZZ mode. 4. Configuration signals LBO and FT are static and should not be changed during operation. -9- Publication Release Date: August 1997 Revision A1 Preliminary W25P222A W25P222A TIMING WAVEFORMS Read Cycle Timing Pipelined Read Single Read Unselected Burst Read TCYC CLK TADSS TKH T KL TADSH ADSP is blocked by CE1 inactive ADSP TADCS TADCH ADSC initiated read ADSC T ADVS TADVH Suspend Burst ADV TAS A[15:0] TAH RD1 RD3 RD2 TWS TWH TWS TWH GW BWE BW[4:1] T CES TCEH TCES TCEH TCES TCEH CE1 masks ADSP CE1 CE2 and CE3 only sampled with ADSP or ADSC Unselected with CE2 CE2 CE3 TOE TOHZ OE TOX TOLZ Data-Out High-Z 1a TKX 2a T KX 2b 2c 2d 3a T KLZ TKHZ TKQ Data-In High-Z DON'T CARE UNDEFINED - 10 - Preliminary W25P222A W25P222A Timing Waveforms, continued Write Cycle Timing Single Write TCYC Burst Write Write Unselected CLK T KH TKL TADSS T ADSH ADSP is blocked by CE1 inactive ADSP TADCS TADCH TADVS TADVH ADSC initiated write ADSC ADV ADV must be inactive for ADSP write T AS T AH A[15:0] WR2 WR1 TWS T WH TWS T WH TWS WR3 GWE allows processor address (and BE=BW) to be pipelined during a writeback TWH GW BWE WR1 BW[4:1] TCES TCEH TCES WR3 T CEH TCES WR2 TCEH CE1 masks ADSP CE1 CE2 and CE3 only sampled with ADSP or ADSC Unselected with CE2 CE2 CE3 OE Data-Out High-Z T DS TDH Data-In High-Z 1a BW[4:1] are applied only to first cycle of WR2 2a 2b 2c 2d 3a DON'T CARE UNDEFINED - 11 - Publication Release Date: August 1997 Revision A1 Preliminary W25P222A W25P222A Timing Waveforms, continued Read/Write Cycle Timing Single Write T CYC Single Read Burst Read Unselected CLK TADSS TKH T KL TADSH ADSP is blocked by CE1 inactive ADSP TADCS TADCH ADSC initiated read ADSC TADVS TADVH Suspend Burst ADV T AS A[15:0] T AH RD1 RD2 WR1 TWS T WH TWS T WH GW BWE TWS TWH WR1 BW[4:1] TCES TCEH TCES TCEH TCES TCEH CE1 masks ADSP CE1 CE2 and CE3 only sampled with ADSP or ADSC CE2 Unselected with CE3 CE3 TOE T OHZ OE T OH T OLZ Data-Out High-Z 1a TKLZ 2a TKHZ T KQ Data-In TKX High-Z TDSTDH 1a DON'T CARE UNDEFINED - 12 - 2b 2c 2d T KHZ Preliminary W25P222A W25P222A Timing Waveforms, continued ZZ and RD Timing Single Read Read Snooze -with Data Retention TCYC CLK TADSS TKH TKL TADSH ADSP ADSC TADVS TADVH ADV TAS A[15:0] TAH RD1 RD2 TWS TWH TWS TWH TWS TWH GW BWE BW[4:1] RD TCES TCES TCEH TCES RD RD TCEH TCEH CE1 CE2 CE3 TOE TOHZ OE TOH TOLZ Data-Out High-Z 1a TKLZ TKQ Data-In TKX TKHZ High-Z TZZS TZZR ZZ DON'T CARE UNDEFINED - 13 - Publication Release Date: August 1997 Revision A1 Preliminary W25P222A W25P222A Timing Waveforms, continued Dual-bank Burst Read Cycle CLK Select Bank 1 Select Bank 0 ADSP ADSC ADV Read 2 Read 1 A[31:3] GW BWE BW[4:1] CE1 CE[3:2] Bank 0 Active NonActive CE[3:2] Bank 1 NonActive Active OE D[63:0] Bank 0 1a 1b 1c D[63:0] Bank 1 1d 2a DON'T CARE UNDEFINED - 14 - 2b 2c 2d Preliminary W25P222A W25P222A ORDERING INFORMATION PART NO. ACCESS TIME (nS) OPERATING CURRENT MAX. (mA) STANDBY CURRENT MAX. (mA) 4 250 80 100-pin QFP W25P222AF-4A W25P222AF-4A 4.5 250 80 100-pin QFP W25P222AD-4 W25P222AD-4 4 250 80 100-pin TQFP 4.5 250 80 100-pin TQFP W25P222AF-4 W25P222AF-4 W25P222AD-4A W25P222AD-4A PACKAGE Notes: 1. Winbond reserves the right to make changes to its products without prior notice. 2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure. - 15 - Publication Release Date: August 1997 Revision A1 Preliminary W25P222A W25P222A PACKAGE DIMENSIONS 100-pin QFP HD D Symbol A A1 A2 b c D E e HD HE L L1 y E HE e Dimension in inches Dimension in mm Min. Nom. Max. Min. Nom. Max. 0.014 0.018 0.25 0.101 0.107 0.01 0.113 2.57 2.72 0.35 2.87 0.45 0.008 0.012 0.016 0.20 0.30 0.40 0.004 0.006 0.008 0.10 0.15 0.20 0.547 0.551 0.555 13.90 14.00 14.10 20.00 20.10 0.783 0.787 0.791 19.90 0.020 0.026 0.032 0.669 0.677 0.685 17.00 17.20 0.905 0.913 0.921 23.00 23.20 23.40 0.025 0.031 0.037 0.80 0.95 0.498 0.65 0.65 1.60 0.063 0.003 0 0.802 17.40 7 0.08 7 0 Notes: b 1. Dimensions D & E do not include interlead flash. 2. Dimension b does not include dambar protrusion/intrusion. 3. Controlling dimension: Millimeters 4. General appearance spec. should be based on final visual inspection spec. C A2 A1 See Detail F Seating Plane L y L1 100-pin TQFP HD D Symbol A A1 A2 b c D E e HD HE L L1 y E HE Dimension in inches Dimension in mm Min. Nom. Max. Min. Nom. Max. 0.002 0.004 0.006 0.05 0.053 0.055 0.057 1035 1.40 0.10 1.45 0.15 0.009 0.013 0.015 0.22 0.32 0.38 0.004 0.006 0.008 0.10 0.15 0.20 0.547 0.551 0.555 13.90 14.00 14.10 20.00 20.10 0.783 0.787 0.791 19.90 0.020 0.026 0.032 0.626 0.630 0.634 15.90 16.00 16.10 0.862 0.866 0.870 21.90 22.00 22.10 0.018 0.024 0.030 0.60 0.498 0.65 0.45 0.75 1.00 0.039 0.003 0 0.802 7 0.08 0 7 Notes: e 1. Dimensions D & E do not include interlead flash. 2. Dimension b does not include dambar protrusion/intrusion. 3. Controlling dimension: Millimeters 4. General appearance spec. should be based on final visual inspection spec. b C A2 A1 See Detail F Seating Plane y L L1 - 16 - Preliminary W25P222A W25P222A Headquarters Winbond Electronics (H.K.) Ltd. Winbond Electronics North America Corp. Rm. 803, World Trade Square, Tower II, Winbond Memory Lab. No. 4, Creation Rd. III, 123 Hoi Bun Rd., Kwun Tong, Science-Based Industrial Park, Winbond Microelectronics Corp. Kowloon, Hong Kong Hsinchu, Taiwan Winbond Systems Lab. TEL: 852-27513100 TEL: 886-3-5770066 2727 N. First Street, San Jose, FAX: 852-27552064 FAX: 886-3-5792647 CA 95134, U.S.A. http://www.winbond.com.tw/ TEL: 1-408-9436666 Voice & Fax-on-demand: 886-2-7197006 FAX: 1-408-5441798 Taipei Office 11F, No. 115, Sec. 3, Min-Sheng East Rd., Taipei, Taiwan TEL: 886-2-7190505 FAX: 886-2-7197502 Note: All data and specifications are subject to change without notice. - 17 - Publication Release Date: August 1997 Revision A1