320ST/B DQ15-DQ0 W19B320ST/B W19B320S W19L320S DQ15/A-1 A0-A20 DQ0-DQ14 - Datasheet Archive

 

4M × 8/2M × 16 3V(3.3V) FLASH MEMORY Table of Contents1. GENERAL DESCRIPTION .

 

W19B(L)320ST/B 320ST/B Data Sheet 4M × 8/2M × 16 3V(3.3V) FLASH MEMORY Table of Contents1. GENERAL DESCRIPTION . 4 2. FEATURES . 4 3. PIN CONFIGURATIONS . 5 4. BLOCK DIAGRAM . 5 5. PIN DESCRIPTION. 5 6. FUNCTIONAL DESCRIPTION . 6 6.1 Device Bus Operation. 6 6.1.1 6.1.2 Reading Array Data .6 6.1.3 Writing Commands/Command Sequences.6 6.1.4 Standby Mode .7 6.1.5 Automatic Sleep Mode .7 6.1.6 #RESET: Hardware Reset Pin.7 6.1.7 Output Disable Mode.8 6.1.8 Autoselect Mode.8 6.1.9 Sector/Sector Block Protection and Unprotection.8 6.1.10 Write Protect (#WP) .8 6.1.11 Temporary Sector Unprotect .9 6.1.12 Security Sector Flash Memory Region .9 6.1.13 6.2 Word/Byte Configuration .6 Hardware Data Protection .10 Command Definitions . 10 6.2.1 Reset Command.11 6.2.3 Autoselect Command Sequence .11 6.2.4 Enter Security Sector/Exit Security Sector Command Sequence .12 6.2.5 Byte/Word Program Command Sequence.12 6.2.6 Unlock Bypass Command Sequence .12 6.2.7 Chip Erase Command Sequence .13 6.2.8 Sector Erase Command Sequence .13 6.2.9 6.3 Reading Array Data .11 6.2.2 Erase Suspend/Erase Resume Commands .14 Write Operation Status . 14 6.3.1 DQ7: #Data Polling.14 6.3.2 RY/#BY: Ready/#Busy .15 6.3.3 DQ6: Toggle Bit I.15 6.3.4 DQ2: Toggle Bit II.16 -1- Publication Release Date: March 23, 2004 Revision A2 W19B(L)320ST/B 320ST/B 6.3.5 6.3.6 DQ5: Exceeded Timing Limits .16 6.3.7 7. Reading Toggle Bits DQ6/DQ2 .16 DQ3: Sector Erase Timer .17 TABLE OF OPERATION MODES . 18 7.1 Device Bus Operations . 18 7.2 7.3 CFI Query Identification String. 26 7.4 Command Definitions . 29 7.5 Write Operation Status . 30 7.6 Temporary Sector Unprotect Algorithm . 31 7.7 In-System Sector Protect/Unprotect Algorithms. 32 7.8 Program Algorithm. 33 7.9 Erase Algorithm . 33 7.10 Data Polling Algorithm . 34 7.11 8. Autoselect Codes (High Voltage Method) . 19 Toggle Bit Algorithm . 35 ELECRICAL CHARACTERISTICS . 36 8.1 Absolute Maximum Ratings . 36 8.2 Operating Ranges. 36 1.1.1 .36 1.1.1 .36 8.3 DC Characteristics. 37 8.3.1 8.4 CMOS Compatible.37 AC Characteristics . 38 8.4.1 AC Test Load and Waveforms .38 8.4.3 Read-Only Operations.39 8.4.4 Hardware Reset (#RESET) .39 8.4.5 Word/Byte Configuration (#BYTE).39 8.4.6 Erase And Program Operation .40 8.4.7 Temporary Sector Unprotect .40 8.4.8 9. Test Condition .38 8.4.2 Alternate #CE Controlled Erase and Program Operations.41 TIMING WAVEFORMS . 42 9.1 AC Read Waveform. 42 9.2 Reset Waveform . 42 9.3 #BYTE Waveform for Read Operation . 43 9.4 #BYTE Waveform for Write Operation . 43 9.5 Programming Waveform. 44 9.6 Accelerated Programming Waveform. 44 -2- W19B(L)320ST/B 320ST/B 9.7 Chip/Sector Erase Waveform . 45 9.8 #Data Polling Waveform (During Embedded Algorithms) . 45 9.9 Toggle Bit Waveform (During Embedded Algorithms) . 46 9.10 DQ 2 vs. DQ6 Waveform . 46 9.11 Temporary Sector Unprotect Timing Diagram. 47 9.12 Sector/Sector Block Protect and Unprotect Timing Diagram . 47 9.13 Alternate #CE Controlled Write (Erase/Program) Operation Timing. 48 10. LATCHUP CHARACTERISTICS . 49 11. CAPACITANCE. 49 12. ORDERING INFORMATION . 50 13. PACKAGE DIMENSIONS . 51 13.1 48-Ball TFBGA (measurements in millimeters) . 51 13.2 14. 48-Pin Standard Thin Small Outline Package (measured in millimeters) . 51 VERSION HISTORY . 52 -3- Publication Release Date: March 23, 2004 Revision A2 W19B(L)320ST/B 320ST/B 1. GENERAL DESCRIPTION The W19B(L)320ST/B 320ST/B is a 32Mbit, 2.7-3.6(3.0-3.6) volt CMOS flash memory organized as 4M × 8 or 2M × 16 bits. For flexible erase capability, the 32 Mbits of data are divided into eight 8KB, and sixtythree 64KB sectors. The word-wide (×16) data appears on DQ15-DQ0 DQ15-DQ0, and byte-wide (×8) data appears on DQ7-DQ0. The device can be programmed and erased in-system with a standard 2.7-3.6V(3.0-3.6V) power supply. A 12-volt VPP is not required. The unique cell architecture of the W19B320ST/B W19B320ST/B results in fast program/erase operations with extremely low current consumption (compared to other comparable 3-volt flash memory products). The device can also be programmed and erased by using standard EPROM programmers. 2. FEATURES Performance · 2.7~3.6-volt write (program and erase) operations (W19B320S W19B320S) · 3.0~3.6-volt write (program and erase) operations (W19L320S W19L320S) · Fast write operation - Sector erase time: 0.7 Sec (typ.) - Chip erase time: 49 Sec (typ.) - Byte programming time: 5 µS (typ.) · Read access time: 90 nS · Typical program/erase cycles: - 100K · Twenty-year data retention · Ultra low power consumption - Active current (Read): 10 mA (typ.) at 5 MHz - Standby current: 0.2 µA (typ.) · TTL compatible I/O · Manufactured on WinStack 0.18µm process technology · Available packages: 48-pin TSOP and 48-ball TFBGA (8x11mm) Software Features · Compatible with common Flash Memory Interface (CFI) specification - Flash device parameters stored directly on the device - Allows software driver to identify and use a variety of different current and future Flash products · Erase Suspend/Erase Resume - Suspends erase operations to allow programming in same bank · End of program detection - Software method: Toggle bit/Data polling Architecture · Sector erase architecture - Eight 8KB, and sixty-three 64KB sectors - Top or bottom boot block configurations available - Supports full chip erase · Unlock Bypass Program command · Security Sector Size: 256 Bytes - The Security Sector is an OTP; once the sector is programmed, it cannot be erased · Ready/#Busy output (RY/#BY) - Detect program or erase cycle completion · JEDEC standard byte-wide and word-wide pinouts - Reduces overall programming time when issuing multiple program command sequences Hardware Features · Hardware reset pin (#RESET) - Reset the internal state machine to the read mode -4- W19B(L)320ST/B 320ST/B · #WP/ACC input pin · Sector Protection - Write protect (#WP) function allows protection of two outermost boot sectors, regardless of sector protect status - Acceleration (ACC) function accelerates program timing 3. PIN CONFIGURATIONS - Sectors can be locked in-system or via programmer - Temporary Sector Unprotect allows changing data in protected sectors in-system 4. BLOCK DIAGRAM VDD VSS 48-Ball TFBGA #CE #OE #WE #WP/ACC #BYTE #RESET (Top View, Balls Face Down) A6 B6 C6 D6 E6 A13 A12 A14 A15 A16 F6 H6 G6 #BYTE DQ15/A-1 DQ15/A-1 Vss A5 B5 C5 D5 E5 F5 G5 H5 A9 A8 A10 A11 DQ7 DQ14 DQ13 DQ6 A4 B4 C4 D4 E4 F4 G4 NC A19 DQ5 DQ12 V DD DQ4 A3 C3 D3 E3 F3 G3 H3 RY/#BY #WP/ACC A18 A20 DQ2 DQ10 DQ11 DQ3 B3 A2 B2 C2 D2 E2 F2 G2 A17 A6 A5 DQ0 DQ8 DQ9 B1 C1 D1 E1 F1 G1 A3 A4 A2 A1 A0 #CE #OE BANK . A20 DQ1 A1 DECODER DQ0 . . DQ15/A-1 DQ15/A-1 . . H2 A7 OUTPUT BUFFER DQ15/A-1 DQ15/A-1 A0 H4 #WE #RESET CONTROL H1 Vss 5. PIN DESCRIPTION A15 A14 A13 A12 A11 A10 A9 A8 A19 A20 #WE #RESET NC #WP/ACC RY/#BY A18 A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 48 4 5 6 7 8 45 44 43 42 9 10 11 12 13 47 46 48-pin TSOP 41 40 39 38 37 36 14 15 16 17 18 35 34 33 32 31 19 20 30 29 28 27 26 21 22 23 24 25 SYMBOL A16 #BYTE Vss DQ15/A-1 DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VDD A0-A20 A0-A20 DQ0-DQ14 DQ0-DQ14 DQ15/A-1 DQ15/A-1 PIN NAME Address Inputs Data Inputs/Outputs Word mode DQ15 is Data Inputs/Outputs Byte mode A-1 is Address input #CE Chip Enable #OE Output Enable #WE DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 Write Enable #WP/ACC #BYTE #OE Vss #CE A0 Hardware Write Protect/ Acceleration Pin Byte Enable Input #RESET Hardware Reset RY/#BY Ready/Busy Status VDD Ground NC -5- Power Supply Vss No Connection Publication Release Date: March 23, 2004 Revision A2 W19B(L)320ST/B 320ST/B 6. FUNCTIONAL DESCRIPTION 6.1 Device Bus Operation 6.1.1 Word/Byte Configuration The #BYTE pin controls the device data I/O pins operate whether in the byte or word configuration. When the #BYTE pin is `1', the device is in word configuration; DQ0-DQ15 DQ0-DQ15 are active and controlled by #CE and #OE. When the #BYTE pin is `0', the device is in byte configuration, and only data I/O pins DQ0-DQ7 are active and controlled by #CE and #OE. The data I/O pins DQ8-DQ14 DQ8-DQ14 are tri-stated, and the DQ15 pin is used as an input for the LSB (A-1) address function. 6.1.2 Reading Array Data To read array data from the outputs, the #CE and #OE pins must be set to VIL. #CE is the power control and used to select the device. #OE is the output control and gates array data to the output pins. #WE should stay at VIH. The #BYTE pin determines the device outputs array data whether in words or bytes. The internal state machine is set for reading array data when device power-up, or after a hardware reset. This ensures that no excess modification of the memory content occurs during the power transition. In this mode there is no command necessary to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. The device remains enabled for read access until the command register contents are changed. 6.1.3 Writing Commands/Command Sequences In writhing a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive #WE and #CE to VIL, and #OE to VIH. For program operations, the #BYTE pin determines the device accepts program data whether in bytes or in words. Refer to "Word/Byte Configuration" for more information. The Unlock Bypass mode of device is to facilitate a faster programming. When the device enters into the Unlock Bypass mode, only two write cycles are required to program a word or byte. Please refer to "Word/Byte Configuration" section for details on programming data to the device using both standard and Unlock Bypass command sequences. The erase operation can erase a sector, multiple sectors, even the entire device. The "sector address" is the address bits required to solely select a sector. Accelerated Program Operation The device provides accelerated program operations through the ACC function. This is one of two functions provided by the #WP/ACC pin. This function is primarily intended to allow a faster manufacturing throughput in the factory. If #WP/ACC pin is set at VHH, the device automatically enters into the Unlock Bypass mode. Then the device will temporarily unprotect any protected sectors, and uses the higher voltage on this pin to reduce the time required for program operations. The system would use a two-cycle program command sequence required by the Unlock Bypass mode. When VHH is removed from the #WP/ACC pin, the device is back to a normal operation. -6- W19B(L)320ST/B 320ST/B Please note that the #WP/ACC pin can not be at VHH for operations excepts accelerated programming; otherwise, the device will be damaged. In addition, the #WP/ACC pin can not be left floating; otherwise, an unconnected inconsistent behavior will occur. Autoselect Functions When the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the internal register (which is separate from the memory array) on DQ0­DQ7. The standard read cycle timings is applied in this mode. Please refer to the Autoselect Mode and Autoselect Command Sequence sections for more information. 6.1.4 Standby Mode When the system is not reading or writing to the device, the device will be in a standby mode. In this mode, current consumption is greatly reduced, and the outputs are in the high impedance state, independent from the #OE input. When the #CE and #RESET pins are both held at VDD ± 0.3V, the device enters into the CMOS standby mode (note that this is a more restricted voltage range than VIH.) When #CE and #RESET are held at VIH, but not within VDD ± 0.3V, the device will be in the standby mode, but the standby current will be greater. The device requires standard access time (tCE) for read access when the device is in either of these standby modes, before it is ready to read data. When the device is deselected during erasing or programming, the device initiates active current until the operation is completed. 6.1.5 Automatic Sleep Mode The automatic sleep mode minimizes device's energy consumption. When addresses remain stable for tACC +30 nS, the device will enable this mode automatically. The automatic sleep mode is independent from the #CE, #WE, and #OE control signals. Standard address access timings provide new data when addresses are changed. In sleep mode, output data is latched and always available to the system. 6.1.6 #RESET: Hardware Reset Pin The #RESET pin provides a hardware method to reset the device to reading array data. When the #RESET pin is set to low for at least a period of tRP, the device will immediately terminate every operations in progress, tri-states all output pins, and ignores all read/write commands for the duration of the #RESET pulse. The device also resets the internal state machine to reading array data mode. To ensure data integrity, the interrupted operation needs to be reinitiated when the device is ready to accept another command sequence. Current is reduced for the duration of the #RESET pulse. When #RESET is held at VSS ± 0.3V, the device initiates the CMOS standby current (ICC4). If #RESET is held at VIL but not within VSS ± 0.3V, the standby current will be greater. The #RESET pin may be tied to the system-reset circuitry. Thus the system reset would also reset the device, enabling the system to read the boot-up firmware from the device. If #RESET is asserted during the program or erase operation, the RY/#BY pin will be at "0" (busy) until the internal reset operation is complete. If #RESET is asserted when a program or erase operation is not processing (RY/#BY pin is "1"), the reset operation is completed within a time of tREADY (not during Embedded Algorithms). After the #RESET pin returns to VIH, the system can read data tRH. -7- Publication Release Date: March 23, 2004 Revision A2 W19B(L)320ST/B 320ST/B 6.1.7 Output Disable Mode When the #OE input is at VIH, output from the device is disabled. The output pins are set in the high impedance state. 6.1.8 Autoselect Mode The autoselect mode offers manufacturer and device identification, as well as sector protection verification, through identifier codes output on DQ0-DQ7. This mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. However, the autoselect codes can also be accessed in-system through the command register. When using programming equipment, the autoselect mode requires VID (8.5 V to 12.5 V) on address pins A9. Address pins A6, A1, and A0 must be as shown in table. In addition, when verifying sector protection, the sector address must appear on the appropriate highest order address bits. When all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on DQ0-DQ7. To access the autoselect codes in-system, the host system can issue the autoselect command through the command register. This method does not require VID. Also refer to the Autoselect Command Sequence section for more information. 6.1.9 Sector/Sector Block Protection and Unprotection The hardware sector protection feature disables both program and erase operations in any sectors. The hardware sector unprotection feature re-enables both program and erase operations in previously protected sectors. Sector protection/unprotection can be implemented through two methods. The primary method requires VID on the #RESET pin, and can be implemented either in-system or through programming equipment. This method uses standard microprocessor bus cycle timing. The alternate method intended only for programming equipment requires VID on address pin A9 and #OE It is possible to determine whether a sector is protected or unprotected. See the Autoselect Mode section for details. 6.1.10 Write Protect (#WP) The Write Protect function provides a hardware method to protect the certain boot sectors without using VID. This function is one of two features provided by the #WP/ACC pin. When the #WP/ACC pin is set at VIL, the device disables program and erase functions in the two outermost 8 Kbyte boot sectors independently of whether those sectors were protected or unprotected using the method described in "Sector/Sector Block Protection and Unprotection." The two outermost 8 Kbyte boot sectors are the two sectors containing either the lowest addresses in a bottom-bootconfigured device or the highest addresses in a top-boot-configured device. When the #WP/ACC pin is set at VIH, the device reverts to the two outermost 8K Byte boot sectors were last set either to be protected or unprotected. That is, sector protection or unprotection for these two sectors depends on whether they were last protected or unprotected using the method described in "Sector/Sector Block Protection and Unprotection". Please note that the #WP/ACC pin must not be left floating or unconnected; otherwise, the inconsistent behavior of the device may occur. -8- W19B(L)320ST/B 320ST/B 6.1.11 Temporary Sector Unprotect This feature allows temporary unprotection of previously protected sectors to change data in-system. When the #RESET pin is set to VID (8.5V-12.5V), the Sector Unprotect mode is activated. During this mode, formerly protected sectors can be programmed or erased by selecting the sector addresses. What if VID is removed from the #RESET pin, all the previously protected sectors are protected again. 6.1.12 Security Sector Flash Memory Region The Security Sector feature provides an OTP memory region that enables permanent device identification through an Electronic Serial Number (ESN). The Security Sector uses a Security Sector Indicator Bit (DQ7) to indicate whether the Security Sector is locked or not when shipped from the factory. The DQ7 is permanently set when it is in the factory and cannot be changed, which prevents copying of a factory locked device. This ensures the security of the ESN when the product is shipped to the field. This issue should be considered during system design. Winbond offers the device with the Security Sector either factory locked or customer lockable. The factory-locked version is always protected when shipped from the factory, and has the Security Sector Indicator Bit permanently set to "1." The customer-lockable version is shipped with the Security Sector unprotected, which allowing customers to utilize the sector in any ways they choose. The customer-lockable version has the Security Sector Indicator Bit permanently set to "0." Thus, the Security Sector Indicator Bit prevents customer-lockable devices from being used to replace devices that are factory locked. The system accesses the Security Sector through a command sequence (see "Enter Security Sector/Exit Security Sector Command Sequence"). After the system has written the Enter Security Sector command sequence, it may read the Security Sector by using the addresses normally occupied by the boot sectors. This mode of operation continues until the system issues the Exit Security Sector command sequence, or until power is removed from the device. On power-up, or following a hardware reset, the device reverts to sending commands to the boot sectors. Factory Locked: Security Sector Programmed and Protected At the Factory The device Security Sector is protected when it is shipped from the factory, and it cannot be modified in any way. The device is available to be preprogrammed by one of the following: · A random, secure ESN only · Customer code through the supplier's service · Both a random, secure ESN and customer code through supplier's service. In devices with an ESN, the Bottom Boot device will be with the 16-byte ESN in the lowest addressable memory area at addresses 000000h­000007h in word mode (or 000000h­00000Fh in byte mode). In the Top Boot device the starting address of the ESN will be at the bottom of the lowest 8 Kbyte boot sector at addresses 1FF000h­1FF007h in word mode (or addresses 3FE000h­3FE00Fh in byte mode). Customers may choose have their code programmed by Winbond. Winbond can program the customer's code, with or without the random ESN. The devices are then shipped with the Security Sector permanently locked. -9- Publication Release Date: March 23, 2004 Revision A2 W19B(L)320ST/B 320ST/B Customer Lockable: Security Sector NOT Programmed or Protected At the Factory If the security feature is not necessary, the Security Sector can be seen as an additional OTP memory space. When in system design, this issue should be considered. The Security Sector can be read, programmed, but cannot be erased. Please note that when programming the Security Sector, the accelerated programming (ACC) and unlock bypass functions are not available. The Security Sector area can be protected using one of the following procedures: · Write the three-cycle Enter Security Sector Region command sequence, and then follow the in-system sector protect algorithm, except that #RESET may be at either VIH or VID. This allows in-system protection of the Security Sector without raising any device pin to a high voltage. Please note that this method is only suitable for the Security Sector. · Write the three-cycle Enter Security Sector Region command sequence, and then use the alternate method of sector protection described in the "Sector/ Sector Block Protection and Unprotection" section. When the Security Sector is locked and verified, the system must write the Exit Security Sector Region command sequence to return to reading and writing the remainder of the array. The Security Sector protection must be used with caution, since there is no procedure available for unprotecting the Security Sector area and none of the bits in the Security Sector memory space can be modified in any ways. 6.1.13 Hardware Data Protection The command sequence requirements of unlock cycles for programming or erasing provides data protection against negligent writes. In addition, the following hardware data protection measures prevent inadvertent erasure or programming, which might be caused by spurious system level signals during VDD power-up and power-down transitions, or from system noise. Write Pulse "Glitch" Protection Noise pulses, which is less than 5 nS (typical) on #OE, #CE or #WE, do not initiate a write cycle. Logical Inhibit Write cycles are inhibited by holding any one of #OE = VIL, #CE = VIH or #WE = VIH. #CE and #WE must be a logical zero while #OE is a logical one to initiate a write cycle. Power-Up Write Inhibit During power up, if #WE = #CE = VIL and #OE = VIH, the device does not accept commands on the rising edge of #WE. The internal state machine is automatically reset to the read mode on power-up. 6.2 Command Definitions The device operation can be initiated by writing specific address and data commands or sequences into the command register. The device will be reset to reading array data when writing incorrect address and data values or writing them in the improper sequence. The addresses will be latched on the falling edge of #WE or #CE, whichever happens later; while the data will be latched on the rising edge of #WE or #CE, whichever happens first. Please refer to timing waveforms. - 10 - W19B(L)320ST/B 320ST/B 6.2.1 Reading Array Data After device power-up, it is automatically set to reading array data. There is no commands are required to retrieve data. After completing an Embedded Program or Embedded Erase algorithm, the device is ready to read array data. After the device accepts an Erase Suspend command, it enters the erase-suspend-read mode. After this the system can read data from any non-erase-suspended sector. And then, after completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. Please refer to Erase Suspend/Erase Resume Commands section for detail information. The system must initiate the reset command to return the device to read (or erase-suspend-read) mode if DQ5 goes high during an active program or erase operation; otherwise, the device is in the autoselect mode. See Reset Command section and Requirements for Reading Array Data in the Device Bus Operations section for more information. 6.2.2 Reset Command The device will be to the read or erase-suspend-read mode when writing the reset command. For this command, the address bits are Don't Care. The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the device to which the system was writing to the read mode. Once erasure begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the device, to which the system was writing to the read mode. If the program command sequence is written to the device, in the Erase Suspend mode, writing the reset command returns the device to the erase-suspend-read mode. When programming begins, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in an autoselect command sequence. When in the autoselect mode, the reset command must be written to return to the read mode. If the device entered into the autoselect mode while in the Erase Suspend mode, writing the reset command returns the device to the erase-suspend-read mode. If DQ5 goes high during a program or erase operation, writing the reset command returns the device to the read mode (or erase-suspend-read mode if the device was in Erase Suspend). 6.2.3 Autoselect Command Sequence The autoselect command sequence provides the host system to access the manufacturer and device codes, and determine whether a sector is protected or not. This is an alternative method, which is intended for PROM programmers and requires VID on address pin A9. The autoselect command sequence may be written to an address within the device that is either in the read or erase-suspendread mode. When the device is actively programming or erasing, the autoselect command may not be written. The first writing two unlock cycles initiate the autoselect command sequence. This is followed by a third write cycle that contains the autoselect command. The device then enters into the autoselect mode. The system may read at any address without initiating another autoselect command sequence: · A read cycle at address XX00h returns the manufacturer code. · A read cycle at address XX01h in word mode(or XX02h in byte mode) returns the device code. - 11 - Publication Release Date: March 23, 2004 Revision A2 W19B(L)320ST/B 320ST/B · A read cycle to an address containing a sector address (SA), and the address 02h on A7-A0 in word mode (or the address 04h on A6-A-1 in byte mode) returns 01h if the sector is protected, or 00h if it is unprotected. To return to read mode (or erase-suspend-read mode if the device was previously in Erase Suspend), the system must write the reset command. 6.2.4 Enter Security Sector/Exit Security Sector Command Sequence The Security Sector region provides a secured data area containing a random, sixteen-byte electronic serial number (ESN). The system can access the Security Sector region by issuing the three-cycle Enter Security Sector command sequence. The device continues to access the Security Sector region until the system issues the four-cycle Exit Security Sector command sequence. The Exit Security Sector command sequence returns the device to normal operation. See "Security Sector Flash Memory Region" for further information. 6.2.5 Byte/Word Program Command Sequence The device can be programmed either by word or byte, which depending on the state of the #BYTE pin. Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program setup command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The device automatically provides internally generated program pulses and verifies the programmed cell margin. Once the Embedded Program algorithm is complete, the device then returns to the read mode and addresses are no longer latched. The system can determine the status of the program operation by using DQ7, DQ6, or RY/#BY. Please refer to the Write Operation Status section for bits' information. Any commands written to the device during the Embedded Program Algorithm are ignored. Please note that a hardware reset will immediately stop the program operation. The program command sequence should be reinitiated when the device has returned to the read mode, in order to ensure data integrity. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from "0" back to "1." If trying to do so may cause that device to set DQ5 = 1, or cause the DQ7 and DQ6 status bits to indicate that the operation is successful. However, a succeeding read will show that the data is still "0." Only erase operations can change "0" to "1." 6.2.6 Unlock Bypass Command Sequence The unlock bypass feature provides the system to program bytes or words to device which is faster than using the standard program command sequence. The unlock bypass command sequence is initiated by first writing two unlock cycles. And a third write cycle containing the unlock bypass command, 20h, is followed. Then, the device enters into the unlock bypass mode. A two-cycle unlock bypass program command sequence is all that required to program in this mode. The first cycle in this sequence contains the unlock bypass program command, A0h; the second cycle contains the program address and data. In the same manner, additional data is programmed. This mode dispenses with the initial two unlock cycles which required in the standard program command sequence, resulting in faster total programming time. All through the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset commands are valid. The system must issue the two-cycle unlock bypass reset command sequence to exit the unlock bypass mode. The first cycle must contain the data 90h. The second cycle need to contain the data 00h. Then, the device returns to the read mode. - 12 - W19B(L)320ST/B 320ST/B The device offers accelerated program operations by the #WP/ACC pin. When the VHH is set at the #WP/ACC pin, the device automatically enters into the Unlock Bypass mode. Then, the two-cycle Unlock Bypass program command sequence may be written. To accelerate the operation, the device must use the higher voltage on the #WP/ACC pin. Please note that the #WP/ACC pin must not be at VHH in any operation other than accelerated programming; otherwise the device may be damaged. In addition, the #WP/ACC pin must not be left floating or unconnected; otherwise the device inconsistent behavior may occur. 6.2.7 Chip Erase Command Sequence Chip erase is a six-bus cycle operation. Writing two unlock cycles initiates the chip erase command sequence, which is followed by a set-up command. After chip erase command, two additional unlock write cycles are then followed, which in turn invokes the Embedded Erase algorithm. The system preprogram is not required prior to erase. Before electrical erase, the Embedded Erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern. Any controls or timings during these operations is not required in system. As the Embedded Erase algorithm is complete, the device returns to the read mode and addresses are no longer latched. The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or RY/#BY. Please refer to the Write Operation Status section for information on these status bits. Any commands written during the chip erase operation will be ignored. However, a hardware reset shall terminate the erase operation immediately. If this happens, to ensure data integrity, the chip erase command sequence should be reinitiated when the device has returned to reading array data. 6.2.8 Sector Erase Command Sequence Sector erase is a six-bus cycle operation. Writing two unlock cycles initiates the sector erase command sequence, which is followed by a set-up command. Two additional unlock cycles are written, and are then followed by the address of the sector to be erased, and the sector erase command. The device does not require the system to preprogram before erase. Before electrical erase, the Embedded Erase algorithm automatically programs and verifies the entire memory for an all zero data pattern. Any controls or timings during these operations is not required in system. A sector erase time-out of 50 µS occurs after the command sequence is written. Additional sector addresses and sector erase commands may be written during the time-out period. Loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. The time between these additional cycles must be less than 50 µS; otherwise, erasure may begin. Any sector erase address and command following the exceeded time-out may or may not be accepted. To ensure all commands are accepted, processor interrupts be disabled during this time is recommended. The interrupts can be re-enabled after the last Sector Erase command is written. Any command other than Sector Erase or Erase Suspend during the time-out period resets the device to the read mode. The system must rewrite the command sequence and any additional addresses and commands. The system can monitor DQ3 to determine whether or not the sector erase timer has timed out (See the section on DQ3: Sector Erase Timer.). The time-out begins from the rising edge of the final #WE pulse in the command sequence. - 13 - Publication Release Date: March 23, 2004 Revision A2 W19B(L)320ST/B 320ST/B As the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. Please refer to the Write Operation Status section for information on these status bits. When the sector erase operation begins, only the Erase Suspend command is valid. All other commands are ignored. However, a hardware reset shall terminate the erase operation immediately. If this occurs, to ensure data integrity, the sector erase command sequence should be reinitiated once the device has returned to reading array data. 6.2.9 Erase Suspend/Erase Resume Commands The Erase Suspend command, B0h, allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. This command is valid only during the sector erase operation, which includes the 50 µS time-out period during the sector erase command sequence. If written during the chip erase operation or Embedded Program algorithm, the Erase Suspend command is ignored. As the Erase Suspend command is written during the sector erase operation, a maximum of 20 µs is required to suspend the erase operation. However, while the Erase Suspend command is written during the sector erase time-out, the device shall terminate the time-out period and suspends the erase operation immediately. The device enters into an erase-suspend-read mode after the erase operation has been suspended. The system can read data from, or program data to, any sector not selected for erasure. (In device "erase suspends" all sectors are selected for erasure.) The "reading at any address within erasesuspended sectors produces status" information is on DQ0-DQ7. The system can use DQ7, or DQ6 and DQ2 together, to determine whether a sector is actively erasing or is erase-suspended. Please refer to the Write Operation Status section for detail information on these status bits. After an erase-suspended program operation is complete, the device returns to the erase-suspendread mode. Using the DQ7 or DQ6 status bits, the system can determine the status of the program operation, just as in the standard Byte Program operation. Please refer to the Write Operation Status section for more information. In the erase-suspend-read mode, the autoselect command sequence also can be issued. Please refer to the Autoselect Mode and Autoselect Command Sequence sections for details. The Erase Resume command must be written to resume the sector erase operation. Further writes of the Resume command are ignored. After the chip has resumed erasing, another Erase Suspend command can be written. 6.3 Write Operation Status The device provides several bits to determine the status of a program or erase operation: DQ2, DQ3, DQ5, DQ6, and DQ7. Each of DQ7 and DQ6 provides a method for determining whether a program or erase operation is complete or in progress. The device also offers a hardware-based output signal, RY/#BY, to determine whether an Embedded Program or Erase operation is in progress or has been completed. 6.3.1 DQ7: #Data Polling The #Data Polling bit, DQ7, indicates whether an Embedded Program or Erase algorithm is in progress or completed, or whether or not the device is in Erase Suspend. Data Polling is valid after the rising edge of the final #WE pulse in the command sequence. - 14 - W19B(L)320ST/B 320ST/B During the Embedded Program algorithm, the device outputs on DQ7 and the complement of the data programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend. Once the Embedded Program algorithm has completed, the device outputs the data programmed to DQ7. The system must provide the program address to read valid status information on DQ7. If a program address falls within a protected sector, #Data Polling on DQ7 is active for about 1µS, and then the device returns to the read mode. During the Embedded Erase algorithm, #Data Polling produces "0" on DQ7. Once the Embedded Erase algorithm has completed, or when the device enters the Erase Suspend mode, #Data Polling produces "1" on DQ7. An address within any of the sectors selected for erasure must be provided to read valid status information on DQ7. After an erase command sequence is written, if all sectors selected for erasing are protected, #Data Polling on DQ7 is active for about 100 µS, and then the device returns to the read mode. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. However, if the system reads DQ7 at an address within a protected sector, the status may not be valid. Just before the completion of an Embedded Program or Erase operation, DQ7 may change asynchronously with DQ0-DQ6 while Output Enable (#OE) is set to low. That is, the device may change from providing status information to valid data on DQ7. Depending on when it samples the DQ7 output, the system may read the status or valid data. Even if the device has completed the program or erase operation and DQ7 has valid data, the data outputs on DQ0-DQ6 may be still invalid. Valid data on DQ0-DQ7 will appear on successive read cycles. 6.3.2 RY/#BY: Ready/#Busy The RY/#BY is a dedicated, open-drain output pin which indicates whether an Embedded Algorithm is in progress or complete. The RY/#BY status is valid after the rising edge of the final #WE pulse in the command sequence. Since RY/#BY is an open-drain output, several RY/#BY pins can be tied together in parallel with a pull-up resistor to VDD. When the output is low (Busy), the device is actively erasing or programming. (This includes programming in the Erase Suspend mode.) When the output is high (Ready), the device is in the read mode, the standby mode is in the erase-suspend-read mode. 6.3.3 DQ6: Toggle Bit I Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising edge of the final #WE pulse in the command sequence (before the program or erase operation), and during the sector erase time-out. During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause DQ6 to toggle. The system may use either #OE or #CE to control the read cycles. Once the operation has completed, DQ6 stops toggling. After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for about 100 µS, and then returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors which are protected. The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erase-suspended. If the device is actively erasing (i.e., the Embedded Erase algorithm is in progress), - 15 - Publication Release Date: March 23, 2004 Revision A2 W19B(L)320ST/B 320ST/B DQ6 toggles. While if the device enters the Erase Suspend mode, DQ6 stops toggling. However, the system must also use DQ2 to determine which sectors are erasing or erase-suspended. Alternatively, the system can use DQ7 (see DQ7: #Data Polling). If a program address falls within a protected sector, DQ6 toggles for about 1 µs after the program command sequence is written, and then returns to reading array data. DQ6 also toggles during the erase-suspend-program mode, and stops toggling when the Embedded Program algorithm is complete. Please also refer to DQ2: Toggle Bit II. 6.3.4 DQ2: Toggle Bit II When used with DQ6, the "Toggle Bit II" on DQ2 indicates whether a particular sector is actively erasing (i.e., the Embedded Erase algorithm is in progress), or the sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final #WE pulse in the command sequence. DQ2 toggles as the system reads at addresses within those sectors that have been selected for erasure. (The system may use either #OE or #CE to control the read cycles.) But DQ2 cannot distinguish that whether the sector is actively erasing or is erase-suspended. By comparison, DQ6 indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Therefore, both status bits are required for sector and mode information. 6.3.5 Reading Toggle Bits DQ6/DQ2 Whenever the system initially starts to read toggle bit status, it must read DQ0-DQ7 at least twice in a row to determine whether a toggle bit is toggling or not. Typically, the system would note and store the value of the toggle bit after the first read. While after the second read, the system would compare the new value of the toggle bit with the first one. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on DQ0-DQ7 on the following read cycle. However, if after the initial two read cycles, the system finds that the toggle bit is still toggling, the system also should note whether the value of DQ5 is high or not(see the section on DQ5). If DQ5 is high, the system should then determine again whether the toggle bit is toggling or not, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not completed the operation, and the system must write the reset command to return to reading array data. Then the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, and determines the status as described in the previous paragraph. Alternatively, the system may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm while it returns to determine the status of the operation. 6.3.6 DQ5: Exceeded Timing Limits DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. DQ5 produces "1" under these conditions which indicates that the program or erase cycle was not successfully completed. - 16 - W19B(L)320ST/B 320ST/B The device may output "1" on DQ5 if the system tries to program "1" to a location that was previously programmed to "0." Only the erase operation can change "0" back to "1." Under this condition, the device stops the operation, and while the timing limit has been exceeded, DQ5 produces "1." Under both these conditions, the system must write the reset command to return to the read mode (or to the erase-suspend-read mode if the device was previously in the erase-suspend-program mode). 6.3.7 DQ3: Sector Erase Timer After writing a sector erase command sequence, the system may read DQ3 to determine whether erasure has begun or not. (The sector erase timer does not apply to the chip erase command.) The entire time-out applies after each additional sector erase command if additional sectors are selected for erasure. Once the timeout period has completed, DQ3 switches from "0" to "1." If the time between additional sector erase commands from the system can be assumed to be less than 50 µS, the system need not monitor, DQ3 does not need to be monitored. Please also refer to Sector Erase Command Sequence section. After the sector erase command is written, the system should read the status of DQ7 (#Data Polling) or DQ6 (Toggle Bit I) to ensure that the device has accepted the command sequence, and then read DQ3. If DQ3 is"1," the Embedded Erase algorithm has begun; all further commands (except Erase Suspend) are ignored until the erase operation is complete. If DQ3 is "0," the device will accept additional sector erase commands. The system software should check the status of DQ3 before and following each subsequent sector erase command to ensure the command has been accepted. If DQ3 is high on the second status check, the last command might not have been accepted. - 17 - Publication Release Date: March 23, 2004 Revision A2 W19B(L)320ST/B 320ST/B 7. TABLE OF OPERATION MODES 7.1 Device Bus Operations MODE #CE #OE #WE #RESET #WP/ACC ADDRESSES (Note2) DQ0-DQ7 DQ8-DQ15 DQ8-DQ15 #BYTE =VIH #BYTE =VIL Read L L H H L/H AIN DOUT DOUT Write L H L H (Note3) AIN (Note 4) (Note 4) Accelerated Program L H L H VHH AIN (Note 4) (Note 4) VDD ± 0.3V X X VDD ± 0.3V H X High-Z High-Z High-Z Output Disable L H H H L/H X High-Z High-Z High-Z Reset X X X L L/H X High-Z High-Z High-Z Sector Protect (note2) L H L VID L/H SA, A6 = L, A1 = H, A0 = L (Note 4) X X Sector Unprotect (note2) L H L VID (Note3) SA, A6 = H, A1 = H, A0 = L (Note 4) X X Temporary Sector Unprotect X X X VID (Note3) AIN (Note 4) (Note 4) High-Z Standby DQ8-DQ14 DQ8-DQ14 = High-Z, DQ15=A-1 Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 8.5-12.5V, VHH = 9.0±0.5V, X = Don't Care, SA = Sector Address, AIN = Address In, DIN = Data In, DOUT = Data Out Notes: 1. Addresses are A20:A0 in word mode (#BYTE = VIH), A20: A-1 in byte mode (#BYTE = VIL). 2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the" Sector/Sector Block Protection and Unprotect ion" section. 3. If #WP/ACC = VIL, the two outermost boot sectors remain protected. If #WP/ACC = VIH, the two outermost boot sector protection depends on whether they were last protected or unprotected using the method described in "Sector/Sector Block Protection and Unprotect ion". If #WP/ACC = VHH, all sectors will be unprotected. 4. DIN or DOUT as required by command sequence, data polling, or sector protection algorithm. - 18 - W19B(L)320ST/B 320ST/B 7.2 Autoselect Codes (High Voltage Method) DESCRIPTION #CE #OE #WE A20 TO A12 A11 TO A10 A9 A8 TO A7 A6 A5 TO A2 A1 A0 DQ8 TO DQ15 #BYTE #BYTE = VIH = VIL DQ7 TO DQ0 Manufacturer ID: Winbond VIL VIL VIH X X VID X VIL X VIL VIL X X DAh Device ID: W19B(L)320ST 320ST (Top Boot Block) VIL VIL VIH X X VID X VIL X VIL VIH 22h X BAh Device ID: W19B(L)320SB 320SB (Bottom Boot Block) VIL VIL VIH X X VID X VIL X VIL VIH 22h X 2Ah VIL VIL VIH SA X VID X VIL X X (protected) X X Sector Protection Verification Security Indicator Bit (DQ7) VIL VIL VIH X X VID X VIL X X VIH VIH VIL VIH X X 01h 00h (unprotected) 99h (factory locked) 19h (not factory locked) Legend: SA = Sector Address, X = Don't Care. - 19 - Publication Release Date: March 23, 2004 Revision A2 W19B(L)320ST/B 320ST/B Sector Address Table (Top Boot Block) SECTOR SECTOR ADDRESS A20-A12 A20-A12 SECTOR SIZE (Kbytes/Kwords) (X8) (X16) ADDRESS RANGE ADDRESS RANGE SA0 000000XXX 000000XXX 64/32 000000h-00FFFFh 000000h-07FFFh SA1 000001XXX 000001XXX 64/32 010000h-01FFFFh 008000h-0FFFFh SA2 000010XXX 000010XXX 64/32 020000h-02FFFFh 010000h-17FFFh SA3 000011XXX 000011XXX 64/32 030000h-03FFFFh 018000h-01FFFFh SA4 000100XXX 000100XXX 64/32 040000h-04FFFFh 020000h-027FFFh SA5 000101XXX 000101XXX 64/32 050000h-05FFFFh 028000h-02FFFFh SA6 000110XXX 000110XXX 64/32 060000h-06FFFFh 030000h-037FFFh SA7 000111XXX 000111XXX 64/32 070000h-07FFFFh 038000h-03FFFFh SA8 001000XXX 001000XXX 64/32 080000h-08FFFFh 040000h-047FFFh SA9 001001XXX 001001XXX 64/32 090000h-09FFFFh 048000h-04FFFFh SA10 001010XXX 001010XXX 64/32 0A0000h-0AFFFFh 050000h-057FFFh SA11 001011XXX 001011XXX 64/32 0B0000h-0BFFFFh 058000h-05FFFFh SA12 001100XXX 001100XXX 64/32 0C0000h-0CFFFFh 060000h-067FFFh SA13 001101XXX 001101XXX 64/32 0D0000h-0DFFFFh 068000h-06FFFFh SA14 001110XXX 001110XXX 64/32 0E0000h-0EFFFFh 070000h-077FFFh SA15 001111XXX 001111XXX 64/32 0F0000h-0FFFFFh 078000h-07FFFFh SA16 010000XXX 010000XXX 64/32 100000h-10FFFFh 080000h-087FFFh SA17 010001XXX 010001XXX 64/32 110000h-11FFFFh 088000h-08FFFFh SA18 010010XXX 010010XXX 64/32 120000h-12FFFFh 090000h-097FFFh SA19 010011XXX 010011XXX 64/32 130000h-13FFFFh 098000h-09FFFFh SA20 010100XXX 010100XXX 64/32 140000h-14FFFFh 0A0000h-0A7FFFh SA21 010101XXX 010101XXX 64/32 150000h-15FFFFh 0A8000h-0AFFFFh SA22 010110XXX 010110XXX 64/32 160000h-16FFFFh 0B0000h-0B7FFFh SA23 010111XXX 010111XXX 64/32 170000h-17FFFFh 0B8000h-0BFFFFh SA24 011000XXX 011000XXX 64/32 180000h-18FFFFh 0C0000h-0C7FFFh SA25 011001XXX 011001XXX 64/32 190000h-19FFFFh 0C8000h-0CFFFFh SA26 011010XXX 011010XXX 64/32 1A0000h-1AFFFFh 0D0000h-0D7FFFh SA27 011011XXX 011011XXX 64/32 1B0000h-1BFFFFh 0D8000h-0DFFFFh SA28 011100XXX 011100XXX 64/32 1C0000h-1CFFFFh 0E0000h-0E7FFFh SA29 011101XXX 011101XXX 64/32 1D0000h-1DFFFFh 0E8000h-0EFFFFh SA30 011110XXX 011110XXX 64/32 1E0000h-1EFFFFh 0F0000h-0F7FFFh SA31 011111XXX 011111XXX 64/32 1F0000h-1FFFFFh 0F8000h-0FFFFFh SA32 100000XXX 100000XXX 64/32 200000h-20FFFFh 100000h-107FFFh SA33 100001XXX 100001XXX 64/32 210000h-21FFFFh 108000h-10FFFFh SA34 100010XXX 100010XXX 64/32 220000h-22FFFFh 110000h-117FFFh SA35 100011XXX 100011XXX 64/32 230000h-23FFFFh 118000h-11FFFFh SA36 100100XXX 100100XXX 64/32 240000h-24FFFFh 120000h-127FFFh SA37 100101XXX 100101XXX 64/32 250000h-25FFFFh 128000h-12FFFFh SA38 100110XXX 100110XXX 64/32 260000h-26FFFFh 130000h-137FFFh SA39 100111XXX 100111XXX 64/32 270000h-27FFFFh 138000h-13FFFFh SA40 101000XXX 101000XXX 64/32 280000h-28FFFFh 140000h-147FFFh - 20 - W19B(L)320ST/B 320ST/B Sector Address Table (Top Boot Block), continued SECTOR ADDRESS (X8) (X16) ADDRESS RANGE ADDRESS RANGE 64/32 290000h-29FFFFh 148000h-14FFFFh 64/32 2A0000h-2AFFFFh 150000h-157FFFh 101011XXX 101011XXX 64/32 2B0000h-2BFFFFh 158000h-15FFFFh SA44 101100XXX 101100XXX 64/32 2C0000h-2CFFFFh 160000h-167FFFh SA45 101101XXX 101101XXX 64/32 2D0000h-2DFFFFh 168000h-16FFFFh A20-A12 A20-A12 SECTOR SIZE (Kbytes/Kwords) SA41 101001XXX 101001XXX SA42 101010XXX 101010XXX SA43 SECTOR SA46 101110XXX 101110XXX 64/32 2E0000h-2EFFFFh 170000h-177FFFh SA47 101111XXX 101111XXX 64/32 2F0000h-2FFFFFh 178000h-17FFFFh SA48 110000XXX 110000XXX 64/32 300000h-30FFFFh 180000h-187FFFh SA49 110001XXX 110001XXX 64/32 310000h-31FFFFh 188000h-18FFFFh SA50 110010XXX 110010XXX 64/32 320000h-32FFFFh 190000h-197FFFh SA51 110011XXX 110011XXX 64/32 330000h-33FFFFh 198000h-19FFFFh SA52 110100XXX 110100XXX 64/32 340000h-34FFFFh 1A0000h-1A7FFFh SA53 110101XXX 110101XXX 64/32 350000h-35FFFFh 1A8000h-1AFFFFh SA54 110110XXX 110110XXX 64/32 360000h-36FFFFh 1B0000h-1B7FFFh SA55 110111XXX 110111XXX 64/32 370000h-37FFFFh 1B8000h-1BFFFFh SA56 111000XXX 111000XXX 64/32 380000h-38FFFFh 1C0000h-1C7FFFh SA57 111001XXX 111001XXX 64/32 390000h-39FFFFh 1C8000h-1CFFFFh SA58 111010XXX 111010XXX 64/32 3A0000h-3AFFFFh 1D0000h-1D7FFFh SA59 111011XXX 111011XXX 64/32 3B0000h-3BFFFFh 1D8000h-1DFFFFh SA60 111100XXX 111100XXX 64/32 3C0000h-3CFFFFh 1E0000h-1E7FFFh SA61 111101XXX 111101XXX 64/32 3D0000h-3DFFFFh 1E8000h-1EFFFFh SA62 111110XXX 111110XXX 64/32 3E0000h-3EFFFFh 1F0000h-1F7FFFh SA63 111111000 8/4 3F0000h-3F1FFFh 1F8000h-1F8FFFh SA64 111111001 8/4 3F2000h-3F3FFFh 1F9000h-1F9FFFh SA65 111111010 8/4 3F4000h-3F5FFFh 1FA000h-1FAFFFh SA66 111111011 8/4 3F6000h-3F7FFFh 1FB000h-1FBFFFh SA67 111111100 8/4 3F8000h-3F9FFFh 1FC000h-1FCFFFh SA68 111111101 8/4 3FA000h-3FBFFFh 1FD000h-1FDFFFh SA69 111111110 8/4 3FC000h-3FDFFFh 1FE000h-1FEFFFh SA70 111111111 8/4 3FE000h-3FFFFFh 1FF000h-1FFFFFh Note: The address range is [A20: A-1] in byte mode (#BYTE =VIL) or [A20:A0] in word mode (#BYTE = VIH). Security Sector Addresses for Top Boot Devices DEVICE W19B320ST W19B320ST SECTOR ADDRESS A20-A12 A20-A12 111111XXX 111111XXX SECTOR SIZE (bytes/words) (X 8) (X 16) ADDRESS RANGE ADDRESS RANGE 256/128 3FE000h-3FE0FFh 1FF000h-1FF07Fh - 21 - Publication Release Date: March 23, 2004 Revision A2 W19B(L)320ST/B 320ST/B Sector Address Table (Bottom Boot Block) SECTOR ADDRESS SECTOR SIZE (Kbytes/Kwords) (X8) (X16) A20-A12 A20-A12 ADDRESS RANGE ADDRESS RANGE SA0 000000000 8/4 000000h-001FFFh 000000h-000FFFh SA1 000000001 8/4 002000h-003FFFh 001000h-001FFFh SA2 000000010 8/4 004000h-005FFFh 002000h-002FFFh SA3 000000011 8/4 006000h-007FFFh 003000h-003FFFh SA4 000000100 8/4 008000h-009FFFh 004000h-004FFFh SA5 000000101 8/4 00A000h-00BFFFh 005000h-005FFFh SA6 000000110 8/4 00C000h-00DFFFh 006000h-006FFFh SA7 000000111 8/4 00E000h-00FFFFh 007000h-007FFFh SA8 000001XXX 000001XXX 64/32 010000h-01FFFFh 008000h-00FFFFh SA9 000010XXX 000010XXX 64/32 020000h-02FFFFh 010000h-017FFFh SA10 000011XXX 000011XXX 64/32 030000h-03FFFFh 018000h-01FFFFh SECTOR SA11 000100XXX 000100XXX 64/32 040000h-04FFFFh 020000h-027FFFh SA12 000101XXX 000101XXX 64/32 050000h-05FFFFh 028000h-02FFFFh SA13 000110XXX 000110XXX 64/32 060000h-06FFFFh 030000h-037FFFh SA14 000111XXX 000111XXX 64/32 070000h-07FFFFh 038000h-03FFFFh SA15 001000XXX 001000XXX 64/32 080000h-08FFFFh 040000h-047FFFh SA16 001001XXX 001001XXX 64/32 090000h-09FFFFh 048000h-04FFFFh SA17 001010XXX 001010XXX 64/32 0A0000h-0AFFFFh 050000h-057FFFh SA18 001011XXX 001011XXX 64/32 0B0000h-0BFFFFh 058000h-05FFFFh SA19 001100XXX 001100XXX 64/32 0C0000h-0CFFFFh 060000h-067FFFh SA20 001101XXX 001101XXX 64/32 0D0000h-0DFFFFh 068000h-06FFFFh SA21 001110XXX 001110XXX 64/32 0E0000h-0EFFFFh 070000h-077FFFh SA22 001111XXX 001111XXX 64/32 0F0000h-0FFFFFh 078000h-07FFFFh SA23 010000XXX 010000XXX 64/32 100000h-10FFFFh 080000h-087FFFh SA24 010001XXX 010001XXX 64/32 110000h-11FFFFh 088000h-08FFFFh SA25 010010XXX 010010XXX 64/32 120000h-12FFFFh 090000h-097FFFh SA26 010011XXX 010011XXX 64/32 130000h-13FFFFh 098000h-09FFFFh SA27 010100XXX 010100XXX 64/32 140000h-14FFFFh 0A0000h-0A7FFFh SA28 010101XXX 010101XXX 64/32 150000h-15FFFFh 0A8000h-0AFFFFh SA29 010110XXX 010110XXX 64/32 160000h-16FFFFh 0B0000h-0B7FFFh SA30 010111XXX 010111XXX 64/32 170000h-17FFFFh 0B8000h-0BFFFFh SA31 011000XXX 011000XXX 64/32 180000h-18FFFFh 0C0000h-0C7FFFh SA32 011001XXX 011001XXX 64/32 190000h-19FFFFh 0C8000h-0CFFFFh SA33 011010XXX 011010XXX 64/32 1A0000h-1AFFFFh 0D0000h-0D7FFFh SA34 011011XXX 011011XXX 64/32 1B0000h-1BFFFFh 0D8000h-0DFFFFh SA35 011100XXX 011100XXX 64/32 1C0000h-1CFFFFh 0E0000h-0E7FFFh SA36 011101XXX 011101XXX 64/32 1D0000h-1DFFFFh 0E8000h-0EFFFFh SA37 011110XXX 011110XXX 64/32 1E0000h-1EFFFFh 0F0000h-0F7FFFh SA38 011111XXX 011111XXX 64/32 1F0000h-1FFFFFh 0F8000h-0FFFFFh SA39 100000XXX 100000XXX 64/32 200000h-20FFFFh 100000h-107FFFh SA40 100001XXX 100001XXX 64/32 210000h-21FFFFh 108000h-10FFFFh - 22 - W19B(L)320ST/B 320ST/B Sector Address Table (Bottom Boot Block), continued SECTOR SECTOR ADDRESS A20-A12 A20-A12 SECTOR SIZE (Kbytes/Kwords) (X8) (X16) ADDRESS RANGE ADDRESS RANGE SA41 100010XXX 100010XXX 64/32 220000h-22FFFFh 110000h-117FFFh SA42 100011XXX 100011XXX 64/32 230000h-23FFFFh 118000h-11FFFFh SA43 100100XXX 100100XXX 64/32 240000h-24FFFFh 120000h-127FFFh SA44 100101XXX 100101XXX 64/32 250000h-25FFFFh 128000h-12FFFFh SA45 100110XXX 100110XXX 64/32 260000h-26FFFFh 130000h-137FFFh SA46 100111XXX 100111XXX 64/32 270000h-27FFFFh 138000h-13FFFFh SA47 101000XXX 101000XXX 64/32 280000h-28FFFFh 140000h-147FFFh SA48 101001XXX 101001XXX 64/32 290000h-29FFFFh 148000h-14FFFFh SA49 101010XXX 101010XXX 64/32 2A0000h-2AFFFFh 150000h-157FFFh SA50 101011XXX 101011XXX 64/32 2B0000h-2BFFFFh 158000h-15FFFFh SA51 101100XXX 101100XXX 64/32 2C0000h-2CFFFFh 160000h-167FFFh SA52 101101XXX 101101XXX 64/32 2D0000h-2DFFFFh 168000h-16FFFFh SA53 101110XXX 101110XXX 64/32 2E0000h-2EFFFFh 170000h-177FFFh SA54 101111XXX 101111XXX 64/32 2F0000h-2FFFFFh 178000h-17FFFFh SA55 111000XXX 111000XXX 64/32 300000h-30FFFFh 180000h-187FFFh SA56 110001XXX 110001XXX 64/32 310000h-31FFFFh 188000h-18FFFFh SA57 110010XXX 110010XXX 64/32 320000h-32FFFFh 190000h-197FFFh SA58 110011XXX 110011XXX 64/32 330000h-33FFFFh 198000h-19FFFFh SA59 110100XXX 110100XXX 64/32 340000h-34FFFFh 1A0000h-1A7FFFh SA60 110101XXX 110101XXX 64/32 350000h-35FFFFh 1A8000h-1AFFFFh SA61 110110XXX 110110XXX 64/32 360000h-36FFFFh 1B0000h-1B7FFFh SA62 110111XXX 110111XXX 64/32 370000h-37FFFFh 1B8000h-1BFFFFh SA63 111000XXX 111000XXX 64/32 380000h-38FFFFh 1C0000h-1C7FFFh SA64 111001XXX 111001XXX 64/32 390000h-39FFFFh 1C8000h-1CFFFFh SA65 111010XXX 111010XXX 64/32 3A0000h-3AFFFFh 1D0000h-1D7FFFh SA65 111011XXX 111011XXX 64/32 3B0000h-3BFFFFh 1D8000h-1DFFFFh SA67 111100XXX 111100XXX 64/32 3C0000h-3CFFFFh 1E0000h-1E7FFFh SA68 111101XXX 111101XXX 64/32 3D0000h-3DFFFFh 1E8000h-1EFFFFh SA69 111110XXX 111110XXX 64/32 3E0000h-3EFFFFh 1F0000h-1F7FFFh SA70 111111XXX 111111XXX 64/32 3F0000h-3FFFFFh 1F8000h-1FFFFFh Note: The address range is [A20: A-1] in byte mode (#BYTE =VIL) or [A20:A0] in word mode (#BYTE =VIH). Security Sector Addresses for Bottom Boot Devices DEVICE W19B320SB W19B320SB SECTOR ADDRESS A20-A12 A20-A12 000000XXX 000000XXX SECTOR SIZE (bytes/words) (X8) (X16) ADDRESS RANGE ADDRESS RANGE 256/128 000000h-0000FFh 000000h-00007Fh - 23 - Publication Release Date: March 23, 2004 Revision A2 W19B(L)320ST/B 320ST/B Top Boot Sector/Sector Block Address for Protection/Unprotection) SECTOR A20-A12 A20-A12 SECTOR/SECTOR BLOCK SIZE SA0-SA3 000000XXX 000000XXX 000001XXX 000001XXX 000010XXX 000010XXX 000011XXX 000011XXX 256(4x64) K bytes SA4-SA7 0001XXXXX 0001XXXXX 256(4x64) K bytes SA8-SA11 SA8-SA11 0010XXXXX 0010XXXXX 256(4x64) K bytes SA12-SA15 SA12-SA15 0011XXXXX 0011XXXXX 256(4x64) K bytes SA16-SA19 SA16-SA19 0100XXXXX 0100XXXXX 256(4x64) K bytes SA20-SA23 SA20-SA23 0101XXXXX 0101XXXXX 256(4x64) K bytes SA24-SA27 SA24-SA27 0110XXXXX 0110XXXXX 256(4x64) K bytes SA28-SA31 SA28-SA31 0111XXXXX 0111XXXXX 256(4x64) K bytes SA32-SA35 SA32-SA35 1000XXXXX 1000XXXXX 256(4x64) K bytes SA36-SA39 SA36-SA39 1001XXXXX 1001XXXXX 256(4x64) K bytes SA40-SA43 SA40-SA43 1010XXXXX 1010XXXXX 256(4x64) K bytes SA44-SA47 SA44-SA47 1011XXXXX 1011XXXXX 256(4x64) K bytes SA48-SA51 SA48-SA51 1100XXXXX 1100XXXXX 256(4x64) K bytes SA52-SA55 SA52-SA55 1101XXXXX 1101XXXXX 256(4x64) K bytes SA56-SA59 SA56-SA59 1110XXXXX 1110XXXXX 256(4x64) K bytes SA60-SA62 SA60-SA62 111100XXX 111100XXX 111101XXX 111101XXX 111110XXX 111110XXX 192(3x64) K bytes SA63 111111000 8 K bytes SA64 111111001 8 K bytes SA65 111111010 8 K bytes SA66 111111011 8 K bytes SA67 111111100 8 K bytes SA68 111111101 8 K bytes SA69 111111110 8 K bytes SA70 111111111 8 K bytes - 24 - W19B(L)320ST/B 320ST/B Bottom Boot Sector/Sector Block Address for Protection/Unprotection) SECTOR A20-A12 A20-A12 SECTOR/SECTOR BLOCK SIZE SA70-SA67 SA70-SA67 111111XXX 111111XXX 111110XXX 111110XXX 111101XXX 111101XXX 111100XXX 111100XXX 256(4x64) K bytes SA66-SA63 SA66-SA63 1110XXXXX 1110XXXXX 256(4x64) K bytes SA62-SA59 SA62-SA59 1101XXXXX 1101XXXXX 256(4x64) K bytes SA58-SA55 SA58-SA55 1100XXXXX 1100XXXXX 256(4x64) K bytes SA54-SA51 SA54-SA51 1011XXXXX 1011XXXXX 256(4x64) K bytes SA50-SA47 SA50-SA47 1010XXXXX 1010XXXXX 256(4x64) K bytes SA46-SA43 SA46-SA43 1001XXXXX 1001XXXXX 256(4x64) K bytes SA42-SA39 SA42-SA39 1000XXXXX 1000XXXXX 256(4x64) K bytes SA38-SA35 SA38-SA35 0111XXXXX 0111XXXXX 256(4x64) K bytes SA34-SA31 SA34-SA31 0110XXXXX 0110XXXXX 256(4x64) K bytes SA30-SA27 SA30-SA27 0101XXXXX 0101XXXXX 256(4x64) K bytes SA26-SA23 SA26-SA23 0100XXXXX 0100XXXXX 256(4x64) K bytes SA22-SA19 SA22-SA19 0011XXXXX 0011XXXXX 256(4x64) K bytes SA18-SA15 SA18-SA15 0010XXXXX 0010XXXXX 256(4x64) K bytes SA14-SA11 SA14-SA11 0001XXXXX 0001XXXXX 256(4x64) K bytes SA10-SA8 SA10-SA8 000011XXX 000011XXX 000010XXX 000010XXX 000001XXX 000001XXX 192(3x64) K bytes SA7 000000111 8 K bytes SA6 000000110 8 K bytes SA5 000000101 8 K bytes SA4 000000100 8 K bytes SA3 000000011 8 K bytes SA2 000000010 8 K bytes SA1 000000001 8 K bytes SA0 000000000 8 K bytes - 25 - Publication Release Date: March 23, 2004 Revision A2 W19B(L)320ST/B 320ST/B 7.3 CFI Query Identification String ADDRESS DESCRIPTION (Word Mode) DATA ADDRESS (Byte Mode) 10h 24h 0006h 26h 0000h 28h 15h 0040h 2Ah 16h 0000h 2Ch 17h 0000h 2Eh 18h Address for Alternate OEM Extended table (00h = none exists) 0059h 14h Alternate OEM Command set (00h = none exists) 22h 13h Address for Primary Extended Table 0052h 12h Primary OEM Command Set 20h 11h Query-unique ASCII string "QRY" 0051h 0000h 30h 19h 0000h 32h 1Ah 0000h 34h System Interface String ADDRESS DESCRIPTION (Word Mode) VDD Min. (write/erase) DATA ADDRESS (Byte Mode) 1Bh 0027h 36h 1Ch 0036h 38h VPP Min. voltage (00h = no Vpp pin present) 1Dh 0000h 3Ah VPP Max. voltage (00h = no Vpp pin present) 1Eh 0000h 3Ch Typical timeout per single byte/word write 2N µS 1Fh 0004h 3Eh 20h 0000h 40h Typical timeout for individual block erase 2N mS 21h 000Ah 42h Typical timeout for full chip erase 2N mS (00h = not supported) 22h 0000h 44h 23h 0005h 46h 24h 0000h 48h 25h 0004h 4Ah 26h 0000h 4Ch D7-D4: volt, D3-D0: 100 mV VDD Max. (write/erase) D7-D4: volt, D3-D0: 100 mV Typical timeout for Min. size buffer write supported) Max. timeout for byte/word write Max. timeout for buffer write 2N 2N times µS (00h = not typical times typical Max. timeout per individual block erase Max. timeout for full chip erase supported) 2N 2N 2N times typical times typical ( 00h = not - 26 - W19B(L)320ST/B 320ST/B Device Geometry Definition ADDRESS DESCRIPTION =2N DATA (Write Mode) ADDRESS (Byte Mode) 27h 0016h 4Eh 28h 0002h 50h 29h 0000h 52h 2Ah 0000h 54h 2Bh 0000h 56h 2Ch 0002h 58h 2Dh 0007h 5Ah Erase block region 1 information 2Eh 0000h 5Ch (refer to the CFI specification or CFI publication 100 ) 2Fh 0020h 5Eh 30h 0000h 60h 31h 003Eh 62h 32h 0000h 64h 33h 0000h 66h 34h 0001h 68h 35h 0000h 6Ah 36h 0000h 6Ch 37h 0000h 6Eh 38h 0000h 70h 39h 0000h 72h 3Ah 0000h 74h 3Bh 0000h 76h 3Ch 0000h 78h Device size bytes Flash device interface description (refer to CFI publication 100) Max. number of bytes in multi-byte supported) write=2N (00h = not Number Of Erase Block Regions Within Devices Erase Block Region 2 Information Erase Block Region 3 Information Erase Block Region 4 Information - 27 - Publication Release Date: March 23, 2004 Revision A2 W19B(L)320ST/B 320ST/B Primary Vendor-Specific Extended Query ADDRESS DESCRIPTION (Word Mode) DATA ADDRESS (Byte Mode) 40h 0050h 80h 41h 0052h 82h 42h 0049h 84h Major version number, ASCII 43h 0031h 86h Minor version number, ASCII 44h 0031h 88h 45h 0000h 8Ah 46h 0002h 8Ch 47h 0001h 8Eh 48h 0001h 90h 49h 0004h 92h 4Ah 0000h 94h 4Bh 0000h 96h 4Ch 0000h 98h 4Dh 0085h 9Ah 4Eh 0095h 9Ch 4Fh 000Xh 9Eh Query-unique ASCII string "PRI" Address sensitive unlock (Bits 1-0) 0 = required, 1 = not required Silicon Revision Number (Bit 7-2) Erase suspend 0 = Not supported, 1 = To read only; 2 = To read & write Sector protect 0 = Note supported, 1 = Supported Sector Temporary Unprotect 00 = Not supported, 01 = Supported Sector protect/unprotect scheme Simultaneous operation 00 = Not supported Burst mode type 00 = Not supported, 01 = Supported Page mode type 00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page ACC (Acceleration) Supply Minimum 00h = Not Supported, D7-D4; Volt, D3-D0: 100 mV ACC (Acceleration) Supply Maximum 00h = Not Supported, D7-D4; Volt, D3-D0: 100 mV Top/bottom boot Sector Flag 02h=Bottom Boot Device, 03h = Top Boot Device - 28 - W19B(L)320ST/B 320ST/B 7.4 Command Definitions COMMAND SEQUENCE (NOTE 1) BUS CYCLES (NOTE 2-5) CYCLE FIRST ADDR DATA Read (note 6) 1 RA 1 XXX ADDR DATA THIRD ADDR FOURTH DATA ADDR DATA A0 PA FIFTH ADDR DATA SIXTH ADDR DATA PD RD Reset (note 7) SECOND F0 Normal Program Unlock Bypass Word Byte Word Byte 4 3 555 AAA 555 AAA AA AA 2AA 555 2AA 555 55 55 Unlock Bypass Program (Note 11) 2 XXX A0 PA 2 XXX 90 XXX 555 AAA 20 PD Unlock Bypass (note12) 555 AAA 00 Chip Erase Sector Erase Reset Word Byte Word Byte 6 6 555 AAA 555 AAA AA AA Erase Suspend (note 13) 1 XXX 1 XXX 555 2AA 555 55 55 555 AAA 555 AAA 80 80 555 AAA 555 AAA AA AA 2AA 555 2AA 555 55 55 555 AAA SA B0 Erase Resume (note 14) 2AA 30 AUTOSELECT(note8) Manufacturer Code Device Code Word Byte Word Byte Security Sector Word Factory Protect Byte (Note 9) Sector/Secto r Block Protect Verify (note 10) 4 4 555 AAA 555 AAA AAA Byte Exit Security Sector Region Word Common Flash Interface (CFI) Query (note 15) Word Byte Byte Byte 4 555 2AA 555 555 AA 555 AAA 555 AAA 55 55 AA 55 AAA AAA 55 2AA 555 2AA 555 90 90 55 X01 X02 X06 90 555 AAA 555 AAA DA (note 16) 99/19 X02 AAA 55 X00 X03 90 555 555 AA 555 AAA 555 55 2AA AAA 3 2AA 2AA AA 555 4 Word AA 555 4 Word Enter Security Sector Region AA 00/01 X04 88 90 XXX 00 55 1 AA 98 Legend: X = Don't Care RA = Address of the memory location to be read. PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the #WE or #CE pulse, whichever happens later. PD = Data to be programmed at location PA. Data latches on the rising edge of #WE or #CE pulse, whichever happens first. RD = Data read from location RA during read operation. SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A20-A12 A20-A12 uniquely select any sector. - 29 - Publication Release Date: March 23, 2004 Revision A2 10 30 W19B(L)320ST/B 320ST/B Notes: 1. See Bus Operations Table for details. 2. All values are in hexadecimal 3. Except for the read cycle and the fourth cycle of the autoselect command sequence, all bus cycles are write cycles. 4. Data bits DQ15-DQ8 DQ15-DQ8 are don't care in command sequences, except for RD and PD. 5. Unless otherwise noted, address bits A20-A11 A20-A11 are don't cares. 6. No unlock or command cycles required when device is in read mode. 7. The Reset command is required to return to the read mode (or to the erase-suspend-read mode if previously in Erase Suspend) when the device is in the autoselect mode, or if DQ5 goes high (while the device is providing status information). 8. The fourth cycle of the autoselect command sequence is a read cycle. Data bits DQ15-DQ8 DQ15-DQ8 are don't care. See the Autoselect Command Sequence section for more information. 9. The data is 99h for factory locked and 19h for not factory locked. 10. The data is 00h for an unprotected sector/sector block and 01h for a protected sector/sector block. 11. The Unlock Bypass command is required prior to the Unlock Bypass Program command. 12. The Unlock Bypass Reset command is required to return to the read mode when the device is in the unlock bypass mode. 13. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Erase Suspend command is valid only during a sector erase operation. 14. The Erase Resume command is valid only during the Erase Suspend mode. 15. Command is valid when device is ready to read array data or when device is in autoselect mode. 16. See Autoselect Codes table for device ID information 7.5 Write Operation Status DQ7 (Note 2) DQ6 DQ5 (Note1) DQ3 DQ2 (Note 2) RY/#BY Embedded Program Algorithm #DQ7 Toggle 0 N/A No toggle 0 Embedded Erase Algorithm STATUS Standard Mode Erase Suspend Mode EraseSuspendRead 0 Toggle 0 1 Toggle 0 Erase Suspended Sector 1 No toggle 0 N/A Toggle 1 Non-Erase Suspended Sector Data Data Data Data Data 1 #DQ7 Toggle 0 N/A N/A 0 Erase-Suspend-Program Notes: 1. DQ5 switches to `1' when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. Refer to the section on DQ5 for more information. 2. DQ7 and DQ2 requires a valid address when reading status information. Please refer to related sections for details. - 30 - W19B(L)320ST/B 320ST/B 7.6 Temporary Sector Unprotect Algorithm START #RESET = VID (Note 1) Perform Erase or Program Operations #RESET = VIH Temporary Sector Unprotect Completed (Note 2) Notes: 1. All protected sectors unprotected (If #WP/ACC = VIL, outermost boot sectors will remain protected). 2. All previously protected sectors are protected once again. - 31 - Publication Release Date: March 23, 2004 Revision A2 W19B(L)320ST/B 320ST/B 7.7 In-System Sector Protect/Unprotect Algorithms START START PLSCNT=1 #RESET=VID Wait 1 µ s No Temporary Sector Unprotect Mode Protect all sectors The indicated portion of the sector protect algorithm must be performed for all unprotected sectors prior to issuing the first sector unprotect address PLSCNT=1 #RESET=V ID Wait 1 µ s First Write Cycle=60h? First Write Cycle=60h? Yes All sector protected? No Sector Protect: Write 60h to sector address with A6=0,A1=1,A0=0 Yes Set up first sector address Wait 150 µ s Increment PLSCNT Sector Unrotect: Write 60h to sector address with A6=1,A1=1,A0=0 Reset PLSCNT=1 Wait 15 mS Increment PLSCNT A1=1,A0=0 Verity Sector Unprotect:Write 40h to sector address with A6=1, Read from sector address with A6=0, A1=1,A0=0 No A1=1,A0=0 Read from sector address with A6=1, A1=1,A0=0 No PLSCNT =25? Data=01h? Yes No Yes Device failed Protect another sector? PLSCNT =1000? Yes Remove V ID from #RESET Data=00h? Yes No Device failed Write reset command Sector Protect complete No Set up next sector address Yes No Sector Protect Algorithm Temporary Sector Unprotect Mode Yes Set up sector address Verity Sector Protect:Write 40h to sector address with A6=0, No Sector Unprotect Algorithm Last sector verified Yes Remove VID from #RESET Write reset command Sector Unprotectt complete - 32 - W19B(L)320ST/B 320ST/B 7.8 Program Algorithm START Write Program Command Sequence Data Poll from System Embedded Program algorithm in progress Verify Data? No Yes No Increment Address Last Address? Yes Programming Completed 7.9 Erase Algorithm START Write Program Command Sequence (Note1,2) Data Poll to Erasing Bank from System Embedded Erase algorithm in progress No Data=FFh? Yes Erase Completed Notes: 1. See Command Definitions Table for erase command sequence details. 2. See DQ3 section for the sector erase timer details. - 33 - Publication Release Date: March 23, 2004 Revision A2 W19B(L)320ST/B 320ST/B 7.10 Data Polling Algorithm START Read DQ7-DQ0 Addr=VA Yes DQ7=Data? No No DQ5=1? Yes Read DQ7-DQ0 Addr=VA DQ7=Data? Yes No FAIL PASS Notes: 1. VA = Valid address for programming. During a sector erase operation; a valid address is any sector address within the sector being erased. During chip erase, a valid address is any non-protected sector address. 2. DQ7 should be rechecked even if DQ5 = "1" because DQ7 may change simultaneously with DQ5. - 34 - W19B(L)320ST/B 320ST/B 7.11 Toggle Bit Algorithm START Read DQ7-DQ0 Read DQ7-DQ0 No Toggle Bit =Toggle? Yes No DQ5=1? Yes Read DQ7-DQ0 Twice No Toggle Bit =Toggle? Yes Program/Erase Operation Not Complete,Write Reset Command Program/Erase Complete Note: The system should recheck the toggle bit even if DQ5 ="1" because the toggle bit may stop toggling as DQ5 changes to "1". See the subsections on DQ6 and DQ2 for more information - 35 - Publication Release Date: March 23, 2004 Revision A2 W19B(L)320ST/B 320ST/B 8. ELECRICAL CHARACTERISTICS 8.1 Absolute Maximum Ratings PARAMETER RATING UNIT Storage Temperature Plastic Packages -65 to +150 °C Ambient Temperature with Power Applied -65 to +125 °C Voltage with Respect to Ground VDD (Note 1) -0.5 to +4.0 V A9, #OE, and #RESET (Note 2) -0.5 to +12.5 V #WP/ACC -0.5 to +10.5 V -0.5 to VDD +0.5 V 200 mA All other pins (Note 1) Output Short Circuit Current (Note 3) Notes: 1. Minimum DC voltage on input or I/O pins is -0.5 V. During voltage transitions, input or I/O pins may overshoot VSS to -2.0 V for periods of up to 20 nS. Maximum DC voltage on input or I/O pins is VDD +0.5 V. During voltage transitions, input or I/O pins may overshoot to VDD +2.0 V for periods up to 20 nS. 2. Minimum DC input voltage on pins A9, #OE, #RESET, and #WP/ACC is -0.5 V. During voltage transitions, A9, #OE, #WP/ACC, and #RESET may overshoot VSS to -2.0 V for periods of up to 20 nS. Maximum DC input voltage on pin A9 is +12.5 V which may overshoot to +14.0 V for periods up to 20 nS. Maximum DC input voltage on #WP/ACC is +9.5 V which may overshoot to +12.0 V for periods up to 20 nS. 3. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second. Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. 8.2 Operating Ranges PARAMETER RATING Industrial Ambient Temperature (TA) -40 to +85 Commercial 0 to +70 Extend VDD Supply Voltages UNIT -20 to +85 W19B320S W19B320S 2.7 to 3.6 W19L320S W19L320S 3.0 to 3.6 °C Operating ranges define those limits between which the functionality of the device is guaranteed. - 36 - V W19B(L)320ST/B 320ST/B 8.3 DC Characteristics 8.3.1 CMOS Compatible PARAMETER SYM. TEST CONDITIONS LIMITS MIN. TYP. MAX. UNIT Input Load Current ILI VIN =VSS to VDD, VDD = VDD (Max.) - - ±3.0 µA A9 Input Load Current ILIT VDD = VDD (Max.), A9 = 12.5 V - - 35 µA #RESET Input Load Current ILR VDD = VDD (Max.), #RESET = 12.5 V - - 35 µA Output Leakage Current ILO VOUT =VSS to VDD, VDD =VDD (Max.) - - ±1.0 µA #CE = VIL, #OE = VIH 5 MHz - 10 16 mA Byte Mode 1 MHz 2 4 mA #CE = VIL, #OE = VIH 5 MHz 10 16 mA Word Mode 1 MHz 2 4 mA VDD Active Read Current (Note 1, 2) ICC1 VDD Active Write Current (Note 2, 3) ICC2 #CE = VIL, #OE = VIH, #WE = VIL - 15 45 mA VDD Standby Current (Note 2) ICC3 #CE, #RESET = VDD ±0.3V - 0.2 5 µA VDD Reset Current (Note 2) ICC4 #RESET = VSS ±0.3V - 0.2 5 µA Automatic Sleep Mode Current (note 2, 4) ICC5 VIH = VDD ±0.3V, VIL = VSS ± 0.3V - 0.2 5 µA Input Low Voltage VIL - -0.5 - 0.8 V Input High Voltage VIH - 0.7 x VDD - VDD +0.3 V Voltage for Autoselect and Temporary Sector protect/ Unprotect and Program Acceleration VHH VDD = 3.0V ±10% (W19B320S W19B320S) or VDD = 3.3V ±10% (W19L320S W19L320S) 8.5 - 9.5 V Voltage for Autoselect and Temporary Sector Unprotected VID VDD = 3.0V ±10% (W19B320S W19B320S) or VDD = 3.3V ±10% (W19L320S W19L320S) 8.5 - 12.5 V Output Low Voltage VOL IOL = 4.0 mA, VDD = VDD (Min.) - - 0.45 V 0.85 x VDD - - V - - VOH1 IOH = -2.0 mA, VDD = VDD (Min.) Output High Voltage VOH2 IOH = -100 µA, VDD = VDD (Min.) VDD0.4 Notes: 1. 2. 3. 4. The ICC current listed is typically less than 2 mA/MHz, with #OE at VIH. Maximum ICC specifications are tested with VDD = VDD max. ICC active while Embedded Erase or Embedded Program is in progress. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 nS. Typical sleep mode current is 200 nA. - 37 - Publication Release Date: March 23, 2004 Revision A2 W19B(L)320ST/B 320ST/B 8.4 AC Characteristics 8.4.1 Test Condition TEST CONDITION 90 nS Output Load UNIT 1 TTL gate Output Load Capacitance, CL (including jig capacitance) 100 pF 5 nS 0 - 3.0 V Input Timing Measurement Reference Levels 1.5 V Output Timing Measurement Reference Levels 1.5 V Input Rise and Fall Times Input Pulse Levels 8.4.2 AC Test Load and Waveforms +3.3V 2.7K D OUT 6.2K 100 pF (Including Jig and Scope) Input Output 3V 1.5V 1.5V 0V Test Point - 38 - Test Point W19B(L)320ST/B 320ST/B 8.4.3 Read-Only Operations PARAMETER SYM. TEST SETUP 90 nS UNIT MIN. MAX. 90 - nS Read Cycle Time TRC Address to Output Delay TACC #CE, #OE =VIL - 90 nS Chip Enable to Output Delay TCE #OE, = VIL - 90 nS Output Enable to Output Delay TOE - 40 nS Chip Enable to Output High Z TDF - 16 nS Output Enable to Output High Z TDF - 16 nS Output Hold Time From Address. #OE or #CE Whichever Occurs First TOH 0 - nS 0 - nS 10 - nS Read Output Enable Hold Time Toggle and #Data polling TOEH Note: Not 100 % tested 8.4.4 Hardware Reset (#RESET) PARAMETER SYM. MIN. MAX. UNIT #RESET PIN Low (During Embedded Algorithms) to Read Mode TReady - 20 µS #RESET Pin Low (Not During Embedded Algorithms) to Read Mode TReady - 500 nS #RESET Pulse Width TRP 500 - nS Reset High Time Before Read TRH 50 - nS #RESET Low to Standby Mode TRPD 20 - µS RY/#BY Recovery Time TRB 0 - nS Note: Not 100 % tested 8.4.5 Word/Byte Configuration (#BYTE) PARAMETER SYM. 90 nS MIN. MAX. UNIT #CE to #BYTE Switching Low or High TELFL/TELFH - 5 nS #BYTE Switching Low to Output High Z TFLQZ - 16 nS #BYTE Switching High to Output Active TFHQV 90 - nS - 39 - Publication Release Date: March 23, 2004 Revision A2 W19B(L)320ST/B 320ST/B 8.4.6 Erase And Program Operation PARAMETER SYM. 90 nS MIN. TYP. MAX. UNIT Write Cycle Timing TWC 90 - - nS Address setup Time TAS 0 - - nS Address Setup Timing to #OE low during toggle bit polling TASO 15 - - Address Hold Time TAH 45 - - nS Address Hold Time From #CE or #OE high during toggle bit polling TAHT 0 - - nS Data Setup Time TDS 45 - - nS Data Hold Time TDH 0 - - nS Output Enable High During toggle bit polling TOEPH 20 - - nS Read Recovery Time Before Write (#OE High to #WE Low) TGHWL 0 - - nS #CE Setup Time TCS 0 - - nS #CE HOLD Time TCH 0 - - nS Write Pulse Width TWP 35 - - nS Write Pulse Width High TWPH 30 - - nS Latency Between Read and Write Operation TSR/W 0 - - nS Byte TPB - 5 - µS Word TPW - 7 - µS TACCP - 4 - µS Sector Erase Time TSE - 0.7 - sec VDD Setup Time (Note 1) TVCS 50 - - µS Write Recovery Time from RY/#BY TRB 0 - - nS TBUSY 90 - - nS Programming Time Accelerated Programming Time Byte Word Program/Erase Valid to RY/#BY Delay nS Note: Not 100 % tested 8.4.7 Temporary Sector Unprotect PARAMETER SYM. MIN. MAX. UNIT VID Rise and Fall Time (See Note) TVIDR 500 - nS VHH Rise and Fall Time (See Note) TVHH 250 - nS #RESET setup Time for Temporary Sector Unprotect TRSP 4 - µS #RESET Hold Time from RY/#BY High for Temporary Sector Unprotect TRRB 4 - µS Note: Not 100 % tested - 40 - W19B(L)320ST/B 320ST/B 8.4.8 Alternate #CE Controlled Erase and Program Operations 90 nS PARAMETER SYM. MIN. TYP. MAX. (Note3) UNIT (Note4) Write Cycle Time (Note 1) TWC 90 - - nS Address Setup Time TAS 0 - - nS Address Hold Time TAH 45 - - nS Data Setup Time TDS 45 - - nS Data Hold Time TDH 0 - - nS TGHEL 0 - - nS #WE Setup Time TWS 0 - - nS #WE Hold Time TWH 0 - - nS #CE Pulse Width TCP 35 - - nS #CE Pulse Width High TCPH 30 - - nS Byte TPB - 5 150 Word TPW - 7 210 TACCP - 4 120 µS Sector Erase Time (Note 2) TSE - 0.7 15 Sec Chip Erase Time (Note 2) TCE - 49 - Sec Byte TCPB - 21 63 Word TCPW - 14 42 Read Recover Time Before Write (#OE High to #WE Low) Programming Time (Note 6) Accelerated Programming Time (Note 6) Chip Program Time (Note 5) Byte Word µS Sec Notes: 1. Not 100 % tested. 2. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure. 3. Typical program and erase time assume the following conditions :25°C, 3.0 V VDD, 10,000 or 100,000 cycles .Additionally, programming typicals assume checkerboard pattern. 4. Under worst case conditions of 90°C, VDD = 2.7V for W19B320S W19B320S or VDD = 3.0V for W19L320S W19L320S, 10,000 or 100,000 cycles. 5. The typical chip programming time is considerably less than the maximun chip programming time listed,since most bytes program faster than maximun program times listed. 6. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. 7. The device has a minimum erase and program cycle endurance of 10,000 or100,000 cycles. - 41 - Publication Release Date: March 23, 2004 Revision A2 W19B(L)320ST/B 320ST/B 9. TIMING WAVEFORMS 9.1 AC Read Waveform TRC Address Addresses Stable TACC #CE TRH #OE TRH TOE TDF TOEH #WE TCE T OH High-Z High-Z Outputs Output Vaild #RESET RY/#BY 0V 9.2 Reset Waveform RY/#BY #OE,#CE TRH #RESET T RP TReady Reset Timing NOT during Embedded Algorithms TReady RY/#BY T RB #OE,#CE #RESET TRP Reset Timings during Embedded Algorithms - 42 - W19B(L)320ST/B 320ST/B 9.3 #BYTE Waveform for Read Operation #CE #OE #BYTE #BYTE Switching from word to byte mode TELFL Data Output (DQ0-DQ14 DQ0-DQ14) DQ0-DQ14 DQ0-DQ14 Data Output (DQ0-DQ7) DQ15 Output DQ15/A-1 DQ15/A-1 TELFH Address Input TFLQZ #BYTE #BYTE Switching from byte to word mode DQ0-DQ14 DQ0-DQ14 DQ15/A-1 DQ15/A-1 Data Output (DQ0-DQ7) Address Input Data Output (DQ0-DQ14 DQ0-DQ14) DQ15 Output T FHQV 9.4 #BYTE Waveform for Write Operation #CE The falling edge of the last #WE signal #WE #BYTE T SET (TAS ) THOLD (T ) AH Note: Refer to the Erase /Program Operations table for TAS and TAH Specifications. - 43 - Publication Release Date: March 23, 2004 Revision A2 W19B(L)320ST/B 320ST/B 9.5 Programming Waveform Program Command Sequence (last two cycles) TWC Address Read Status Data (last two cycles) T AS 555h PA PA PA T AH #CE T CH #OE TWP #WE TPW TWPH TDH TCS T DS A0h Data Status PD DOUT T BUSY TRB RY/#BY VDD T VCS Notes: 1. PA = program address, PD = program data, Dout is the true data at the program address. 2. Illustration shows device in word mode. 9.6 Accelerated Programming Waveform V HH #WP/ACC V IL or V IL or V IH TVHH TVHH - 44 - V IH W19B(L)320ST/B 320ST/B 9.7 Chip/Sector Erase Waveform Erase Command Sequence (last two cycles) TWC T AS 2AAh Address Read Status Data VA SA VA 555h for chip erase TAH #CE T CH #OE TWP #WE TCS Data TWPH TDS 55h TSE TDH In Progress 30h 10 for Chip Erase TBUSY RY/#BY VDD Complete TRB TVCS Notes: 1. SA= sector address (for Sector Erase), VA= Valid Address for reading status data (see "Write operation Status"). 2. These waveforms are for the word mode 9.8 #Data Polling Waveform (During Embedded Algorithms) T RC Addresses VA VA VA ACC T T CE #CE TCH TOE #OE T OEH #WE TDF TOH High Z DQ7 Complement Complement True Valid Data DQ0-DQ6 Status Data Status Data True Valid Data T BUSY High Z RY/#BY Note: VA= Valid Address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle. - 45 - Publication Release Date: March 23, 2004 Revision A2 W19B(L)320ST/B 320ST/B 9.9 Toggle Bit Waveform (During Embedded Algorithms) T AHT TAS Addresses TAHT TASO #CE TCEPH TOEH #WE TOEPH #OE TDH DQ6/DQ2 Valid Status Valid Data (first read) TOE Valid Status Valid Status (second read) (stop toggling) Valid Data RY/#BY Note: VA = Valid address;not requires for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle. 9.10 DQ 2 vs. DQ6 Waveform Enter Embedded Erasing Enter Erase Suspend Program Erase Suspend Erase Resume #WE Erase Erase Suspend Read Erase Suspend Program Erase Suspend Read Erase Erase Complete DQ6 DQ2 Note: DQ2 toggles only when read at an address within an erase-suspended sector. The sysytem may use #OE or #CE to toggle DQ2 and DQ6. - 46 - W19B(L)320ST/B 320ST/B 9.11 Temporary Sector Unprotect Timing Diagram VID #RESET VID VSS ,VIL, or VIH VSS ,VIL, or VIH TVIDR TVIDR Program or Erase Command Sequence #CE #WE TRSP TRRB RY/#BY 9.12 Sector/Sector Block Protect and Unprotect Timing Diagram VID #RESET VIH SA,A6, A1,A0 Valid* Valid* Sector/sector Block Protect or Unprotect 60h DATA Valid* Verify 40h 60h Status Sector/Sector Block Protect:150 s, Sector/Sector Block Unprotect:15ms #CE s 1 #WE #OE *For sector protect,A6=0,A1=1,A0=0.For sector unprotect ,A6=1,A1=1,A0=0 - 47 - Publication Release Date: March 23, 2004 Revision A2 W19B(L)320ST/B 320ST/B 9.13 Alternate #CE Controlled Write (Erase/Program) Operation Timing #Data Polling Address PA for program 555 for program 2AA for erase 555 for chip erase TWC TWH t GHEL #WE TAS #OE PA SA for sector