NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
| Part | Manufacturer | Description | Type | Ordering |
| Viterbi Decoder | Lattice Semiconductor | Viterbi Decoder Data Sheet |
9 pages, |
Original |  |
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| Viterbi Decoders | Altera Corporation | Viterbi Decoders White Paper |
12 pages, |
Original | |
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| Catalog Datasheet Results | Type | Document Tags |
| Abstract: Viterbi Compiler Errata Sheet June 2005, Compiler Version 4.2.2 Introduction This document addresses known errata and documentation changes for version 4.2.2 of the Viterbi Compiler. Errata are design functional defects or errors. Errata may cause the Viterbi Compiler to deviate from , clarifications will be incorporated into an upcoming release of the Viterbi Compiler. Viterbi Compiler v4.2.2 Issues Altera has identified the following issue that affects the Viterbi Compiler v4.2.2: 1. ... | Original |
4 pages, |
introduction to viterbi decoder viterbi Viterbi Decoder datasheet abstract |
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| Abstract: Viterbi Compiler Errata Sheet December 2006, Compiler Version 7.0 This document addresses known errata and documentation issues for the Viterbi Compiler version 7.0. Errata are functional defects or errors, which may cause the Viterbi Compiler to deviate from published specifications. , or product documents. Table 1 shows the issues that affect the Viterbi Compiler v7.0. Table 1. Viterbi Compiler v7.0 Issues Issue Page Hybrid & Parallel Architectures Can Be Selected ... | Original |
4 pages, |
Viterbi Decoder datasheet abstract |
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| Abstract: Viterbi Compiler Errata Sheet December 2006, Compiler Version 6.1 This document addresses known errata and documentation issues for the Viterbi Compiler version 6.1. Errata are functional defects or errors, which may cause the Viterbi Compiler to deviate from published specifications. , or product documents. Table 1 shows the issues that affect the Viterbi Compiler v6.1. Table 1. Viterbi Compiler v6.1 Issues Issue Page Hybrid & Parallel Architectures Can Be Selected ... | Original |
4 pages, |
Viterbi Decoder datasheet abstract |
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| Abstract: Viterbi Compiler Errata Sheet October 2006, Compiler Version 4.4.0 This document addresses known errata and documentation issues for the Viterbi Compiler version 4.4.0. Errata are functional defects or errors, which may cause the Viterbi Compiler to deviate from published specifications. , or product documents. Table 1 shows the issues that affect the Viterbi Compiler v4.4.0. Table 1. Viterbi Compiler v4.4.0 Issues Issue Page Hybrid & Parallel Architectures Can Be Selected ... | Original |
3 pages, |
datasheet abstract |
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| Abstract: Viterbi Compiler Errata Sheet April 2005, Compiler Version 4.2.1 Introduction This document addresses known errata and documentation changes for version 4.2.1 of the Viterbi Compiler. Errata are design functional defects or errors. Errata may cause the Viterbi Compiler to deviate from , clarifications will be incorporated into an upcoming release of the Viterbi Compiler. Viterbi Compiler v4.2.1 Issues Altera has identified the following issue that affects the Viterbi Compiler v4.2.1: 1. ... | Original |
2 pages, |
Viterbi Decoder viterbi datasheet abstract |
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| Abstract: error at , >\viterbiv4.2.0\sim_lib\vhdl\testbench, where is the installation directory. To correct these files , Viterbi Compiler Errata Sheet February 2005, Compiler Version 4.2.0 Introduction This document addresses known errata and documentation changes for version 4.2.0 of the Viterbi Compiler. Errata are design functional defects or errors. Errata may cause the Viterbi Compiler to deviate from ... | Original |
3 pages, |
Viterbi Decoder datasheet abstract |
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| Abstract: Viterbi Compiler Errata Sheet September 2005, Compiler Version 4.2.3 Introduction This document addresses known errata and documentation changes for version 4.2.3 of the Viterbi Compiler. Errata are design functional defects or errors. Errata may cause the Viterbi Compiler to deviate from , clarifications will be incorporated into an upcoming release of the Viterbi Compiler. Viterbi Compiler v4.2.3 Issues Altera has identified the following issue that affects the Viterbi Compiler v4.2.3 ... | Original |
2 pages, |
datasheet abstract |
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| Abstract: Viterbi Compiler Errata Sheet July 2007, Compiler Version 7.1 This document addresses known errata and documentation issues for the Viterbi Compiler version 7.1. Errata are functional defects or errors, which may cause the Viterbi Compiler to deviate from published specifications. , sheet on the Altera® website: www.altera.com/literature/es/es_viterbi_71.pdf Viterbi Compiler v7.1 Issues Altera has identified the following issue that affects the Viterbi Compiler v7.1. Trellis ... | Original |
2 pages, |
Trellis datasheet abstract |
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| Abstract: Soft-Decision Viterbi Decoder January 10, 2000 Product Specification AllianceCORETM Facts , Soft-Decision Viterbi DecoderCAST, Inc. Branch Metric Unit Add Compare Select Trace Back Iin [2 , RST X9008 X9008 Figure 1: Soft-Decision Viterbi Decoder Block Diagram General Description Branch Metric Unit (BMU) A Viterbi decoder performs a maximum likelihood detection of 1-bit data transmitted , from the Convolutional Encoder to the Viterbi Decoder. The Branch Metric Unit calculates the ... | Original |
4 pages, |
Implementation of convolutional encoder viterbi decoder soft bit verilog hdl code for encoder 3 to 8 bit decoder vhdl IEEE format acs transistor viterbi algorithm Convolutional vhdl code for data memory vhdl code for bpsk modulation qpsk implementation using verilog Viterbi Decoder V50-6 V50-6 abstract |
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| Abstract: Viterbi Compiler v4.1.0 Errata Sheet October 2004, ver. 1.0 Introduction This document addresses known errata and documentation changes for version 4.1.0 of the Viterbi Compiler. Errata are design functional defects or errors. Errata may cause the Viterbi Compiler to deviate from published , incorporated into the next version release of the Viterbi Compiler. Viterbi Compiler 4.1.0 Issues Altera has identified the following issues that affect the Viterbi Compiler v4.1.0: 1. Polynomials ... | Original |
8 pages, |
Viterbi Decoder vhdl code for modulation verilog code for TCM decoder datasheet abstract |
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| Microsoft Developer Studio Workspace File, Format Version 5.00 # WARNING: DO NOT EDIT OR DELETE THIS WORKSPACE FILE! ############################################################################### Project: "viterbi_hmm"=".\viterbi_hmm.dsp" - Package Owner= Package= {{{ begin source code control "$/viterbi_hmm", IQBAAAAA . end source code control }}} Package= {{{ }}} ############################################################################### Global: Package= {{{ begin source code control "$/viterbi_hmm", IQBAAAAA . end www.datasheetarchive.com/download/2787525-279939ZC/samples.zip (viterbi_hmm.dsw) |
Intel | 04/03/1999 | 5.96 Kb | ZIP | samples.zip |
| Microsoft Developer Studio Workspace File, Format Version 5.00 # WARNING: DO NOT EDIT OR DELETE THIS WORKSPACE FILE! ############################################################################### Project: "viterbi_hmm"=".\viterbi_hmm.dsp" - Package Owner= Package= {{{ begin source code control "$/viterbi_hmm", IQBAAAAA . end source code control }}} Package= {{{ }}} ############################################################################### Global: Package= {{{ begin source code control "$/viterbi_hmm", IQBAAAAA . end www.datasheetarchive.com/download/88356709-284212ZC/samples.zip (viterbi_hmm.dsw) |
Intel | 04/03/1999 | 5.96 Kb | ZIP | samples.zip |
| # $Header: viterbi.wai,v 1.3 1998/07/01 18:26:06 tonyw Exp $ module=Viterbi Decoder description=Viterbi_Decoder author=AllianceCORE elaborator=NullElaborator symbolGenerator= customizerGUI= chipFamily=XC4000E XC4000E XC4000E XC4000E Virtex Spartan_II dieExceptions= version=1.15 path=alliance.catalog www.datasheetarchive.com/download/55018419-977412ZC/rp069e2.zip (viterbi.wai) |
Xilinx | 22/02/2000 | 3361.97 Kb | ZIP | rp069e2.zip |
| App Note Abstract: IMPLEMENTING V.32BIS 32BIS 32BIS 32BIS VITERBI DECODING ON THE TMS320C62XX TMS320C62XX TMS320C62XX TMS320C62XX DSP IMPLEMENTING V.32BIS 32BIS 32BIS 32BIS VITERBI DECODING ON THE TMS320C62XX TMS320C62XX TMS320C62XX TMS320C62XX DSP This paper describes the implementation of the V (DSP). The V.32bis Viterbi decoder algorithm is based on a soft-decision maximum-likelihood decoding of the V.32bis Viterbi algorithm. Appendix B contains the C62xx assembly code implementation. Appendix C contains the main C program to test the performance of the Viterbi code. View the complete www.datasheetarchive.com/files/texas-instruments/sc/psheets/abstract/apps/spra444.htm |
Texas Instruments | 01/07/1998 | 4.82 Kb | HTM | spra444.htm |
| App Note Abstract: VITERBI IMPLEMENTATION ON THE TMS320C5X TMS320C5X TMS320C5X TMS320C5X FOR V.32 MODEMS VITERBI IMPLEMENTATION ON THE TMS320C5X TMS320C5X TMS320C5X TMS320C5X FOR V.32 MODEMS The TMS320C5x 16-bit fixed-point digital signal processor (DSP) is well suited for data communications applications, especially the soft decision encoding/decoding found in V.32 modems. This document discusses the V.32 standard, the Viterbi encoder, and the Viterbi decoder. A performance analysis of the V.32 modem application is provided. A code source for this www.datasheetarchive.com/files/texas-instruments/sc/psheets/abstract/apps/spra099.htm |
Texas Instruments | 01/07/1998 | 4.13 Kb | HTM | spra099.htm |
| App Note Abstract: VITERBI DECODING TECHNIQUES IN THE TMS320C54X TMS320C54X TMS320C54X TMS320C54X FAMILY APPLICATION REPORT VITERBI DECODING TECHNIQUES IN THE TMS320C54X TMS320C54X TMS320C54X TMS320C54X FAMILY APPLICATION REPORT Convolutional coding is the perferred method of error correction to overcome transmission distortion in wireless communications. This document outlines the theory of convolutional coding and decoding and explains the programming techniques for Viterbi decoding on the TMS320C54x DSP family. Since the basic method is the same to decode any www.datasheetarchive.com/files/texas-instruments/sc/psheets/abstract/apps/spra071.htm |
Texas Instruments | 01/07/1998 | 4.23 Kb | HTM | spra071.htm |
| single CLB: HMAP symbol "< " (output ) FMAP symbol "FMAP_3285" (output signal=N943) FMAP symbol "< " (output ) FDCE symbol "< " (output www.datasheetarchive.com/files/xilinx/docs/rp0001b/rp01bd5.htm |
Xilinx | 29/02/2000 | 6.7 Kb | HTM | rp01bd5.htm |
| . Instead, the Viterbi decoding algorithm offers a more practical approach. The Viterbi decoding algorithm Pentium III processor, complex algorithms such as the Viterbi decoding algorithm can now be accelerated There are three steps to the Viterbi decoding algorithm [Rabner89]. The step that contains most of the : Figure 2. The recursion step of the Viterbi decoding algorithm figure 2. There are two ways the Streaming SIMD Extensions can be used to implement the Viterbi decoding www.datasheetarchive.com/files/intel/technologies/soluti~1/issue/stories/ss1.htm |
Intel | 04/05/1999 | 16.98 Kb | HTM | ss1.htm |
| Benefits Integrated Viterbi accelerator Reduces Viterbi butterfly update (compare ) featuring a dual and supports Viterbi accelerators 16-bit configuration capability www.datasheetarchive.com/files/texas-instruments/data/sc/docs/news/1995/95033.htm |
Texas Instruments | 08/02/1999 | 5.39 Kb | HTM | 95033.htm |
| Benefits Integrated Viterbi accelerator Reduces Viterbi butterfly update (compare ) featuring a dual and supports Viterbi accelerators 16-bit configuration capability www.datasheetarchive.com/files/texas-instruments/sc/docs/news/1995/95033.htm |
Texas Instruments | 03/01/1997 | 4.74 Kb | HTM | 95033.htm |