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VTERB-BLK-XM-U4 Lattice Semiconductor Corporation LICENSE VITERBI DECODER XP visit Digikey Buy
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VTERB-BLK-E3-UT4 Lattice Semiconductor Corporation LICENSE BLK VITERBI DECODER ECP3 visit Digikey Buy
VTERB-BLK-PM-UT4 Lattice Semiconductor Corporation IP CORE VITERBI DECODER ECP2M visit Digikey Buy
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Viterbi Decoder Datasheet

Part Manufacturer Description PDF Type
Viterbi Decoder Lattice Semiconductor Viterbi Decoder Data Sheet Original
Viterbi Decoders Altera Viterbi Decoders White Paper Original

Viterbi Decoder

Catalog Datasheet MFG & Type PDF Document Tags

GSM Viterbi

Abstract: Viterbi Decoder How to Implement a Viterbi Decoder on the StarCore SC140 Application Note Abstract The application note describes how to implement an efficient Viterbi decoder on the StarCore SC140. It begins , description of the StarCore SC140 special instructions that allow you to program an efficient Viterbi decoder , Implement a Viterbi Decoder on the StarCore SC140 Page i Table of Contents Chapter 6: Optimizations to the Viterbi Decoder Kernel . . . . . . . . . . . . . . . . 47 6.1 Memory Map of the Kernel . .
Motorola
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GSM Viterbi Trellis branch metric Convolutional trellis 5/6 decoder viterbi ANSC140VIT/D
Abstract: ispLever CORE TM Viterbi Decoder Userâ'™s Guide October 2005 ipug04_02.0 Lattice Semiconductor Viterbi Decoder Userâ'™s Guide Introduction Latticeâ'™s Viterbi Decoder core is a , given in the next section. Viterbi Decoder Basics Viterbi decoding is an efficient algorithm for , Figure 1, which uses a Viterbi decoder for decoding the convolutionally coded data. The digital data , demodulated and then decoded using the Viterbi decoder. The decoded output is equivalent to the transmitted Lattice Semiconductor
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LFX1200B FE680

X9009

Abstract: verilog code for BPSK Soft-Decision Viterbi Decoder April 19, 1999 Product Specification AllianceCORETM Facts Core , Trace-Back Length Number of ACS Element 1/2 7 3 55 4 Soft-Decision Viterbi Decoder Branch Metric Unit , : Soft-Decision Viterbi Decoder Block Diagram General Description A Viterbi decoder performs a maximum , 2 shows the simplified data path from the Convolutional Encoder to the Viterbi Decoder. The source , applications. The Viterbi Decoder netlist can also be delivered with customized parameter settings differing
Xilinx
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X9009 verilog code for BPSK qpsk implementation using verilog qpsk modulation VHDL CODE 2 bit address decoder coding using verilog hdl BPSK modulation VHDL CODE V50-6
Abstract: Block Viterbi Decoder Userâ'™s Guide June 2010 IPUG32_02.7 Table of Contents Chapter 1 , . 10 Configuring the Block Viterbi Decoder , . 12 Interfacing with the Block Viterbi Decoder , change without notice. IPUG32_02.7, June 2010 2 Block Viterbi Decoder Userâ'™s Guide Lattice , . 34 IPUG32_02.7, June 2010 3 Block Viterbi Decoder Userâ'™s Guide Chapter 1 Lattice Semiconductor
Original
2004-SC-PHY 2004-OFDM LFXP2-17E-7F484C D-2009 12L-1

5 to 32 decoder using 3 to 8 decoder vhdl code

Abstract: branch metric Soft-Decision Viterbi Decoder January 10, 2000 Product Specification AllianceCORETM Facts , RST X9008 Figure 1: Soft-Decision Viterbi Decoder Block Diagram General Description Branch Metric Unit (BMU) A Viterbi decoder performs a maximum likelihood detection of 1-bit data transmitted , from the Convolutional Encoder to the Viterbi Decoder. The Branch Metric Unit calculates the , for easy adaptation to a wide variety of applications. The Viterbi Decoder netlist can also be
Xilinx
Original
5 to 32 decoder using 3 to 8 decoder vhdl code 5 to 32 decoder using 3 to 8 decoder verilog QPSK using xilinx vhdl code for modulation vhdl code for bpsk modulation branch metric unit VHDL coding

Viterbi Trellis Decoder

Abstract: about the decoder ic Freescale Semiconductor, Inc. How to Implement a Viterbi Decoder on the StarCore SC140 , implement an efficient Viterbi decoder on the StarCore SC140. It begins with an overview of convolutional , instructions that allow you to program an efficient Viterbi decoder. The note describes how to efficiently , concludes with optimized assembly code for a complete Viterbi decoder according to the GSM TCH/FS standard , Viterbi Decoder on the StarCore SC140 This Product, For More Information On Go to: www.freescale.com
Motorola
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Viterbi Trellis Decoder about the decoder ic ic 7495 shift registers SP10 SP11 SP12

vhdl code for march c algorithm

Abstract: Viterbi Decoder Viterbi Decoder February 8, 1998 Product Specification AllianceCORETM Facts CAST, Inc , memory (RAM) word length Value 16 8 4 30 5 -4 8 Viterbi Decoder RstX Clk LoadData , General Description Viterbi_Memory A Viterbi decoder is used for decoding convolutional codes. It , example only. The Viterbi Decoder can be delivered in a specific format (see Ordering Information). The Viterbi Decoder core can be customized to include: Core Modifications Viterbi_AcsUnit ·
Xilinx
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XC4000XL vhdl code for march c algorithm sample vhdl code for memory write vhdl code for branch metric unit Viterbi ram memory vhdl trans metrics ram memory vhdl XC4013XL-09 XCS30-3

viterbi decoder for tcm decoders

Abstract: viterbi convolution 0 Viterbi Decoder v6.2 DS247 October 10, 2007 Product Specification 0 Introduction The Viterbi Decoder is used in many Forward Error Correction (FEC) applications and in systems where data are transmitted and subject to errors before reception. The Viterbi Decoder is compatible with , , compact Viterbi Decoder · Available for VirtexTM-II, Virtex-II Pro, Virtex-4, Virtex-5, SpartanTM , decoder · Serial architecture for small area This core implements a Viterbi Decoder for decoding
Xilinx
Original
IESS-308/309 viterbi decoder for tcm decoders viterbi convolution viterbi IESS-308/309 express card DVB XAPP551

Viterbi Trellis Decoder

Abstract: Viterbi Decoder Viterbi Decoder March 2003 IP Data Sheet Features General Description Parameterizable Viterbi decoder Viterbi decoding is an efficient algorithm for decoding convolutionally encoded sequences. In the Viterbi Decoder, the convolutional code sequences that have been corrupted by channel , Decoder Top-level Block Diagram din_0 dout din_1 din_2 clk valid Viterbi Decoder pd_out , 1 ip1016_01 Lattice Semiconductor Viterbi Decoder Figure 2. 1/2 Rate Convolutional
Lattice Semiconductor
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viterbi algorithm parallel viterbi convolution polynomials

XCV5LX50

Abstract: Convolutional Encoding Viterbi Decoding Using DSP 0 Viterbi Decoder v6.1 DS247 May 17, 2006 0 Product Specification Introduction The Viterbi Decoder is used in many Forward Error Correction (FEC) applications and in systems where data are transmitted and subject to errors before reception. The Viterbi Decoder is compatible with many common , Generator Features · High-speed, compact Viterbi Decoder · Available for VirtexTM-II, Virtex-II Pro , DS247_01_051806 BMU Costs to each state ACS TB Figure 1: Viterbi Decoder Block Diagram
Xilinx
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XCV5LX50 Convolutional Encoding Viterbi Decoding Using DSP

L64711

Abstract: OXF*9 . Preface v Chapter 6, Viterbi Decoder Module, describes the structure and operation of the Viterbi decoder module. Chapter 7, Deinterleaver Module, describes how the data stream is reordered , Output 4.4.6 Viterbi Decoder Output 4.4.7 Viterbi Depuncture/Synchronization Output Synchronization 5.1 Synchronization Scheme 5.2 Viterbi Decoder Synchronization 5.3 Reed-Solomon Deinterleaver Synchronization 5.4 Descrambler Synchronization Viterbi Decoder Module 6.1 Viterbi Decoder Architecture 6.1.1 Features 6.1.2 Code
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L64709 L64711 OXF*9 L6471 H14002 L64713 DB14-000011-00

scrambler satellite

Abstract: Viterbi Decoder Qualco/wva Q1650 k=7 MULTI-CODE RATE VITERBI DECODER 2.5, 10, 25 Mbps Data Rates Technical Data Sheet Powered by ICminer.com Electronic-Library Service CopyRight 2003 2 Q1650 Viterbi Decoder , CopyRight 2003 Q1650 Viterbi Decoder 3 CONTENTS Title Page FEATURES , .6 Convolutional Encoder.6 Viterbi Decoder , ICminer.com Electronic-Library Service CopyRight 2003 4 Q1650 Viterbi Decoder 4 FEATURES â'¢ Stand-Alone
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scrambler satellite AN1650-2 AN1650-1 R0702 qualcomm IQ InMarSat modulator DL90-1650

branch metric

Abstract: Viterbi Decoder needed for implementation of a Viterbi decoder. Motorola, Incorporated Semiconductor Products Sector , . . . . . . . . . . . . . . . . 2-3 2.3 Viterbi Decoder. . . . . . . . . . . . . . . . . . . . . . , . . . . . . . . 5-3 MOTOROLA Viterbi Decoder Implementation For More Information On This , Program Listing . . . . . . . . . . . B-1 B.1 16-Bit Enhanced Viterbi Decoder PROGRAM LISTING . . . . . , -Bit Enhanced Viterbi Decoder PROGRAM LISTING . . . . . . C-3 iv Viterbi Decoder Implementation For
Motorola
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DSP56300 DSP56600 IS-136 Viterbi Trellis Decoder texas APR40/D

Viterbi Decoder

Abstract: DSP56300 polynomials, the assembly code needed for implementation of a Viterbi decoder. © Freescale Semiconductor , Viterbi Decoder. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 2.4 , . . . . . . . . . . . . . . . . . . . . . . . . 5-3 Viterbi Decoder Implementation For More , Program Listing . . . . . . . . . . . B-1 B.1 16-Bit Enhanced Viterbi Decoder PROGRAM LISTING . . . . . , -Bit Enhanced Viterbi Decoder PROGRAM LISTING . . . . . . C-3 iv Viterbi Decoder Implementation For
Freescale Semiconductor
Original

MIL-STD-188-182

Abstract: MIL-STD-188-183 Dual Constraint Length Viterbi Decoder March, 1999, ver. 2.1.1_ Data Sheet (PN F805SC , Re-Programmable for Customized Interfaces and Processing Algorithms Viterbi Decoder Modes: v Dual Constraint , =7 rate 3/4, Punctured k=7 rate 7/8, and k=9, rate 3/4. Viterbi Decoder Function r (2:0 , Nova Engineering, Inc. Viterbi Decoder Data Sheet P1 = 171 (octal) Encoder Data In P2 = , Figure FEC-3: Viterbi Decoder Block Diagram Page 2 Nova Engineering, Inc. Viterbi Decoder Data
Nova Engineering
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MIL-STD-188-181 MIL-STD-188-182 MIL-STD-188-183 MIL-STD-188-183A MIl-STD-188-181B 16 bit qpsk VHDL CODE

branch metric

Abstract: Convolutional Encoder details and application Freescale Semiconductor, Inc. How to Implement a Viterbi Decoder on the StarCore SC140 , implement an efficient Viterbi decoder on the StarCore SC140. It begins with an overview of convolutional , instructions that allow you to program an efficient Viterbi decoder. The note describes how to efficiently , concludes with optimized assembly code for a complete Viterbi decoder according to the GSM TCH/FS standard , . 46 How to Implement a Viterbi Decoder on the StarCore SC140 This Product, For More Information
Motorola
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Convolutional Encoder details and application SP14 CH370

vhdl code for branch metric unit

Abstract: branch metric codes. The Viterbi decoder performs maximumlikelihood decoding to achieve optimum performance. However, the Viterbi decoder requires extensive hardware for computation and storage. The Viterbi algorithm , codes. The Viterbi decoder is especially good for short constraint length, and it makes decoding , time, and each branch represents a transition to other states at the next stage. The Viterbi decoder , e V i te rb i D e c o d e r A rc h i te c tu re The Viterbi decoder is divided into three
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AC121 A32200DX branch metric unit VHDL design vhdl program for branch metric unit Signal Path Designer

branch metric

Abstract: Viterbi Decoder code polynomials, the assembly code needed for implementation of a Viterbi decoder. Motorola , . . . . . . . . . . . . . . . 2-3 2.3 Viterbi Decoder. . . . . . . . . . . . . . . . . . . . . . . , 5-3 MOTOROLA Viterbi Decoder Implementation iii 5.2 5.3 Conclusions . . . . . . . . . , -Bit Enhanced Viterbi Decoder PROGRAM LISTING . . . . . . B-3 APPENDIX C 24-Bit Algorithm Program Listing . . . . . . . . . . . . . . C-1 C.1 24-Bit Enhanced Viterbi Decoder PROGRAM LISTING . . . . . . C
Motorola
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Convolutional decoder branch metric report

ram memory testbench vhdl

Abstract: testbench vhdl ram 16 x 4 Viterbi Decoder Megafunction Solution Brief 33 Target Applications: Data Communications , General Description The Viterbi decoder megafunction is used to decode convolutional codes. It can also , interference (ISI). Figure 1 shows the symbol for the Viterbi decoder megafunction. Figure 1. Viterbi Decoder Symbol Bits2Smu[X.0] Web RstX CLK Oeb Viterbi Decoder LoadData AdSmu[X , adapted to a wide variety of applications. Figure 2 shows the block diagram for the Viterbi decoder
Altera
Original
EPF10K30A EPF6016 ram memory testbench vhdl testbench vhdl ram 16 x 4 ram memory testbench vhdl code acs transistor

Viterbi Decoder

Abstract: viterbi . "Parallel Viterbi Decoder Fails When Number of Code Sets 5 and N = 2" on page 1. 2. "Parallel Viterbi Decoder May Fail to Assert sink_ena_master" on page 2. 3. "Parallel Viterbi Decoder May Produce Spurious source_val Assertions" on page 3. Parallel Viterbi Decoder Fails When Number of Code Sets 5 and N = 2 For the parallel Viterbi decoder, if you choose 5 or more for Number of Code Sets with every code set with N = 2 and in Viterbi mode, the Viterbi decoder fails in one of two ways. If
Altera
Original
introduction to viterbi decoder 800-EPLD
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