VSC9112 STS-192/STM-64 GR-253-CORE G52210-0 STS-48 STS-192 BIP-384 D4-D12 - Datasheet Archive

 

SEMICONDUCTOR CORPORATION Datasheet STS-48c Physical Layer Packet/ATM Over SONET/SDH Device VSC9112 Features · Prepared

 

VITESSE SEMICONDUCTOR CORPORATION Datasheet STS-48c Physical Layer Packet/ATM Over SONET/SDH Device VSC9112 VSC9112 Features · Prepared for STS-192/STM-64 STS-192/STM-64 Applications · Dual Mode STS-48c/STM-16c to Packet/ ATM Framing Device for User Network Interface and Network Node Interface Applications · Provides JTAG TAP controller Conforming to the IEEE 1149.1 standard · Generic 8-bit Microprocessor Interface · Terminates and Generates SONET/SDH Section, Line, and Path Layers · 16-bit PECL Interface to High-speed MUX/ DEMUX Transceivers · Dedictated Ports for Section/Line Overhead Access (Extraction/Insertion) · +3.3V Power Supply · 0.35 Micron CMOS Technology · Extensive SONET/Packet/Cell Performance Monitoring Features · Compliant with SONET and SDH Requirements as Stated in ANSI T1.105, Bellcore GR-253-CORE GR-253-CORE and ITU-T G.707 Documents · Programmable Packet/Cell Filtering and Discarding Functionalities · Compliant with PPP in HDLC-like Framing as Defined in IETF RFC 1619/1661/1662 · Industry Compliant Drop Side Packet/Cell Interface for Single-PHY Applications TDO TDI TCK TMS TRSTB OE TTOHCLK TTOHREN TTOHFP TTOHEN TTOH[3.0] TXRCLK TSPCLK1 TSPFP1 TSPREN1 TSPDAT1 TSPCLK2 TSPFP2 TSPREN2 TSPDAT2 VSC9112 VSC9112 Block Diagram Transport Overhead Insertion TOAP Line Side Interface CLKRSTEN Section Generation TSOP Line Generation TLOP 32 32 Section Trace Buffer SSTB SPE/Path Generation TPOP 32 Packet/ATM Mapping TPP/TACP 32 Drop Side Interface Packet Interface/UTOPIA Interface 32 +/- JTAG TAP Path Trace Buffer SPTB RLCLK+/RLIN[15.0]+/RLPRTY+/RLFP+/Section Termination RSOP Line Termination RLOP 32 32 SPE/Path Termination RPOP 32 Packet/ATM Demapping RPP/RACP G52210-0 G52210-0, Rev. 4.3 3/30/00 BERM LCD-P RTOHCLK RTOHVALID RTOHFP RTOH[3.0] RSPFP RSPCLK2 RSPVALID2 RSPDAT2 RSPCLK1 RSPVALID1 RSPDAT1 LOS LOF RXRCLK LOPC Transport Overhead Extraction ROAP 32 PIF/UIF CPU RFCLK RFCLKO RENB RVAL RSOP RPRTY RDAT[31:0] RMOD[1.0] REOP RERR GPIOO[7.0] PMTICK D[7.0] A[8.0] ALE CSB WRB RDB RSTB INTB 32 LIF TFCLK TFCLKO TENB DTPA TSOP TPRTY TDAT[31:0] TMOD[1.0] TEOP TERR © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 · 805/388-3700 · FAX: 805/987-5896 Page 1 VITESSE SEMICONDUCTOR CORPORATION STS-48c Physical Layer Packet/ATM Over SONET/SDH Device Datasheet VSC9112 VSC9112 Functional Overview The VSC9112 VSC9112 is a dual mode SONET/SDH to Packet/ATM framing device. In the Packet over SONET (POS) mode, this device can be used in equipment interconnecting IP/PPP/HDLC equipment over public or private SONET/SDH networks. Similarly, in the ATM over SONET (ATM) mode, this device can be used in equipment interconnecting ATM switches. Features of the VSC9112 VSC9112 include: full insertion/extraction of the transport overhead, bit error rate and extensive SONET/packet/cell performance monitoring, packet/cell filtering and discarding functionalities, JTAG TAP controller, and an 8-bit CPU interface with 8 general purpose I/O ports. When used in conjunction with a high-speed mux/demux tranceiver, this device provides a complete physical layer solution for Packet/ATM over SONET/SDH, LAPS (ITU COM 7-224), and certain Ethernet over SONET/SDH applications at the STS-48 STS-48 rate. In addition, this device provides the interface for higher bandwidth applications at the STS-192/STM-64 STS-192/STM-64 rate. Line Interface (LIF) · A parity bit, programmable for even/odd parity, is provided each for the incoming and outgoing datapaths. · A reference clock output derived from the receive clock input can be programmed to be 8kHz, 19MHz, 38MHz, or 78MHz frequency locked to the receive clock. · A reference clock output derived from the transmit clock input can be programmed to be 8kHz, 19MHz, 38MHz, or 78MHz frequency locked to the transmit clock. · A Loss of Optical Carrier (LOPC) input signal is provided for monitoring and alarm purposes. · The TLSYNC, RLFP and TLFP signals are intended to be used in STS-192/STM-64 STS-192/STM-64 applications. Receive Section Overhead Processor (RSOP) · Two mechanisms for frame alignment are provided. One is based on searching for A1/A2 framing patterns and the other uses an external frame pulse (RLFP). The latter is intended for STS-192 STS-192 applications. · 12/24/48-bit A1/A2 framing patterns are supported. · Out Of Frame (OOF) and Loss Of Frame (LOF) alarm condition are detected. · The incoming data stream is optionally descrambled using the generating polynomial 1 + x6 + x7 with a sequence length of 127. · Section BIP-8 (B1) errors are detected and accumulated. Both individual and block mode accumulation of B1 error indications are supported. · The incoming data stream, before descrambling, is monitored for absence of transitions or "all-zero patterns". The Loss Of Signal (LOS) detection and termination criterias are programmable. · It is possible to force insertion of all "1" in the data stream, except for the Section overhead. The Line AIS (AIS-L) condition may be automatically inserted in case of LOS, LOF, or Loss of Optical Carrier (LOPC) alarm events. · It is possible to extract the entire Section overhead through the Receive Overhead Access Port (ROAP). Page 2 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 · 805/388-3700 · FAX: 805/987-5896 G52210-0 G52210-0, Rev. 4.3 3/30/00 VITESSE SEMICONDUCTOR CORPORATION Datasheet VSC9112 VSC9112 STS-48c Physical Layer Packet/ATM Over SONET/SDH Device · The J0, E1, F1, and D1-D3 bytes can be extracted from the Section overhead and inserted into bytes on the special purpose ports of the ROAP. Receive Line Overhead Processor (RLOP) · The Line Remote Defect Indication (RDI-L) and Line Alarm Indication Signal (AIS-L) alarms carried in the K2 byte are extracted and filtered. The filter constants are programmable. · Line BIP-384 BIP-384 errors carried in the B2 bytes are detected and accumulated. Both individual and block mode accumulation of B2 errors are supported. · Line REI error indications carried in the M1 byte are accumulated. Both individual and block mode accumulation of M1 error indications are supported. · The Synchronization Status carried in the S1 byte is extracted and filtered. Unstable and mismatch alarms are supported. The filter constants are programmable. · The Automatic Protection Switching (APS) bytes, K1 and K2, are extracted and filtered. Unstable alarm is supported. The filter constants are programmable. · It is possible to extract the entire Line overhead through the ROAP. · The D4-D12 D4-D12, S1, E2, K1-K2 bytes can be extracted from the Line overhead and inserted into bytes on the special purpose ports of the ROAP. Receive Path Overhead Processor (RPOP) · The H1 and H2 pointer bytes are detected and interpreted according to ANSI T1.105 and ITU-T G.707. The mechanism is programmable to support both SONET and SDH. Path Alarm Indication Signal (AISP) and Loss of Pointer (LOP-P) alarm declarations are provided. Several pointer functions are also provided for diagnostic purposes. · The H1 and H2 pointer bytes are monitored for Concatenation Indication (CI). Loss of Pointer (LOPX) and AIS (AISX) alarm declarations are provided. · Path BIP-8 errors carried in the B3 byte are detected and accumulated. Both individual and block mode accumulation of B3 errors are supported. · Path REI error indications carried in the G1 byte are detected and accumulated. Up to 64000 individual errors can be detected per second. Both individual and block mode accumulation of Path REI error indications are supported. · The Path RDI carried in the G1 byte is detected and programmable. · The Signal Label carried in the C2 byte is detected, alarmed and is programmable. Receive Packet Processor (RPP) · The byte value used to identify the HDLC Flag Sequence is programmable. · The detection and discarding of invalid frames are programmable. · The expected Control Escape byte value and the Octet Destuffing Masking byte are programmable. G52210-0 G52210-0, Rev. 4.3 3/30/00 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 · 805/388-3700 · FAX: 805/987-5896 Page 3 VITESSE SEMICONDUCTOR CORPORATION STS-48c Physical Layer Packet/ATM Over SONET/SDH Device Datasheet VSC9112 VSC9112 · The expected Address and Control Field values are programmable. · The Protocol Field declaration and processing is programmable. · The Abort Sequence is detected in the incoming HDLC frames. · The received Frame Check Sequence (FCS) field is verified. The FCS checksum is calculated using either a 16-bit, CRC-CCITT generating polynomial 1 + x5 + x12 + x16, or a 32-bit, CRC-32 CRC-32 generating polynomial 1 + x + x2 + x4 + x5 + x7 + x8 + x10 + x11 + x12 + x16 + x22 + x23 + x26 + x32. · The received data is descrambled with the self synchronizing scrambler (SSS) polynomial 1 + x43. Full and/or partial descrambling can be independently enabled/disabled. · Long and short packet checking are provided and are programmable. · Self Describing Padding is supported and programmable. · The storage of the PPP Protocol Field in the Rx FIFO may be enabled/disabled. · The size of the Rx FIFO size is 4095 words, which may accommodate storage for a total of 16380 PPP Protocol/Information Field bytes. · The definition of received "errored" HDLC frames is programmable. For these errored HDLC frames two different procedures can be applied. · A filtering function is provided to perform packet discartion and error marking based on a set of programmable labels. There are four programmable label matching triggers, and one compliment word matching trigger that functions the packet discard and TERR marking. · The following statistics are provided in the performance monitoring 32-bit counters: · Received Aborted HDLC frames · Received FCS errored HDLC frames · Received Empty HDLC frames · Received HDLC frames where Address-and-Control-Field-Compression was found · Received Long packets · Received Short packets · Received Invalid Frames · Received bytes pre-octet destuffing · Received bytes post-octet destuffing · Received number of frames excluding Invalid Frames · Packets discarded by label filtering · Packets error-marked by label filtering · Packets stored in the Rx FIFO · Packets stored in the Rx FIFO that are error marked · Packet bytes stored in the Rx FIFO · Number of received PPP padding bytes Page 4 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 · 805/388-3700 · FAX: 805/987-5896 G52210-0 G52210-0, Rev. 4.3 3/30/00 VITESSE SEMICONDUCTOR CORPORATION Datasheet STS-48c Physical Layer Packet/ATM Over SONET/SDH Device VSC9112 VSC9112 · The SPE Transparent Mode is provided to allow all of the SPE payload to pass directly to the Rx FIFO without further processing. Receive ATM Cell Processor (RACP) · Cell Delineation is provided using shortened cyclic code with a generating polynomial 1 + x + x2 + x8. The coset polynomial 1 + x2 + x4 + x8 can be added to the calculated HEC check bits before comparison. · Single-bit header error correction is supported. The dropping of cells during single or multiple error detection is programmable. · The 48 byte information field is descrambled with a self-synchronizing descrambler polynomial 1 + x43. Descrambling can be enabled/disabled. · Cells can be filtered based on a programmable cell header pattern in the GFC, PTI, or CLP fields. · The number of correctable and uncorrectable HEC errors detected, and the number of cells written to the Rx FIFO are monitored. · The Rx FIFO can accommodate storage of eight ATM cells. Drop Side Interface (POS/ATM Interface) · A parity bit, programmable for even/odd parity, is provided for each transmit and receive datapaths. · The Drop Side Interface provides an industry compliant packet interface for POS operations. · The packet interface supports word-level and packet-level transfer modes. · The DTPA signal is provided to indicate the waterlevel of the Tx FIFO counted at word level and is programmable. · It is possible to force reset/flush the contents in the Tx FIFO via the CPU interface. · It is possible to force reset/flush the contents in the Rx FIFO via the CPU interface. · The Drop Side Interface provides a Single-PHY UTOPIA-3 interface for ATM operations. · Two formats of the ATM cells are supported: 52 byte cell or 56 byte cell containing the HEC. · The UTOPIA-3 interface supports both word-level and cell-level flow control. Transmit ATM Cell Processor (TACP) · The ATM cells are mapped into the STS-48c SPE or equivalent SDH VC-16-16c. Programmable idle/ unassigned cells are inserted into the cell stream. · The 48 byte information field is scrambled with a self-synchronizing descrambler polynomial 1 + x43. Scrambling can be enabled/disabled. · The HEC generator performs a CRC-8 calculation over the first four header octets using the generating polynomial 1 + x + x2 + x8. The coset polynomial 1 + x2 + x4 +x6 can be added to the result. The HEC is optionally inserted into the fifth octet of the header of cells read from the Tx FIFO. · The Tx FIFO can accomodate storage of eight ATM cells. G52210-0 G52210-0, Rev. 4.3 3/30/00 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 · 805/388-3700 · FAX: 805/987-5896 Page 5 VITESSE SEMICONDUCTOR CORPORATION STS-48c Physical Layer Packet/ATM Over SONET/SDH Device Datasheet VSC9112 VSC9112 Transmit Packet Processor (TPP) · The inserted HDLC Flag Sequence byte and the minimum number of Flag Sequence bytes separating HDLC frames are programmable. · The insertion of the Address and Control fields can be controlled by the HDLC Address-and-ControlField-Compression mechanism. · The Address Field inserted after the beginning Flag Sequence is programmable. · The Control Field inserted after the the Address Field is programmable. · The Frame Check Sequence (FCS) can be generated using either a 16-bit, CRC-CCITT generating polynomial 1 + x5 + x12 + x16, or a 32-bit CRC-32 CRC-32 generating polynomial 1 + x + x2 + x4 + x5 + x7 + x8 + x10 + x11 + x12 + x16 + x22 + x23 + x26 + x32. · Octet Stuffing, or "escaping", can be applied after the FCS generation and partial scrambling, if enabled. The Control Escape byte and the Octet Stuffing Masking byte are programmable. The Asyc-ControlCharacter-Map (ACCM) can accommodate a maximum of 5 byte values. Each value can be individually enabled/disabled. · The transmitted data is scrambled with a self-synchronizing scrambler (SSS) polynomial 1 + x 43. Full and/or partial scrambling can be independently enabled/disabled. · The PPP Protocol Field can be generated internally or extracted from the transmit FIFO. The size and value of the inserted Protocol Field are programmable when generated internally. · The Tx FIFO is programmable in the range from 1 to 4095 words or 16380 bytes of data storage. All valid packet bytes stored in the Tx FIFO are read out and mapped into the PPP Protocol/Information Fields of generated PPP/HDLC frames. · Two Tx PIF packet transfer modes are supported: packet transfer mode and word transfer mode. · The TXF_ERR signal is provided to force insertion of errors into the FCS, or to force abort the transmitted HDLC frame. · It is possible to force XOR'ing of the transmitted Address, Control or Protocol Fields with a programmable mask value via the CPU interface for diagnostic purposes. · The following statistics are provided in the performance monitoring 32-bit counters: · Bytes read from Tx FIFO · Transmitted good HDLC frames (non-aborted, non-FCS errored) · Transmitted Aborted HDLC frames · Transmitted FCS Errored HDLC frames · Long packets read from Tx FIFO · Short packets read from Tx FIFO · Transmitted empty HDLC frames · Bytes pre octet-stuffing (excluding Abort sequences) · Bytes post octet-stuffing (excluding Abort sequences) Page 6 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 · 805/388-3700 · FAX: 805/987-5896 G52210-0 G52210-0, Rev. 4.3 3/30/00 VITESSE SEMICONDUCTOR CORPORATION Datasheet STS-48c Physical Layer Packet/ATM Over SONET/SDH Device VSC9112 VSC9112 · The SPE Transparent Mode is provided to allow the Tx FIFO content to be passed directly into the SPE payload without further processing. Transmit Path Overhead Processor (TPOP) · The H1 and H2 pointer byte values are programmable to support both SONET and SDH. Several pointer functions are provided for diagnostics purposes. The remaining 47 H1 and H2 bytes are programmable. · The Path BIP-8 is computed and placed in the B3 byte of the current frame. It is possible to insert B3 errors for diagnostic purposes. · The number of Path BIP-8 errors detected in the Receive Path Overhead Processor (RPOP) is backreported as Path REI in the G1 byte. Both individual and block mode backreporting for G1 are supported. · It is possible to enable/disable RDI-P insertion for each of the following alarms: LOS, LOF, AIS-L, AISP, LOP-P, TIM-P, UNEQ-P, LCD-P and PLM-P. Both the latest and earlier definitions of RDI-P are supported. · The Path Signal Label (C2) byte value is programmable. · The Path Trace (J1) byte value is programmable. · The F2, H4, Z3, Z4, and Z5 bytes are programmable. Transmit Line Overhead Processor (TLOP) · It is possible to insert programmable sets of K1 and K2 bytes into the outgoing data stream. · RDI-L can be automatically inserted during the detection of an LOS, LOF, or AIS-L alarm in the receive data stream. · The Line BIP-384 BIP-384 code is computed and placed in the B2 bytes of the current frame. It is possible to insert B2 errors for diagnostics purposes. · The number of Line BIP-384 BIP-384 errors detected in the Receive Line Overhead Processor (RLOP) is backreported as Line REI in the M1 byte. Up to 255 errors can be backreported per frame in individual mode. Both individual and block mode backreporting for M1 are supported. It is possible to insert M1 error indications for diagnostics purposes. · The Synchronization Status value inserted in the S1 byte is programmable. · Bytes input to the special purpose ports of the Transmit Overhead Access Port (TOAP) can be inserted into the D4-D12 D4-D12, E2, S1, K1 and K2 bytes of the outgoing Line overhead. · All bytes in the line overhead that are reserved for national or future international standardization use can be overwritten with 0x00. · The H1, H2, and H3 bytes from the Transmit Overhead Access Port (TOAP) can be inserted into the H1, H2, and H3 overhead bytes, or applied as an error mask to the H1, H2, and H3 overhead bytes. Transmit Section Overhead Processor (TSOP) G52210-0 G52210-0, Rev. 4.3 3/30/00 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 · 805/388-3700 · FAX: 805/987-5896 Page 7 VITESSE SEMICONDUCTOR CORPORATION STS-48c Physical Layer Packet/ATM Over SONET/SDH Device Datasheet VSC9112 VSC9112 · It is possible to forced insert all "1"s into the data stream, before scrambling, with the exception of the section overhead. The AIS-L condition can be automatically inserted through activity from the special purpose serial interfaces. · The Section BIP-8 code is computed and can be placed in the B1 byte of the current frame. It is possible to insert B1 errors for diagnostics purposes. · The A1 and A2 framing bytes can be inserted into the frame. It is also possible to introduce bit errors in the framing word. · The J0 byte supports both SONET and SDH formats. The J0 byte can be programmed to a fixed value for interworking with older equipment implementing the C1 indentification byte. · The Z0 growth bytes supports both SONET and SDH formats. The Z0 bytes can be programmed to carry the C1 identification bytes for interworking with older equipment. · The outgoing data stream is optionally scrambled using the generating polynomial 1 + x6 + x7 with a sequence length of 127. · It is possible to force insert all "0"s in the outgoing data stream after scrambling for diagnostic purposes (LOS). · Bytes input to the special purpose ports of the TOAP can be inserted into the D1-D3, E1, F1 and J0 bytes of the outgoing Section overhead. · All bytes in the section overhead that are reserved for national or future international standardization use can be overwritten with 0x00. · A frame pulse is provided for the outgoing data stream and is programmable. Receive Overhead Access Port (ROAP) · Two identical, but independent, special purpose ports are provided for the extraction of special purpose bytes from the SONET/SDH transport overhead and of certain SONET/SDH alarms specific to automatic protection switching (APS) applications. · The frame pulse RSPFP is synchronized to the receive drop side frame pulses RXFPOUTA-D. · The entire section/line transport overhead can be extracted from the serial output port RTOH[3.0]. Transmit Overhead Access Port (TOAP) · Two identical, but independent, special purpose ports are provided for the insertion of special purpose bytes into the SONET/SDH transport overhead and of certain SONET/SDH alarms specific to automatic protection switching (APS) applications. · The entire transport overhead is captured from the serial input ports TTOH[3.0]. The captured data can be selectively inserted into the corresponding overhead bytes of the transmitted SONET/SDH frame. SONET/SDH Section Trace Buffers (SSTB) · Three different Section Trace Message (J0) formats are supported in both transmit and receive directions: one byte (SONET) message, 16 byte (SDH) message, and 64 byte (SONET CLLI) message. Page 8 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 · 805/388-3700 · FAX: 805/987-5896 G52210-0 G52210-0, Rev. 4.3 3/30/00 VITESSE SEMICONDUCTOR CORPORATION Datasheet STS-48c Physical Layer Packet/ATM Over SONET/SDH Device VSC9112 VSC9112 · The received section trace message is checked for persistency. A mismatch alarm is supported. CPU Interface · All configuration bits are both writeable and readable and can be accessed regardless of the device clock source status, except for the reset state. Configuration bits include selection bits, interrupt masking bits, and programmable counter/control values. · Eight programmable General Purpose Input/Output (GPIO) ports are available for monitoring and controlling external signals. All GPIOs support bistable interrupts when configured as input ports. · Clock activity monitors are implemented for all input clocks. Bit Error Rate Monitoring · Bit error rate monitoring is based on the Line BIP (B2) error code and is capable of measuring BERs down to 10-10 . · There are four independent BER monitors with individual accumulation periods and alarm thresholds. · A saturation threshold is implemented for each BER monitor to specify the maximum number of errors that can be accumulated per frame. · The BER Signal Degrade (BER-SD) alarm is based on BER monitors 1 and 2. · The BER Signal Fail (BER-SF) alarm is based on BER monitors 3 and 4. JTAG · Standard IEEE 1149.1 compliant JTAG interface. Loopback Modes · Equipment loopback is supported by looping the output from the Transmit Section Overhead Processor (TSOP), in the transmit direction, back to the input of the Receive Section Overhead Processor (RSOP), in the receive direction. · Facility loopback is supported by looping the data received on the receive Line Side Interface back to the transmit Line Side Interface. · Section loopback is supported by looping the output from the Recieve Section Overhead Processor (RSOP) in the receive direction back to the input of the Transmit Section Overhead Processor (TSOP), in the transmit direction. · Line loopback is supported by looping the output from the Recieve Line Overhead Processor (RLOP) in the receive direction back to the input of the Transmit Line Overhead Processor (TLOP), in the transmit direction. · Drop side loopback is supported by looping the output from the Tx FIFO to the input of the Rx FIFO. This loopback is supported for both packet and ATM cell mode. G52210-0 G52210-0, Rev. 4.3 3/30/00 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 · 805/388-3700 · FAX: 805/987-5896 Page 9 VITESSE SEMICONDUCTOR CORPORATION Datasheet STS-48c Physical Layer Packet/ATM Over SONET/SDH Device VSC9112 VSC9112 AC Characteristics Figure 1: Rx Line Interface Timing Dependencies RLCLK+ TSU,RLIN TH,RLIN RLIN[15.0]+/RLPRTY+/RLFP+/TP,RXRCLK RXRCLK Table 1: Rx Line Interface Symbol Description fRLCLK RLCLK+/- Clock Frequency (nominal) dcRLCLK RLCLK+/- Duty Cycle TR/F, RLCLK RLCLK+/- Rise/Fall Time TSU, RLIN RLIN[15.0]+/-, RLPRTY+/-, RLFP+/- Setup Time to RLCLK+ Rising Edge TH, RLIN Min Max Unit - 155.52 MHz 40 60 % - 1.0 ns 1.5 - ns RLIN[15.0]+/-, RLPRTY+/-, RLFP+/- Hold Time to RLCLK+ Rising Edge 1.0 - ns 1.0 20.0 ns - - MHz 30 70 % TP, RXRCLK RLCLK+ Rising Edge to RXRCLK Rising/Falling Edge fRXRCLK fRLCLK Divided by 2/4/8/19440 dcRXRCLK RXRCLK Duty Cycle RXRCLK times are for 50 pF load. Page 10 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 · 805/388-3700 · FAX: 805/987-5896 G52210-0 G52210-0, Rev. 4.3 3/30/00 VITESSE SEMICONDUCTOR CORPORATION Datasheet STS-48c Physical Layer Packet/ATM Over SONET/SDH Device VSC9112 VSC9112 Figure 2: Tx Line Interface Timing Dependencies TLCLK+ TP,TLCLK TLOUT[15.0]+/TLPRTY+/TLFP+/TP,TLCLKO TLCLKOUT+ TP,TXRCLK TXRCLK TSU,TLIN TH,TLIN TLSYNC+/TPW, TLSYNC Table 2: Tx Line Interface Symbol Description fTLCLK TLCLK+/- Clock Frequency (nominal) dcTLCLK TR/F, TLCLK Min Unit - TLCLK+/- Duty Cycle Max 155.52 MHz 40 60 % - TLCLK+/- Rise/Fall Time 1.0 ns TP, TLOUT TLCLK+ Rising Edge to TLOUT[15.0]+/- and TLPRTY+/-, TLFP+/- Valid 1.0 4.0 ns TP, TXRCLK TLCLK+ Rising Edge to TXRCLK Rising/Falling Edge 1.0 15.0 ns TP, CLKOUT TLCLKOUT+ Rising Edge to TLOUT[15.0]+/-, TLPRTY+/-, TLFP+/- Valid 0 1.3 ns - - MHz 30 70 % fTXRCLK dcTXRCLK fTLCLK Divided by 2/4/8/19440 TXRCLK Duty Cycle 1) TSU, TLIN TLSYNC +/- Setup Time to TLCLK+ Rising Edge TH, TLIN TLSYNC +/- Hold Time to TLCLK+ Rising Edge 1) TPW, TLSYNC Minimum Pulse Width of TLSYNC (measured in TLCLK Clock Cycles) 2.0 ns 1.0 ns 2 - 1) It is not required that TSU, TLIN and TH, TLIN are met. TXRCLK times are for 50 pF load. G52210-0 G52210-0, Rev. 4.3 3/30/00 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 · 805/388-3700 · FAX: 805/987-5896 Page 11 VITESSE SEMICONDUCTOR CORPORATION Datasheet STS-48c Physical Layer Packet/ATM Over SONET/SDH Device VSC9112 VSC9112 Figure 3: Rx Drop Interface Timing Dependencies RFCLK TSU,RXIN TH,RXIN RENB RDAT[31.0] RPRTY RMOD[1.0] RSOP REOP RVAL RERR TP,RXOUT TP,RXCLKO RCLKO Table 3: Rx Drop Interface Symbol fRFCLK dcRFCLK TR/F, RFCLK Description Min Max Unit RFCLK Clock Frequency (nominal) 50 104 MHz RFCLK Duty Cycle 40 60 % - 2.0 ns RFCLK Rise/Fall Time dcRFCLK - (1.0 ns x fRFCLK)% dcRFCLKO RFCLKO Duty Cycle TSU, RXIN RENB Setup Time to RFCLK Rising Edge 2.0 TH, RXIN RENB Hold Time to RFCLK Rising Edge 0.5 - ns TP, RXOUT RFCLK Rising Edge to RDATA[31.0], RPRTY, RMOD[1.0], RSOP, REOP, RVAL and RERR Valid 1.0 6.0 ns 1) 0.5 4.2 ns 2) TP, RXCLKO RFCLKO Rising Edge RDAT[31.0], RPRTY, RMOD[1.0], RSOP, REOP, RVAL and RERR Valid 0.0 1.5 ns 3) - % ns 1) Output times are for 25 pF load. Output times are for 5 pF load. 3) Output times are for 5 to 15 pF load. 2) Page 12 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 · 805/388-3700 · FAX: 805/987-5896 G52210-0 G52210-0, Rev. 4.3 3/30/00 VITESSE SEMICONDUCTOR CORPORATION Datasheet STS-48c Physical Layer Packet/ATM Over SONET/SDH Device VSC9112 VSC9112 Figure 4: Tx Drop Interface Timing Dependencies TFCLK TDAT[31.0] TPRTY TMOD[1.0] TSOP TEOP TERR TENB TSU,TXIN TH,TXIN TP,TXOUT DTPA TP,TXCLKO TCLKO Table 4: Tx Drop Interface Symbol fTFCLK dcTFCLK TR/F, TFCLK Description Min Max Unit TFCLK Clock Frequency 50 104 MHz TFCLK Duty Cycle 40 60 % - 2.0 ns TFCLK Rise/Fall Time dcTFCLK - (1.0 ns x fTFCLK)% dcTFCLKO TFCLKO Duty Cycle TSU, TXIN TDAT[31.0], TPRTY, TMOD[1.0], TSOP, TEOP, TERR and TENB Setup Time to TFCLK Rising Edge 2.0 - ns TH, TXIN TDAT[31.0], TPRTY, TMOD[1.0], TSOP, TEOP, TERR and TENB Hold Time to TFCLK Rising Edge 0.5 - ns TP, TXOUT TFCLK Rising Edge to DTPA Valid 1.0 6.0 ns 1) 0.5 4.2 ns 2) TP, TXCLKO TFCLKO Rising Edge to DTPA Valid. 0.0 1.5 ns 3) % 1) Output times are for 25 pF load. Output times are for 5 pF load. 3) Output times are for 5 to 15 pF load. 2) G52210-0 G52210-0, Rev. 4.3 3/30/00 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 · 805/388-3700 · FAX: 805/987-5896 Page 13 VITESSE SEMICONDUCTOR CORPORATION Datasheet STS-48c Physical Layer Packet/ATM Over SONET/SDH Device VSC9112 VSC9112 Figure 5: Rx Overhead Access Port Timing Dependencies RSPCLK1-2 TP,RSP RSPDAT1-2 RSPVALID1-2 RSPFP RTOHCLK TP,RTOH RTOH[3.0] RTOHVALID RTOHFP Table 5: Rx Overhead Access Port Symbol Description fRSPCLK RSPCLK1-2 Clock Frequency (optionally gapped) RSPCLK1-2 Duty Cycle dcRSPCLK TR/F, RSPCLK RSPCLK1-2 Rise/Fall Time RSPCLK1-2 Rising/Falling Edge2) to RSPDAT1-2, RSPVALID1-2, RSPFP Valid TP, RSP fRTOHCLK RTOHCLK Clock Frequency (nominal) dcRTOHCLK RTOHCLK Duty Cycle TR/F, RTOHCLK TP, RTOH RTOHCLK Rise/Fall Time RTOHCLK Rising/Falling Edge3) to RTOH[0.3], RTOHVALID, RTOHFP Valid Min Max Unit - 2.16 MHz 40 60 % - 2.0 ns -6.0 +15.0 ns - 38.88 MHz 40 60 % - 2.0 ns -3.0 +7.0 ns 2) Active edge of clock is programmable for group of inputs for each independent port. Active edge of clock is programmable for group of inputs. All output times are for 50 pF load. 3) Page 14 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 · 805/388-3700 · FAX: 805/987-5896 G52210-0 G52210-0, Rev. 4.3 3/30/00 VITESSE SEMICONDUCTOR CORPORATION Datasheet STS-48c Physical Layer Packet/ATM Over SONET/SDH Device VSC9112 VSC9112 Figure 6: Tx Overhead Access Port Timing Dependencies TSPCLK1-2 TSU,TSP TH,TSP TSU,TTOH TH,TTOH TSPDAT1-2 TP,TSP TSPFP1-2 TSPREN1-2 TTOHCLK TTOH[3.0] TTOHEN TP,TTOH TTOHFP TTOHREN Table 6: Tx Overhead Access Port Symbol fTSPCLK dcTSPCLK Description TSPCLK1-2 Clock Frequency (optionally gapped) TSPCLK1-2 Duty Cycle Max Unit - 2.16 MHz 40 60 % - 2.0 ns TSU, TSP TSPDAT1-2 Setup Time to TSPCLK1-2 Rising/Falling Edge5) 25.0 - ns TH, TSP TSPDAT1-2 Hold Time to TSPCLK1-2 Rising/Falling Edge5) 0 - ns TP, TSP TSPCLK1-2 Rising/Falling Edge6) to TSPREN1-2, TSPFP1-2 Valid -10.0 +20.0 ns TR/F, TSPCLK fTTOHCLK dcTTOHCLK TR/F, TTOHCLK TSPCLK1-2 Rise/Fall Time Min TTOHCLK Clock Frequency (nominal) TTOHCLK Duty Cycle 38.88 MHz 60 % - 2.0 ns TSU, TTOH TTOH[0.3], TTOHEN Setup Time to TTOHCLK Rising/Falling Edge7) 15.0 - ns TH, TTOH TTOH[0.3], TTOHEN Hold Time to TTOHCLK Rising/Falling Edge7) -1.0 - ns G52210-0 G52210-0, Rev. 4.3 3/30/00 TTOHCLK Rise/Fall Time 40 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 · 805/388-3700 · FAX: 805/987-5896 Page 15 VITESSE SEMICONDUCTOR CORPORATION Datasheet STS-48c Physical Layer Packet/ATM Over SONET/SDH Device VSC9112 VSC9112 Table 6: Tx Overhead Access Port Symbol Description Min Max Unit -3.0 +7.0 ns Min Max Unit MHz 8) TTOHCLK Rising/Falling Edge to TTOHREN, TTOHFP Valid TP, TTOH 5) Active edge of clock is programmable for group of inputs for each independent port. Active edge of clock is programmable for group of outputs for each independent port. 7) Active edge of clock is programmable for group of inputs. 8) Active edge of clock is programmable for group of outputs. All output times are for 50 pF load. 6) Figure 7: JTAG Interface Timing Dependencies TCK TSU, JTIN TH, JTIN TMS TDI TP, JTOUT TDO Table 7: JTAG Interface Symbol Description fTCK TCK Frequency - 1 dcTCK 40 60 % TMS/TDI Setup Time to TCK Rising Edge 50 - ns TH, JTIN TMS/TDI Hold Time to TCK Rising Edge 50 - ns TP, JOUT Page 16 TCK Duty Cycle TSU, JTIN TCK Falling Edge to TDO Valid 1.5 50 ns © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 · 805/388-3700 · FAX: 805/987-5896 G52210-0 G52210-0, Rev. 4.3 3/30/00 VITESSE SEMICONDUCTOR CORPORATION Datasheet STS-48c Physical Layer Packet/ATM Over SONET/SDH Device VSC9112 VSC9112 Figure 8: CPU Read Access Timing Dependencies A[7.0] Valid Address TSU,ALE TH,ALE TPW,ALE TH,AR/W ALE TSU,LR/W TH,LR/W CSB RDB TSU,AR/W TPW,R/W TZ,INTR INTB TP,RD TZ,RD D[7.0] Valid Data Figure 9: CPU Write Access Timing Dependencies A[7.0] Valid Address TSU,ALE TH,ALE TPW,ALE TH,AR/W ALE TSU,LR/W TH,LR/W CSB WRB TSU,AR/W TPW,R/W TSU, DW D[7.0] G52210-0 G52210-0, Rev. 4.3 3/30/00 TH, DW Valid Data © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 · 805/388-3700 · FAX: 805/987-5896 Page 17 VITESSE SEMICONDUCTOR CORPORATION Datasheet STS-48c Physical Layer Packet/ATM Over SONET/SDH Device VSC9112 VSC9112 Table 8: CPU Read/Write Access Symbol Description Min Max Unit TSU, ALE Address to Address Latch Setup Time 10 - ns TH, ALE Address to Address Latch Hold Time 10 - ns TPW, ALE Address Latch Pulse Width 20 - ns TSU, LR/W Latch to Valid Read/Write Setup Time 0 - ns TH, LR/W Latch to Valid Read/Write Hold Time 5 - ns TSU, AR/W Address to Valid Read/Write Setup Time 10 - ns TH, AR/W Address to Valid Read/Write Hold Time 10 / 5 - ns TPW, R/W Valid Read/Write Pulse Width 20 / 25 - ns TSU, DW Data to Valid Write Setup Time 20 - ns TH, DW Data to Valid Write Hold Time 10 - ns TP, RD Valid Read to Valid Data Propagation Delay 80 ns TZ, RD Valid Read Negated to Output Tristate 1 25 ns 100 ns TZ, INTH Valid Read Negated to Interrupt Release/Pull-down All output times are for 100 pF load. Page 18 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 · 805/388-3700 · FAX: 805/987-5896 G52210-0 G52210-0, Rev. 4.3 3/30/00 VITESSE SEMICONDUCTOR CORPORATION Datasheet STS-48c Physical Layer Packet/ATM Over SONET/SDH Device VSC9112 VSC9112 DC Characteristics Parameters Description Min Max Units Conditions VOH Output HIGH voltage (TTL) 2.4 - V IOH = -2,-4,-8,-16 mA VOL Output LOW voltage (TTL) - 0.5 V IOL = 2,4,8,16 mA VIH Input HIGH voltage (TTL) 2.0 5.5 V - VIL Input LOW voltage (TTL) 0 0.8 V - IIT Input current (TTL) - 10 µA 0V< VIN < 5V VOCM O/P Common Mode Range (PECL) 1600 2300 mV At Min VOUT VOUT75 VOUT75 Differential Output Voltage (PECL) 1000 1500 mV 75 to VDD ­ 2.0 V VOUT50 VOUT50 Differential Output Voltage (PECL) 700 1200 mV 50 to VDD ­ 2.0 V VICM I/P Common Mode Range (PECL) 1500 1800 mV At Min VIN VIN Differential Input Voltage (PECL) 300 2600 mV - Input current (PECL) - 1000 µA 0V< VIN < 3.3V IIP Power Dissipation Parameter Description (Typ) (Max) Units IDD Power supply current from VDD 833 972 mA PD Power dissipation 2.5 3.0 W G52210-0 G52210-0, Rev. 4.3 3/30/00 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 · 805/388-3700 · FAX: 805/987-5896 Page 19 VITESSE SEMICONDUCTOR CORPORATION STS-48c Physical Layer Packet/ATM Over SONET/SDH Device Datasheet VSC9112 VSC9112 Absolute Maximum Ratings(1) Power Supply Voltage (VDD) Potential to GND .-0.5V to +4V Power Supply Voltage (VDD5) Potential to GND.-0.5V to +6V DC Input Voltage (PECL inputs). -0.5V to VDD + 0.5V DC Input Voltage (TTL inputs) .-0.5V to VDD5 + 0.5V DC Output Voltage (TTL Outputs). -0.5V to VDD + 0.5V DC Output Voltage (TTL 5V Tolerant Outputs) .-0.5V to VDD5 + 0.5V Output Current (TTL Outputs) . +/-50mA Output Current (PECL Outputs).+/-50mA Case Temperature Under Bias .-55o to +125oC Storage Temperature. -65oC to +150oC Maximum Input ESD (Human Body Model). 2000 V Note: Caution: Stresses listed under "Absolute Maximummanent damage. Functionality at or exceeding the values listedods may affect device reliability. Recommended Operating Conditions Power Supply Voltage (VDD) . +3.3V ± 10 % Power Supply Voltage (VDD5). +5.0V ± 10 % Operating Temperature Range* (T). -40o to 95oC * Lower limit of specification is ambient temperature and upper limit is case temperature. Page 20 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 · 805/388-3700 · FAX: 805/987-5896 G52210-0 G52210-0, Rev. 4.3 3/30/00 VITESSE SEMICONDUCTOR CORPORATION Datasheet STS-48c Physical Layer Packet/ATM Over SONET/SDH Device VSC9112 VSC9112 Package Pin Description Signal Name I/O Type Description RLCLK+/- Parallel Line Receive Clock I PECL Clock reference for the 2.5Gb/s receive flow carried in RLIN[15.0]. The clock frequency is nominally 155.52MHz equivalent to STS-48/STM-16 STS-48/STM-16 operation. RLIN[15.0]+/- Parallel Line Receive Data I PECL Parallel data bus for the incoming STS-48/STM-16 STS-48/STM-16 data stream. RLIN[15] is the most significant bit. RLIN[15] is the first arriving bit on the serial data stream.is sampled on the rising edge of RLCLK+. RLPRTY+/- Parallel Line Receive Parity I PECL Parity input (even/odd parity) for the parallel receive line data, RLIN[15.0] (optionally include RLFP). RLPRTY is sampled on the rising edge of RLCLK+. RLFP+/- Parallel Line Receive Frame Pulse I PECL Frame pulse for the receive line interface. RLFP can be used instead of the internal framing circuit (based on A1A2 patterns) for synchronizing the receive processor. RLFP is sampled on the rising edge of RLCLK+. RLFP is intended for use in STS-192/STM-64 STS-192/STM-64 applications. RXRCLK Receive Reference Clock O TTL Reference clock derived from RLCLK in a 78MHz/38MHz/ 19MHz/8kHz version. Loss of Optical Carrier I TTL LOPC is monitored and changes in the signal status may cause generation of an interrupt. This allows monitoring of optical failures via the device CPU interface. When LOPC is asserted, the receive processor is optionally clocked by the transmit clock (derived from TLCLK). Clock Reset Enable I TTL If CLKRSTEN is asserted, all primary clock outputs (TXRCLK, RXRCLK, RSPCLK1, RSPCLK2, RTOHCLK, TSPCLK1, TSPCLK2, and TTOHCLK) will halt during master reset. If CLKRSTEN is deasserted, all primary clock outputs will be running during device master reset. Parallel Line Transmit Clock I PECL Clock reference for the 2.5Gb/s transmit flow carried in TLOUT[15.0]. The clock frequency is nominally 155.52MHz equivalent to STS-48/STM-16 STS-48/STM-16 operation. Parallel Line Transmit Looped Clock O PECL Looped TLCLK signal. Timing for this clock is defined with reference to the TLOUT data bus signals. The clock frequency is nominally 155.52MHz equivalent to STS-48/ STS-48/ STM-16 STM-16 operation (same as TLCLK). TLOUT[15.0]+/- Parallel Line Transmit Data O PECL Parallel data bus for the outgoing STS-48/ STS-48/ STM-16 STM-16 data stream. TLOUT[15] is the most significant bit.TLOUT[15] is the first transmitted bit on the serial data stream. TLOUT[15.0] is generated on the rising edge of the incoming TLCLK+. TLPRTY+/- Parallel Line Transmit Parity O PECL Parity output (even/odd parity) for the parallel transmitdata, TLOUT[15.0] (optionally includes TLFP). TLPRTY is generated on the rising edge of TLCLK+. LOPC CLKRSTEN TLCLK+/- TLCLKOUT+/- G52210-0 G52210-0, Rev. 4.3 3/30/00 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 · 805/388-3700 · FAX: 805/987-5896 Page 21 VITESSE SEMICONDUCTOR CORPORATION Datasheet STS-48c Physical Layer Packet/ATM Over SONET/SDH Device Signal VSC9112 VSC9112 Name I/O Type Description TLFP+/- Parallel Line Transmit Frame Pulse O PECL Frame pulse for the transmit line interface. TLFP is a one clock cycle wide pulse coincident with either the first framing byte (A1), the first paylod byte (first byte followingZ0) or a 24 clock cycle wide pulse coincident with the A2 framing bytes. TLFP is generated on the rising edge of TLCLK+. TLFP is intended for use in STS-192/STM-64 STS-192/STM-64 applications. TLSYNC+/- Synchronization I PECL TLSYNC is used for synchronously resetting the device transmit processor only. TLSYNC is intended for use in STS-192/STM-64 STS-192/STM-64 applications. TXRCLK Transmit Reference Clock O TTL Reference clock derived from TLCLK in a 78MHz/38MHz/ 19MHz/8kHz version. LOS Loss Of Signal O TTL Status signal indicating if Loss Of Signal (LOS) has been detected. The LOS status is also available in an internal status register bit. The signal is active high. LOF Loss Of Frame O TTL Status signal indicating if Loss Of Frame (LOF) has been detected. The LOF status is also available in an internal status register bit. The signal is active high. LCD-P Loss of Cell Delineation O TTL This signal is asserted when the cell delineation state machine is not in SYNC state. This alarm indication is also available via internal register access. RSPFP Receive Special Purpose Frame Pulse O TTL Frame reference for special purpose serial output ports RSPDATx. The frame pulse is a one clock cycle wide pulse coincident with the first bit on the serial dataActive high. RSPFP changes on the falling edge of RSPCLKx. x = [1,2]. RSPCLK1 Receive Special Purpose Clock 1 O TTL Clock reference for receive special purpose serial output port 1. The clock is a 2.16MHz, 50% duty-cycle signal (optionally gapped to match the bandwidth of RSPDAT1. RSPDAT1 Receive Special Purpose Data 1 O TTL Data output for special purpose serial port 1. RSPDAT1 changes on the falling edge of RSPCLK1. RSPVALID1 Receive Special Purpose Valid 1 O TTL Valid qualifier for special purpose serial port 1. RSPVALID1 is asserted (programmable level) when there is valid data on RSPDAT1. RSPVALID1 changes on the falling edge of RSPCLK1. RSPCLK2 Receive Special Purpose Clock 2 O TTL Clock reference for receive special purpose serial output port 2. The clock is a 2.16MHz, 50% duty-cycle signal (optionally gapped to match the bandwidth of RSPDAT2. RSPDAT2 Receive Special Purpose Data 2 O TTL Data output for special purpose serial port 2. RSPDAT2 changes on the falling edge of RSPCLK2. Page 22 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 · 805/388-3700 · FAX: 805/987-5896 G52210-0 G52210-0, Rev. 4.3 3/30/00 VITESSE SEMICONDUCTOR CORPORATION Datasheet STS-48c Physical Layer Packet/ATM Over SONET/SDH Device VSC9112 VSC9112 Signal Name I/O Type Description Receive Special Purpose Valid 2 O TTL Valid qualifier for special purpose serial port 2. RSPVALID2 is asserted (programmable level) when there is valid data on RSPDAT2. RSPVALID2 changes on the falling edge of RSPCLK2. RTOHCLK Receive Transport Overhead Clock O TTL Clock reference for the receive transport overhead port. The clock is a 38.88MHz, 50% duty-cycle signal. RTOHVALID Receive Transport Overhead Valid O TTL Valid qualifier for the receive transport overhead port. RTOHVALID is asserted (programmable level) when there is valid data on RTOH[3.0]. RTOHVALID changes on the falling edge of RTOHCLK. RTOHFP Receive Transport Overhead Frame Pulse O TTL Frame reference for the receive transport overhead port. RTOHFP is a one clock cycle wide pulse coincident with the first bit(s) of the first A1 being output on RTOH[3.0]. RTOHFP changes on the falling edge of RTOHCLK. RTOH[3.0] Receive Transport Overhead Data O TTL Data output for the receive transport overhead (section and line) bytes extracted from the incoming STS-48 STS-48 signal. RTOH[3.0] changes on the falling edge of RTOHCLK. Mode 1: RTOH[3] carries the transport overhead from STS12 STS12 #1 (first interleaved STS-12 STS-12), RTOH[2] carries the transport overhead from STS-12 STS-12 #2, etc. Mode 2: RTOH[3.0] carries the entire transport overhead in the order the overhead bytes are received. The most significant nibble (first received) is output first. RTOH[3] ismost significant bit. TSPCLK1 Transmit Special Purpose Clock 1 O TTL Clock reference for the transmit special purpose serialport 1. The clock is a 2.16MHz, 50% duty-cycle signal (optionally gapped to match the bandwidth of TSPDAT1). TSPFP1 Transmit Special Purpose Frame Pulse 1 O TTL Frame reference for the special purpose serial output port TSPDAT1. Mode 1 (TSPCLK1 continuous): The frame pulse is a one clock cycle wide pulse indicating the start of a new data stream on TSPDAT1. When TSPFP1 is asserted, the first bit of TSPDAT1 is sampled on the second rising edge thereafter. TSPFP1 changes on the falling edge of TSPCLK1. Mode 2 (TSPCLK1 gapped): The frame pulse is a one clock cycle wide pulse (variable width due to the gapped clock) indicating the start of a new data stream on TSPDAT1. When TSPFP1 is asserted, the first bit of TSPDAT1 is sampled on the second rising edge thereafter. TSPFP1 changes on the falling edge of TSPCLK1. TSPREN1 Transmit Special Purpose Read Enable 1 O TTL Read enable signal for the TSPDAT1 data stream. The response latency from TSPREN1 is asserted until TSPDAT1 is sampled is programmable. TSPREN1 changes on the falling edge of TSPCLK1. RSPVALID2 G52210-0 G52210-0, Rev. 4.3 3/30/00 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 · 805/388-3700 · FAX: 805/987-5896 Page 23 VITESSE SEMICONDUCTOR CORPORATION Datasheet STS-48c Physical Layer Packet/ATM Over SONET/SDH Device Signal VSC9112 VSC9112 Name I/O Type TSPDAT1 Transmit Special Purpose Data 1 I TTL Serial data input for transmit special purpose port 1. TSPDAT1 is sampled on the rising edge of TSPCLK1. TSPCLK2 Transmit Special Purpose Clock 2 O TTL Clock reference for the transmit special purpose serialport 2. The clock is a 2.16MHz, 50% duty-cycle signal (optionally gapped to match the bandwidth of TSPDAT2). TSPFP2 Transmit Special Purpose Frame Pulse 2 O TTL Frame reference for the special purpose serial output port TSPDAT2. Mode 1 (TSPCLK2 continuous): The frame pulse is a one clock cycle wide pulse indicating the start of a new data stream on TSPDAT2. When TSPFP2 is asserted, the first bit of TSPDAT_2 is sampled on the second rising edge thereafter. TSPFP2 changes on the falling edge of TSPCLK2. Mode 2 (TSPCLK2 gapped): The frame pulse is a one clock cycle wide pulse (variable width due to the gapped clock) indicating the start of a new data stream on TSPDAT2. When TSPFP2 is asserted, the first bit of TSPDAT2 is sampled on the second rising edge thereafter. TSPFP2 changes on the falling edge of TSPCLK2. TSPREN2 Transmit Special Purpose Read Enable 2 O TTL Read enable signal for the TSPDAT2 data stream. The response latency from TSPREN2 is asserted until TSPDAT2 is sampled is programmable. TSPREN2 changes on the falling edge of TSPCLK2. TSPDAT2 Transmit Special Purpose Data 2 I TTL Serial data input for transmit special purpose port 2. TSPDAT2 is sampled on the rising edge of TSPCLK2. TTOHCLK Transmit Transport Overhead Clock O TTL Clock reference for the transmit transport overhead port. The clock is a 38.88MHz, 50% duty-cycle signal. TTOHFP Transmit Transport Overhead Frame Pulse O TTL Frame reference for the transmit transport overhead port. TTOHFP is a one clock cycle wide pulse indicating the start of a new data stream on TTOH[3.0]. The response latency from TTOHFP is asserted until the first bit on TTOH[3.0] is sampled is programmable (see TTOHREN). TTOHFP changes on the falling edge of TTOHCLK. TTOHREN Transmit Transport Overhead Read Enable O TTL Read enable signal for the TTOH[3.0] data stream. The response latency from TTOHREN is asserted until TTOH[3.0] is sampled is programmable. TTOHREN changes on the falling edge of TTOHCLK. Page 24 Description © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 · 805/388-3700 · FAX: 805/987-5896 G52210-0 G52210-0, Rev. 4.3 3/30/00 VITESSE SEMICONDUCTOR CORPORATION Datasheet STS-48c Physical Layer Packet/ATM Over SONET/SDH Device VSC9112 VSC9112 Signal Name I/O Type Description Transmit Transport Overhead Enable I TTL Enable signal for the TTOH[3.0] data stream. If TTOHEN is asserted, the corresponding byte will be inserted in the corresponding transport overhead byte of the outgoing STS48 STS48 data stream. Mode 1: Transport overhead for each of the four STS-12 STS-12 channels will be input in bit-serial format on the four data inputs (see TTOH[3.0] description). If TTOHEN is asserted during the first bit of an overhead byte, the corresponding overhead byte on TTOH[3] will be enabled, if TTOHEN is asserted during the third bit of an overhead byte, the corresponding overhead byte on TTOH[2] will be enabled (similar for TTOHEN assertion during fifth and seventh bits). Mode 2: Transport overhead for the entire STS-48 STS-48 is input as 4-bit nibbles on the TTOH[3.0] port (see TTOH[3.0] description). If TTOHEN is asserted during the first nibble of an overhead byte, the corresponding overhead byte is enabled. Note: The transmit section and line processing blocks can selectively overwrite/modify overhead bytes inserted through the TTOH interface. Transmit Transport Ovehead Data I TTL Data input for the transport overhead (section and line) bytes to be inserted in the outgoing STS-48 STS-48 signal. TTOH[3.0] is sampled on the rising edge of TTOHCLK. Mode 1: TTOH[3] carries the transport overhead for STS12 STS12 #1 (first interleaved STS-12 STS-12), TTOH[2] carries the transport overhead for STS-12 STS-12 #2, etc. Mode 2: TTOH[3.0] carries the entire STS-48 STS-48 transport overhead in the order the overhead bytes are to be inserted. The most significant nibble (first received) is input first. TTOH[3] is the most significant bit. D[7.0] CPU Data B TTL Bidirectional data bus is used to transfer data for microcontroller read/write access to internal UNI registers. A[8.0] CPU Address I TTL Address bus selects specific internal registers during register read/write access. ALE CPU Address Latch Enable I TTL Controls internal latching of the address bus signals. When low the address bus A[8.0] is latched internal. When high the internal address bus latches are transparent. Thiswill allow for interfacing to a multiplexed address/data. The ALE signal has an internal pull-up resistor. CSB CPU Chip Select (active low) I TTL Must always be asserted during register read/write access cycles. The CSB signal is used in conjunction with either the RDB or the WRB signal. The CSB signal has an internal pull-up resistor. WRB CPU Write Enable (active low) I TTL Used for register write operations. The D[7.0] content is written into the by A[8.0] selected register when WRB and CSB are both asserted (low). The WRB signal has an internal pull-up resistor. TTOHEN TTOH[3.0] G52210-0 G52210-0, Rev. 4.3 3/30/00 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 · 805/388-3700 · FAX: 805/987-5896 Page 25 VITESSE SEMICONDUCTOR CORPORATION Datasheet STS-48c Physical Layer Packet/ATM Over SONET/SDH Device Signal VSC9112 VSC9112 Name I/O Type Description RDB CPU Read Enable (active low) I TTL Used for register read operations. The D[7.0] will driveregister content of the by A[8.0] selected register when RDB and CSB are both asserted (low). The RDB signal has an internal pull-up resistor. INTB CPU Interrupt (active low) O TTL Asserted when an internal interrupt source is pending and the interrupt is unmasked (enabled). The INTB signal is deasserted when the interrupt pending bits have been cleared. The INTB is an open drain signal. RSTB Chip Reset (active low) I TTL Asynchronous reset of the device. The device is held in a reset state while the RSTB signal is low. The signal istrigged with an internal pull-up resistor. All outputs are tristated when RSTB is asserted. PMTICK Performance Monitoring Tick B TTL Output. Asserted when the internal PMTICK timer generates a tick for latching performance counters in the device. Input: A low-to-high transition will (optionally) trigger latching of performance monitoring counters in the device. GPIO[7.0] General Purpose Input/Output BI TTL Individually configurable as inputs or outputs. Intended for controlling monitoring external devices. TDO JTAG Test Data Output O TTL This signal carries test data out of the device via the IEEE P1149 P1149.1 test access port. TDO is updated on the falling edge of TCK. The TDO signal is a tristate output which is inactive except when data scan shifting is in progress. TDI JTAG Test Data Input I TTL The signal carries test data into the device via the IEEE P1149 P1149.1 test access port. TDI is sampled on the rising edge of TCK. TDI has an internal pull-up resistor. TCK JTAG Test Clock I TTL This signal provides timing for test operations that are carried out using the IEEE P1149 P1149.1 test access port. TMS JTAG Test Mode Select I TTL This signal controls the test operations that are carried out using the IEEE P1149 P1149.1 test access port. TMS is sampled on the rising edge of TCK. TMS has an internal pull-up resistor. TRSTB JTAG Test Reset (active low) I TTL This signal provides an asynchronous test access port reset via the IEEE P1149 P1149.1 test access port. TRSTB is a schmitt triggered input with an internal pull-up resistor. Chip Output Enable (active high) I TTL When deasserted (set low), all TTL device outputs are tristated. The OE signal has an internal pull-up. OE Page 26 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 · 805/388-3700 · FAX: 805/987-5896 G52210-0 G52210-0, Rev. 4.3 3/30/00 VITESSE SEMICONDUCTOR CORPORATION Datasheet STS-48c Physical Layer Packet/ATM Over SONET/SDH Device VSC9112 VSC9112 Signal POS Mode: TDAT[31.0] ATM Mode: TUDATA[31.0] POS Mode: TPRTY ATM Mode: TUPRTY POS Mode: TMOD[1.0] Name I/O Type Transmit Packet Data Bus / UTOPIA Transmit Data Bus I TTL Description POS Mode: Four-octet true data driven from Packet to PHY layer. TDAT[31] is MSB. Packets are aligned to 32 bit TDAT boundary. ATM Mode: Four-octet true data driven from ATM to PHY layer. TUDATA[31] is MSB. Transmit Bus Parity / UTOPIA Transmit Bus Parity I TTL POS Mode: TPRTY is the odd/even (programmable, default odd) parity bit over TDAT[31.0]. The signal is only valid when asserted simultaneously with TENB. ATM Mode: TUPRTY is the odd/even (programmable, default odd) parity bit over TUDATA[31.0], driven by the ATM layer. The signal is only valid when asserted simultaneously with TUENB*. Transmit Word Modulo I TTL POS Mode only: Data Qualifier. Qualifer for the four TDAT bytes. Defines which of the four TDAT bytes contains valid data when TEOP and TENB are asserted. Non-EOP words always contains 4 valid TDAT bytes. POS Mode: TSOP ATM Mode: TUSOC Transmit Start Of Packet / UTOPIA Transmit Start Of Cell I TTL POS Mode: Active high signal asserted by the packet layer when TDAT contains the first valid byte of the packet. The signal isvalid when asserted simultaneously with TENB. The packet interface can be operated without using this signal. ATM Mode: Start Of Cell. Active high signal asserted by the ATM layer when TUDATA contains the first valid byte of the cell. The signal is only valid when asserted simultaneously with TUENB*. POS Mode: TEOP G52210-0 G52210-0, Rev. 4.3 3/30/00 Transmit End Of packet I TTL POS Mode only: Is asserted by the packet layer when TDAT contains the last valid byte of the packet. The signal is only valid when asserted simultaneously with TENB. Active high signal. © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 · 805/388-3700 · FAX: 805/987-5896 Page 27 VITESSE SEMICONDUCTOR CORPORATION Datasheet STS-48c Physical Layer Packet/ATM Over SONET/SDH Device Signal POS Mode: DTPA ATM Mode: TUFULL*/ TUCLAV VSC9112 VSC9112 Name I/O Type Transmit PolledPHY Packet Available / Transmit Full/Cell Available O TTL Description POS Mode: DTPA transitions high when a programmable minimum number of bytes are available in the Tx FIFO. Once high, the DTPA indicates that the Tx FIFO is not full. WHEN DTPA transitions low, it optionally indicates that the Tx FIFO is full or near full. ATM Mode: For UTOPIA flow control. The TUFULL* definition applies to word level flow control, and TUCLAV definition applies to cell level flow control. POS Mode: TERR Transmit Error Indicator I TTL POS Mode only: May be used to force HDLC frame abortion of insertion of FCS error in the transmitted HDLC/PPP frames. The TERR value is only relevant for the TEOP marked word, and ingored for all other word writes. POS Mode: TENB Transmit Write Enable / Transmit Write Enable I TTL POS Mode: Active low signal asserted by the packet layer during cycles when TDAT contains valid packet data. Transmit FIFO Write Clock / Transmit Write Clock I Transmit FIFO Write Clock Looped / Transmit Clock Looped O ATM Mode: TUENB* POS Mode: TFCLK ATM Mode: TUCLK POS Mode: TFCLKO ATM Mode: TUCLKO Page 28 ATM Mode: Active low signal asserted by the ATM layer during cycles when TUDATA contains valid cell data. TTL POS Mode: Transfer/synchronization clock provided by the packet layer to the PHY layer for synchronizing transfers on TDAT. ATM Mode: Transfer/synchronization clock provided by the ATM layer to the PHY layer for synchronizing transfers on TUDATA. TTL POS Mode: The TFCLK input looped back out. ATM Mode: The TUCLK input looped back out. © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 · 805/388-3700 · FAX: 805/987-5896 G52210-0 G52210-0, Rev. 4.3 3/30/00 VITESSE SEMICONDUCTOR CORPORATION Datasheet STS-48c Physical Layer Packet/ATM Over SONET/SDH Device VSC9112 VSC9112 Signal POS Mode: RDAT[31.0] ATM Mode: RUDATA[31.0] POS Mode: RPRTY ATM Mode: RUPRTY POS Mode: RMOD[1.0] Name I/O Type Receive Packet Data Bus / Receive Cell Data Bus O TTL Description POS Mode: Four-octet true data driven from PHY to packet layer. RDAT[31] is MSB. Packets are aligned to 32 bit RDAT boundary. ATM Mode: Four-octet wide data driven from PHY to ATM layer. RUDATA[31] is the MSB. Receive Bus Parity / Receive Bus Parity O TTL POS Mode: RXPRTY is the odd/even (programmable, default odd) parity bit over RDAT[31.0]. ATM Mode: RUPRTY is the odd/even (programmable, default odd) parity for RUDATA[31.0]. Receive Word Module O TTL POS Mode only: Data Qualifier. Qualifer for the four RDAT bytes. Defines which of the four RDAT bytes contains valid data. This signal is ignored when REOP is not asserted. POS Mode: RSOP ATM Mode: RUSOC POS Mode: REOP G52210-0 G52210-0, Rev. 4.3 3/30/00 Receive Start Of Packet / Receive Start Of Cell O TTL POS Mode: Start Of Packet. Is asserted when TDAT contains the first valid byte of the packet. Active high signal. The interface can be operated without using this signal. ATM Mode: Active high signal asserted by the PHY layer when RUDATA contains the first valid byte of a cell. To support multiple PHY configurations. Receive End Of Packet O TTL POS Mode only: End Of Packet. Is asserted when RDAT contains the last valid byte of the packet. Active high signal. © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 · 805/388-3700 · FAX: 805/987-5896 Page 29 VITESSE SEMICONDUCTOR CORPORATION Datasheet STS-48c Physical Layer Packet/ATM Over SONET/SDH Device Signal POS Mode: RVAL ATM Mode: RUEMPTY*/ RUCLAV VSC9112 VSC9112 Name I/O Type Description Receive Data Valid / Receive Empty/ Cell Available. O TTL POS Mode: RVAL indicates the validity of the receive data signals. When RVAL is high, the receive signals (RDAT, RSOP, REOP, RMOD, RXPRTY and RERR) are valid. When RVAL is low, all receive signals are invalid and must be disregarded. RVAL will transition low on a FIFO empty condition or on an end of packet. No data will be removed from the receive FIFO while RVAL is deasserted. Once deasserted, RVAL will remain deasserted until current PHY has been deselected. ATM Mode: For UTOPIA flow control. The RUEMPTY* definition applies to word level flow control, and RUCLAV definition applies to cell level flow control. POS Mode: RERR Receive Error Indicator O TTL POS Mode only: Indicates if the packet contained an error (e.g. Abort/FCS error). This is an active high signal which is asserted during an EOP word. POS Mode: RENB Receive Read Enable / UTOPIA Read Enable I TTL POS Mode: Active low signal asserted by the packet layer to indicate that RVAL, RSOP, RPRTY, RDAT[31.0], RMOD[1.0], REOP, and RERR output signals will be sampled at the end of the next cycle. ATM Mode: RUENB ATM Mode: Active low signal asserted by the ATM layer to indicate that RUDATA, RUSOC and RPRTY will be sampled at the end of the next cycle. POS Mode: RFCLK ATM Mode: RUCLK POS Mode: RFCLKO ATM Mode: RUCLKO Page 30 Receive FIFO Write Clock / Receive Clock I TTL POS Mode: Clock. Transfer/synchronization clock provided by the packet layer to the PHY layer for synchronizing transfers on TDAT. ATM Mode: Clock. Transfer/synchronization clock provided by the ATM layer to the PHY layer for synchronizing transfers on RUDATA. Receive FIFO Write Clock Looped / Receive Clock Looped O TTL POS Mode: Looped clock. The RXCLK input looped back out. ATM Mode: The RUCLK looped back out. © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 · 805/388-3700 · FAX: 805/987-5896 G52210-0 G52210-0, Rev. 4.3 3/30/00 VITESSE SEMICONDUCTOR CORPORATION Datasheet STS-48c Physical Layer Packet/ATM Over SONET/SDH Device VSC9112 VSC9112 Package Pin List Signal BGA Pin Signal BGA Pin Signal BGA Pin GND A1 GND A2 RLIN[10]+ A3 RLIN[12]+ A4 RLIN[14]+ A5 RLPRTY+ A6 RLFP- A7 A[8] A8 A[7] A9 A[5] A10 A[3] A11 A[1] A12 GND A13 GND A14 D[4] A15 D[1] A16 NC A17 TESTPIN A18 NC A19 NC A20 REOP A21 RFCLK A22 RSOP A23 RDAT[0] A24 GND A25 GND A26 GND B1 VDD B2 GND B3 RLIN[10]- B4 RLIN[12]- B5 RLIN[14]- B6 RLPRTY- B7 RXRCLK B8 LOF B9 A[6] B10 A[4] B11 A[2] B12 D[7] B13 D[6] B14 D[3] B15 D[0] B16 LCD-P B17 NC B18 NC B19 NC B20 RFCLKO B21 RERR B22 RMOD[1] B23 GND B24 VDD B25 GND B26 RLIN[9]- C1 GND C2 VDD C3 RLIN[11]+ C4 RLIN[13]+ C5 RLIN[15]+ C6 RLCLK- C7 RLFP+ C8 LOPC C9 PMTICK C10 CSB C11 A[0] C12 INTB C13 D[5] C14 D[2] C15 LOS C16 TESTPIN C17 NC C18 NC C19 NC C20 RVAL C21 RMOD[0] C22 RDAT[2] C23 VDD C24 GND C25 RDAT[5] C26 RLIN[7]- D1 RLIN[9]+ D2 RLIN[8]- D3 VDD D4 RLIN[11]- D5 RLIN[13]- D6 RLIN[15]- D7 RLCLK+ D8 VDD D9 CLKRSTEN D10 ALE D11 WRB D12 RDB D13 VDD D14 RSTB D15 NC D16 NC D17 VDD D18 NC D19 RENB D20 RPRTY D21 RDAT[1] D22 VDD D23 RDAT[3] D24 RDAT[6] D25 RDAT[9] D26 RLIN[5]- E1 RLIN[7]+ E2 RLIN[6]- E3 RLIN[8]+ E4 RDAT[4] E23 RDAT[7] E24 RDAT[10] E25 G52210-0 G52210-0, Rev. 4.3 3/30/00 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 · 805/388-3700 · FAX: 805/987-5896 Page 31 VITESSE SEMICONDUCTOR CORPORATION Datasheet STS-48c Physical Layer Packet/ATM Over SONET/SDH Device Signal BGA Pin RDAT[13] RLIN[4]- VSC9112 VSC9112 Signal BGA Pin Signal BGA Pin E26 RLIN[3]- F1 RLIN[5]+ F2 F3 RLIN[6]+ F4 RDAT[8] F23 RDAT[11] F24 RDAT[14] F25 RDAT[17] F26 RLIN[1]- G1 RLIN[3]+ G2 RLIN[2]- G3 RLIN[4]+ G4 RDAT[12] G23 RDAT[15] G24 RDAT[18] G25 RDAT[20] G26 GPIO[6] H1 RLIN[0]- H2 RLIN[1]+ H3 RLIN[2]+ H4 RDAT[16] H23 RDAT[19] H24 RDAT[21] H25 RDAT[24] H26 GPIO[3] J1 GPIO[5] J2 RLIN[0]+ J3 VDD J4 VDD J23 RDAT[22] J24 RDAT[25] J25 RDAT[27] J26 VDD5 9) K1 GPIO[1] K2 GPIO[4] K3 GPIO[7] K4 RDAT[23] K23 RDAT[26] K24 RDAT[29] K25 RDAT[31] K26 TDI L1 OE L2 GPIO[0] L3 GPIO[2] L4 RDAT[28] L23 RDAT[30] L24 NC L25 VDD5 9) L26 TRSTB M1 TMS M2 TCK M3 TDO M4 NC M23 NC M24 NC M25 NC M26 GND N1 TLSYNC- N2 TLSYNC+ N3 VDD N4 NC N23 NC N24 NC N25 GND N26 GND P1 TLOUT[0]- P2 TLOUT[0]+ P3 TLOUT[2]+ P4 VDD P23 NC P24 NC P25 GND P26 TLOUT[2]- R1 TLOUT[1]+ R2 TLOUT[1]- R3 TLOUT[3]+ R4 TDAT[2] R23 TDAT[0] R24 NC R25 NC R26 TLOUT[3]- T1 TLOUT[5]+ T2 TLOUT[4]+ T3 TLOUT[6]+ T4 TDAT[7] T23 TDAT[5] T24 TDAT[3] T25 TDAT[1] T26 TLOUT[5]- U1 TLOUT[4]- U2 TLOUT[7]+ U3 TLOUT[8]+ U4 TDAT[12] U23 TDAT[9] U24 TDAT[6] U25 TDAT[4] U26 TLOUT[6]- V1 TLOUT[7]- V2 TLOUT[9]+ V3 VDD V4 VDD V23 TDAT[13] V24 TDAT[10] V25 TDAT[8] V26 TLOUT[8]- W1 TLOUT[9]- W2 TLOUT[10]+ W3 TLOUT[11]+ W4 TDAT[19] W23 TDAT[16] W24 TDAT[14] W25 TDAT[11] W26 TLOUT[10]- Y1 TLOUT[12]+ Y2 TLOUT[11]- Y3 TLOUT[13]+ Y4 Page 32 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 · 805/388-3700 · FAX: 805/987-5896 G52210-0 G52210-0, Rev. 4.3 3/30/00 VITESSE SEMICONDUCTOR CORPORATION Datasheet STS-48c Physical Layer Packet/ATM Over SONET/SDH Device VSC9112 VSC9112 Signal BGA Pin Signal BGA Pin Signal BGA Pin TDAT[23] Y23 TDAT[20] Y24 TDAT[17] Y25 TDAT[15] Y26 TLOUT[12]- AA1 TLOUT[14]+ AA2 TLOUT[13]- AA3 TLOUT[15]+ AA4 TDAT[27] AA23 TDAT[24] AA24 TDAT[21] AA25 TDAT[18] AA26 TLOUT[14]- AB1 TLPRTY+ AB2 TLOUT[15]- AB3 TLCLKOUT- AB4 TDAT[31] AB23 TDAT[28] AB24 TDAT[25] AB25 TDAT[22] AB26 TLPRTY- AC1 TLCLK- AC2 TLCLKOUT+ AC3 VDD AC4 TLFP- AC5 RSPVALID1 AC6 RTOHVALID AC7 RTOHFP AC8 VDD AC9 TSPDAT1 AC10 TSPFP1 AC11 TSPFP2 AC12 VDD AC13 NC AC14 NC AC15 NC AC16 NC AC17 VDD AC18 NC AC19 NC AC20 DTPA AC21 TPRTY AC22 VDD AC23 TMOD[0] AC24 TDAT[29] AC25 TDAT[26] AC26 TLCLK+ AD1 GND AD2 VDD AD3 TLFP+ AD4 RSPDAT1 AD5 RTOH[3] AD6 RSPCLK2 AD7 RTOHCLK AD8 TSPCLK1 AD9 TSPREN1 AD10 TSPCLK2 AD11 TSPREN2 AD12 NC AD13 NC AD14 NC AD15 NC AD16 NC AD17 NC AD18 NC AD19 NC AD20 TFCLK AD21 TERR AD22 TMOD[1] AD23 VDD AD24 GND AD25 TDAT[30] AD26 GND AE1 VDD AE2 GND AE3 RTOH[0] AE4 RTOH[2] AE5 RSPFP AE6 RSPVALID2 AE7 TTOH[1] AE8 TTOH[3] AE9 TTOHREN AE10 TSPDAT2 AE11 NC AE12 NC AE13 NC AE14 NC AE15 NC AE16 NC AE17 NC AE18 NC AE19 NC AE20 NC AE21 TFCLKO AE22 TEOP AE23 GND AE24 VDD AE25 GND AE26 GND AF1 GND AF2 TXRCLK AF3 RTOH[1] AF4 RSPCLK1 AF5 RSPDAT2 AF6 TTOH[0] AF7 TTOH[2] AF8 TTOHEN AF9 TTOHCLK AF10 TTOHFP AF11 NC AF12 GND AF13 GND AF14 NC AF15 NC AF16 NC AF17 NC AF18 NC AF19 G52210-0 G52210-0, Rev. 4.3 3/30/00 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 · 805/388-3700 · FAX: 805/987-5896 Page 33 VITESSE SEMICONDUCTOR CORPORATION Datasheet STS-48c Physical Layer Packet/ATM Over SONET/SDH Device Signal BGA Pin Signal VSC9112 VSC9112 BGA Pin Signal BGA Pin NC AF20 NC AF21 NC AF22 TENB AF23 TSOP AF24 GND AF25 GND AF26 9) VDD5 is used only as a bias for protection. These pins should be tied to the same +3.3V, along with other VDD pins, in a +3.3V only environment. Page 34 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 · 805/388-3700 · FAX: 805/987-5896 G52210-0 G52210-0, Rev. 4.3 3/30/00 VITESSE SEMICONDUCTOR CORPORATION Datasheet STS-48c Physical Layer Packet/ATM Over SONET/SDH Device VSC9112 VSC9112 Package Information 352 BGA Package Dimensions SIDE VIEW TOP VIEW BOTTOM VIEW DIE SIDE G52210-0 G52210-0, Rev. 4.3 3/30/00 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 · 805/388-3700 · FAX: 805/987-5896 Page 35 VITESSE SEMICONDUCTOR CORPORATION Datasheet STS-48c Physical Layer Packet/ATM Over SONET/SDH Device VSC9112 VSC9112 Ordering Information The ordering number for this product is formed by a combination of the device number and package type. VSC9112 VSC9112 SB Device Type VSC9112SB VSC9112SB - 2.5Gb/s Transport Terminating Transciever Package Type SB: 352-pin Super BGA Notice Vitesse Semiconductor Corporation reserves the right to make changes in its products specifications or other information at any time without prior notice. Therefore the reader is cautioned to confirm that this datasheet is current prior to placing orders. The company assumes no responsibility for any circuitry described other than circuitry entirely embodied in a Vitesse product. Warning Vitesse Semiconductor Corporation's product are not intended for use in life support appliances, devices or systems. Use of a Vitesse product in such applications without the written consent is prohibited. Page 36 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 · 805/388-3700 · FAX: 805/987-5896 G52210-0 G52210-0, Rev. 4.3 3/30/00