VSC8175 VSC8185 PB-VSC8175-001 STS-192/SDH STM-64 CK/16 5G-12

VSC8175 9.9-10.7Gb/s 16:1 Multiplexer and Clock Generator with High-speed Clock Output F E AT U R E S : Fully Compliant with OIF

PHYSICAL LAYER PRODUCT VSC8175 VSC8175 9.9-10.7Gb/s 16:1 Multiplexer and Clock Generator with High-speed Clock Output F E AT U R E S : Fully Compliant with OIF 99.102 SONET/SDH Jitter Compliant High-speed Output Clock Narrow Clock-to-Data Skew Range Low Power 1.7W (Typ) +3.3V Single Supply Continuous Tuning Operation from 9.953 to 10.709Gb/s Rates BENEFITS: 155-168/622-670 MHz Reference Clock Input Provides High-speed Output Clock for RZ and Re-timed Laser Driver Applications Reliable 90-Ball BGA Package Provides Lowest Power Solution in its Performance Class Up to 85°C Case Temperature Pin-compatible Upgrade Paths to Advance FEC (11.5 to 12.5Gb/s) Solutions (VSC8185 VSC8185) A P P L I C AT I O N S : Integrated PLL Based Clock Generator SONET/SDH Networking Meets SONET/SDH Jitter Generation Requirements RZ Modulation Compliant LVDS Interface Re-Timing Laser Drivers Thermal Expansion of TBGA Package is Matched to the PC Board for High Reliability DWDM Systems G.975/709 Forward Error Correction (FEC) Input FIFO to Simplify Parallel Interface Timing Ultra-Long Haul System Loss-of-Lock and Internal Temperature Sensing to Assist in Monitoring Device Operation Telecommunications Transmission Systems Data Polarity Invert and Bit Order Swap for Ease of Layout Test Equipment PB-VSC8175-001 PB-VSC8175-001 VSC8175 VSC8175 9.9-10.7Gb/s 16:1 Multiplexer and Clock Generator with High-speed Clock Output GENERAL DESCRIPTION: The VSC8175 VSC8175 consists of a 16:1 multiplexer and a clock generator for use in SONET STS-192/SDH STS-192/SDH STM-64 STM-64 systems. The 16:1 multiplexer accepts 16 parallel LVDS inputs and PARITY at a data rate of 622.08Mb/s to 669.31Mb/s. This parallel data stream is then serialized into a 9.953Gb/s to 10.709Gb/s output. The clock generator creates the 9.953GHz to 10.709GHz clock signal used to re-time the transmitted serialized data. The clock generator requires a 155 to 167MHz or 622 to 669MHz LVPECL reference clock input. To ease timing constraints on the parallel interface, a 16-bit wide FIFO is included. A high-speed clock output (COUT+ ) is provided that is structured to the high-speed serial data output. A divided-by-16 or divide-by-64 LVDS clock output is available for use as a clock input to the parallel data source. Additional features include parity checking of a parity bit that is clocked in with the 16-bit parallel data, Bit Order Swap and Data Polarity Invert. To assist in monitoring device operation a Loss-of-Lock alarm and internal temperature sensing are provided. The device is packaged in a modified 90-Ball Grid Array (BGA). S P E C I F I C AT I O N S : VSC8175 VSC8175 BLOCK DIAGRAM: 9.953 to 10.709Gb/s Continuous Operation AUTORSTN OVERFLOW DELAY RESETN Data Output Voltage Swing: 600 mV (Min) DINVERT Data Output Rise/Fall: 25ps (Typ) BITORDER DINVALID+ PARSENSE DELAY DINVALIDPARITY+ 10ps Wideband Jitter (Max) PARITYD0+ RST High Speed Clock Voltage Swing: 600 MV (Min) OVR D0- +/- 15 ps Clock to Data Skew Range Over Temperature D1+ D1- Supply Voltage: 3.3V (Typ) DOUT+ 16:1 FIFO Total Power Dissipation: 1.7W (Typ) DOUT- D14+ D14- Operating Temperature Range: 0°C to +85°C (case) COUT+ COUT- D15+ 15x15mm Low Profile 90 Ball TBGA (Taped BGA) Package D15- DCK+ DCK- CK/16 CK/16 CKSEL TIMING CK16_64+ GENERATOR CK16_64719MHz/180MHz LOLN REFSEL 11.5G-12 5G-12.5G REFCK+ PLL LOSS OF LOCK DETECT REFCK- NOREFN Your Partner for Success. For more information on Vitesse Products visit the Vitesse web site at www.vitesse.com or contact Vitesse Sales at (800) VITESSE or sales@vitesse.com ©2002 Vitesse Semiconductor Corporation 741 Calle Plano Camarillo, CA 93012 Tel: 805.388.3700 Fax: 805.388.7565 www.vitesse.com