32/64KB VRS51X570 VRS51X580 PLCC-44 QFP-44 DIP-40 80C51/52 80C51/80C52 - Datasheet Archive

 

Datasheet Rev 1.3 Versa 8051 MCUs with 32/64KB Feature Set PWM2/P1.5 6 7 P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 P4.2 VDD FIGURE 2:

 

VRS51x570/580 Datasheet Rev 1.3 Versa 8051 MCUs with 32/64KB 32/64KB Feature Set PWM2/P1.5 6 7 P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 P4.2 VDD FIGURE 2: VRS51X570 VRS51X570 / VRS51X580 VRS51X580 PLCC AND QFP PINOUT DIAGRAMS P1.2 The VRS51x570 and VRS51x580 are available in PLCC-44 PLCC-44, QFP-44 QFP-44 and DIP-40 DIP-40 packages in the Industrial temperature range. The Flash memory can be programmed using programmers from Ramtron or other 3rd party commercial programmer suppliers. 5-Channel PWM on P1.3 to P1.7 Full duplex serial port (UART) Three 16-bit Timers/Counters Watch Dog Timer 8-bit Unsigned Division / Multiply BCD arithmetic Direct and Indirect Addressing Two levels of interrupt priority and nested interrupts Power saving modes Code protection function Operates at a clock frequency of up to 40MHz Low EMI (inhibit ALE) Programming voltage: 12V Industrial Temperature range (-40°C to +85°C) 5V and 3V versions available (see Ordering information.) T2/P1.0 These devices also include a fifth, 4-bit, I/O port mapped into the "no connect" pins of the standard 8051/52 package. This provides a total of 36 I/Os while maintaining compatibility with standard 80C51/52 80C51/52 pin outs. 80C51/80C52 80C51/80C52 pin compatible 12 clock periods per machine cycle 32KB / 64KB on-chip Flash memory 1024 Bytes on-chip data SRAM 36 I/O lines: P0-P3 = 8-bit, P4 = 4-bit PWM0/P1.3 Ideal for a wide range of applications requiring large amounts of program/data memory, coupled with comprehensive peripheral support, the VRS51x570/580 devices include 32KB/64KB 32KB/64KB of Flash memory, respectively, and 1KB of SRAM, 5 PWM output channels, a UART, three 16-bit timers, a Watch Dog timer and power down features. · · · · · · · · · · · · · · · · · · · · T2EX/P1.1 The VRS51x570 and the VRS51x580 are low cost 8-bit microcontrollers based on the standard 80C51 80C51 microcontroller family architecture. They are pin compatible and drop-in replacements for most 8051 MCUs. PWM1/P1.4 Overview 40 1 39 PWM3/P1.6 FIGURE 1: VRS51X570 VRS51X570 / VRS51X580 VRS51X580 FUNCTIONAL DIAGRAM 8051 PROCESSOR RESET RXD/P3.0 P0.7/AD7 #EA VRS51x570/580 PLCC-44 PLCC-44 P4.3 TXD/P3.1 ADDRESS/ DATA BUS P4.1 ALE #PSEN P2.7/A15 7/A15 #INT0/P3.2 #INT1/P3.3 T0/P3.4 T1/P3.5 P2.6/A14 6/A14 P2.5/A13 5/A13 P0.0/AD0 VDD P2.4/A12 4/A12 P2.1/A9 P2.2/A10 2/A10 P2.3/A11 3/A11 P2.6/A14 6/A14 P2.5/A13 5/A13 P2.1/A9 P2.0/A8 VRS51x570/580 QFP-44 QFP-44 P4.2 T2/P1.0 P4.0 VSS T2EX/P1.1 P1.2 44 Ramtron International Corporation 1850 Ramtron Drive Colorado Springs Colorado, USA, 80921 12 11 #INT1/P3.3 #INT0/P3.2 P4.3 TXD/P3.1 RESET 1 #RD/P3.7 #WR/P3.6 T0/P3.4 T1/P3.5 5 XTAL1 XTAL2 RXD/P3.0 PWM PWM0/P1.3 PWM1/P1.4 P2.4/A12 4/A12 P2.3/A11 3/A11 P2.2/A10 2/A10 PWM4/P1.7 WATCHDOG TIMER 23 22 PWM3/P1.6 RESET 33 P0.2/AD2 P0.1/AD1 PWM2/P1.5 TIMER 2 POWER CONTROL #PSEN P2.7/A15 7/A15 4 TIMER 1 34 P4.0 PORT 4 TIMER 0 P0.3/AD3 P2.0/A8 8 P4.1 ALE PORT 3 VSS 2 INTERRUPT INPUTS P0.7/AD7 #EA 8 XTAL1 PORT 2 XTAL2 UART #RD/P3.7 8 #WR/P3.6 PORT 1 29 8 1024 Bytes of SRAM 28 P0.5/AD5 P0.6/AD6 PORT 0 17 18 P0.4/AD4 64KB FLASH P0.4/AD4 P0.5/AD5 P0.6/AD6 PWM4/P1.7 http://www.ramtron.com MCU customer service: 1-800-943-4625, 1-514-871-2447, ext. 208 1-800-545-FRAM 1-800-545-FRAM, 1-719-481-7000 page 1 of 45 VRS51x570/580 Pin Descriptions for QFP-44 QFP-44 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 O I/O O I/O O I/O I I I/O I/O O I/O I I/O I I/O I I/O I I/O O I/O O I/O O I I/O I/O O I/O O I/O O I/O O I/O O I/O O PWM Channel 2 Bit 5 of Port 1 PWM Channel 3 Bit 6 of Port 1 PWM Channel 4 Bit 7 of Port 1 Reset Receive Data Bit 0 of Port 3 Bit 3 of Port 4 Transmit Data & Bit 1 of Port 3 External Interrupt 0 Bit 2 of Port 3 External Interrupt 1 Bit 3 of Port 3 Timer 0 Bit 4 of Port 3 Timer 1 & 3 Bit 5 of Port Ext. Memory Write Bit 6 of Port 3 Ext. Memory Read Bit 7 of Port 3 Oscillator/Crystal Output Oscillator/Crystal In Ground Bit 0 of Port 4 Bit 0 of Port 2 Bit 8 of External Memory Address Bit 1 of Port 2 Bit 9 of External Memory Address Bit 2 of Port 2 Bit 10 of External Memory Address Bit 3 of Port 2 & Bit 11 of External Memory Address Bit 4 of Port 2 Bit 12 of External Memory Address Bit 5 of Port 2 Bit 13 of External Memory Address 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 I/O Function I/O O I/O O O O I/O I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I/O I I/O I/O O Bit 6 of Port 2 Bit 14 of External Memory Address Bit 7 of Port 2 Bit 15 of External Memory Address Program Store Enable Address Latch Enable Bit 1 of Port 4 External Access Bit 7 Of Port 0 Data/Address Bit 7 of External Memory Bit 6 of Port 0 Data/Address Bit 6 of External Memory Bit 5 of Port 0 Data/Address Bit 5 of External Memory Bit 4 of Port 0 Data/Address Bit 4 of External Memory Bit 3 Of Port 0 Data/Address Bit 3 of External Memory Bit 2 of Port 0 Data/Address Bit 2 of External Memory Bit 1 of Port 0 & Data Address Bit 1 of External Memory Bit 0 Of Port 0 & Data Address Bit 0 of External Memory VCC Bit 2 of Port 4 Timer 2 Clock Out Bit 0 of Port 1 Timer 2 Control Bit 1 of Port 1 Bit 2 of Port 1 PWM Channel 0 P1.3 I/O Bit 3 of Port 1 PWM1 O PWM Channel 1 P1.4 I/O Bit 4 of Port 1 33 P0.3/AD3 P2.6/A14 6/A14 P2.5/A13 5/A13 4 PWM2 P1.5 PWM3 P1.6 PWM4 P1.7 RES RXD P3.0 P4.3 TXD P3.1 #INT0 P3.2 #INT1 P3.3 T0 P3.4 T1 P3.5 #WR P3.6 #RD P3.7 XTAL2 XTAL1 VSS P4.0 P2.0 A8 P2.1 A9 P2.2 A10 P2.3 A11 P2.4 A12 P2.5 A13 Name P2.6 A14 P2.7 A15 #PSEN ALE P4.1 #EA P0.7 AD7 P0.6 AD6 P0.5 AD5 P0.4 AD4 P0.3 AD3 P0.2 AD2 P0. 1 AD1 P0.0 AD0 VDD P4.2 T2 P1.0 T2EX P1.1 P1.2 PWM0 #PSEN P2.7/A15 7/A15 3 Function P4.1 ALE 2 I/O P0.7/AD7 #EA 1 Name P0.5/AD5 P0.6/AD6 QFP - 44 P0.4/AD4 QFP - 44 TABLE 1: PIN DESCRIPTIONS FOR QFP-44/ QFP-44/ 23 22 34 P0.2/AD2 P0.1/AD1 P2.3/A11 3/A11 P2.2/A10 2/A10 P0.0/AD0 VDD P2.1/A9 P2.0/A8 VRS51x570/580 QFP-44 QFP-44 P4.2 T2/P1.0 P4.0 VSS T2EX/P1.1 P1.2 XTAL1 XTAL2 44 12 11 #INT1/P3.3 P4.3 TXD/P3.1 #INT0/P3.2 RESET RXD/P3.0 PWM4/P1.7 PWM3/P1.6 PWM2/P1.5 1 #RD/P3.7 #WR/P3.6 T0/P3.4 T1/P3.5 PWM0/P1.3 PWM1/P1.4 P2.4/A12 4/A12 _ page 2 of 45 www.ramtron.com VRS51x570/580 Pin Descriptions for PLCC-44 PLCC-44 TABLE 2: PIN DESCRIPTIONS FOR PLCC-44 PLCC-44 11 12 13 14 15 16 17 18 19 20 21 22 23 28 29 30 31 32 33 34 35 36 AD7 I/O P0.6 37 I/O AD6 I/O P0.5 39 I/O AD5 I/O P0.4 38 I/O AD4 I/O P0.3 40 I/O AD3 I/O P0.2 41 42 43 I/O P0. 1 AD1 P0.0 AD0 VDD I/O I/O I/O I/O PWM1/P1.4 44 I/O AD2 PWM2/P1.5 7 6 P0.3/AD3 9 10 27 P0.2/AD2 8 26 Function Bit 0 of Port 2 Bit 8 of External Memory Address Bit 1 of Port 2 Bit 9 of External Memory Address Bit 2 of Port 2 Bit 10 of External Memory Address Bit 3 of Port 2 & Bit 11 of External Memory Address Bit 4 of Port 2 Bit 12 of External Memory Address Bit 5 of Port 2 Bit 13 of External Memory Address Bit 6 of Port 2 Bit 14 of External Memory Address Bit 7 of Port 2 Bit 15 of External Memory Address Program Store Enable Address Latch Enable Bit 1 of Port 4 External Access Bit 7 Of Port 0 Data/Address Bit 7 of External Memory Bit 6 of Port 0 Data/Address Bit 6 of External Memory Bit 5 of Port 0 Data/Address Bit 5 of External Memory Bit 4 of Port 0 Data/Address Bit 4 of External Memory Bit 3 Of Port 0 Data/Address Bit 3 of External Memory Bit 2 of Port 0 Data/Address Bit 2 of External Memory Bit 1 of Port 0 & Data Address Bit 1 of External Memory Bit 0 Of Port 0 & Data Address Bit 0 of External Memory VCC P0.1/AD1 7 25 I/O I/O O I/O O I/O O I/O O I/O O I/O O I/O O I/O O O O I/O I I/O VDD 6 24 Name P2.0 A8 P2.1 A9 P2.2 A10 P2.3 A11 P2.4 A12 P2.5 A13 P2.6 A14 P2.7 A15 #PSEN ALE P4.1 #EA P0.7 P0.0/AD0 5 Bit 2 of Port 4 Timer 2 Clock Out Bit 0 of Port 1 Timer 2 Control Bit 1 of Port 1 Bit 2 of Port 1 PWM Channel 0 Bit 3 of Port 1 PWM Channel 1 Bit 4 of Port 1 PWM Channel 2 Bit 5 of Port 1 PWM Channel 3 Bit 6 of Port 1 PWM Channel 4 Bit 7 of Port 1 Reset Receive Data Bit 0 of Port 3 Bit 3 of Port 4 Transmit Data & Bit 1 of Port 3 External Interrupt 0 Bit 2 of Port 3 External Interrupt 1 Bit 3 of Port 3 Timer 0 Bit 4 of Port 3 Timer 1 & 3 Bit 5 of Port Ext. Memory Write Bit 6 of Port 3 Ext. Memory Read Bit 7 of Port 3 Oscillator/Crystal Output Oscillator/Crystal In Ground Bit 0 of Port 4 T2/P1.0 4 I/O I I/O I I/O I/O O I/O O I/O O I/O O I/O O I/O I I I/O I/O O I/O I I/O I I/O I I/O I I/O O I/O O I/O O I I/O PLCC - 44 P4.2 3 P4.2 T2 P1.0 T2EX P1.1 P1.2 PWM0 P1.3 PWM1 P1.4 PWM2 P1.5 PWM3 P1.6 PWM4 P1.7 RES RXD P3.0 P4.3 TXD P3.1 #INT0 P3.2 #INT1 P3.3 T0 P3.4 T1 P3.5 #WR P3.6 #RD P3.7 XTAL2 XTAL1 VSS P4.0 Function P1.2 2 I/O T2EX/P1.1 1 Name PWM0/P1.3 PLCC - 44 40 1 39 PWM3/P1.6 P0.5/AD5 P0.6/AD6 PWM4/P1.7 RESET RXD/P3.0 P0.7/AD7 #EA VRS51x570/580 PLCC-44 PLCC-44 P4.3 TXD/P3.1 P4.1 ALE #PSEN P2.7/A15 7/A15 #INT0/P3.2 #INT1/P3.3 17 18 P2.3/A11 3/A11 P2.2/A10 2/A10 29 P2.6/A14 6/A14 P2.5/A13 5/A13 P2.4/A12 4/A12 P2.1/A9 VSS P4.0 P2.0/A8 XTAL1 XTAL2 28 #RD/P3.7 #WR/P3.6 T0/P3.4 T1/P3.5 P0.4/AD4 _ www.ramtron.com page 3 of 45 VRS51x570/580 VRS51x570 ­ VRS51x580 DIP-40 DIP-40 Pin Descriptions DIP40 DIP40 TABLE 3: VRS51X570 VRS51X570 ­ VRS51X580 VRS51X580 PIN DESCRIPTIONS FOR DIP40 DIP40 PACKAGE DIP40 DIP40 Name 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 I/O T2 P1.0 T2EX P1.1 P1.2 PWM0 P1.3 PWM1 P1.4 PWM2 P1.5 PWM3 P1.6 PWM4 P1.7 RESET RXD P3.0 TXD P3.1 #INT0 P3.2 #INT1 P3.3 T0 P3.4 T1 P3.5 #WR P3.6 #RD P3.7 XTAL2 XTAL1 VSS I I/O I I/O I/O O I/O O I/O O I/O O I/O O I/O I I I/O O I/O I I/O I I/O I I/O I I/O O I/O O I/O O I - Function Timer 2 Clock Out Bit 0 of Port 1 Timer 2 Control Bit 1 of Port 1 Bit 2 of Port 1 PWM Channel 0 Bit 3 of Port 1 PWM Channel 1 Bit 4 of Port 1 PWM Channel 2 Bit 5 of Port 1 PWM Channel 3 Bit 6 of Port 1 PWM Channel 4 Bit 7 of Port 1 Reset Receive Data Bit 0 of Port 3 Transmit Data & Bit 1 of Port 3 External Interrupt 0 Bit 2 of Port 3 External Interrupt 1 Bit 3 of Port 3 Timer 0 Bit 4 of Port 3 Timer 1 & 3 Bit 5 of Port Ext. Memory Write Bit 6 of Port 3 Ext. Memory Read Bit 7 of Port 3 Oscillator/Crystal Output Oscillator/Crystal In Ground 22 23 24 25 26 27 28 29 30 31 32 33 1 40 VDD T2EX / P1.1 2 39 I/O I/O O I/O O I/O O I/O O I/O O I/O O I/O O I/O O O O AD7 I/O I/O AD6 I/O I I/O P0.5 34 I/O AD5 I/O P0.4 35 I/O AD4 I/O P0.3 37 38 40 I/O AD3 I/O P0.2 36 39 T2 / P1.0 Name P2.0 A8 P2.1 A9 P2.2 A10 P2.3 A11 P2.4 A12 P2.5 A13 P2.6 A14 P2.7 A15 #PSEN ALE #EA / VPP P0.7 P0.6 21 I/O AD2 I/O P0. 1 AD1 P0.0 AD0 VDD I/O I/O I/O I/O - Function Bit 0 of Port 2 Bit 8 of External Memory Address Bit 1 of Port 2 Bit 9 of External Memory Address Bit 2 of Port 2 Bit 10 of External Memory Address Bit 3 of Port 2 & Bit 11 of External Memory Address Bit 4 of Port 2 Bit 12 of External Memory Address Bit 5 of Port 2 Bit 13 of External Memory Address Bit 6 of Port 2 Bit 14 of External Memory Address Bit 7 of Port 2 Bit 15 of External Memory Address Program Store Enable Address Latch Enable External Access Flash programming voltage input Bit 7 Of Port 0 Data/Address Bit 7 of External Memory Bit 6 of Port 0 Data/Address Bit 6 of External Memory Bit 5 of Port 0 Data/Address Bit 5 of External Memory Bit 4 of Port 0 Data/Address Bit 4 of External Memory Bit 3 Of Port 0 Data/Address Bit 3 of External Memory Bit 2 of Port 0 Data/Address Bit 2 of External Memory Bit 1 of Port 0 & Data Address Bit 1 of External Memory Bit 0 Of Port 0 & Data Address Bit 0 of External Memory Supply input P0.0 / AD0 P1.2 3 38 P0.1 / AD1 PWM0 / P1.3 4 37 P0.2 / AD2 PWM1 / P1.4 5 36 P0.3 / AD3 PWM2 / P1.5 6 35 P0.4 / AD4 PWM3 / P1.6 7 34 P0.5 / AD5 PWM4 / P1.7 8 33 P0.6 / AD6 RESET 9 32 P0.7 / AD7 31 #EA / VPP 30 ALE VRS51x570 VRS51x580 DIP-40 DIP-40 RXD / P3.0 10 TXD / P3.1 11 #INT0 / P3.2 12 29 PSEN #INT1 / P3.3 13 28 P2.7 / A15 T0 / P3.4 14 27 P2.6 / A14 T1 / P3.5 15 26 P2.5 / A13 #WR / P3.6 16 25 P2.4 / A12 #RD / P3.7 17 24 P2.3 / A11 XTAL2 18 23 P2.2 / A10 XTAL1 19 22 P2.1 / A9 VSS 20 21 P2.0 / A8 _ www.ramtron.com page 4 of 45 VRS51x570/580 Instruction Set Mnemonic The following tables describe the instruction set of the VRS51x570 and VRS51x580 devices. The instructions are functional and binary code compatible with industry standard 8051s. TABLE 4: LEGEND FOR INSTRUCTION SET TABLE Symbol A Rn Direct @Ri rel bit #data #data 16 addr 16 addr 11 Function Accumulator Register R0-R7 Internal register address Internal register pointed to by R0 or R1 (except MOVX) Two's complement offset byte Direct bit address 8-bit constant 16-bit constant 16-bit destination address 11-bit destination address TABLE 5: VRS51X570/VRS51X580 VRS51X570/VRS51X580 INSTRUCTION SET Mnemonic Description Arithmetic instructions Add register to A ADD A, Rn Add direct byte to A ADD A, direct Add data memory to A ADD A, @Ri Add immediate to A ADD A, #data Add register to A with carry ADDC A, Rn Add direct byte to A with carry ADDC A, direct Add data memory to A with carry ADDC A, @Ri Add immediate to A with carry ADDC A, #data Subtract register from A with borrow SUBB A, Rn Subtract direct byte from A with borrow SUBB A, direct Subtract data mem from A with borrow SUBB A, @Ri Subtract immediate from A with borrow SUBB A, #data Increment A INC A Increment register INC Rn Increment direct byte INC direct Increment data memory INC @Ri Decrement A DEC A Decrement register DEC Rn Decrement direct byte DEC direct Decrement data memory DEC @Ri Increment data pointer INC DPTR Multiply A by B MUL AB Divide A by B DIV AB Decimal adjust A DA A Logical Instructions AND register to A ANL A, Rn AND direct byte to A ANL A, direct AND data memory to A ANL A, @Ri AND immediate to A ANL A, #data AND A to direct byte ANL direct, A AND immediate data to direct byte ANL direct, #data OR register to A ORL A, Rn OR direct byte to A ORL A, direct OR data memory to A ORL A, @Ri OR immediate to A ORL A, #data OR A to direct byte ORL direct, A OR immediate data to direct byte ORL direct, #data Exclusive-OR register to A XRL A, Rn Exclusive-OR direct byte to A XRL A, direct Exclusive-OR data memory to A XRL A, @Ri Exclusive-OR immediate to A XRL A, #data Exclusive-OR A to direct byte XRL direct, A Exclusive-OR immediate to direct byte XRL direct, #data Clear A CLR A Compliment A CPL A Swap nibbles of A SWAP A Rotate A left RL A Rotate A left through carry RLC A Rotate A right RR A Rotate A right through carry RRC A Size (bytes) Instr. Cycles 1 2 1 2 1 2 1 2 1 2 1 2 1 1 2 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 4 4 1 1 2 1 2 2 3 1 2 1 2 2 3 1 2 1 2 2 3 1 1 1 1 1 1 1 1 1 1 1 1 2 1 1 1 1 1 2 1 1 1 1 1 2 1 1 1 1 1 1 1 Description Boolean Instruction Clear Carry bit CLR C Clear bit CLR bit Set Carry bit to 1 SETB C Set bit to 1 SETB bit Complement Carry bit CPL C Complement bit CPL bit Logical AND between Carry and bit ANL C,bit Logical AND between Carry and not bit ANL C,#bit Logical ORL between Carry and bit ORL C,bit Logical ORL between Carry and not bit ORL C,#bit Copy bit value into Carry MOV C,bit Copy Carry value into Bit MOV bit,C Data Transfer Instructions Move register to A MOV A, Rn Move direct byte to A MOV A, direct Move data memory to A MOV A, @Ri Move immediate to A MOV A, #data Move A to register MOV Rn, A Move direct byte to register MOV Rn, direct Move immediate to register MOV Rn, #data Move A to direct byte MOV direct, A Move register to direct byte MOV direct, Rn Move direct byte to direct byte MOV direct, direct Move data memory to direct byte MOV direct, @Ri Move immediate to direct byte MOV direct, #data Move A to data memory MOV @Ri, A Move direct byte to data memory MOV @Ri, direct Move immediate to data memory MOV @Ri, #data Move immediate to data pointer MOV DPTR, #data MOVC A, @A+DPTR Move code byte relative DPTR to A Move code byte relative PC to A MOVC A, @A+PC Move external data (A8) to A MOVX A, @Ri Move external data (A16) to A MOVX A, @DPTR Move A to external data (A8) MOVX @Ri, A Move A to external data (A16) MOVX @DPTR, A Push direct byte onto stack PUSH direct Pop direct byte from stack POP direct Exchange A and register XCH A, Rn Exchange A and direct byte XCH A, direct Exchange A and data memory XCH A, @Ri Exchange A and data memory nibble XCHD A, @Ri Branching Instructions Absolute call to subroutine ACALL addr 11 Long call to subroutine LCALL addr 16 Return from subroutine RET Return from interrupt RETI Absolute jump unconditional AJMP addr 11 Long jump unconditional LJMP addr 16 Short jump (relative address) SJMP rel Jump on carry = 1 JC rel Jump on carry = 0 JNC rel Jump on direct bit = 1 JB bit, rel Jump on direct bit = 0 JNB bit, rel Jump on direct bit = 1 and clear JBC bit, rel Jump indirect relative DPTR JMP @A+DPTR Jump on accumulator = 0 JZ rel Jump on accumulator 1= 0 JNZ rel Compare A, direct JNE relative CJNE A, direct, rel Compare A, immediate JNE relative CJNE A, #d, rel Compare reg, immediate JNE relative CJNE Rn, #d, rel Compare ind, immediate JNE relative CJNE @Ri, #d, rel Decrement register, JNZ relative DJNZ Rn, rel Decrement direct byte, JNZ relative DJNZ direct, rel Miscellaneous Instruction No operation NOP Rn: Any of the register R0 to R7 @Ri: Indirect addressing using Register R0 or R1 #data: immediate Data provided with Instruction #data16: Immediate data included with instruction bit: address at the bit level rel: relative address to Program counter from +127 to ­128 Addr11: 11-bit address range Addr16: 16-bit address range #d: Immediate Data supplied with instruction Size (bytes) Instr. Cycles 1 2 1 2 1 2 2 2 2 2 2 2 1 1 1 1 1 1 2 2 2 2 1 2 1 2 1 2 1 2 2 2 2 3 2 3 1 2 2 3 1 1 1 1 1 1 2 2 1 2 1 1 1 1 1 1 1 2 1 1 2 2 2 2 1 2 1 2 2 2 2 2 2 2 2 2 1 1 1 1 2 3 1 1 2 3 2 2 2 3 3 3 1 2 2 3 3 3 3 2 3 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 1 _ www.ramtron.com page 5 of 45 VRS51x570/580 Special Function Registers (SFR) Addresses 80h to FFh of the SFR address space can be accessed in direct addressing mode only. The following table lists the VRS51x570 and VRS51x580 Special Function Registers. TABLE 6: SPECIAL FUNCTION REGISTERS (SFR) SFR Register P0 SP DPL DPH Reserved RCON DBANK PCON TCON TMOD TL0 TL1 TH0 TH1 P1 WDTLOCK SCON SBUF PWMEN WDTCON P2 PWMCON PWMD0 PWMD1 PWMD2 PWMD3 IE PWMD4 P3 IP SYSCON T2CON RCAP2L RCAP2H TL2 TH2 PSW P4 ACC B SFR Adrs 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 90h 97h 98h 99h 9Bh 9Fh A0h A3h A4h A5h A6h A7h A8h ACh B0h B8h BFh C8h CAh CBh CCh CDh D0h D8h E0h F0h Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 - - - - - - - - DBANKE SMOD TF1 GATE1 - TR1 C/T1 - TF0 M1.1 - TR0 M0.1 - DBK3 GF1 IE1 GATE0 - DBK2 GF0 IT1 C/T0 - RAM1 DBK1 PDOWN IE0 M1.0 - RAM0 DBK0 IDLE IT0 M0.0 - SM0 PWM4E WDTE PWMD0.4 PWMD1.4 PWMD2.4 PWMD3.4 EA PWMD4.4 WDRESET TF2 - SM1 PWM3E PWMD0.3 PWMD1.3 PWMD2.3 PWMD3.3 PWMD4.3 EXF2 - SM2 PWM2E WDCLR PWMD0.2 PWMD1.2 PWMD2.2 PWMD3.2 ET2 PWMD4.2 PT2 RCLK - REN PWM1E PWMD0.1 PWMD1.1 PWMD2.1 PWMD3.1 ES PWMD4.1 PS TCLK - TB8 PWM0E PWMD0.0 PWMD1.0 PWMD2.0 PWMD3.0 ET1 PWMD4.0 PT1 EXEN2 - RB8 WDPS2 NP0.2 NP1.2 NP2.2 NP3.2 EX1 NP4.2 PX1 TR2 - TI WDPS1 PDCK1 NP0.1 NP1.1 NP2.1 NP3.1 ET0 NP4.1 PT0 XRAME C/T2 - RI WDPS0 PDCK0 NP0.0 NP1.0 NP2.0 NP3.0 EX0 NP4.0 PX0 ALEI CP/RL2 - CY - AC - F0 - RS1 - RS0 P4.3 - OV P4.2 - P4.1 - P P4.0 - Reset Value *00b 0*0001b 00000000b 00000000b 00000000b 00000000b 00000000b 00000*b 0*0*000b *00b 00000000b 00000000b 00000000b 00000000b 00000000b 00000000b 00000000b 0*00b 00000000b 00000000b 00000000b *1111b _ www.ramtron.com page 6 of 45 VRS51x570/580 Program Memory Structure Data Pointer Program Memory The VRS51x570 and VRS51x580 have one 16-bit data pointer (DPTR). The DPTR is accessed via two SFR addresses: DPL located at address 82h and DPH located at address 83h. The VRS51x580 includes 64KB of on-chip Flash that can be used as general program memory. The Flash memory size of the VRS51x570 is 32KB. Data Memory FIGURE 3: VRS51X580 VRS51X580 / VRS51X570 VRS51X570 INTERNAL PROGRAM MEMORY The VRS51x580 and VRS51x570 have a total of 1KB of on-chip SRAM with a 256 byte subset of this block mapped as the internal memory structure of a standard 8052. The remaining 768 byte sub-block can be accessed using external memory addressing via MOVX instruction. FFFFh VRS580 VRS580 Flash Memory (64K Bytes) 7FFFh FIGURE 4: VRS51X570 VRS51X570 /VRS51X580 /VRS51X580 SRAM MEMORY 02FF VRS570 VRS570 Flash Memory (32K Bytes) 0000h 0000h Externally mapped 768 bytes SRAM (Can by accessed by direct external addressing mode, using the MOVX instruction) Program Status Word Register The PSW register is a bit addressable that contains the status flags (CY, AC, OV, P), user flag (F0) and register bank select bits (RS1, RS0) of the 8051 processor. (XRAME=1) FF 80 7F 00 Upper 128 bytes (Indirect addressing only) SFR (Direct addressing only) Lower 128 bytes (Can be accessed in indirect and direct addressing mode) TABLE 7: PROGRAM STATUS WORD REGISTER (PSW) - SFR DOH 7 CY Bit 7 6 5 4 3 2 1 0 RS1 0 0 1 1 6 AC 5 F0 Mnemonic CY AC F0 RS1 RS0 OV P RS0 0 1 0 1 4 RS1 3 RS0 2 OV 1 - Description Carry Bit Auxiliary Carry Bit from bit 3 to 4. User definer flag R0-R7 Registers bank select bit 0 R0-R7 Registers bank select bit 1 Overflow flag Parity flag Active Bank 0 1 2 3 Address 00h-07h 08h-0Fh 10h-17h 18-1Fh 0 P By default, after reset, the externally mapped block of 768 bytes of SRAM is disabled and can be enabled by setting the XRAME bit of the SYSCON register located at address BFh in the SFR space. Lower 128 bytes (00h to 7Fh, Bank 0 & Bank 1) The lower 128 bytes of data memory (from 00h to 7Fh) is summarized as follows: · · · · Address range 00h to 7Fh can be accessed in direct and indirect addressing modes. Address range 00h to 1Fh includes R0-R7 registers area. Address range 20h to 2Fh is bit addressable. Address range 30h to 7Fh is not bit addressable and can be used as general-purpose storage. _ www.ramtron.com page 7 of 45 0000 VRS51x570/580 Upper 128 bytes (80h to FFh, Bank 2 & Bank 3) The upper 128 bytes of the data memory ranging from 80h to FFh can be accessed using indirect addressing or by using the bank mapping in direct addressing mode. 256 byte block will be accessed by the MOVX @Rn instruction (configuring by bits RAM0 and RAM1). The default setting of the RAM1 and RAM0 bits is 00 (page 0). Each page has 256 bytes. TABLE 8: INTERNAL SRAM CONTROL REGISTER (RCON) - SFR 85H 7 6 FIGURE 5: VRS51X570 VRS51X570 / VRS51X580 VRS51X580 INTERNAL LOWER 256 BYTES SRAM STRUCTURE FFh FFh SFR Area Direct or Bit Access Only 128 Bytes of Indirect Access RAM (SP, R0,R1) DPH 85 84 83 82 81 80 DPL SP P0 80h 7Fh Bit 7 6 5 4 3 2 1 0 Mnemonic Unused Unused Unused Unused Unused Unused RAM1 RAM0 80 Bytes of General Purpose RAM 30h 2Fh 10h 08h 00h 7D 7C 7B 7A 79 78 76 75 74 73 72 71 70 0F 18h 7E 77 20h 7F 0E 0D 0C 0B 0A 09 08 07 06 05 04 03 02 01 00 R7 R0 R7 R0 R7 R0 R7 R0 5 4 Unused 3 2 1 RAM1 0 RAM0 Description These two bits are used with Rn of instruction MOVX @Rn, n=1,0 for mapping (see section on extended 768 bytes) RAM1, RAM0 Mapped area 00 000h-0FFh 01 100h-1FFh 10 200h-2FFh 11 XY00h-XYFF* *Externally generated Registers Bank 3 Registers Bank 2 Registers Bank 1 Registers Bank 0 Expanded SRAM Access Using the MOVX @DPTR Instruction (0000-02FF 0000-02FF, Bank4-Bank15) The 768 bytes of the expanded SRAM data memory occupy addresses 0000h to 02FFh. This block can be accessed using external direct addressing (i.e. using the MOVX instruction) or by using bank mapping direct addressing. Example: Suppose that RAM1, RAM0 are set to 0 and 1 respectively and Rn has a value of 45h. Performing MOVX @Rn, A, (where n is 0 or 1) allows the user to transfer the value of A to the expanded SRAM at address 145h (page 1). Note that when both RAM1, RAM0 are set to 1, the value of P2 defines the upper byte and Rn defines the lower byte of the external address. In this case the device will access off-chip memory in the external memory space using the external memory control signals, Off chip peripherals can therefore be mapped into the "P2value"00h to "P2value"FFh address range. Note that when accessing addresses above 02FFh, the VRS51x570/VRS51x580 devices will access off-chip memory in the external memory space using the external memory control signals. Expanded SRAM Control Register The 768 bytes of expanded SRAM can also be accessed using the MOVX @Rn instruction (where n = 0,1). The scope of this instruction is limited to a data range of 256 bytes and therefore the internal SRAM Control Register RCON should be used to select which _ www.ramtron.com page 8 of 45 VRS51x570/580 TABLE 10: BANK MAPPING DIRECT ADDRESSING MODE Data Bank Control Register DBK2 DBK1 BSO 040h~07fh mapping address 0 0 0 0 000h-03Fh 0 0 0 1 040h-07Fh 0 0 1 0 080h-0BFh 0 0 1 1 0C0h-0FFh 0 1 0 0 0000h-003Fh 0 1 0 1 0040h-007Fh 1 1 0 0080h-00BFh 0 1 1 1 00C0h-00FFh 1 0 0 0 0100h-013Fh 1 0 0 1 0140h-017Fh 1 0 1 0 0180h-01BFh 1 0 1 1 01C0h-01FFh 1 1 0 0 0200h-023Fh 1 1 0 1 0240h-027Fh 1 1 1 0 0280h-02BFh 1 The Data Bank Select function is activated by setting the Data Bank Select enable bit (DBANKSE) to 1 (setting this bit to zero disables this function). The four least significant bits of this register control the mapping of the entire 1K Byte on-chip SRAM space into the 40h-7Fh range. DBK3 0 The DBANK register allows the user to enable the Data Bank Select function and map the entire content of the SRAM memory in the range of 40h to 7Fh for applications that would require direct addressing of the expanded SRAM content. 1 1 1 02C0h-02FFh TABLE 9: DATA BANK CONTROL REGISTER (DBANK) ­ SFR 86H 7 DBANKE 6 5 4 Unused Bit 7 Mnemonic 6 5 4 3 2 1 0 Unused Unused Unused DBK3 DBK2 DBK1 DBK0 DBANKSE 3 DBK3 2 1 DBK2 DBK1 0 DBK0 Description Data Bank Select Enable Bit DBANKE=1, Data Bank Select enabled DBANKE=0, Data Bank Select disabled Allows the mapping of the 1K SRAM into the 040h - 07Fh SRAM space. Windowed access to all the 1KB on-chip SRAM in the range of 40h-7Fh is described in the following table. Note Lower 128 bytes SRAM Lower 128 bytes SRAM Upper 128 bytes SRAM Upper 128 bytes SRAM On-chip externally mapped 768 bytes SRAM On-chip externally mapped 768 bytes SRAM On-chip externally mapped 768 bytes SRAM On-chip externally mapped 768 bytes SRAM On-chip externally mapped 768 bytes SRAM On-chip externally mapped 768 bytes SRAM On-chip externally mapped 768 bytes SRAM On-chip externally mapped 768 bytes SRAM On-chip externally mapped 768 bytes SRAM On-chip externally mapped 768 bytes SRAM On-chip externally mapped 768 bytes SRAM On-chip externally mapped 768 bytes SRAM Example: User writes #55h to 203h address: MOV DBANK, #8CH MOV A, #55H MOV 43H, A ;Set bank mapping 40h-07Fh ;0200h-023Fh ;Store #55H to A to ;Write #55H to 0203h ;address _ www.ramtron.com page 9 of 45 VRS51x570/580 TABLE 12: POWER CONTROL REGISTER (PCON) - SFR 87H Description of Peripherals 7 6 System Control Register The following table describes the System Control Register (SYSCON). Bit 7 Mnemonic SMOD The WDRESET bit (7) indicates whether a reset was due to the Watch Dog Timer overflow. When set to 1, the XRAME bit allows the user to enable the on-chip expanded 768 bytes of SRAM. By default, upon reset, the XRAME bit is set to 0. Bit 0 of the SYSCON register is the ALE output inhibit bit. Setting this bit to 1 will inhibit the Fosc/6 clock signal output to the ALE pin. 5 4 Unused 3 2 1 RAM1 0 RAM0 Description 1: Double the baud rate of the serial port frequency that was generated by Timer 1. 0: Normal serial port baud rate generated by Timer 1. 6 5 4 3 2 1 0 GF1 GF0 PDOWN IDLE General Purpose Flag General Purpose Flag Power down mode control bit Idle mode control bit TABLE 11: SYSTEM CONTROL REGISTER (SYSCON) ­ SFR BFH 7 6 5 WDRESET Bit 7 WDRESET Mnemonic 6 5 4 3 2 1 0 Unused Unused Unused Unused Unused XRAME ALEI 4 3 Unused 2 1 XRAME 0 ALEI Description This is the Watch Dog Timer reset bit. It will be set to 1 when the reset signal generated by WDT overflows. 768 byte on-chip enable bit ALE output inhibit bit, which is used to reduce EMI. Power Control Register The VRS51x570/VRS51x580 devices provide two power saving modes: Idle and Power Down. These two modes serve to reduce the power consumption of the device. In Idle mode, the processor is stopped but the oscillator continues to run. The content of the SRAM, I/O state and SFR registers are maintained and the Timer and external interrupts are left operational. The processor will be woken up when an external event, triggering an interrupt, occurs. In power down mode, the oscillator and peripherals are disabled . The contents of the SRAM and the SFR registers, however, are maintained The minimum VCC in power down mode is 2V. These power saving modes are controlled by the PDOWN and IDLE bits of the PCON register at address 87h. _ www.ramtron.com page 10 of 45 VRS51x570/580 Input/Output Ports The VRS51x570 and VRS51x580 have a total of 36 bidirectional I/O lines grouped into four 8-bit I/O ports and one 4-bit I/O port. These I/Os can be individually configured as inputs or outputs. With the exception of the P0 I/Os, which are of the open drain type, each I/O is made of a transistor connected to ground and a weak pull-up resistor. Writing a 0 in a given I/O port bit register will activate the transistor connected to VSS and bring the I/O to a LOW level. FIGURE 6: INTERNAL STRUCTURE OF ONE OF THE EIGHT I/O PORT LINES Read Register Internal Bus Q D Flip-Flop Write to Register Output Stage IC Pin Q Read Pin Writing a 1 into a given I/O port bit register de-activates the transistor between the pin and ground. In this case the pull-up resistor will bring the corresponding pin to a HIGH level. To use a given I/O as an input, a 1 must be written into its associated port register bit. By default, upon reset all I/Os are configured as inputs. General Structure of an I/O Port The following elements establish the link between the core unit and the pins of the microcontroller: · · Special Function Register (same name as port) Output Stage Amplifier (the structure of this element varies with its auxiliary function) From the following figure, one can see that the D flipflop stores the value received from the internal bus after receiving a write signal from the core. Also, note that the Q output of the flip-flop can be linked to the internal bus by executing a read instruction. This is how one would read the content of the register. It is also possible to link the value of the pin to the internal bus. This is done by the "read pin" instruction. In short, the user may read the value of the register or the pin. Structure of the P1, P2, P3 and P4 The following figure provides a general idea of the structure of the P1, P2, P3 and P4 ports. Note that the intermediary logic that connects the output of the register and the output stage together is not shown because this logic varies with the auxiliary function of each port. FIGURE 7: GENERAL STRUCTURE OF THE OUTPUT STAGE OF P1, P2 AND P3 Read Register Vcc Pull-up Network Internal Bus Q IC Pin D Flip-Flop Write to Register Q X1 Read Pin Each line may be used independently as a logical input or output. When used as an input, as mentioned earlier, the corresponding port register bit must be high. _ www.ramtron.com page 11 of 45 VRS51x570/580 Structure of Port 0 Port P0 and P2 as Address and Data Bus The internal structure of P0 is shown below. The auxiliary function of this port requires a particular logic. As opposed to the other ports, P0 is truly bi-directional. In other words, when used as an input, it is considered to be in a floating logical state (high impedance state). This arises from the absence of the internal pull-up resistance. The pull-up resistance is actually replaced by a transistor that is only used when the port is configured to access the external memory/data bus (EA=0). The output stage may receive data from two sources When used as an I/O port, P0 acts as an open drain port and the use of an external pull-up resistor is likely to be required for most applications. FIGURE 9: P2 PORT STRUCTURE · The outputs of register P0 or the bus address itself multiplexed with the data bus for P0. · The outputs of the P2 register or the high byte (A8 through A15) of the bus address for the P2 port. Read Register Address Vcc Pull-up Network FIGURE 8: PORT P0'S PARTICULAR STRUCTURE Q Internal Bus IC Pin D Flip-Flop Address A0/A7 Read Register Write to Register Control Control Vcc Internal Bus Read Pin Q IC Pin D Flip-Flop Write to Register Q X1 Q X1 Read Pin When P0 is used as an external memory bus input (for a MOVX instruction, for example), the outputs of the register are automatically forced to 1. When the ports are used as an address or data bus, the special function registers P0 and P2 are disconnected from the output stage. The 8-bits of the P0 register are forced to 1 and the content of the P2 register remains constant. Auxiliary Port1 Functions The Port1 I/O pins are shared with the PWM outputs, Timer 2 EXT and T2 inputs as shown below: Pin P1.0 P1.1 P1.2 Mnemonic T2 T2EX Function Timer 2 counter input Timer2 Auxiliary input P1.3 P1.4 P1.5 P1.6 PWM0 PWM1 PWM2 PWM3 PWM0 output PWM1 output PWM2 output PWM3 output P1.7 PWM4 PWM4 output _ www.ramtron.com page 12 of 45 VRS51x570/580 Auxiliary P3 Port Functions Port4 The Port3 I/O pins are shared with the UART interface, INT0 and INT1 interrupts, Timer 0 and Timer 1 inputs and finally the #WR and #RD lines when external memory access is performed. Port4 has four pins and its port address is located at 0D8H. FIGURE 10: P3 PORT STRUCTURE Auxiliary Function: Output Read Register Vcc IC Pin Q Internal Bus X1 TABLE 14: PORT 4 (P4) - SFR D8H 7 Bit 7 6 5 4 3 2 1 0 6 5 Unused Mnemonic Unused Unused Unused Unused P4.3 P4.2 P4.1 P4.0 4 3 P4.3 2 P4.2 1 P4.1 0 P4.0 Description Used to output the setting to pins P4.3, P4.2, P4.1, P4.0 respectively. D Flip-Flop Write to Register Q Read Pin Auxiliary Function: Input The following table describes the auxiliary function of the port 3 I/O pins. TABLE 13: P3 AUXILIARY FUNCTION TABLE Pin P3.0 P3.3 INT1 P3.4 P3.5 P3.6 T0 T1 WR Function Serial Port: Receive data in asynchronous mode. Input and output data in synchronous mode. Serial Port: Transmit data in asynchronous mode. Output clock value in synchronous mode. External Interrupt 0 Timer 0 Control Input External Interrupt 1 Timer 1 Control Input Timer 0 Counter Input Timer 1 Counter Input Write signal for external memory P3.7 RD Read signal for external memory P3.1 P3.2 Mnemonic RXD TXD INT0 Port4 uses the pins that normally appear as noconnects (N/C) on standard 8051 By default the Port4 pins are configured as inputs and internally pulled­up, and therefore the VRS51x570 and VRS51x580 devices can be safely used in existing 80C51/80C52 80C51/80C52 designs where the corresponding pins have been left unconnected. In the case of an existing design where a pin corresponding to the Port4 I/O is grounded, a small current will flow through the P4 pull-up resistor. In the case where those pins would be connected to Vcc, care must be taken to avoid writing into the P4 register. Software Particularities Concerning the Ports Some instructions allow the user to read the logic state of the output pin, while others allow the user to read the content of the associated port register. These instructions are called read-modify-write instructions. A list of these instructions may be found in the table below. Upon execution of these instructions, the content of the port register (at least 1 bit) is modified. The other read instructions take the present state of the input into account. For example, the instruction ANL P3, #01h obtains the value in the P3 register; performs the desired logic operation with the constant 01h, and recopies the result into the P3 register. When users _ www.ramtron.com page 13 of 45 VRS51x570/580 want to take the present state of the inputs into account, they must first read these states and perform an AND operation between the read value and the constant. MOV A, P3; State of the inputs in the accumulator ANL A, #01; AND operation between P3 and 01h When the port is used as an output, the register contains information on the state of the output pins. Measuring the state of an output directly on the pin is inaccurate because the electrical level depends mostly on the type of charge that is applied to it. The functions shown below take the value of the register rather than that of the pin. TABLE 15: LIST OF INSTRUCTIONS THAT READ AND MODIFY THE PORT USING REGISTER VALUES Instruction ANL ORL XRL JBC CPL INC DEC DJNZ MOV P., C CLR P.x SETB P.x Function Logical AND ex: ANL P0, A Logical OR ex: ORL P2, #01110000B 01110000B Exclusive OR ex: XRL P1, A Jump if the bit of the port is set to 0 Complement one bit of the port Increment the port register by 1 Decrement the port register by 1 Decrement by 1 and jump if the result is not equal to 0 Copy the held bit C to the port Set the port bit to 0 Set the port bit to 1 Port Operation Timing Reading a Port (Input) The reading of an I/O pin takes place: · · · During T9 cycle for P0, P1 During T10 cycle for P2, P3 When the ports are configured as I/Os (see Figure 25). In order to be sampled, the signal duration present on the I/O inputs must be longer than Fosc/12. I/O Ports Driving Capability The maximum allowable continuous current that the device can sink on an I/O port is defined by the following Maximum sink current on one given I/O Maximum total sink current for P0 Maximum total sink current for P1, 2, 3 Maximum total sink current on all I/O 10mA 26mA 15mA 70mA On the VRS51x580, the Port4 output buffers can sink up to 20mA, allowing direct driving of LED displays. It is not recommended to exceed the sink current outlined in the above table. Doing so is likely to make the low-level output voltage exceed the device's specification and it is likely to affect the device's reliability. The VRS51x570/VRS51x580 designed to source current. I/O ports are not Writing to a Port (Output) When an operation results in a modification of the content in a port register, the new value is placed at the output of the D flip-flop during the T12 period of the last machine cycle that the instruction needed to execute. It is important to note, however, that the output stage only samples the output of the registers on the P1 phase of each period. It follows that the new value only appears at the output after the T12 period of the following machine cycle. _ www.ramtron.com page 14 of 45 VRS51x570/580 Timers Both the VRS51x570 and the VRS51x580 include three 16-bit timers: T0, T1 and T2. The timers can operate in two specific modes: · Event counting mode · Timer mode When operating in counting mode, the counter is incremented each time an external event, such as a transition in the logical state of the timer input (T0, T1, T2 input), is detected. When operating in timer mode, the counter is incremented by the microcontroller's direct clock pulse or by a divided version of this pulse. Timer 0 and Timer 1 Timers 0 and 1 have four modes of operation. These modes allow the user to change the size of the counting register or to authorize an automatic reload when provided with a specific value. Timer 1 can also be used as a baud rate generator to generate communication frequencies for the serial interface. Timer 1 and Timer 0 are configured by the TMOD and TCON registers. TABLE 16: TIMER MODE CONTROL REGISTER (TMOD) ­ SFR 89H 7 GATE 6 C/T 5 M1 Bit 7 Mnemonic GATE1 6 C/T1 5 4 3 M1.1 M0.1 GATE0 2 C/T0 1 0 M1.0 M0.0 4 M0 3 GATE 2 C/T 1 M1.0 0 M0.0 Description 1: Enables external gate control (pin INT1 for Counter 1). When INT1 is high, and TRx bit is set (see TCON register), a counter is incremented every falling edge on the T1IN input pin. Selects timer or counter operation (Timer 1). 1 = A counter operation is performed 0 = The corresponding register will function as a timer. Selects mode for Timer/Counter 1 Selects mode for Timer/Counter 1 If set, enables external gate control (pin INT0 for Counter 0). When INT0 is high, and TRx bit is set (see TCON register), a counter is incremented every falling edge on the T0IN input pin. Selects timer or counter operation (Timer 0). 1 = A counter operation is performed 0 = The corresponding register will function as a timer. Selects mode for Timer/Counter 0. Selects mode for Timer/Counter 0. The table below summarizes the four modes of operation of timers 0 and 1. The timer-operating mode is selected by the bits M1 and M0 of the TMOD register. TABLE 17: TIMER/COUNTER MODE DESCRIPTION SUMMARY M1 M0 Mode Function 0 0 1 0 1 0 Mode 0 Mode 1 Mode 2 1 1 Mode 3 13-bit Counter 16-bit Counter 8-bit auto-reload Counter/Timer. The reload value is kept in TH0 or TH1, while TL0 or TL1 is incremented every machine cycle. When TLx overflows, the value of THx is copied to TLx. If Timer 1 M1 and M0 bits are set to 1, Timer 1 stops. _ www.ramtron.com page 15 of 45 VRS51x570/580 Timer 0/ Timer 1 Counter / Timer Functions Operating Modes Timing Function The user may change the operating mode by varying the M1 and M0 bits of the TMOD SFR. When operating as a timer, the counter is automatically incremented at every system cycle (Fosc/12). A flag is raised in the event that an overflow occurs and the counter acquires a value of zero. These flags (TF0 and TF1) are located in the TCON register. TABLE 18: TIMER 0 AND 1 CONTROL REGISTER (TCON) ­SFR 88H 7 6 5 4 3 2 1 0 TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 Bit 7 Mnemonic TF1 6 TR1 5 TF0 4 TR0 3 IE1 2 IT1 1 IE0 0 IT0 Description Timer 1 Overflow Flag. Set by hardware on Timer/Counter overflow. Cleared by hardware on Timer/Counter overflow. Cleared by hardware when processor vectors to interrupt routine. Timer 1 Run Control Bit. Set/cleared by software to turn Timer/Counter on or off. Timer 0 Overflow Flag. Set by hardware on Timer/Counter overflow. Cleared by hardware when processor vectors to interrupt routine. Timer 0 Run Control Bit. Set/cleared by software to turn Timer/Counter on or off. Interrupt Edge Flag. Set by hardware when external interrupt edge is detected. Cleared when interrupt processed. Interrupt 1 Type Control Bit. Set/cleared by software to specify falling edge/low level triggered external interrupts. Interrupt 0 Edge Flag. Set by hardware when external interrupt edge is detected. Cleared when interrupt processed. Interrupt 0 Type control bit. Set/cleared by software to specify falling edge/low level triggered external interrupts. Counting Function When operating as a counter, the timer's register is incremented at every falling edge of the T0, T1 and T2 signals located at the input of the timer. In this case, the signal is sampled at the T10 phase of each machine cycle for Timer 0, Timer 1 and T9 for Timer 2. When the sampler sees a high immediately followed by a low in the next machine cycle, the counter is incremented. Two system cycles are required to detect and record an event. This reduces the counting frequency by a factor of 24 (24 times less than the oscillator's frequency). Mode 0 A schematic representation of this mode of operation can be found below in Figure 11. From the figure, we notice that the timer operates as an 8-bit counter preceded by a divide-by-32 prescaler composed of the 5LSB of TL1. The register of the counter is configured to be 13 bits long. When an overflow causes the value of the register to roll over to 0, the TFx interrupt signal goes to 1. The count value is validated as soon as TRx goes to 1 and the GATE bit is 0, or when INTx is 1. FIGURE 11: TIMER/COUNTER 1 MODE 0: 13-BIT 13-BIT COUNTER CLK ÷12 0 TL1 C/T =0 CLK 1 T1PIN 0 4 7 Mode 0 C/T =1 Control Mode 1 TR1 GATE 0 TH1 7 INT1 PIN TF1 INT Mode 1 Mode 1 is almost identical to Mode 0. They differ in that, in Mode 1, the counter uses the full 16 bits and has no prescaler. Mode 2 In this mode, the register of the timer is configured as an 8-bit automatically re-loadable counter. In Mode 2, it is the lower byte TLx that is used as the counter. In the event of a counter overflow, the TFx flag is set to 1 and the value contained in THx, which is preset by software, is reloaded into the TLx counter. The value of THx remains unchanged. _ www.ramtron.com page 16 of 45 VRS51x570/580 Timer 2 FIGURE 12: TIMER/COUNTER 1 MODE 2: 8-BIT AUTOMATIC RELOAD CLK ÷12 0 C/T =0 1 C/T=1 TL1 0 7 Control T1 Pin Reload 0 7 TH1 Timer 2 of the VRS51x570 / VRS51x580 devices is a 16-bit Timer/Counter. Similar to timers 0 and 1, Timer 2 can operate either as an event counter or as a timer. The user may switch functions by writing to the C/T2 bit located in the T2CON special function register. Timer 2 has three operating modes: "Auto-Load" "Capture", and "Baud Rate Generator". The T2CON SFR configures the modes of operation of Timer 2. The following table describes each bit in the T2CON special function register. TR1 GATE TF1 INT TABLE 19: TIMER 2 CONTROL REGISTER (T2CON) ­SFR C8H INT0 PIN 7 6 5 4 3 2 1 0 TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2 CP/RL2 Bit In Mode 3, Timer 1 is blocked as if its control bit, TR1, was set to 0. In this mode, Timer 0's registers TL0 and TH0 are configured as two separate 8-bit counters. Also, the TL0 counter uses Timer 0's control bits C/T, GATE, TR0, INT0, TF0 and the TH0 counter is held in Timer Mode (counting machine cycles) and gains control over TR1 and TF1 from Timer 1. At this point, TH0 controls the Timer 1 interrupt. Mnemonic 7 Mode 3 TF2 6 EXF2 5 RCLK FIGURE 13: TIMER/COUNTER 0 MODE 3 TH0 CLK 0 7 4 TCLK Control TF1 TR1 CLK INTERRUPT ÷12 0 TL0 C/T =0 CLK 0 7 3 C/T =1 Control TF0 EXEN2 2 1 T0PIN TR2 INTERRUPT TR0 GATE INT0 PIN 1 C/T2 Description Timer 2 Overflow Flag: Set by an overflow of Timer 2 and must be cleared by software. TF2 will not be set when either RCLK =1 or TCLK =1. Timer 2 external flag change in state occurs when either a capture or reload is caused by a negative transition on T2EX and EXEN2=1. When Timer 2 is enabled, EXF=1 will cause the CPU to Vector to the Timer 2 interrupt routine. Note that EXF2 must be cleared by software. Serial Port Receive Clock Source. 1: Causes Serial Port to use Timer 2 overflow pulses for its receive clock in modes 1 and 3. 0: Causes Timer 1 overflow to be used for the Serial Port receive clock. Serial Port Transmit Clock. 1: Causes Serial Port to use Timer 2 overflow pulses for its transmit clock in modes 1 and 3. 0: Causes Timer 1 overflow to be used for the Serial Port transmit clock. Timer 2 External Mode Enable. 1: Allows a capture or reload to occur as a result of a negative transition on T2EX if Timer 2 is not being used to clock the Serial Port. 0: Causes Timer 2 to ignore events at T2EX. Start/Stop Control for Timer 2. 1: Start Timer 2 0: Stop Timer 2 Timer or Counter Select (Timer 2) 1: External event counter falling edge triggered. 0: Internal Timer (OSC/12 OSC/12) _ www.ramtron.com page 17 of 45 VRS51x570/580 Capture/Reload Select. 1: Capture of Timer 2 value into RCAP2H, RCAP2L is performed if EXEN2=1 and a negative transitions occurs on the T2EX pin. The capture mode requires RCLK and TCLK to be 0. 0 CP/RL2 0: Auto-reload reloads will occur either with Timer 2 overflows or negative transitions at T2EX when EXEN2=1. When either RCK =1 or TCLK =1, this bit is ignored and the timer is forced to auto-reload on Timer 2 overflow. As shown below, there are different possible combinations of control bits that may be used for the mode selection of Timer 2. TABLE 20: TIMER 2 MODE SELECTION BITS RCLK + TCLK CP/RL2 TR2 0 0 1 0 1 1 1 X 1 X X 0 MODE 16-bit AutoReload Mode 16-bit Capture Mode Baud Rate Generator Mode Off When EXEN2 = 1, the above still applies. Additionally, it is possible to allow a 1 to 0 transition at the T2EX input to cause the current value stored in the Timer 2 registers (TL2 and TH2) to be captured by the RCAP2L and RCAP2H registers. Furthermore, the transition at T2EX causes bit EXF2 in T2CON to be set, and EXF2, like TF2, can generate an interrupt. Note that both EXF2 and TF2 share the same interrupt vector. Auto-Reload Mode In this mode, there are also two options. The user may choose either option by writing to bit EXEN2 in T2CON. If EXEN2 = 0, when Timer 2 rolls over, it not only sets TF2, but also causes the Timer 2 registers to be reloaded with the 16-bit value in the RCAP2L and RCAP2H registers previously initialised. In this mode, Timer 2 can be used as a baud rate generator source for the serial port. If EXEN2=1, then Timer 2 still performs the above operation, but a 1 to 0 transition at the external T2EX input will also trigger an anticipated reload of the Timer 2 with the value stored in RCAP2L, RCAP2H and set EXF2. FIGURE 15: TIMER 2 IN AUTO-RELOAD MODE The details of each mode are described as follows. FOSC Capture Mode In Capture Mode the EXEN2 bit value defines if the external transition on the T2EX pin will be able to trigger the capture of the timer value. When EXEN2 = 0, Timer 2 acts as a 16-bit timer or counter, which, upon overflowing, will set bit TF2 (Timer 2 overflow bit). This overflow can be used to generate an interrupt. ÷12 0 TIMER 0 C/T2 1 TL2 TH2 7 0 7 0 7 COUNTER T2 Pin 0 RCAP2L RCAP2H 7 TR2 TF2 EXF2 T2 EX Pin EXEN2 Timer 2 Interrupt FIGURE 14: TIMER 2 IN CAPTURE MODE FOSC ÷12 0 TIMER 0 TL2 TH2 7 0 7 0 7 C/T2 1 COUNTER T2 Pin 0 RCAP2L RCAP2H 7 TR2 TF2 T2 EX Pin EXF2 EXEN2 Timer 2 Interrupt _ www.ramtron.com page 18 of 45 VRS51x570/580 Baud Rate Generator Mode The baud rate generator mode is activated when RCLK is set to 1 and/or TCLK is set to 1. This mode will be described in the serial port section. FIGURE 16: TIMER 2 IN AUTOMATIC BAUD GENERATOR MODE FOSC ÷2 0 TIMER TL2 0 C/T2 1 TH2 7 0 7 0 7 COUNTER T2 Pin 0 RCAP2L TR2 RCAP2H 1 0 0 Timer 1 Overflow ÷2 ÷16 TCLK TX Clock ÷16 RX Clock 1 0 1 SMOD RCLK EXF2 T2 EX Pin 7 Timer 2 Interrupt Request EXEN2 _ www.ramtron.com page 19 of 45 VRS51x570/580 th 3 Serial Port The serial port included in the VRS51x570 and the VRS51x580 can operate in full duplex; in other words, it can transmit and receive data simultaneously. This occurs at the same speed if one timer is assigned as the clock source for both transmission and reception, and at different speeds if transmission and reception are each controlled by their own timer. The serial port receive is buffered, which means that it can begin reception of a byte even if the one previously received byte has not been retrieved from the receive register by the processor. However, if the first byte still has not been read by the time reception of the second byte is complete, the byte present in the receive buffer will be lost. The SBUF register provides access to the transmit and receive registers of the serial port. Reading from the SBUF register will access the receive register, while a write to the SBUF loads the transmit register. TB8 2 RB8 9 data bit transmitted in modes 2 and 3 This bit must be set by software and cleared by software. th 9 data bit received in modes 2 and 3. TI In Mode 1, if SM2 = 0 , RB8 is the stop bit that was received. In Mode 0, this bit is not used. This bit must be cleared by software. Transmission Interrupt flag. RI Automatically set to 1 when: th · The 8 bit has been sent in Mode 0. · Automatically set to 1 when the stop bit has been sent in the other modes. This bit must be cleared by software. Reception Interrupt flag 1 0 Automatically set to 1 when: th · The 8 bit has been received in Mode 0. · Automatically set to 1 when the stop bit has been sent in the other modes (see SM2 exception). This bit must be cleared by software. TABLE 22: SERIAL PORT MODES OF OPERATION SM0 Serial Port Control Register The SCON (serial port control) register contains control and status information, and includes the 9th data bit for transmit/receive (TB8/RB8 if required), mode selection bits and serial port interrupt bits (TI and RI). SM1 Mode Description Baud Rate 0 0 1 0 1 0 0 1 2 Shift Register 8-bit UART 9-bit UART 1 1 3 9-bit UART Fosc/12 Variable Fosc/64 or Fosc/32 Variable Modes of Operation TABLE 21: SERIAL PORT CONTROL REGISTER (SCON) ­ SFR 98H 7 6 5 4 3 2 1 0 SM0 SM1 SM2 REN TB8 RB8 TI RI Bit 7 Mnemonic SM0 6 SM1 5 SM2 Description Bit to select mode of operation (see table below) Bit to select mode of operation (see table below) Multiprocessor communication is possible in modes 2 and 3. The VRS51x570/VRS51x580 devices serial port can operate in four different modes. In all four modes, a transmission is initiated by an instruction that uses the SBUF SFR as a destination register. In Mode 0, reception is initiated by setting RI to 0 and REN to 1. An incoming start bit initiates reception in the other modes provided that REN is set to 1. The following paragraphs describe the four modes. In modes 2 or 3 if SM2 is set to 1, RI will th not be activated if the received 9 data bit (RB8) is 0. 4 REN In Mode 1, if SM2 = 1 then RI will not be activated if a valid stop bit was not received. Serial Reception Enable Bit This bit must be set by software and cleared by software. 1: Serial reception enabled 0: Serial reception disabled _ www.ramtron.com page 20 of 45 VRS51x570/580 Mode 0 In this mode, the serial data exits and enters through the RXD pin. TXD is used to output the shift clock. The signal is composed of 8 data bits starting with the LSB. The baud rate in this mode is 1/12 the oscillator frequency. Internal Bus 1 Write to SBUF Q S SBUF RXD P3.0 D Shift CLK ZERO DETECTOR Shift Clock TXD P3.1 Shift Start TX Control Unit TX Clock Fosc/12 Send TI Serial Port Interrupt RI RX Clock Receive The SEND signal enables the output of the shift register to the alternate output function line of P3.0 and enables SHIFT CLOCK to the alternate output function line of P3.1. SHIFT CLOCK is high during T11, T12 and T1, T2 and T3, T4 of every machine cycle and low during T5, T6, T7, T8, T9 and T10. At T12 of every machine cycle in which SEND is active and the contents of the transmit shift register are shifted to the right by one position. Zeros come in from the left as data bits shift out to the right. The TX control block sends its final shift and deactivates SEND while setting T1 after one condition is fulfilled: When the MSB of the data byte is at the output position of the shift register; the 1 that was initially loaded into the 9th position is just to the left of the MSB; and all positions to the left of that contain zeros. Once these conditions are met, the deactivation of SEND and the setting of T1 occur at T1 of the 10th machine cycle after the "write to SBUF" pulse. RX Control Unit RI REN Start Shift 1 RXD P3.0 Input Function 1 1 1 1 1 1 Shift Register SBUF Reception in Mode 0 0 RXD P3.0 READ SBUF Internal Bus FIGURE 17: SERIAL PORT MODE 0 BLOCK DIAGRAM Transmission in Mode 0 Any instruction that uses SBUF as a destination register may initiate a transmission. The "write to SBUF" signal also loads a 1 into the 9th position of the transmit shift register and tells the TX control block to begin a transmission. The internal timing is such that one full machine cycle will elapse between a write to SBUF instruction and the activation of SEND. When REN and R1 are set to 1 and 0 respectively, reception is initiated. The bits 11111110 are written to the receive shift register at T12 of the next machine cycle by the RX control unit. In the following phase, the RX control unit will activate RECEIVE. SHIFT CLOCK to the alternate output function line of P3.1 is enabled by RECEIVE. At every machine cycle, SHIFT CLOCK makes transitions at T5 and T11. The contents of the receive shift register are shifted one position to the left at T12 of every machine in which RECEIVE is active. The value that comes in from the right is the value that was sampled at the P3.0 pin at T10 of the same machine cycle. 1's are shifted out to the left as data bits are shifted in from the right. The RX control block is flagged to do one last shift and load SBUF when the 0 that was initially loaded into the rightmost position arrives at the leftmost position in the shift register. _ www.ramtron.com page 21 of 45 VRS51x570/580 Mode 1 For an operation in Mode 1, 10 bits are transmitted through TXD or received through RXD. The transactions are composed of: a Start bit (Low); 8 data bits (LSB first) and one Stop bit (high). The reception is completed once the Stop bit sets the RB8 flag in the SCON register. Either Timer 1 or Timer 2 controls the baud rate in this mode. The following diagram shows the serial port structure when configured in Mode 1. FIGURE 18: SERIAL PORT MODE 1 AND 3 BLOCK DIAGRAM Internal Bus When a transmission begins, it places the start bit at TXD. Data transmission is activated one bit time later. This activation enables the output bit of the transmit shift register to TXD. One bit time after that, the first shift pulse occurs. In this mode, zeros are clocked in from the left as data bits are shifted out to the right. When the most significant bit of the data byte is at the output position of the shift register, the 1 that was initially loaded into the 9th position is to the immediate left of the MSB, and all positions to the left of that contain zeros. This condition flags the TX Control Unit to shift one more time. Reception in Mode 1 1 Write to SBUF Timer 1 Overflow Q S SBUF TXD D CLK Timer 2 Overflow ÷2 ZERO DETECTOR 0 1 SMOD 0 Shift Start 1 ÷16 0 TX Clock Send TI 1 RCLK ÷16 Serial Port Interrupt RI RX Clock 1-0 Transition Detector RXD Data TX Control Unit TCLK Start Load SBUF RX Control Unit Bit Detector SHIFT 9-Bit Shift Register Shift LOAD SBUF SBUF READ SBUF Internal Bus Transmission in Mode 1 Transmission is initiated by any instruction that makes use of SBUF as a destination register. The 9th bit position of the transmit shift register is loaded by the "write to SBUF" signal. This event also flags the TX Control Unit that a transmission has been requested. It is after the next rollover in the divide-by-16 counter when transmission actually begins at T1 of the machine cycle. It follows that the bit times are synchronized to the divide-by-16 counter and not to the "write to SBUF" signal. A one to zero transition at RXD initiates reception. It is for this reason that RXD is sampled at a rate of 16 multiplied by the baud rate that has been established. When a transition is detected, 1FFh is written into the input shift register and the divide-by-16 counter is immediately reset. The divide-by-16 counter is reset in order to align its rollovers with the boundaries of the incoming bit times. In total, there are 16 states in the counter. During the 7th, 8th and 9th counter states of each bit time; the bit detector samples the value of RXD. The accepted value is the value that was seen in at least two of the three samples. The purpose of doing this is for noise rejection. If the value accepted during the first bit time is not zero, the receive circuits are reset and the unit goes back to searching for another one to zero transition. All false start bits are rejected by doing this. If the start bit is valid, it is shifted into the input shift register, and the reception of the rest of the frame will proceed. For a receive operation, the data bits come in from the right as 1's shift out on the left. As soon as the start bit arrives at the leftmost position in the shift register, (9bit register), it tells the RX control block to perform one last shift operation: to set RI and to load SBUF and RB8. The signal to load SBUF and RB8, and to set RI, will be generated if, and only if, the following conditions are met at the time the final shift pulse is generated: - Either SM2 = 0 or the received stop bit = 1 RI = 0 _ www.ramtron.com page 22 of 45 VRS51x570/580 If both conditions are met, the stop bit goes into RB8, the 8 data bits go into SBUF, and RI is activated. If one of these conditions is not met, the received frame is completely lost. At this time, whether the above conditions are met or not, the unit goes back to searching for a one to zero transition in RXD. Mode 3 Mode 2 Mode 3 is identical to Mode 2 in all respects but one: the baud rate. Either Timer 1 or Timer 2 generates the baud rate in Mode 3. In Mode 3, 11 bits are transmitted through TXD or received through RXD. The transactions are composed of: a Start bit (Low), 8 data bits (LSB first), a programmable 9th data bit, and one Stop bit (High). In Mode 2 a total of 11 bits are transmitted through TXD or received through RXD. The transactions are composed of: a Start bit (Low), 8 data bits (LSB first), a programmable 9th data bit, and one Stop bit (High). FIGURE 20: SERIAL PORT MODE 3 BLOCK DIAGRAM Internal Bus For transmission, the 9th data bit comes from the TB8 bit of SCON. For example, the parity bit P in the PSW could be moved into TB8. 1 Write to SBUF Timer 1 Overflow Q S SBUF TXD D th In the case of receive, the 9 data bit is automatically written into RB8 of the SCON register. CLK Timer 2 Overflow ÷2 ZERO DETECTOR 0 1 SMOD In Mode 2, the baud rate is programmable to either 1/32 or 1/64 the oscillator frequency. 0 Start 1 Shift ÷16 0 Data TX Control Unit TCLK TX Clock 1 RCLK Send TI ÷16 Serial Port Interrupt FIGURE 19: SERIAL PORT MODE 2 BLOCK DIAGRAM SAMPLE Internal Bus RX Clock 1-0 Transition Detector Start RI Load SBUF RX Control Unit SHIFT 1 Write to SBUF RXD Bit Detector 9-Bit Shift Register Shift LOAD SBUF Q S Fosc/2 SBUF TXD D SBUF CLK READ SBUF ZERO DETECTOR ÷2 Internal Bus 0 1 Shift Stop Start SMOD ÷16 TX Control Unit TX Clock Send TI ÷16 Sample 1-0 Transition Detector RXD Start Data Serial Port Interrupt RX Clock Control Bit Detector RI Load SBUF RX Control Unit SHIFT 9-Bit Shift Register Shift LOAD SBUF SBUF READ SBUF Internal Bus _ www.ramtron.com page 23 of 45 VRS51x570/580 Mode 2 and 3: Additional Information Reception in Mode 2 and Mode 3 As mentioned previously, for an operation in these modes, 11 bits are transmitted through TXD or received through RXD. The signal comprises: a logical low Start bit, 8 data bits (LSB first), a programmable 9th data bit, and one logical high Stop bit. One to zero transitions at RXD initiate reception. It is for this reason that RXD is sampled at a rate of 16 multiplied by the baud rate that has been established. When a transition is detected, the 1FFh is written into the input shift register and the divide-by-16 counter is immediately reset. On transmit, (TB8 in SCON) can be assigned the value of 0 or 1. On receive; the 9th data bit goes into RB8 in SCON. The baud rate is programmable to either 1/32 or 1/64 the oscillator frequency in Mode 2. Mode 3 may have a variable baud rate generated from either Timer 1 or Timer 2 depending on the states of TCLK and RCLK. Transmission in Mode 2 and Mode 3 The transmission is initiated by any instruction that makes use of SBUF as the destination register. The 9th bit position of the transmit shift register is loaded by the "write to SBUF" signal. This event also informs the TX control unit that a transmission has been requested. After the next rollover in the divide-by-16 counter, a transmission actually begins at T1 of the machine cycle. It follows that the bit times are synchronized to the divide-by-16 counter and not to the "write to SBUF" signal, as in the previous mode. Transmissions begin when the SEND signal is activated, which places the Start bit at TXD. Data is activated one bit time later. This activation enables the output bit of the transmit shift register to TXD. The first shift pulse occurs one bit time after that. The first shift clocks a Stop bit (1) into the 9th bit position of the shift register to TXD. Thereafter, only zeros are clocked in. Thus, as data bits shift out to the right, zeros are clocked in from the left. When TB8 is at the output position of the shift register, the stop bit is just to the left of TB8, and all positions to the left of that contain zeros. This condition signals to the TX control unit to shift one more time and set TI, while deactivating SEND. This occurs at the 11th divide-by-16 rollover after "write to SBUF". During the 7th, 8th and 9th counter states of each bit time; the bit detector samples the value of RXD. The accepted value is the value that was seen in at least two of the three samples. If the value accepted during the first bit time is not zero, the receive circuits are reset and the unit goes back to searching for another one to zero transition. If the start bit is valid, it is shifted into the input shift register, and the reception of the rest of the frame will proceed. For a receive operation, the data bits come in from the right as 1's shift out on the left. As soon as the start bit arrives at the leftmost position in the shift register (9-bit register), it tells the RX control block to do one more shift, to set RI, and to load SBUF and RB8. The signal to set RI and to load SBUF and RB8 will be generated if, and only if, the following conditions are satisfied at the instance when the final shift pulse is generated: - Either SM2 = 0 or the received 9th bit is equal to 1 - RI = 0 If both conditions are met, the 9th data bit received goes into RB8, and the first 8 data bits go into SBUF. If one of these conditions is not met, the received frame is completely lost. One bit time later, whether the above conditions are met or not, the unit goes back to searching for a one to zero transition at the RXD input. Please note that the value of the received stop bit is unrelated to SBUF, RB8 or RI. _ www.ramtron.com page 24 of 45 VRS51x570/580 UART Baud Rates Calculation In Mode 0, the baud rate is fixed and can be represented by the following formula: Mode 0 Baud Rate = Oscillator Frequency 12 In Mode 2, the baud rate depends on the value of the SMOD bit in the PCON SFR. From the formula below, we can see that if SMOD = 0 (which is the value on reset), the baud rate is 1/32 the oscillator frequency. SMOD Mode 2 Baud Rate = 2 x (Oscillator Frequency) 64 The Timer 1 and/or Timer 2 overflow rate determines the baud rates in modes 1 and 3. Generating Baud Rates with Timer 1 When Timer 1 functions as a baud rate generator, the baud rate in modes 1 and 3 are determined by the Timer 1 overflow rate. Mode 1, 3 Baud Rate = 2SMODx Timer 1 Overflow Rate 32 Timer 1 must be configured as an 8-bit timer (TL1) with auto-reload with TH1 value when an overflow occurs (Mode 2). In this application, the Timer 1 interrupt should be disabled. The two following formulas can be used to calculate the baud rate and the reload value to be written into the TH1 register. Mode 1, 3 Baud Rate = The value to write into the TH1 register is defined by the following formula: TH1 = 256 - SMOD x Fosc 2 32 x 12x (Baud Rate) It is possible to use Timer 1 in 16-bit mode to generate the baud rate for the serial port. To do this, leave the Timer 1 interrupt enabled, configure the timer to run as a 16-bit timer (high nibble of TMOD = 0001B 0001B), and use the Timer 1 interrupt to perform a 16-bit software reload. This can achieve very low baud rates. Generating Baud Rates with Timer 2 Timer 2 is often preferred to generate the baud rate, as it can be easily configured to operate as a 16-bit timer with auto-reload. This allows for much better resolution than using Timer 1 in 8-bit auto-reload mode. The baud rate using Timer 2 is defined as: Mode 1, 3 Baud Rate = Timer 2 Overflow Rate 16 The timer can be configured as either a timer or a counter in any of its 3 running modes. In most typical application, it is configured as a timer (C/T2 is set to 0). To make the Timer 2 operate as a baud rate generator the TCLK and RCLK bits of the T2CON register must be set to 1. The baud rate generator mode is similar to the autoreload mode in that an overflow in TH2 causes the Timer 2 registers to be reloaded with the 16-bit value in registers RCAP2H and RCAP2L, which are preset by software. However, when Timer 2 is configured as a baud rate generator, its clock source is Osc/2. 2SMODx Fosc 32 x 12(256 ­ TH1) _ www.ramtron.com page 25 of 45 VRS51x570/580 The following formula can be used to calculate the baud rate in modes 1 and 3 using the Timer 2: Modes 1, 3 Baud Rate = Oscillator Frequency 32x[65536 ­ (RCAP2H, RCAP2L)] The formula below is used to define the reload value to put into the RCAP2h, RCAP2L registers to achieve a given baud rate. (RCAP2H, RCAP2L) = 65536 - Fosc 32x[Baud Rate] In the above formula, RCAP2H and RCAP2L are the content of RCAP2H and RCAP2L taken as a 16-bit unsigned integer. Note that a rollover in TH2 does not set TF2, and will not generate an interrupt and because of this, the Timer 2 interrupt does not have to be disabled when Timer 2 is configured in baud rate generator mode. Also, if EXEN2 is set, a 1-to-0 transition in T2EX will set EXF2 but will not cause a reload from RCAP2x to Tx2. Therefore, when Timer 2 is used as a baud rate generator, T2EX can be used as an extra external interrupt. Furthermore, when Timer 2 is running (TR2 is set to 1) as a timer in baud rate generator mode, the user should not try to read or write to TH2 or TL2. When operating under these conditions, the timer is being incremented every state time and the results of a read or write command may be inaccurate. The RCAP2 registers, however, may be read but should not be written to, because a write may overlap a reload operation and generate write and/or reload errors. In this case, before accessing the Timer 2 or RCAP2 registers, be sure to turn the timer off by clearing TR2. Pulse Width Modulation (PWM) The VRS51x570 and VRS51x580 devices include a Pulse Width Modulation (PWM) module that has five 8bit channels. Each channel uses an 8-bit PWM data register (PWMD) to set the number of continuous pulses within a PWM frame cycle. PWM Function Description Each 8-bit PWM channel is composed of an 8-bit register that consists of a 5-bit PWM (5 MSBs) and a 3bit (LSBs) Narrow pulse generator (NP). The 5-bit PWM determines the duty cycle of the output. The 3-bit NPx generates and inserts narrow pulses among the PWM frame made of 8 cycles. The number of pulses generated is equal to the number programmed into the 3-bit NP. The NP is used to generate an equivalent 8-bit resolution PWM type DAC with a reasonably high repetition rate through a 5bit PWM clock speed. The PDCK [1:0] setting of the PWMCON (A3h) register is used to derive the PWM clock from Fosc. PWM Clock = Fosc 2(PDCK [1:0] +1) The PWM output cycle frame repetition rate (frequency) is calculated using the following formula: PWM Frame = Or Simply PWM Frame = Fosc 32 x 2(PDCK [1:0] +1) PWM Clock 32 _ www.ramtron.com page 26 of 45 VRS51x570/580 PWM Registers - P1 CON, PWMCON, PWMR PWM Data Registers PWM Registers - Port1 Configuration Register The following tables describe the PWM Data Register bits. The 5 most significant bits of the PWMDx registers determine the duty cycle of the PWM output waveform. TABLE 23: PORT1 CONFIGURATION REGISTER (PWME, $9B) 7 PWM4E 6 PWM3E Bit 7 6 5 4 3 Mnemonic PWM4E PWM3E PWM2E PWM1E PWM0E [2:0] Unused 4 PWM1E 2 3 PWM0E 5 PWM2E 1 Unused 0 Description When bit is set to one, the corresponding PWM pin is active as a PWM function. When the bit is cleared, the corresponding PWM pin is active as an I/O pin. These five bits are cleared upon reset. - TABLE 24: PWM CONTROL REGISTER (PWMCON) ­ SFR A3H Bit [7:2] 1 0 5 4 Unused Mnemonic Unused PDCK1 PDCK0 TABLE 25: PWM DATA REGISTER 0 (PWMD0) ­ SFR A4H 3 PWMD0.0 The following table describes the PWM Control Register signals. 6 The net result of this system is that the average PWM output will have an equivalent resolution of 8-bits. 7 PWMD0.4 PWM Registers -PWM Control Register 7 The three least significant bits of the PWMDx registers control a system that will insert short pulses into the PWM frame cycle. The number of narrow pulses inserted during PWM Frame cycle is proportional to the value written into the 3 least significant bits of the PWMDx register. 3 2 1 0 PDCK1 PDCK0 Description Input Clock Frequency Divider Bit 1 Input Clock Frequency Divider Bit 0 The following table describes the relationship between the values of PDCK1/PDCK0 and the value of the divider. Numerical values of the corresponding frequencies are also provided. PDCK1 PDCKO Divider 0 0 1 1 0 1 0 1 2 4 8 16 PWM clock, Fosc=12MHz 6 MHz 3 MHz 1.5 MHz 0.75 MHz PWM clock, Fosc=25MHz 12.5 MHz 6.25 MHz 3.12 MHz 1.56 MHz Bit 7 6 5 4 3 2 1 0 Mnemonic PWMD0.4] PWMD0.3 PWMD0.2 PWMD0.1 PWMD0.0 NP0.2 NP0.1 NP0.0 6 PWMD0.3 5 PWMD0.2 4 PWMD0.1 2 NP0.2 1 NP0.1 0 NP0.0 Description Contents of PWM Data Register 0 Bit 4 Contents of PWM Data Register 0 Bit 3 Contents of PWM Data Register 0 Bit 2 Contents of PWM Data Register 0 Bit 1 Contents of PWM Data Register 0 Bit 0 Inserts Narrow Pulses in a 8-PWM-Cycle Frame TABLE 26: PWM DATA REGISTER 1 (PWMD1) ­ SFR A5H 7 PWMD1.4 3 PWMD1.0 Bit 7 6 5 4 3 2 1 0 Mnemonic PWMD1.4 PWMD1.3 PWMD1.2 PWMD1.1 PWMD1.0 NP1.2 NP1.1 NP1.0 6 PWMD1.3 5 PWMD1.2 4 PWMD1.1 2 NP1.2 1 NP1.1 0 NP1.0 Description Contents of PWM Data Register 1 Bit 4 Contents of PWM Data Register 1 Bit 3 Contents of PWM Data Register 1 Bit 2 Contents of PWM Data Register 1 Bit 1 Contents of PWM Data Register 1 Bit 0 Inserts Narrow Pulses in a 8-PWM-Cycle Frame _ www.ramtron.com page 27 of 45 VRS51x570/580 TABLE 27: PWM DATA REGISTER 2 (PWMD2) ­ SFR A6H 7 PWMD2.4 5 PWMD2.2 4 PWMD2.1 2 NP2.2 3 PWMD2.0 Bit 7 6 5 4 3 2 1 0 TABLE 29: PWM DATA REGISTER 4 (PWMD1) ­ SFR ACH 6 PWMD2.3 1 NP2.1 0 NP2.0 Mnemonic PWMD2.4 PWMD2.3 PWMD2.2 PWMD2.1 PWMD2.0 NP2.2 NP2.1 NP2.0 7 PWMD4.4 Description Contents of PWM Data Register 2 Bit 4 Contents of PWM Data Register 2 Bit 3 Contents of PWM Data Register 2 Bit 2 Contents of PWM Data Register 2 Bit 1 Contents of PWM Data Register 2 Bit 0 Inserts Narrow Pulses in a 8-PWM-Cycle Frame Bit 7 6 5 4 3 2 1 0 6 PWMD3.3 1 NP3.1 4 PWMD4.1 1 NP4.1 0 NP4.0 Mnemonic PWMD4.4 PWMD4.3 PWMD4.2 PWMD4.1 PWMD4.0 NP4.2 NP4.1 NP4.0 Description Contents of PWM Data Register 4 Bit 4 Contents of PWM Data Register 4 Bit 3 Contents of PWM Data Register 4 Bit 2 Contents of PWM Data Register 4 Bit 1 Contents of PWM Data Register 4 Bit 0 Inserts Narrow Pulses in a 8-PWM-Cycle Frame The following table shows the number of extra short pulses inserted in an 8-PWM cycles frame when we vary the NP number. 4 PWMD3.1 2 NP3.2 3 PWMD3.0 5 PWMD3.2 5 PWMD4.2 2 NP4.2 3 PWMD4.0 TABLE 28: PWM DATA REGISTER 3 (PWMD1) ­ SFR A7H 7 PWMD3.4 6 PWMD4.3 0 NP3.0 N = NP [4:0][2:0] Bit 7 6 5 4 3 2 1 0 Mnemonic PWMD3.4 PWMD3.3 PWMD3.2 PWMD3.1 PWMD3.0 NP3.2 NP3.1 NP3.0 Description Contents of PWM Data Register 3 Bit 4 Contents of PWM Data Register 3 Bit 3 Contents of PWM Data Register 3 Bit 2 Contents of PWM Data Register 3 Bit 1 Contents of PWM Data Register 3 Bit 0 Inserts Narrow Pulses in a 8-PWM-Cycle Frame 000 001 010 011 100 101 110 111 Number of PWM cycles inserted in an 8-cycle frame 0 1 2 3 4 5 6 7 Example of PWM Timing MOV PWMD0 #83H MOV PWME, #08H ; PWMD04 PWMD04:0]=10h (=16T high, 16T low), NP02:0] = 3 ; Enable P1.3 as PWM output pin FIGURE 21: PWM TIMING DIAGRAM 1st Cycle frame 2nd Cycle frame 32T 32T 16 3rd Cycle frame 4th Cycle frame 32T 32T 16 1T 5th Cycle frame 6th Cycle frame 7th Cycle frame 8th Cycle frame 32T 32T 32T 32T 16 1T 16 16 1T (Narrow pulse inserted by NP0[2:0]=3) SPWM clock= 1/T= Fosc / 2^(PDCK+1) The SPWM output cycle frame frequency = SPWM clock/32 = [Fosc/2^(PDCK+1)]/32 If Fosc = 20MHz, PDCK[1:0] of SPWWC = #03H, then PWM clock = 20MHz/2^4 = 20MHz/16 = 1.25MHz. PWM output cycle frame frequency = (20MHz/2^4)/32 = 39.1 kHz. _ www.ramtron.com page 28 of 45 VRS51x570/580 Interrupts Interrupt Vectors The VRS51x570 and VRS51x580 have 8 interrupt sources (9 if we include the WDT) and 7 interrupt vectors (including reset) used for handling. The interrupts are enabled via the IE register shown below: TABLE 30: IEN0 INTERRUPT ENABLE REGISTER ­SFR A8H 7 6 5 4 3 EA - ET2 ES ET1 Bit 7 Mnemonic EA 6 1 0 ET0 EX0 Description Disables All Interrupts 0: no interrupt acknowledgment 1: Each interrupt source is individually enabled or disabled by setting or clearing its enable bit. Reserved Timer 2 Interrupt Enable Bit Serial Port Interrupt Enable Bit Timer 1 Interrupt Enable Bit External Interrupt 1 Enable Bit Timer 0 Interrupt Enable Bit External Interrupt 0 Enable Bit - 5 4 3 2 1 0 2 EX1 ET2 ES ET1 EX1 ET0 EX0 The following figure illustrates the various interrupt sources on the VRS51x570 / VRS51x580. FIGURE 22: INTERRUPT SOURCES INT0 IT0 TF1 TABLE 31: INTERRUPT VECTOR CORRESPONDING FLAGS ANS VECTOR ADDRESS Interrupt Source RESET (+ WDT) INT0 Timer 0 INT1 Timer 1 Serial Port Timer 2 Flag WDRESET IE0 TF0 IE1 TF1 RI+TI TF2+EXF2 Vector Address 0000h 0003h 000Bh 0013h 001Bh 0023h 002Bh External Interrupts The VRS51x570 and VRS51x580 have two external interrupt inputs (INT0 and INT1). These interrupt lines are shared with P3.2 and P3.3. The bits IT0 and IT1 of the TCON register determine whether the external interrupts are level or edge sensitive. If ITx = 1, the interrupt will be raised when a 1 to 0 transition occurs at the interrupt pin. For the interrupt to be noticed by the processor the duration of the sum high and low condition must be at least equal to 12 oscillator cycles. If ITx = 0, the interrupt will occur when a logic low condition is present on the interrupt pin. IE0 The state of the external interrupt, when enabled, can be monitored using the flags, IE0 and IE1 of the TCON register that are set when the interrupt condition occurs. TF0 INT1 The following table specifies each interrupt source, its flag and its vector address. IT1 IE1 INTERRUPT SOURCES In the case where the interrupt was configured as edge sensitive, the associated flag is automatically cleared when the interrupt is serviced. If the interrupt is configured as level sensitive, then the interrupt flag must be cleared by the software. T1 RI TF2 EXF2 _ www.ramtron.com page 29 of 45 VRS51x570/580 Timer 0 and Timer 1 Interrupt Execution of an Interrupt Both Timer 0 and Timer 1 can be configured to generate an interrupt when a rollover of the timer/counter occurs (except Timer 0 in Mode 3). When the processor receives an interrupt request, an automatic jump to the desired subroutine occurs. This jump is similar to executing a branch to a subroutine instruction: the processor automatically saves the address of the next instruction on the stack. An internal flag is set to indicate that an interrupt is taking place, and then the jump instruction is executed. An interrupt subroutine must always end with the RETI instruction. This instruction allows users to retrieve the return address placed on the stack. The TF0 and TF1 flags serve to monitor timer overflow occurring from Timer 0 and Timer 1. These interrupt flags are automatically cleared when the interrupt is serviced. Timer 2 interrupt A Timer 2 interrupt can occur if TF2 and/or EXF2 flags are set to 1 and if the Timer 2 interrupt is enabled. The RETI instruction also allows updating of the internal flag that will take into account an interrupt with the same priority. The TF2 flag is set when a rollover of the Timer 2 Counter/Timer occurs. The EXF2 flag can be set by a 1 to 0 transition on the T2EX pin by the software. Interrupt Enable and Interrupt Priority Note that neither flag is cleared by the hardware upon execution of the interrupt service routine. The service routine may have to determine whether it was TF2 or EXF2 that generated the interrupt. These flag bits will have to be cleared by the software. When the VRS51x570/VRS51x580 device is initialized, all interrupt sources are inhibited by the bits of the IE register being reset to 0. It is necessary to start by enabling the interrupt sources that the application requires. This is achieved by setting bits in the IE register, as discussed previously. Every bit that generates interrupts can either be cleared or set by the software, yielding the same result as when the operation is done by the hardware. In other words, pending interrupts can be cancelled and interrupts can be generated by the software. This register is part of the bit addressable internal SRAM. For this reason, it is possible to modify each bit individually in one instruction without having to modify the other bits of the register. All interrupts can be inhibited by setting EA to 0. Serial Port Interrupt The order in which interrupts are serviced is shown in the following table: The serial port can generate an interrupt upon byte reception or once the byte transmission is completed. TABLE 32: INTERRUPT NATURAL PRIORITY Those two conditions share the same interrupt vector and it is up to the user developed interrupt service routine software to ascertain the cause of the interrupt by looking at the serial interrupt flags RI and TI. Note that neither of these flags is cleared by the hardware upon execution of the interrupt service routine. The software must clear these flags. Interrupt Source RESET + WDT (Highest Priority) IE0 TF0 IE1 TF1 RI+TI TF2+EXF2 (Lowest Priority) _ www.ramtron.com page 30 of 45 VRS51x570/580 Modifying the Interrupt Order of Priority The VRS51x570 / VRS51x580 devices allow the user to modify the natural priority of the interrupts. One may modify the order by programming the bits in the IP (Interrupt Priority) register. When any bit in this register is set to 1, it gives the corresponding source a greater priority than interrupts coming from sources that don't have their corresponding IP bit set to 1. The IP register is represented in the table below. TABLE 33: IP INTERRUPT PRIORITY REGISTER ­SFR B8H 7 6 5 4 3 EA - ET2 ES ET1 2 EX1 1 0 ET0 EX0 Bit 7 6 Mnemonic - Description 5 4 3 2 1 0 PT2 PS PT1 PX1 PT0 PX0 Gives Timer 2 Interrupt Higher Priority Gives Serial Port Interrupt Higher Priority Gives Timer 1 Interrupt Higher Priority Gives INT1 Interrupt Higher Priority Gives Timer 0 Interrupt Higher Priority Gives INT0 Interrupt Higher Priority Watch Dog Timer The Watch Dog Timer (WDT) is a 16-bit free-running counter that generates a reset signal if the counter overflows. The WDT is useful for systems that are susceptible to noise, power glitches and other conditions that can cause the software to go into infinite dead loops or runaways. The WDT function gives the user software a recovery mechanism from abnormal software conditions. The Watch Dog Timer of the VRS51x570 and VRS51x580 devices is driven by an auxiliary RC oscillator having an operating frequency of about 250kHz. This makes the WDT operation independent of the processor oscillator operation. Once the WDT is enabled, the user software must clear it periodically. In the case where the WDT is not cleared, its overflow will trigger a reset of the device. The user should check the WDRESET bit of the SYSCON register whenever an unpredicted reset has taken place. The WDT timeout delay can be adjusted by configuring the clock divider input for the time base source clock of the WDT. To select the divider value, bit2-bit0 (WDPS2~WDPS0) of the Watch Dog Timer Control Register (WDTCON) should be set accordingly. Clearing the WDT is accomplished by setting the CLR bit of the WDTCON to 1. This action will clear the contents of the 16-bit counter and force it to restart. Watch Dog Timer Registers Three registers of the VRS51x570/VRS51x580 devices are associated with the Watch Dog Timer: WDTCON, the WDTLOCK and the SYSCON registers. The WDTCON register allows the user to enable the WDT, to clear the counter and to divide the clock source. The WDRESET bit of the SYSCON register indicates whether the Watch Dog Timer has caused the device reset. TABLE 34: WATCHDOG TIMER REGISTERS: WDTCON ­ SFR 9FH 7 WDTE Bit 7 6 5 [4:3] 2 1 0 6 Unused 5 WDCLR 4 3 Unused 2 1 0 WDTPS [2:0] Mnemonic WDTE Unused WDCLR Unused Description Watch Dog Timer Enable Bit Watch Dog Timer Counter Clear Bit - WDPS [2:0] Watchdog Timer Clock Source Divider To enable the WDT, the user must set bit 7 (WDTE) of the WDTCON register to 1. Once WDTE has been set to 1, the 16-bit counter will start to count with the selected time base source clock configured in WDPS2~WDPS0. The Watch Dog Timer will generate a reset signal if an overflow has taken place. The WDTE bit will be cleared to 0 automatically when the device is reset by either the hardware or a WDT reset. _ www.ramtron.com page 31 of 45 VRS51x570/580 The table below provides examples of Watch Dog timeout periods the user will obtain for different values of the WDPSx bits of the Watch Dog Timer Register. TABLE 35: WATCH DOG TIMER PERIOD VS. WDWDPS [2:0] BIT WDPS [2:0] WDT Timeout (ms) 000 2 001 4.1 010 System Control Register The System Control register is used to monitor the status of the Watch Dog Timer, enabling the operation of the 768 bytes of Expanded SRAM and inhibiting the address Latch Enable signal output. 8.2 011 32.7 101 65.5 110 131 111 7 6 5 WDRESET 16.4 100 TABLE 37: THE SYSTEM CONTROL REGISTER (SYSCON)­SFR BFH 262 Bit 7 [6:3] 2 1 0 Mnemonic WDRESET Unused Unused XRAME ALEI 4 Unused 3 2 1 XRAME 0 ALEI Description Watch Dog Timer Reset Status Bit 1: Enable Electromagnetic Interference Reducer 0: Disable Electromagnetic Interference Reducer Accessing the WDTCON Register By default and as a protection feature, the WDTCON register is read only. This feature is in place to prevent inadvertently writing to this register. The WDTLOCK register is located at SFR address 97h. In order to be able to perform a write operation to the WDTCON register, two consecutive write operations to the WDTLOCK register must first be performed. TABLE 36: WATCHDOG TIMER LOCK REGISTERS: WDTLOCK ­ SFR 97H 7 6 5 4 3 WDTLOCK [7:0] 2 1 0 The WDRESET bit of the SYSCON register is the Watch Dog Timer Reset bit. It will be set to 1 when a reset signal is generated by the WDT overflow. The user should check the WDRESET bit state if a reset has taken place in application where the Watchdog timer is activated Reduced EMI Function The VRS51x570 and VRS51x580 devices can also be set up to reduce its EMI (electromagnetic interference) by setting bit 0 (ALEI) of the SYSCON register to 1. This function will inhibit the Fosc/6Hz clock signal output to the ALE pin. To Enable Write operations into the WDTCON register: You must perform the two following operations: MOV MOV WDTLOCK, #01Eh WDTLOCK, #0E1h .At this point, write operations are allowed to the WDTCON register such as Watch Dog timer Configuration or Watch Dog Timer Clear operations. To disable any further Write operations to the WDTCON register, you must then perform the two following operations: MOV MOV WDTLOCK, #0E1h WDTLOCK, #01Eh _ www.ramtron.com page 32 of 45 VRS51x570/580 Crystal Consideration The crystal connected to the VRS51x570/VRS51x580 oscillator input should be of a parallel type, operating in fundamental mode. The following table shows the value of capacitors and feedback resistor that must be used at different operating frequencies. XTAL C1 C2 R 3MHz 30 pF 30 pF open 6MHz 30 pF 30 pF open 12MHz 30 pF 30 pF open 16MHz 30 pF 30 pF open 25MHz 15 pF 15 pF 62K Note: Oscillator circuits may differ with different crystals or ceramic resonators in higher oscillation frequency. Crystals or ceramic resonator characteristics vary from one manufacturer to the other. The user should check the specific crystal or ceramic resonator technical literature available or contact the manufacturer to select the appropriate values for the external components. XTAL1 XTAL VRS51x570 VRS51x580 R XTAL2 C1 C2 _ www.ramtron.com page 33 of 45 VRS51x570/580 Operating Conditions TABLE 38: OPERATING CONDITIONS Symbol TA TS VCC5V VCC3V Description Operating temperature Storage temperature Supply voltage Supply voltage Min. -40 -55 4.5 3.0 Typ. 25 25 5.0 3.3 Max. 85 155 5.5 3.6 Unit ºC ºC V V Remarks Ambient temperature operating 5 Volts devices 3.3 Volts devices DC Characteristics TABLE 39: DC CHARACTERISTICS AMBIENT TEMPERATURE = -40°C TO 85°C, 3.0V TO 5.5V Symbol VIL1 VIL2 VIH1 VI H2 VOL1 VOL2 Parameter Input Low Voltage Input Low Voltage Input High Voltage Input High Voltage Output Low Voltage Output Low Voltage Valid P o r t 0 ,1,2,3,4,#EA RES, XTAL1 P o r t 0,1,2,3,4,#EA RES, XTAL1 Port 0, ALE, #PSEN P o r t 1,2,3,4 VOH1 Output High Voltage Port 0 VOH2 Output High Voltage Port 1,2,3,4,ALE,#PSEN IIL Logical 0 Input Current C -10 IC C IOL=3.2mA IOL=1.6mA IOH=-800uA (Vcc = 5V) IOH=-80uA IOH=-60uA (Vcc = 5V) IOH=-10uA -75 uA Vin=0.45V P o r t 1,2,3,4 -650 uA Vin=2.OV P o r t 0, #EA +10 uA 0.45V