VMMK-1225 VMMK-125 RX303-92SKHO J-STD-020 J-SDT-020C J-STD-020C AV02-1078EN

Application Note 5378 Description Package Features Avago Technologies has combined our industry leading EpHEMT technology with a

VMMK-1225 VMMK-1225 production assembly process Application Note 5378 Description Package Features Avago Technologies has combined our industry leading EpHEMT technology with a revolutionary wafer level chip scale package design (WLCSP). This wafer level chip scale package is shown next to a typical 0402 capacitor for comparison in Figure 1. The 0402 capacitor is on the right, and the 1 mm x 0.5 mm WLCSP is on the left. This WLCSP is attractive compared to other packaging in terms of cost and size. · Similar board area usage as 0402 (1mm x 0.5mm) · Lower height than 0402 (0.25mm) · Tape and reel capability for chip shooter pick and place applications. Package Dimension Tolerances D E A Figure 1. The VMMK-125 VMMK-125 is nearly the same size as a typical 0402 capacitor, at about half the height. Dimensions Symbol E D A Notes: All dimensions are in mm Min (mm) 0.520 1.020 0.225 Max (mm) 0.575 1.075 0.275 Package Construction This package is a non-hermetic wafer level chip scale package which contains a cavity and comprises a Gallium Arsenide top cover (Cap) and a bottom Gallium Arsenide substrate (base). Active circuitry is on the base and is internal to the cavity. There is a gasket around the interface to join the cap and base. This construction should be a consideration for handling and shear testing. Top cover (Cap) Final Thickness 140um Gasket Thickness 10um Substrate (Base) Final Thickness 100um Total Package Thickness 250um Cap wafer top GASKET CAVITY TOPSIDE Cap wafer bottom Cap Wafer Connect Pad Circuitry Connect Pad IC Wafer Base wafer top Pad for solder Via Base wafer bottom Figure 2. Cross section side view showing major elements, lid,cap, and gasket (not to scale) A photo of a soldered unit is shown in figure 3. A tilt of 6 to 16 degrees along the long axis is typical for this device after the solder reflow process. This passed solder qualification tests. When performing die shear tests, the shear head must be placed on the die edge with the Cap vertical or tilting away from the shear tool. If the tilted die is sheared such that the shear head makes contact with the Cap instead of the base wafer, it is possible to sever the Cap at the gasket, giving a false shear reading. See Figure 4. Cap edge Wrong direction of shear tool WLCSP Cap WLCSP Base Solder Area PCB Figure 3. Soldered unit with 6 to 16 degrees of tilt on the PCB Figure 4. Side view (not to scale) Shear tool should not push against top edge of cap. Soldermask design A properly designed solder screen or stencil is required to ensure optimum amount of solder paste is deposited onto the PCB pads. The stencil is suggested to have a solder paste deposition opening approximately 90% of the PCB land pattern. The stencil should be 4 mils thick. Too little stencil opening could potentially generate voids underneath. Also, a stencil opening larger than 100% will lead to excessive solder paste thickness and can bridge the lands to cause shorts or otherwise affect the quality of the solder joint. are also other lead-free alloy compositions in the industry which have slight variations in melt temperature. Important: Conductive epoxy should not be used as an alternative to solder paste. Conductive epoxy can smear across the gap between the input, ground, and output pads, resulting in device shorts. Lead-free solder paste should be screen printed before reflow. The electronics industry has accepted the use of Pbfree solder 96.5/3.0/0.5 SAC alloy as a standard for reflow. This composition has a melting point of 217-219 ºC. There The specific solder paste used in our solder evaluation was: RX303-92SKHO RX303-92SKHO manufactured by Nihon Handa, which has a solder composition of Sn96.5 Ag3.5 and a melting point of 218-220 ºC. This paste is only an example, not required for assembly. Solder profiles could require variation depending upon the different alloys and brands of solder paste. Other factors that can affect the profile include the density and types of components on the board, and board material being used. Figure 5. This bottom view of the device shows the metal pad footprint dimensions for the solder process. (dimensions in mm) A non-wetable metal layer (solder stop) surrounds the pads to inhibit solder bridging. Figure 6. The suggested PCB footprint. (dimensions in mm). This is a nonsolder mask defined footprint (NSMD). The solder mask opening does not overlap the metal pads or separate the metal pads. Solder paste Device footprint notes: 1. Pin 1 is identified by the notch on the corner of the input pad 2. Pad material is minimum 5.0 um thick Au under maximum 1.0um thick Ni with Au flash. The Ni is the layer that is wettable by solder. 3. This device follows the standard 0402 capacitor form factor, but does not use a standard 0402 land pattern. The device backside metal pattern comprises of three solder pads as depicted in the bottom view. The gap between the pads must not be bridged with solder. Automated Assembly for Production This device is designed to be handled and processed onto the PCB using standard 0402 handling and assembly processes. Process flow: 1. Incoming tape and reel inspection 4. Solder reflow and inspection 2. Solder paste print and inspection 5. Optional board cleaning process to remove flux 3. Placement of unit onto PCB 6. Final inspection Solder Reflow Process overview Reliable assembly of surface mount components is a complex process that involves many material, process, and equipment factors, including: method of heating, circuit board material, conductor thickness, pattern, type of solder paste and solder alloy, thermal conductivity, and thermal loading and mass of components. Chip scale components such as this WLCSP will reach solder reflow temperatures faster than those with a greater mass. Reflow temperature settings need to be determined by the end user based on these considerations. Also, moisture sensitivity MSL level 2a has been qualified for this device. The MSL level 2a conditions must not be exceeded. After ramping up from room temperature, the circuit board with components held in place with solder paste, passes through one or more preheat zones. The preheat zones increase the temperature of the board and components to prevent thermal shock and being evaporating the solvents from the solder paste. The reflow zone briefly elevates the temperature sufficiently to produce a reflow of the solder. Profile for Reflow Soldering The reflow profile investigated and recommended by Avago for this product is based on JEDEC/IPC standard J-STD-020 J-STD-020 revision C. This device has been qualified to withstand a maximum of 3 cycles of solder reflow according to the conditions of J-SDT-020C J-SDT-020C and this device has been qualified for moisture sensitivity level 2a. Figure 7 depicts this standard lead-free JEDEC/IPC profile. Table 1 lists the parameters and peak temperatures as indicated by JEDEC/IPC. The most recommended and most common reflow method is accomplished in a belt furnace using convection/ IR heat transfer. This profile shows the actual temperature range that should occur on the surface of a test board at or near a central solder joint. During this type of reflow soldering, the circuit board and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs thermal energy more efficiently, then distributes this heat to the components. Do not use prolonged hot preheat due to excessive oxidation which can occur on the solder powder surface. The time at peak is not critical and usually not measured as it is very dependent upon the type of oven used. However, time over 217 ºC is critical and will determine the appearance of the solder joint after reflow. Longer reflow time may result in dull and gritty solder joint appearance and charring of flux residues. Time below 30 seconds may result in insufficient wetting and poor intermetallic formation. The cooling rate too fast could result in insufficient wetting and poor intermetallic formation. As a general guideline, this WLCSP should be exposed to only the minimum leadfree process temperature and times necessary to achieve a uniform reflow of solder on the board. The rates of change of temperature for the ramp-up and cool-down zones are specified by J-STD020c standard to be low enough to not cause deformation of the board or damage to components due to thermal shock. This profile allows a reflow temperature which is low enough to avoid damaging the internal circuitry during solder reflow operations provided the time of exposure at peak reflow temperature is not too excessive. Also refer to the VMMK-1225 VMMK-1225 product data sheet for further information. tp Tp Critical Zone TL to Tp Ramp-up Temperature TL tL Ts max Ts min Ramp-down ts Preheat 25 t 25°C to Peak Time Figure 7. Standard J-STD-020C J-STD-020C lead-free solder reflow profile Table 1. Typical SMT Reflow Profile for Maximum Temperature = 260+0 / -5°C Profile Feature Sn-Pb Solder Pb-Free Solder Average ramp-up rate (TL to TP) 3°C/sec max 3° C/sec max Preheat - Temperature Min (Tsmin) - Temperature Max (Tsmax) - Time (min to max) (ts) 100°C 150°C 60-120 sec 150°C 200°C 60-180 sec Tsmax to TL - Ramp-up Rate 3°C /sec max Time maintained above: - Temperature (TL) - Time (TL) 183°C 60-150 sec 217°C 60-150 sec Peak temperature (Tp) 240 +0/-5°C 260 +0/-5°C Time within 5°C of actual Peak Temperature (tp) 10-30 sec 20-40 sec Ramp-down Rate 6°C /sec max 6°C /sec max Time 25°C to Peak Temperature 6 min max. 8 min max. For product information and a complete list of distributors, please go to our web site: www.avagotech.com Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies Limited in the United States and other countries. Data subject to change. Copyright © 2005-2008 Avago Technologies Limited. All rights reserved. AV02-1078EN AV02-1078EN - April 2, 2008