NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
VIC64 VIC068A VAC068A CY7C964 EME-6300H 7C964 STD-008 UL-94V C/125 - Datasheet Archive
November, 1994 - QTP# 93101 Version 1.1 CMOS2AN PROCESS MARKETING PART NUMBER VIC64 DEVICE DESCRIPTION VMEbus Interface
Qualification Report November, 1994 - QTP# 93101 Version 1.1 CMOS2AN PROCESS MARKETING PART NUMBER VIC64 VIC64 DEVICE DESCRIPTION VMEbus Interface Controller with D64 VIC068A VIC068A VMEbus Interface Controller VAC068A VAC068A VMEbus Address Controller CY7C964 CY7C964 Bus Interface Logic Circuit PRODUCT DESCRIPTION (for qualification) Information provided in this document is intended for generic qualification and technically describes the Cypress part supplied: Bus Interface Products Marketing Part #: VIC64 VIC64, VIC068A VIC068A Device Description: Bus Interface Products Cypress Division: Cypress Semiconductor Corporation Overall Die (or Mask) REV Level (pre-requisite for qualification): Die Size (stepping): 315 mils x 312 mils Rev. A What ID markings on Die: Cypress Qualification completion/Marketing Availability Dates (Current REV): November, 1994 TECHNOLOGY/FAB PROCESS DESCRIPTION - CMOS2AN Number of Metal Layers: 2 Metal Composition: Passivation Type and Materials: 7K TEOS + 6K Nitride Free Phosphorus contents in top glass layer(%): Die Coating(s), if used: Metal 1: Al, 1% Si Metal 2: Al, 1% Si None N/A Generic Process Technology/Design Rule (µ-drawn): CMOS, 1.2 µm Gate Oxide Material/Thickness (MOS): SiO2 / 250 A Name/Location of Die Fab (prime) Facility: Fab 3, Bloomington, MN Die Fab Line ID/Wafer Process ID: Fab3 / CMOS2AN PAGE 3 CYPRESS SEMICONDUCTOR PLASTIC PACKAGE/ASSEMBLY DESCRIPTION Package Outline, Type, or Name: 144-Pin Plastic Pin Grid Array Die to Package edge clearance: 42 mils per side Mold Compound Name/Manufacturer: Lead Frame material: Sumitomo EME-6300H EME-6300H(R) Copper Lead Finish, composition: Solder Dipped, 90%Sn, 10%Pb Die Attach Area Plating: Gold Die Attach Pad Dim: 400 mils x 400 mils Die Attach Method: Gold Ball Die Attach Material: Silver Epoxy Wire Bond Method: Wire Wire Material/Size: Gold / 1.3 mil Name/Location of Assembly (prime) facility: VLSI, Texas Assembly Line ID and Process ID: USA-V /PPGA HERMETIC PACKAGE/ASSEMBLY DESCRIPTION Package Outline, Type, or Name: 144-Pin Ceramic Pin Grid Array Die to Package edge clearance: 80 mils per side Mold Compound Name/Manufacturer: Lead Frame material: N/A Kovar/Gold Lead Finish, composition: .06 mil. Au over 0.1 mil. Nikel Die Attach Area Plating: Au Die Attach Pad Dim: 400 mils x 400 mils Die Attach Method: Silver Glass Die Attach Material: Silver Epoxy Wire Bond Method: Wire Wire Material/Size: Al-Si / 1.25 mil Name/Location of Assembly (prime) facility: VLSI, Texas Assembly Line ID and Process ID: USA-V /CPGA HERMETIC PACKAGE/ASSEMBLY DESCRIPTION Package Outline, Type, or Name: 160 Lead Ceramic Quad Flatpack Die to Package edge clearance: 55 mils per side Mold Compound Name/Manufacturer: Lead Frame material: N/A Alloy 42 Lead Finish, composition: Gold Plate Die Attach Area Plating: None Die Attach Pad Dim: 425 mils x 425 mils Die Attach Method: Silver Glass Die Attach Material: Silver Epoxy Wire Bond Method: Ultrasonic Wire Material/Size: Al-Si / 1.25 mil Name/Location of Assembly (prime) facility: VLSI, Texas Assembly Line ID and Process ID: USA-V /CQFP PAGE 4 CYPRESS SEMICONDUCTOR OTHER INFORMATION For approval by similarity, identify other devices using the same basic die with bonding or metal mask options or test selections and explain: All CMOS2N products: VIC068A VIC068A, VAC068A VAC068A, VIC64 VIC64, 7C964 7C964 If Cypress is planning any changes in the near future, identify change (Qtr/Yr) in: Die Design Rev./Shrink: Die Process Change: Fab/Assembly site change: Cross Licensee/Licensor: Other Devices to be qualified in this technology: Other Packages to be qualified for this device: Ceramic/plastic Quad Flatpack Ceramic/Plastic Pin Grid Array ESD Voltage Rating (per MIL STD-008 STD-008, Method 3018): >1,000V Flammability Classification (UL-94V UL-94V): None Alternate Fab/Assembly Locations: Assembly : Please attach the following Qualification / Reliability data for the die revision and Package type, for the fab and assembly sites identified above (mark [X] if included): 1 X HAST (5.5V, 140°C, 85%RH, 15psig) 7 X Operating Life at (temp): 2 X Temperature Cycles (-65°C to 150°C) 8 X Steady State Life (HTSSL, 5.75V, 150°C) 3 Temperature Cycles (-40°C to 165°C) 9 X Steady State Life (HTSSL, 5.5V, 125°C) 4 Data Retention Bake, Plastic (165°C) 10 X Latchup Testing 5 Data Retention Bake, Hermetic (250°C) 11 X ESD Tests (MIL-STD 883, method 3015) Autoclave (PCT, 121°C, 100%RH) 12 X Other: 6 X Current Density Input Capacitance Internal Water Vapor Aged Bond Strength SEM Analysis Long Life Verification 150°C/125 C/125°C PAGE 5 CYPRESS SEMICONDUCTOR PRODUCT INFORMATION FOR QUALIFICATION BY SIMILARITY Product Family: VMEBus CMOS2AN Process Mfg Division: Cypress Semiconductor Supplier's Part Number Pkg Size/ Type Die Rev. Die Size mil x mil (stepping) Design Rule (µ) µ Fabrication Process ID Passivation Type Assembly ESD Volt Availa Line Rating bility Location Line ID VIC64 VIC64 -BC -GC/GM/GMB -NC -UC/UM/UMB 144-Pin PPGA 144-Pin CPGA 160-Lead PQFP 160-Lead CQFP A 315 x 312 1.2µm CMOS2N 3 TEOS + NITRIDE VLSI, TX >1,000V HBM 5/94 VIC068A VIC068A -BC -GC/GI/GM/GMB -NC -UC/UI/UM/UMB 144-Pin PPGA 144-Pin CPGA 160-Lead PQFP 160-Lead CQFP A 315 x 312 1.2µm CMOS2N 3 TEOS + NITRIDE VLSI, TX >1,000V HBM 5/94 VAC068A VAC068A -BC -GC/GI/GM/GMB -NC -UC/UI/UM/UMB 144-Pin PPGA 144-Pin CPGA 160-Lead PQFP 160-Lead CQFP A 315 x 312 1.2µm CMOS2N 3 TEOS + NITRIDE VLSI, TX >1,000V HBM 5/94 CY7C964 CY7C964 -NC 64-Lead PQFP -UC/UI/UM/UMB 64-Lead CQFP A 148 x 145 1.2µm CMOS2N 3 TEOS + NITRIDE VLSI, TX >1,000V HBM 5/94 PAGE 6 CYPRESS SEMICONDUCTOR Marketing Part: Pkg Description: DEVICE RELIABILITY SUMMARY VIC064/VIC068A VIC064/VIC068A 144-pins Ceramic Pin Grid Array 144-pins Plastic Pin Grid Array Wafer Fab: Assembly: Fab3, Bloomington, Mn VLSI, Texas High Temperature Dynamic Operating Life (HTOL, 5.5V, 150°C) - Early Failure Rate Device Assy Lot# 48 Hours Cumulative 7C068D-GMB 7C068D-GMB 49306887 0/337 0/337 High Temperature Dynamic Operating Life (HTOL, 5.5V, 125°C) - Early Failure Rate Device Assy Lot# 96 Hours Cumulative 7C068D-BC 7C068D-BC 7C068D-BC 7C068D-BC 49306061 49306148 0/336 0/336 0/672 High Temperature Dynamic Operating Life (HTOL, 6.5V, 125°C) - Latent Failure Rate Device Assy Lot# 168 Hours 1000 Hours Cumulative 7C068D-BC 7C068D-BC 7C068D-BC 7C068D-BC 49306061 49306148 0/77 0/77 0/77 0/77 0/154 High Temperature Dynamic Operating Life (HTOL, 5.5V, 150°C) - Latent Failure Rate Device Assy Lot# 80 Hours 500 Hours Cumulative 7C068D-GM 7C068D-GM 49306887 0/77 0/77 0/77 High Temperature Steady State Life Test (HTSSL, 5.75V, 150°C) Device Assy Lot# 168 Hours Cumulative 7C068D-GMB 7C068D-GMB 49306887 0/78 0/78 PAGE 7 CYPRESS SEMICONDUCTOR High Temperature Steady State Life Test (HTSSL, 5.75V, 125°C) Device Assy Lot# 336 Hours Cumulative 7C068D-BC 7C068D-BC 7C068D-BC 7C068D-BC 49306148 49306061 0/78 0/78 0/156 Long Life Verification (LLVA , 5.5V, 150C) Device Assy Lot# 1000 Hours 2000 Hours 7C068D-GM 7C068D-GM 49306887 0/76 Cumulative 0/76 0/76 Group C, Subgroup1, Lifet Test (HTOL, 5.75V, 125°C) Device Assy Lot# 184 Hours Cumulative 7C064-UMB 7C064-UMB V05032 V05032 0/80 0/80 Temperature Cycle (Condition C, -65°C to 150°C) Device Assy Lot# 7C068D-BC 7C068D-BC 7C068D-BC 7C068D-BC 7C068D-GMB 7C068D-GMB 49306061 V11012 V11012 V11139 V11139 100 Cycles 1000 Cycles Cumulative 0/47 0/47 0/45 300 Cycles 0/47 0/47 0/45 0/139 High Accelerated Saturation Test (HAST, 5.5V, 140°C, 85%RH, 15psig) Device Assy Lot# 128 Hours Cumulative 7C068D-BC 7C068D-BC 7C068D-BC 7C068D-BC 49306061 49306148 0/45 0/45 0/90 Pressure Cooker Test (PCT 100% RH 121°C, 15psig) Device Assy Lot# 168 Hours Cumulative 7C068D-BC 7C068D-BC 7C068D-BC 7C068D-BC 11048A 11049A 0/50 0/50 0/100 PAGE 8 CYPRESS SEMICONDUCTOR Marketing Part: Pkg Description: DEVICE RELIABILITY SUMMARY VIC064/VIC068A VIC064/VIC068A Wafer Fab: 144-pins Ceramic Pin Grid Array Assembly: 144-pins Plastic Pin Grid Array Fab3, Bloomington, Mn VLSI, Texas CMOS2AN PROCESS VIC64/VIC068A/VAC068A/7C964 VIC64/VIC068A/VAC068A/7C964 Electrostatic Discharge Human Body Model Circuit per Mil Std 883, Method 3015 >+1,000V Unit 1 >-1,000V >+1,000V Unit 2 >-1,000V >+1,000V Unit 3 >-1,000V (Highest passing voltage, +10% Guard banded) Latchup Testing to Cypress Internal Latch-up Procedure 3 Tests: Current Injection = 200mA Trigger Hot Socket = VCC 0 - 8V Temp = 125°C Other miscellaneous tests Current Density SEM Cross Section (3 wafers) Pass Pass Input Capacitance Internal Water Vapor Aged Bond Strength Pass Pass Pass Assembly In Line Pass