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VHDL PROGRAM for ofdm

Catalog Datasheet MFG & Type PDF Document Tags

vhdl code for ofdm

Abstract: vhdl code for ofdm transmitter core. VHDL Test Bench and Simulation Vectors used for verification are provided with the core , AllianceCORE Facts Provided with Core Documentation S.r.l. User Guide Design File Formats VHDL , Xilinx ISE User Constrains File VHDL Test Bench and Test Vectors Instantiation Templates VHDL , (ETSI EN 300 744 V1.5.1 (2004-11) - annex F) Configurable for 2K, 4K and 8K Transmission Modes Support Hierarchical Transmission Mode Status and control registers available for start up and continuous test and
Xilinx
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vhdl code for ofdm

Abstract: ofdm matlab simulation block AllianceCORE Facts Provided with Core Documentation S.r.l. User Guide Design File Formats VHDL , Xilinx ISE User Constrains File VHDL Test Bench and Test Vectors Instantiation Templates VHDL , (ETSI EN 300 744 V1.5.1 (2004-11) - annex F) Configurable for 2K, 4K and 8K Transmission Modes Support Hierarchical Transmission Mode Status and control registers available for start up and continuous test and management Internal 20 bit architecture for high level MER and BER performances Options: - SFN
Xilinx
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code iir filter in vhdl

Abstract: digital IIR Filter VHDL code the core. VHDL Test Bench and Simulation Vectors used for verification are provided with the core , AllianceCORE Facts Provided with Core Documentation User Guide Design File Formats VHDL , Xilinx ISE User Constrains File VHDL Test Bench and Test Vectors Instantiation Templates VHDL , microcontroller interface could be added Table 1: Example Implementation Statistics for Xilinx® FPGAs Fmax , correction coefficients necessary to correct an OFDM symbol; OFDM symbol carriers are grouped by 8, 4 or 2
Xilinx
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CRC matlab

Abstract: mini project simulink DSP Program IP IP IP IEEE PLD IP DSP PLD IP IP , AHDL Altera Hardware Description Language VHDL Verilog HDL MegaWizard Plug-InMATLABSimulink VHDL Verilog HDL 4 Altera Corporation MATLAB/Simulink PLD IPIP MegaStoreweb IP , Corporation 5 IPLAN 802.11a OFDM 802.16HiperLAN/2 FEC IP FFT IP OFDM , GSMGlobal System for Mobile communication s s s s s s s DSP MMDS DVD VDSL LMDSLocal
Altera
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dvb-t matlab simulation code

Abstract: vhdl code for dvb-t performed on the core. VHDL Test Bench and Simulation Vectors used for verification are provided with the , AllianceCORE Facts Provided with Core Documentation S.r.l. User Guide Design File Formats VHDL , Xilinx ISE User Constrains File VHDL Test Bench and Test Vectors Instantiation Templates VHDL , for Xilinx® FPGAs Fmax Family Example Device (MHz) Slices 1 IOB MULT/ GCLK , fixed 4X interpolator filter. Signal gain control and low-pass filter for out-of-band removal should
Xilinx
Original

GSM 900 simulink matlab

Abstract: verilog code for ofdm transmitter generate high-level simulation output files for the MATLAB and Simulink software as well as and VHDL or , parallel, they offer OFDM has recently surged in popularity for wireless systems. Broadcast , ® Signal Processing IP Megafunctions Signal Processing Solutions for System-on-a , for Existing Designs portfolio-including MegaCore® and Altera Megafunction Signal processing IP can be integrated easily into the Partners Program (AMPP ) functions-has been rigorously
Altera
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dvbt transmitter

Abstract: Xilinx asi Provided with Core Documentation S.r.l. User Guide Design File Formats VHDL synthesizable , Xilinx ISE User Constrains File VHDL Test Bench and Test Vectors Instantiation Templates VHDL , flags available for start up and continuous test and management Table 1: Example Implementation Statistics for Xilinx® FPGAs Fmax Family Example Device (MHz) 1 MULT/ Slices IOB GCLK , on-air Symbol Rate. Thus it is possible for the input Transport Stream rate to be greater than the
Xilinx
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7809 data sheet national semiconductor

Abstract: design of FM reciever final year project for Altera Customers Altera Unleashes Quartus II Software Version 1.0 Altera's new QuartusTM II , productivity. Featuring PowerFitTM technology, support for ExcaliburTM embedded processor solutions, the , other productivity tools, the Quartus II software offers a superior development environment for SOPC , fMAX 2.0 1.5 1.0 New fitting technology for placement and routing in the Quartus II software , available only in application specific standard products (ASSPs). With support for up to 18 channels of
Altera
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vhdl code for ofdm transceiver using QPSK

Abstract: soft 16 QAM modulation matlab code process and has been fully optimized for Altera devices. All third-party IP in the AMPP program have the , Altera's DSP portfolio. OFDM OFDM has recently surged in popularity for wireless systems. Broadcast , Figure 7. Complete System Solution for a Typical OFDM Transmitter Data In FEC Coder , Intellectual Property Selector Guide IP Functions for System-on-a-Programmable-Chip Solutions , FPGA users. These vendors, called AMPP partners, develop IP that is optimized for Altera devices and
Altera
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vhdl code for radix-4 fft

Abstract: verilog for 8 point fft Image processing Atmospheric imaging Spectral representation OFDM modulation scheme for: - ADSL (up , the input signal YSC. Assert CLR to program the core for required transform type and transform , . Assert CLR to program the core for required transform type and transform size Output Figure 4 , CS2410 TM 8-1024 Point FFT/IFFT Virtual Components for the Converging World The CS2410 is , required Optimized for both ASIC and FPGA technologies with the same functionality KEY METRICS Logic
Amphion Semiconductor
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DS2410 vhdl code for radix-4 fft verilog for 8 point fft verilog code for radix-4 complex fast fourier transform vhdl for 8 point fft verilog code for 256 point fft based on asic 16 point FFT radix-4 VHDL

verilog code for twiddle factor radix 2 butterfly

Abstract: FFT CODING BY VERILOG FOR 8 POINT WITH RADIX 2 memory required Optimized for both ASIC and FPGA technologies with the same functionality KEY METRICS Logic: 59k gates Memory: , Clock Cycle I/O and Transform Timing 8 1 1 TM Assert CLR to program the core for , CS2420 TM 2048/4096/8192 Point FFT/IFFT Virtual Components for the Converging World The
Amphion Semiconductor
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verilog code for twiddle factor radix 2 butterfly FFT CODING BY VERILOG FOR 8 POINT WITH RADIX 2 VHDL code for radix-2 fft vhdl code for FFT 32 point verilog code radix 4 multiplication vhdl code for 16 point radix 2 FFT DS2420

matlab programs for impulse noise removal

Abstract: verilog code for cordic algorithm for wireless , pipelined hardware for the target FPGA device and clock rate. DSP Builder implements the hardware as VHDL , the DSP Builder Handbook. The VHDL model for standard blockset subsystems is generated when you , communications blockset, refer to the MATLAB Help. A VHDL model generates for subsystems with the advanced , Builder for all users of MATLAB. In this case, the install program updates the pathdef.m and classpath.m , install program searches for an existing installation of DSP Builder before it installs a new version. If
Altera
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matlab programs for impulse noise removal verilog code for cordic algorithm for wireless verilog code for CORDIC to generate sine wave block interleaver in modelsim matlab programs for impulse noise removal in image vhdl code for cordic

xc6slx150t

Abstract: STR Y 6763 computationally efficient method for calculating the Discrete Fourier Transform (DFT). Supported Device Family (1 , -6, Spartan-6 AXI4-Stream See Tables 25 to 28 Features · · · · · · · Drop-in module for Virtex®-7 and , Design Test Bench Constraints File Simulation Model Product Specification Netlist Not Provided VHDL N/A VHDL Verilog C Model Tested Design Tools Design Entry Tools CORE Generator 13.1 System Generator for DSP 13.1 Mentor Graphics ModelSim 6.6d Cadence Incisive Enterprise Simulator (IES) 10.2 Synopsys
Xilinx
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xc6slx150t STR Y 6763 64 point FFT radix-4 VHDL documentation 16 point FFT radix-4 VHDL documentation radix-2 DIT FFT vhdl program fft matlab code using 8 point DIT butterfly DS808

str 5653

Abstract: STR - Z 2757 algorithm, a computationally efficient method for calculating the Discrete Fourier Transform (DFT). The , . Features · Drop-in module for Virtex®-6, Virtex-5, Virtex-4, Spartan®-6, Spartan-3/XA, Spartan-3E/XA , factor precision bw = 8 ­ 34 · Arithmetic types: Scaled fixed-point For , bits for each of the real and imaginary components of the output data. Input data is presented in , (full-precision) fixed-point For fixed-point inputs, the input data is a vector of N complex values
Xilinx
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str 5653 STR - Z 2757 STR M 6545 STR G 5653 STR F 5653 RTL 8376 DS260

T5757

Abstract: Microcontroller - AT89s52 connections with lcd a wide range of applications for many customers), ASSPs (a single application for a limited number of customers) and ASICs (implementing a specific application for a single customer). Atmel ICs are , evolution and product innovation by means of an on-going program of research and development, undertaken in , processes are migrating from a 0.18-micron minimum feature size to 0.13 microns. Ideally suited for advances , those of CMOS. Atmel's high-voltage BCDMOS and BCD on SOI processes are optimized for high-voltage
Atmel
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T5757 Microcontroller - AT89s52 connections with lcd Stepper motor control using AT89S52 DC MOTOR SPEED CONTROL SYSTEM USING AT89S52 MICRO AVR voltage regulator schematic using Triac hand dryer circuit using 8051 U2270B U4289BM U2538B U4311B-FS U2730B U4468B

night vision technology documentation

Abstract: DP8051 Programming Support for Low-Cost SPI Configuration Memory Lattice Expands Lead-Free Support Designing , ispLEVER® v.4.2 Design Tools New Boards for LatticeEC Evaluation and Development Lattice and Mentor , pipelining logic for extra speed and density. The LatticeECP and LatticeEC devices are implemented on a , LatticeEC33 FPGAs provide optimal support for customers whose requirements fall between the previously , combined with the lowest total solution costs of any FPGAs. The LatticeECP-DSP products, targeted for
Lattice Semiconductor
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night vision technology documentation DP8051 atmel 336 M25PXX diF fft algorithm VHDL FIR filter verilog abstract ECP-DSP20 NL0109

64 point FFT radix-4 VHDL documentation

Abstract: matlab code for half adder VHDL/Verilog design. Please refer to the ispLEVER documentation for instructions on how to accomplish , DSP Guide for FPGAs Lattice Semiconductor Corporation 5555 NE Moore Court Hillsboro, OR 97124 , , The Simple Machine for Complex Design, TransFR, UltraMOS, and specific product designations are , service marks of Lattice Semiconductor Corporation. Other product names used in this publication are for , PROPERTY, OR FITNESS FOR ANY PARTICULAR PURPOSE. IN NO EVENT WILL LATTICE SEMICONDUCTOR CORPORATION (LSC
Lattice Semiconductor
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matlab code for half adder FSK matlab CORDIC to generate sine wave fpga vhdl code for ofdm simulink 3 phase inverter verilog code for fir filter using DA

AT90SC7272C

Abstract: T5757 OFDM), Capable of Supporting 802.11a/b/g, Includes Hardware, AES and TKIP for Security, (32 , 48 MHz. Includes Integrated SRAM for both Program and Data Now AT76C713-0T100 Based on , Microcontrollers . . . . . . . . . . . . . . . . . . 34-35 Secure Microcontrollers for Smart Card Applications ­ , for Smart Card Applications ­ AT91SC Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Secure Microcontrollers for Smart Card Applications ­ AT05SC Family . . . . . . . . . . . .
Atmel
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AT90SC7272C AVR atmega8515 led matrix ATSAM2193 fingerprint scanner circuit AT78C5010 STK502 voltage regulator U5021M U6032B U6043B U6046B U6083B U6084B

sandisk micro sd

Abstract: digital clock using at89s52 microcontroller + Dual BB (CCK + OFDM), Capable of Supporting USB 2.0, Includes in Hardware, AES and TKIP for , (CCK + OFDM), Capable of Supporting PCI/mini-PCI , Includes in Hardware, AES and TKIP for Security, 32 , warranty for the use of its products, other than those expressly contained in the Company's standard , assumes no responsibility for any errors which may appear in this document, reserves the right to change , . Atmel's products are not authorized for use as critical components in life support devices or systems
Atmel
Original
sandisk micro sd digital clock using at89s52 microcontroller sandisk micro sd card pin configuration stepper motor control with avr application notes vhdl code for rs232 receiver STK 435 power amplifier CH-1705 ARM946E-STM ARM920TTM MIPS64TM 3271B

pure sine wave dimmer

Abstract: philips ingenuity ct . 1 A -la w / A C L in e a rity -A A-law: A European standard for the non-linear digitization of voice signals. Also see (u-law). A/D Converter (also A/D or ADC): Short for analog-to-digit:.l converter , . The most common architectures for video-speed A/D converters are "flash" and "subranging" foi lower speeds. A/PC: Auto PC - Windows CD devices for cars AAC: Analog to Amplitude Converter AAMI: Association for the Advancement of Medical Instrumentation AAL: see A7M Adaptation Layer. AAU: Analog Audio ABCMOS
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OCR Scan
pure sine wave dimmer philips ingenuity ct heart beat sensor using led and ldr transistor smd DAG north american philips controls stepper motor vhdl code for msk modulation B4-30 IS-54 10BASE-T 10BASE-2 10BASE-5
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