V850ES/JG3-H V850ES/JH3-H PD70F3760 PD70F3765 PD70F3761 PD70F3766 PD70F3762

32 V850ES/JG3-H, V850ES/JH3-H User's Manual: Hardware RENESAS MCU V850ES/Jx3-H Microcontrollers V850ES/JG3-H V850ES/JH3-H

User's Manual 32 V850ES/JG3-H V850ES/JG3-H, V850ES/JH3-H V850ES/JH3-H User's Manual: Hardware RENESAS MCU V850ES/Jx3-H Microcontrollers V850ES/JG3-H V850ES/JG3-H V850ES/JH3-H V850ES/JH3-H PD70F3760 PD70F3760 PD70F3765 PD70F3765 PD70F3761 PD70F3761 PD70F3766 PD70F3766 PD70F3762 PD70F3762 PD70F3767 PD70F3767 PD70F3770 PD70F3770 PD70F3771 PD70F3771 All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas Electronics Corp. without notice. Please review the latest information published by Renesas Electronics Corp. through various means, including the Renesas Electronics Corp. website (http://www.renesas.com). www.renesas.com Rev.4.00 Sep, 2010 Notice 1. 2. 3. 4. 5. 6. 7. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. 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Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of Renesas Electronics. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries. (Note 1) "Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its majorityowned subsidiaries. (Note 2) "Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics. NOTES FOR CMOS DEVICES 1 VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (MAX) and VIH (MIN). 2 HANDLING OF UNUSED INPUT PINS Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must be judged separately for each device and according to related specifications governing the device. 3 PRECAUTION AGAINST ESD A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors should be grounded. The operator should be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with mounted semiconductor devices. 4 STATUS BEFORE INITIALIZATION Power-on does not necessarily define the initial status of a MOS device. Immediately after the power source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the reset signal is received. A reset operation must be executed immediately after power-on for devices with reset functions. 5 POWER ON/OFF SEQUENCE In the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. When switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. Use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. The correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. 6 INPUT OF SIGNAL DURING POWER OFF STATE Do not input signals or an I/O pull-up power supply while the device is not powered. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. Input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. How to Use This Manual Readers This manual is intended for users who wish to understand the functions of the V850ES/JG3-H V850ES/JG3-H and V850ES/JH3-H V850ES/JH3-H and design application systems using the V850ES/JG3-H V850ES/JG3-H and V850ES/JH3-H V850ES/JH3-H. Purpose This manual is intended to give users an understanding of the hardware functions of the V850ES/JG3-H V850ES/JG3-H and V850ES/JH3-H V850ES/JH3-H shown in the Organization below. Organization The manual of these products is divided into two volumes: Hardware (this volume) and Architecture (V850ES V850ES Architecture User's Manual). Hardware Architecture · Pin functions · CPU function · Register set · On-chip peripheral functions · Instruction format and instruction set · Flash memory programming · Interrupts and exceptions · Electrical specifications How to Read This Manual · Data types · Pipeline operation It is assumed that the readers of this manual have general knowledge in the fields of electrical engineering, logic circuits, and microcontrollers. To understand the overall functions of the V850ES/JG3-H V850ES/JG3-H and V850ES/JH3-H V850ES/JH3-H Read this manual according to the CONTENTS. To find the details of a register where the name is known Use APPENDIX C REGISTER INDEX. Register format The name of the bit whose number is in angle brackets () in the figure of the register format of each register is defined as a reserved word in the device file. To understand the details of an instruction function Refer to the V850ES V850ES Architecture User's Manual available separately. To know the electrical specifications of the V850ES/JG3-H V850ES/JG3-H and V850ES/JH3-H V850ES/JH3-H Refer to the CHAPTER 33 ELECTRICAL SPECIFICATIONS. The "yyy bit of the xxx register" is described as the "xxx.yyy bit" in this manual. Note with caution that if "xxx.yyy" is described as is in a program, however, the compiler/assembler cannot recognize it correctly. The mark shows major revised points. The revised points can be easily searched by copying an "" in the PDF file and specifying it in the "Find what: " field. Conventions Data significance: Higher digits on the left and lower digits on the right Active low representation: xxx (overscore over pin or signal name) Memory map address: Higher addresses on the top and lower addresses on the Note: Footnote for item marked with Note in the text bottom Caution: Information requiring particular attention Remark: Supplementary information Numeric representation: Binary . xxxx or xxxxB Decimal . xxxx Hexadecimal . xxxxH Prefix indicating power of 2 (address space, memory capacity): K (kilo): 210 = 1,024 M (mega): 220 = 1,0242 G (giga): 230 = 1,0243 Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Documents related to V850ES/JG3-H V850ES/JG3-H and V850ES/JH3-H V850ES/JH3-H Document Name Document No. V850ES V850ES Architecture User's Manual U15943E U15943E V850ES/JG3-H V850ES/JG3-H, V850ES/JH3-H V850ES/JH3-H Hardware User's Manual This manual Documents related to development tools Document Name Document No. QB-V850ESJX3H QB-V850ESJX3H In-Circuit Emulator U19170J U19170J QB-V850MINI QB-V850MINI On-Chip Debug Emulator U17638E U17638E QB-MINI2 On-Chip Debug Emulator with Programming Function U18371E U18371E CA850 CA850 Ver. 3.20 C Compiler Package Operation U18512E U18512E C Language U18513E U18513E Assembly Language U18514E U18514E Link Directives U18515E U18515E PM+ Ver. 6.30 Project Manager U18416E U18416E ID850QB ID850QB Ver. 3.40 Integrated Debugger Operation U18604E U18604E SM850 SM850 Ver. 2.50 System Simulator Operation U16218E U16218E SM850 SM850 Ver. 2.00 or Later System Simulator External Part User Open U14873E U14873E Interface Specification SM+ System Simulator U18601E U18601E User Open Interface U18212E U18212E Basics U13430E U13430E Installation RX850 RX850 Ver. 3.20 Real-Time OS Operation U17419E U17419E Technical U17420E U17420E Basics U18165E U18165E Installation U17421E U17421E Task Debugger RX850 RX850 Pro Ver. 3.21 Real-Time OS U13431E U13431E Task Debugger U17422E U17422E AZ850 AZ850 Ver. 3.30 System Performance Analyzer U17423E U17423E PG-FP5 Flash Memory Programmer U18865E U18865E Caution: This product uses SuperFlash® technology licensed from Silicon Storage Technology, Inc. EEPROM is a trademark of Renesas Electronics Corporation. IECUBE is a registered trademark of Renesas Electronics Corporation in Japan and Germany. MINICUBE is a registered trademark of Renesas Electronics Corporation in Japan and Germany or a trademark in the United States of America. Windows and Windows NT are either registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries. SuperFlash is a registered trademark of Silicon Storage Technology, Inc. in several countries, including the United States and Japan. PC/AT is a trademark of International Business Machines Corporation. SPARCstation is a trademark of SPARC International, Inc. Solaris and SunOS are trademarks of Sun Microsystems, Inc. TRON is an abbreviation of The Real-Time Operating system Nucleus. ITRON is an abbreviation of Industrial TRON. Table of Contents CHAPTER 1 INTRODUCTION. 19 1.1 General . 19 1.2 Features . 22 1.3 Application Fields . 24 1.4 Ordering Information . 24 1.5 Pin Configuration (Top View). 25 1.6 Function Block Configuration. 28 1.6.1 Internal block diagram.28 1.6.2 Internal units .30 CHAPTER 2 PIN FUNCTIONS . 33 2.1 List of Pin Functions. 33 2.2 Pin States . 47 2.3 Pin I/O Circuit Types, I/O Buffer Power Supplies and Connection of Unused Pins. 48 2.4 Cautions . 53 CHAPTER 3 CPU FUNCTION . 54 3.1 Features . 54 3.2 CPU Register Set. 55 3.2.1 Program register set .56 3.2.2 System register set .57 3.3 Operation Modes . 63 3.3.1 Specifying operation mode.63 3.4 Address Space . 64 3.4.1 3.4.2 3.4.3 3.4.4 3.4.5 3.4.6 3.4.7 3.4.8 3.4.9 CPU address space .64 Wraparound of CPU address space .65 Memory map .66 Areas .68 Recommended use of address space.74 Peripheral I/O registers .77 Programmable peripheral I/O registers .91 Special registers .92 Cautions.96 CHAPTER 4 PORT FUNCTIONS . 100 4.1 Features . 100 4.2 Basic Port Configuration. 100 4.3 Port Configuration . 102 4.3.1 4.3.2 4.3.3 4.3.4 4.3.5 4.3.6 4.3.7 4.3.8 4.3.9 4.3.10 4.3.11 4.3.12 4.3.13 4.3.14 4.4 4.5 Port 0 .108 Port 1 .113 Port 2 (V850ES/JH3-H V850ES/JH3-H only) .114 Port 3 .118 Port 4 .123 Port 5 .126 Port 6 .133 Port 7 .137 Port 9 .139 Port CM.149 Port CS (V850ES/JH3-H V850ES/JH3-H only) .152 Port CT .154 Port DH (V850ES/JH3-H V850ES/JH3-H only) .157 Port DL.159 Port Register Settings When Alternate Function Is Used. 161 Cautions . 172 4.5.1 4.5.2 4.5.3 4.5.4 4.5.5 4.5.6 Cautions on setting port pins.172 Cautions on bit manipulation instruction for port n register (Pn).175 Cautions on on-chip debug pins (V850ES/JG3-H V850ES/JG3-H only) .176 Cautions on P56/INTP05/DRST P56/INTP05/DRST pin.176 Cautions on P10, P11, and P53 pins when power is turned on .176 Hysteresis characteristics .176 CHAPTER 5 BUS CONTROL FUNCTION . 177 5.1 Features . 177 5.2 Bus Control Pins . 178 5.2.1 Pin status when internal ROM, internal RAM, or on-chip peripheral I/O is accessed .179 5.2.2 Pin status in each operation mode.179 5.3 5.4 Memory Block Function . 180 Bus Access . 181 5.4.1 Number of clocks for access .181 5.4.2 Bus size setting function .181 5.4.3 Access by bus size .182 5.5 Wait Function. 189 5.5.1 5.5.2 5.5.3 5.5.4 5.6 5.7 Programmable wait function.189 External wait function.190 Relationship between programmable wait and external wait.191 Programmable address wait function .192 Idle State Insertion Function. 193 Bus Hold Function (V850ES/JH3-H V850ES/JH3-H only). 194 5.7.1 Functional outline.194 5.7.2 Bus hold procedure.195 5.7.3 Operation in power save mode .195 5.8 5.9 Bus Priority . 196 Bus Timing. 197 CHAPTER 6 CLOCK GENERATION FUNCTION . 200 6.1 Overview . 200 6.2 Configuration. 201 6.3 Registers . 203 6.4 Operation . 208 6.4.1 Operation of each clock .208 6.4.2 Clock output function .208 6.5 PLL Function . 209 6.5.1 Overview .209 6.5.2 Registers.209 6.5.3 Usage .212 CHAPTER 7 16-BIT 16-BIT TIMER/EVENT COUNTER AA (TAA). 213 7.1 Overview . 213 7.2 Functions . 213 7.3 Configuration. 214 7.3.1 Pin configuration .216 7.4 7.5 Registers . 217 Operation . 234 7.5.1 7.5.2 7.5.3 7.5.4 7.5.5 7.5.6 7.5.7 Interval timer mode (TAAmMD2 to TAAmMD0 bits = 000) .240 External event count mode (TAAnMD2 to TAAnMD0 bits = 001).250 External trigger pulse output mode (TAAnMD2 to TAAnMD0 bits = 010) .258 One-shot pulse output mode (TAAnMD2 to TAAnMD0 bits = 011) .270 PWM output mode (TAAnMD2 to TAAnMD0 bits = 100) .277 Free-running timer mode (TAAnMD2 to TAAnMD0 bits = 101).286 Pulse width measurement mode (TAAnMD2 to TAAnMD0 bits = 110) .303 7.5.8 Timer output operations .308 7.6 Timer-Tuned Operation Function . 309 7.6.1 Free-running timer mode (during timer-tuned operation) .311 7.6.2 PWM output mode (during timer-tuned operation) .318 7.7 Simultaneous-Start Function . 320 7.7.1 PWM output mode (simultaneous-start operation) .321 7.8 Cascade Connection. 323 7.9 Selector Function . 328 7.10 Cautions . 329 CHAPTER 8 16-BIT 16-BIT TIMER/EVENT COUNTER AB (TAB). 330 8.1 Overview . 330 8.2 Functions . 330 8.3 Configuration. 331 8.4 Registers . 334 8.5 Operation . 351 8.5.1 8.5.2 8.5.3 8.5.4 8.5.5 8.5.6 8.5.7 8.5.8 8.5.9 8.6 8.7 Interval timer mode (TABnMD2 to TABnMD0 bits = 000) .352 External event count mode (TABnMD2 to TABnMD0 bits = 001).361 External trigger pulse output mode (TABnMD2 to TABnMD0 bits = 010) .370 One-shot pulse output mode (TABnMD2 to TABnMD0 bits = 011) .383 PWM output mode (TABnMD2 to TABnMD0 bits = 100) .392 Free-running timer mode (TABnMD2 to TABnMD0 bits = 101).403 Pulse width measurement mode (TABnMD2 to TABnMD0 bits = 110) .423 Triangular wave PWM mode (TABnMD2 to TABnMD0 bits = 111) .429 Timer output operations .431 Timer-Tuned Operation Function/Simultaneous-Start Function . 432 Cautions . 433 CHAPTER 9 16-BIT 16-BIT TIMER/EVENT COUNTER T (TMT) . 434 9.1 Overview . 434 9.2 Functions . 434 9.3 Configuration. 435 9.3.1 Pin configuration .438 9.4 9.5 9.6 Registers . 439 Timer Output Operations. 460 Operation . 461 9.6.1 9.6.2 9.6.3 9.6.4 9.6.5 9.6.6 9.6.7 9.6.8 9.6.9 9.6.10 Interval timer mode (TT0MD3 to TT0MD0 bits = 0000).469 External event count mode (TT0MD3 to TT0MD0 bits = 0001).479 External trigger pulse output mode (TT0MD3 to TT0MD0 bits = 0010).489 One-shot pulse output mode (TT0MD3 to TT0MD0 bits = 0011) .502 PWM output mode (TT0MD3 to TT0MD0 bits = 0100).509 Free-running timer mode (TT0MD3 to TT0MD0 bits = 0101) .518 Pulse width measurement mode (TT0MD3 to TT0MD0 bits = 0110) .534 Triangular-wave PWM output mode (TT0MD3 to TT0MD0 bits = 0111) .540 Encoder count function .542 Encoder compare mode (TT0MD3 to TT0MD0 bits = 1000) .558 CHAPTER 10 16-BIT 16-BIT INTERVAL TIMER M (TMM) . 566 10.1 Overview . 566 10.2 Configuration. 567 10.3 Registers . 569 10.4 Operation . 571 10.4.1 Interval timer mode .571 10.4.2 Cautions.575 CHAPTER 11 MOTOR CONTROL FUNCTION . 576 11.1 Functional Overview . 576 11.2 Configuration. 577 11.3 Control Registers . 581 11.4 Operation . 591 11.4.1 11.4.2 11.4.3 11.4.4 11.4.5 11.4.6 System outline .591 Dead-time control (generation of negative-phase wave signal).596 Interrupt culling function .603 Operation to rewrite register with transfer function.610 TAA4 tuning operation for A/D conversion start trigger signal output.628 A/D conversion start trigger output function .631 CHAPTER 12 REAL-TIME COUNTER. 636 12.1 Functions . 636 12.2 Configuration. 637 12.2.1 Pin configuration .639 12.2.2 Interrupt functions .639 12.3 Registers . 640 12.4 Operation . 655 12.4.1 12.4.2 12.4.3 12.4.4 12.4.5 12.4.6 12.4.7 12.4.8 12.4.9 Initial settings .655 Rewriting each counter during the real-time counter operation .656 Reading each counter during the real-time counter operation.657 Changing INTRTC0 interrupt setting during the real-time counter operation .658 Changing INTRTC1 interrupt setting during the real-time counter operation .659 Initial INTRTC2 interrupt settings .660 Changing INTRTC2 interrupt setting during the real-time counter operation .661 Initializing real-time counter .662 Watch error correction example of real-time counter .663 CHAPTER 13 FUNCTIONS OF WATCHDOG TIMER 2 . 667 13.1 Functions . 667 13.2 Configuration. 668 13.3 Registers . 669 13.4 Operation . 671 CHAPTER 14 REAL-TIME OUTPUT FUNCTION (RTO). 672 14.1 Function . 672 14.2 Configuration. 673 14.3 Registers . 675 14.4 Operation . 677 14.5 Usage. 678 14.6 Cautions . 678 CHAPTER 15 A/D CONVERTER . 679 15.1 Overview . 679 15.2 Functions . 679 15.3 Configuration. 680 15.4 Registers . 683 15.5 Operation . 694 15.5.1 15.5.2 15.5.3 15.5.4 15.5.5 Basic operation .694 Conversion operation timing .695 Trigger mode.696 Operation mode .698 Power-fail compare mode .702 15.6 Cautions . 707 15.7 How to Read A/D Converter Characteristics Table . 711 CHAPTER 16 D/A CONVERTER . 715 16.1 Functions . 715 16.2 Configuration. 715 16.3 Registers . 716 16.4 Operation . 718 16.4.1 Operation in normal mode.718 16.4.2 Operation in real-time output mode.718 16.4.3 Cautions.719 CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC) . 720 17.1 Features . 720 17.2 Configuration. 721 17.3 Mode Switching Between UARTC and Other Serial Interfaces . 723 17.3.1 17.3.2 17.3.3 17.3.4 17.3.5 Mode switching between UARTC0 and CSIF4 .723 Mode switching between UARTC1 and I2C02 I2C02 .724 Mode switching between UARTC2 and CSIF3 .725 Mode switching between UARTC3, I2C00 I2C00 and CAN0.726 Mode switching between UARTC4, CSIF0, and I2C01 I2C01 .727 17.4 Registers . 728 17.5 Interrupt Request Signals . 738 17.6 Operation . 739 17.6.1 Data format .739 17.6.2 SBF transmission/reception format .741 17.6.3 SBF transmission.743 17.6.4 SBF reception .744 17.6.5 UART transmission .745 17.6.6 Continuous transmission procedure.746 17.6.7 UART reception .748 17.6.8 Reception errors .749 17.6.9 Parity types and operations.751 17.6.10 Receive data noise filter .752 17.7 Dedicated Baud Rate Generator. 753 17.8 Cautions . 761 CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF) . 762 18.1 Mode Switching of CSIF and Other Serial Interfaces . 762 18.1.1 CSIF4 and UARTC0 mode switching .762 18.1.2 CSIF0, UARTC4, and I2C01 I2C01 mode switching .763 18.1.3 CSIF3 and UARTC2 mode switching .764 18.2 18.3 18.4 18.5 18.6 Features . 765 Configuration. 766 Registers . 769 Interrupt Request Signals . 776 Operation . 777 18.6.1 Single transfer mode (master mode, transmission mode).777 18.6.2 Single transfer mode (master mode, reception mode) .779 18.6.3 Single transfer mode (master mode, transmission/reception mode) .781 18.6.4 Single transfer mode (slave mode, transmission mode) .783 18.6.5 Single transfer mode (slave mode, reception mode).785 18.6.6 Single transfer mode (slave mode, transmission/reception mode).787 18.6.7 Continuous transfer mode (master mode, transmission mode).789 18.6.8 Continuous transfer mode (master mode, reception mode) .791 18.6.9 Continuous transfer mode (master mode, transmission/reception mode) .794 18.6.10 Continuous transfer mode (slave mode, transmission mode) .798 18.6.11 Continuous transfer mode (slave mode, reception mode).800 18.6.12 Continuous transfer mode (slave mode, transmission/reception mode).803 18.6.13 Reception error .807 18.6.14 Clock timing.808 18.7 Output Pins . 810 18.8 Baud Rate Generator . 811 18.8.1 Baud rate generation .812 18.9 Cautions . 813 CHAPTER 19 I2C BUS . 814 19.1 Mode Switching of I2C Bus and Other Serial Interfaces. 814 19.1.1 UARTC3 and I2C00 I2C00 mode switching .814 19.1.2 UARTC4, CSIF0, and I2C01 I2C01 mode switching .815 19.1.3 UARTC1 and I2C02 I2C02 mode switching .816 19.2 19.3 19.4 19.5 Features . 817 Configuration. 818 Registers . 822 I2C Bus Mode Functions . 837 19.5.1 Pin configuration .837 19.6 I2C Bus Definitions and Control Methods . 838 19.6.1 19.6.2 19.6.3 19.6.4 19.6.5 19.6.6 19.6.7 Start condition .838 Addresses .839 Transfer direction specification .840 ACK .841 Stop condition .842 Wait state.843 Wait state cancellation method .845 19.7 I2C Interrupt Request Signals (INTIICn). 846 19.7.1 19.7.2 19.7.3 19.7.4 19.7.5 19.7.6 Master device operation.846 Slave device operation (when receiving slave address data (address match) .849 Slave device operation (when receiving extension code).853 Operation without communication.857 Arbitration loss operation (operation as slave after arbitration loss).857 Operation when arbitration loss occurs (no communication after arbitration loss) .859 19.8 Interrupt Request Signal (INTIICn) Generation Timing and Wait Control . 866 19.9 Address Match Detection Method . 868 19.10 Error Detection . 868 19.11 Extension Code . 868 19.12 Arbitration . 869 19.13 Wakeup Function . 870 19.14 Communication Reservation . 871 19.14.1 19.14.2 When communication reservation function is enabled (IICFn.IICRSVn bit = 0).871 When communication reservation function is disabled (IICFn.IICRSVn bit = 1) .875 19.15 Cautions . 876 19.16 Communication Operations . 877 19.16.1 19.16.2 19.16.3 Master operation in single master system .878 Master operation in multimaster system.879 Slave operation .882 19.17 Timing of Data Communication . 885 CHAPTER 20 CAN CONTROLLER . 892 20.1 Overview . 892 20.1.1 Features.892 20.1.2 Overview of functions.893 20.1.3 Configuration.894 20.2 CAN Protocol . 895 20.2.1 20.2.2 20.2.3 20.2.4 20.2.5 Frame format .895 Frame types .896 Data frame and remote frame .896 Error frame.904 Overload frame .905 20.3 Functions . 906 20.3.1 20.3.2 20.3.3 20.3.4 Determining bus priority .906 Bit stuffing .906 Multi masters.906 Multi cast.906 20.3.5 CAN sleep mode/CAN stop mode function .907 20.3.6 Error control function.907 20.3.7 Baud rate control function .914 20.4 Connection with Target System . 918 20.5 Internal Registers of CAN Controller . 919 20.5.1 CAN controller configuration .919 20.5.2 Register access type.920 20.5.3 Register bit configuration .937 20.6 Registers . 941 20.7 Bit Set/Clear Function. 977 20.8 CAN Controller Initialization . 979 20.8.1 20.8.2 20.8.3 20.8.4 20.8.5 Initialization of CAN module .979 Initialization of message buffer.979 Redefinition of message buffer .979 Transition from initialization mode to operation mode .980 Resetting error counter C0ERC of CAN module .981 20.9 Message Reception. 982 20.9.1 20.9.2 20.9.3 20.9.4 20.9.5 20.9.6 Message reception.982 Reading reception data .983 Receive history list function.984 Mask function.986 Multi buffer receive block function.988 Remote frame reception.989 20.10 Message Transmission. 990 20.10.1 20.10.2 20.10.3 20.10.4 20.10.5 Message transmission.990 Transmit history list function.992 Automatic block transmission (ABT) .994 Transmission abort process .996 Remote frame transmission .997 20.11 Power Saving Modes . 998 20.11.1 20.11.2 20.11.3 CAN sleep mode .998 CAN stop mode.1000 Example of using power saving modes .1001 20.12 Interrupt Function . 1002 20.13 Diagnosis Functions and Special Operational Modes . 1003 20.13.1 20.13.2 20.13.3 20.13.4 Receive-only mode .1003 Single-shot mode .1004 Self-test mode .1005 Transmission/reception operation in each operation mode .1006 20.14 Time Stamp Function. 1007 20.14.1 Time stamp function.1007 20.15 Baud Rate Settings . 1009 20.15.1 20.15.2 Bit rate setting conditions .1009 Representative examples of baud rate settings .1013 20.16 Operation of CAN Controller. 1017 CHAPTER 21 USB FUNCTION CONTROLLER (USBF) . 1043 21.1 Overview . 1043 21.2 Configuration. 1044 21.2.1 Block diagram .1044 21.2.2 USB memory map.1045 21.3 External Circuit Configuration . 1046 21.3.1 Outline .1046 21.3.2 Connection configuration .1047 21.4 Cautions . 1049 21.5 Requests . 1050 21.5.1 Automatic requests .1050 21.5.2 Other requests .1057 21.6 Register Configuration . 1058 21.6.1 USB control registers .1058 21.6.2 USB function controller register list .1060 21.6.3 EPC control registers .1076 21.6.4 Data hold registers.1128 21.6.5 EPC request data registers .1151 21.6.6 Bridge register.1166 21.6.7 DMA register .1170 21.6.8 Bulk-in register .1174 21.6.9 Bulk-out register.1175 21.6.10 Peripheral control registers .1177 21.7 STALL Handshake or No Handshake. 1181 21.8 Register Values in Specific Status . 1182 21.9 FW Processing . 1184 21.9.1 21.9.2 21.9.3 21.9.4 21.9.5 21.9.6 21.9.7 Initialization processing .1186 Interrupt servicing .1189 USB main processing .1190 Suspend/Resume processing .1216 Processing after power application .1219 Receiving data for bulk transfer (OUT) in DMA mode .1222 Transmitting data for bulk transfer (IN) in DMA mode.1227 CHAPTER 22 DMA FUNCTION (DMA CONTROLLER) . 1232 22.1 Features . 1232 22.2 Configuration. 1233 22.3 Registers . 1234 22.4 Transfer Targets. 1243 22.5 Transfer Modes . 1243 22.6 Transfer Types . 1244 22.7 DMA Channel Priorities . 1245 22.8 Time Related to DMA Transfer. 1245 22.9 DMA Transfer Start Factors . 1246 22.10 DMA Abort Factors . 1247 22.11 End of DMA Transfer . 1247 22.12 Operation Timing. 1247 22.13 Cautions . 1251 CHAPTER 23 INTERRUPT/EXCEPTION PROCESSING FUNCTION. 1256 23.1 Features . 1256 23.2 Non-Maskable Interrupts . 1267 23.2.1 Operation .1269 23.2.2 Restore .1270 23.2.3 NP flag .1271 23.3 Maskable Interrupts . 1272 23.3.1 23.3.2 23.3.3 23.3.4 23.3.5 23.3.6 23.3.7 23.3.8 Operation .1272 Restore .1274 Priorities of maskable interrupts.1275 Interrupt control register (xxICn) .1279 Interrupt mask registers 0 to 5 (IMR0 to IMR5) .1283 In-service priority register (ISPR) .1285 ID flag .1286 Watchdog timer mode register 2 (WDTM2).1286 23.4 Software Exception. 1287 23.4.1 Operation .1287 23.4.2 Restore .1288 23.4.3 EP flag .1289 23.5 Exception Trap . 1290 23.5.1 Illegal opcode.1290 23.5.2 Debug trap .1292 23.6 External Interrupt Request Input Pins (NMI and INTP00 INTP00 to INTP18 INTP18). 1294 23.6.1 Noise elimination.1294 23.6.2 Edge detection .1294 23.7 Interrupt Acknowledge Time of CPU. 1302 23.8 Periods in Which Interrupts Are Not Acknowledged by CPU . 1303 23.9 Cautions . 1303 CHAPTER 24 KEY INTERRUPT FUNCTION . 1304 24.1 Function . 1304 24.2 Register . 1305 24.3 Cautions . 1305 CHAPTER 25 STANDBY FUNCTION . 1306 25.1 Overview . 1306 25.2 Registers . 1308 25.3 HALT Mode . 1311 25.3.1 Setting and operation status .1311 25.3.2 Releasing HALT mode .1311 25.4 IDLE1 Mode. 1313 25.4.1 Setting and operation status .1313 25.4.2 Releasing IDLE1 mode .1314 25.5 IDLE2 Mode. 1316 25.5.1 Setting and operation status .1316 25.5.2 Releasing IDLE2 mode .1317 25.5.3 Securing setup time when releasing IDLE2 mode.1319 25.6 STOP Mode . 1320 25.6.1 Setting and operation status .1320 25.6.2 Releasing STOP mode .1320 25.6.3 Securing oscillation stabilization time when releasing STOP mode .1323 25.7 Subclock Operation Mode. 1324 25.7.1 Setting and operation status .1324 25.7.2 Releasing subclock operation mode .1324 25.8 Sub-IDLE Mode. 1326 25.8.1 Setting and operation status .1326 25.8.2 Releasing sub-IDLE mode .1326 CHAPTER 26 RESET FUNCTIONS . 1328 26.1 Overview . 1328 26.2 Registers to Check Reset Source . 1329 26.3 Operation . 1330 26.3.1 26.3.2 26.3.3 26.3.4 26.3.5 Reset operation via RESET pin .1330 Reset operation by watchdog timer 2.1332 Reset operation by low-voltage detector .1334 Operation after reset release .1335 Reset function operation flow.1336 CHAPTER 27 CLOCK MONITOR . 1337 27.1 Functions . 1337 27.2 Configuration. 1337 27.3 Register . 1338 27.4 Operation . 1339 CHAPTER 28 LOW-VOLTAGE DETECTOR (LVI) . 1342 28.1 Functions . 1342 28.2 Configuration. 1342 28.3 Registers . 1343 28.4 Operation . 1345 28.4.1 To use for internal reset signal.1345 28.4.2 To use for interrupt.1346 28.5 RAM Retention Voltage Detection Operation. 1346 CHAPTER 29 CRC FUNCTION. 1348 29.1 Functions . 1348 29.2 Configuration. 1348 29.3 Registers . 1349 29.4 Operation . 1350 29.5 Usage Method. 1351 CHAPTER 30 REGULATOR . 1353 30.1 Overview . 1353 30.2 Operation . 1354 CHAPTER 31 FLASH MEMORY . 1355 31.1 Features . 1355 31.2 Memory Configuration. 1356 31.3 Functional Overview . 1357 31.4 Rewriting by Dedicated Flash Programmer . 1360 31.4.1 31.4.2 31.4.3 31.4.4 31.4.5 31.4.6 Programming environment.1360 Communication mode .1361 Flash memory control .1375 Selection of communication mode .1376 Communication commands.1377 Pin connection .1378 31.5 Rewriting by Self Programming. 1382 31.5.1 31.5.2 31.5.3 31.5.4 31.5.5 31.5.6 Overview .1382 Features.1383 Standard self programming flow .1384 Flash functions.1385 Pin processing .1385 Internal resources used.1386 31.6 Creating ROM code to place order for previously written product . 1387 31.6.1 Procedure for using ROM code to place an order .1387 CHAPTER 32 ON-CHIP DEBUG FUNCTION . 1388 32.1 Debugging with DCU . 1389 32.1.1 32.1.2 32.1.3 32.1.4 32.1.5 32.1.6 Connection circuit example .1389 Interface signals .1389 Maskable functions.1391 Register.1391 Operation .1393 Cautions .1393 32.2 Debugging Without Using DCU . 1394 32.2.1 32.2.2 32.2.3 32.2.4 Circuit connection examples.1394 Maskable functions.1397 Securement of user resources .1398 Cautions .1405 32.3 ROM Security Function. 1406 32.3.1 Security ID.1406 32.3.2 Setting .1407 CHAPTER 33 ELECTRICAL SPECIFICATIONS . 1409 33.1 Absolute Maximum Ratings . 1409 33.2 Capacitance . 1411 33.3 Operating Conditions . 1411 33.4 Oscillator Characteristics. 1412 33.4.1 Main clock oscillator characteristics .1412 33.4.2 Subclock oscillator characteristics .1414 33.4.3 PLL characteristics.1416 33.4.4 Internal oscillator characteristics .1416 33.5 DC Characteristics . 1417 33.5.1 I/O level.1417 33.5.2 Supply current.1419 33.6 Data Retention Characteristics. 1420 33.7 AC Characteristics . 1421 33.7.1 CLKOUT output timing.1422 33.7.2 Bus timing .1423 33.8 Basic Operation. 1430 33.9 Flash Memory Programming Characteristics . 1443 CHAPTER 34 PACKAGE DRAWINGS . 1445 CHAPTER 35 RECOMMENDED SOLDERING CONDITIONS. 1447 APPENDIX A DEVELOPMENT TOOLS. 1449 A.1 Software Package . 1451 A.2 Language Processing Software . 1451 A.3 Control Software . 1451 A.4 Debugging Tools (Hardware) . 1452 A.4.1 When using IECUBE QB-V850ESJX3H QB-V850ESJX3H.1452 A.4.2 When using MINICUBE QB-V850MINI QB-V850MINI .1455 A.4.3 When using MINICUBE2 QB-MINI2.1456 A.5 Debugging Tools (Software) . 1456 A.6 Embedded Software. 1457 A.7 Flash Memory Writing Tools . 1457 APPENDIX B MAJOR DIFFERENCES BETWEEN V850ES/Jx3-H AND V850ES/Jx3 . 1458 APPENDIX C REGISTER INDEX . 1459 APPENDIX D INSTRUCTION SET LIST . 1496 D.1 Conventions. 1496 D.2 Instruction Set (in Alphabetical Order) . 1499 APPENDIX E REVISION HISTORY. 1506 E.1 Major Revisions in This Edition. 1506 E.2 Revision History of Preceding Editions. 1507 R01UH0042EJ0400 R01UH0042EJ0400 Rev.4.00 Sep 30, 2010 V850ES/JG3-H V850ES/JG3-H, V850ES/JH3-H V850ES/JH3-H RENESAS MCU CHAPTER 1 INTRODUCTION The V850ES/JG3-H V850ES/JG3-H and V850ES/JH3-H V850ES/JH3-H are products in the low-power series of Renesas Electronics' V850 single-chip microcontrollers designed for real-time control applications. 1.1 General The V850ES/JG3-H V850ES/JG3-H and V850ES/JH3-H V850ES/JH3-H are 32-bit single-chip microcontrollers that use the V850ES V850ES CPU core and incorporate peripheral functions such as ROM/RAM, a timer/counter, serial interfaces, an A/D converter, a D/A converter, a DMA controller, CAN, and a USB function controller. In addition to high real-time response characteristics and 1-clock-pitch basic instructions, the V850ES/JG3-H V850ES/JG3-H and V850ES/JH3-H V850ES/JH3-H feature multiply instructions realized by a hardware multiplier, saturated operation instructions, and bit manipulation instructions. Table 1-1 lists the products of the V850ES/JG3-H V850ES/JG3-H, and Table 1-2 lists the products of the V850ES/JH3-H V850ES/JH3-H. R01UH0042EJ0400 R01UH0042EJ0400 Rev.4.00 Sep 30, 2010 Page 19 of 1509 V850ES/JG3-H V850ES/JG3-H, V850ES/JH3-H V850ES/JH3-H CHAPTER 1 INTRODUCTION Table 1-1. V850ES/JG3-H V850ES/JG3-H Product List Generic Name V850ES/JG3-H V850ES/JG3-H PD70F3760 PD70F3760 PD70F3761 PD70F3761 PD70F3762 PD70F3762 PD70F3770 PD70F3770 256 KB 384 KB 512 KB 256 KB 40 KB Part Number 48 KB 56 KB 40 KB Internal memory Flash memory Memory space Logical space 64 MB External memory area 64 KB RAM Note 1 External bus interface Address data bus: 16 Multiplexed bus General-purpose register 32 bits × 32 registers Clock (PLL mode: fX = 3 to 6 MHz, fXX = 24 to 48 MHz (multiplied by 8) Clock through mode: fX = 3 to 6 MHz (internal: fXX = 3 to 6 MHz) Main clock Subclock fXT = 32.768 kHz Internal oscillator fR = 220 kHz (TYP.) Minimum instruction e