V23814-K1306-M230 V23815-K1306-M230 V23814/15-K1306-M230 V23814-S1306-M931 - Datasheet Archive

 

Parallel Optical Link: PAROLI® Tx DC/MUX-ENC V23815-K1306-M230 Parallel Optical Link: PAROLI® Rx DC/DEMUX-DEC

 

V23814-K1306-M230 V23814-K1306-M230 Parallel Optical Link: PAROLI® Tx DC/MUX-ENC V23815-K1306-M230 V23815-K1306-M230 Parallel Optical Link: PAROLI® Rx DC/DEMUX-DEC APPLICATIONS Telecommunication · Switching equipment · Access network Data Communication · Interframe (rack-to-rack) · Intraframe (board-to-board) · On board (optical backplane) Absolute Maximum Ratings FEATURES · Power supply (3.3 V) · Low voltage differential signal electrical interface (LVDS) · 22 electrical data + 1 clock channels · Low skew, bit parallel transmission · Interface to SCI and HIPPI 6400 standard · 12 optical data channels · Electrical transmission data rate of 150-500 Mbit/s per channel, total link data rate up to 11 Gbit/s · Two clocking modes can be selected (SCI/Strobe) · Transmission distance up to 75 m at maximum data rate · 850 nm VCSEL array technology · PIN diode array technology · 62.5 µm graded index multimode fiber ribbon · MT based optical port · SMD technology · Class 1 FDA and Class 3A IEC laser safety compliant · FC open fiber control (OFC) interface supported (to configure a Class 1 IEC laser safety compliant system) Stress beyond the values stated below may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods of time may affect device reliability. Supply Voltage (VCC­VEE). ­0.3 V to 4.5 V Data/Control Input Levels (VIN)(1) . ­0.5 V to VCC+0.5 V LVDS Input Differential Voltage (|VID|)(2) . 2.0 V Operating Case Temperature (TCASE)(3) . 0°C to 80°C Storage Ambient Temperature (TSTG). ­20°C to 100°C Operating Moisture . 20% to 85% Storage Moisture. 20% to 85% Soldering Conditions Temp/Time (TSOLD, tSOLD)(4) .260°C/10s ESD Resistance (all pins to VEE human body model)(5) . 1 kV Notes 1. At LVDS and LVCMOS inputs. 2. |VID|=|(input voltage of non-inverted input minus input voltage of inverted input)|. 3. Measured at case temperature reference point (see dimensional drawing, Figure 13 on page 12). 4. Hot bar or hot air soldering. 5. To avoid electrostatic damage, handling cautions similar to those used for MOS devices must be observed. PAROLI® is a registered trademark of Infineon Technologies AG Fiber Optics MAY 2000 DESCRIPTION strobed. Inputs 1 to 11 are routed before inputs 12 to 22. 4B words are then fed through eleven separate 4B/5B encoders to form the signals to be transmitted over the optical interface. Coding is based on the running disparity of previously transmitted output data. With a running disparity 0, either more High than Low levels or an equal number of Highs and Lows have been transmitted. The next output nibble will be inverted if High levels again dominate; otherwise it will be sent without inversion. With a running disparity 10 MHz. Voltage is peak-to-peak value. 3. Level diagram Figure 3. Input level diagram mV 1900 |VID| 500 Time 4. |VID|=|(input voltage of non-inverted input minus input voltage of inverted input)|. 5. 20% - 80% level. 6. Measured between 0.8 V and 2.0 V. 7 Lower limit of clock frequency due to PLL frequency limitations. . 8. Measured at 50% level. 9. The unit interval UI refers to a strobe cycle in this case. 1 UI = 1/fCLOCK in Strobe Mode and 1 UI = 1/(2 · fCLOCK) in SCI Mode Fiber Optics V23814/15-K1306-M230 V23814/15-K1306-M230 Parallel Optical Link: PAROLI® Tx/Rx DC 3 Transmitter Electro-Optical Characteristics Parameter Symbol Min. Typ. Max. Units Parameter Symbol Time(1) Min. Max. Units 400 ps UI Supply Current lCC 1100 1300 mA Optical Rise Power Consumption P 3.6 Optical Fall Time(1) tF Random Jitter (14)(2) DRSCI JR 0.26 Data Rate in SCI Mode(1) Deterministic Jitter JD 0.17 Data Rate in Strobe Mode(1) DRSTR Launched Average Power PAVG LVDS Differential Input Impedance(2) RIN Launched Power Shutdown PSD LVCMOS Output Voltage Low VLVCMOSOL Center Wavelength C Spectral Width (FWHM) 2.0 LVCMOS Output Voltage High VLVCMOSOH 2.5 LVCMOS Input Current High/Low ILVCMOSI LVCMOS Output Current High(3) W 500 150 4.7 Mbit/s 120 0.4 80 V tR ­11 ­6.0 ­30 820 860 Spectral Width (rms) 500 ILVCMOSOH 0.5 mA LVCMOS Output Current Low(4) ILVCMOSOL 4.0 LVDS Differential Input Current |II| 5.0 ­116 ER nm 0.85 RIN Extinction Ratio (dynamic) µA Relative Intensity Noise ­500 dBm 5.0 dB/Hz dB Notes Optical parameters valid for each channel. 1. 20%­80% level, measured using a GBE (Gigabit Ethernet) filter. 2. Measured with 01010. (square) optical output pattern and in module thermal steady state status. Without cooling this steady state status is reached after approximately 10 minutes. Notes Figure 5. Timing diagrams 1. Data rate on electrical channel. Number of consecutive high or low bits is unlimited. Strobe Mode 2. P Figure 4. LVDS Input stage Clock Out N VCC 14 k Data In P Rin/2 Rin/2 |VID| min. Data In 1.22 t1 1.2 V ± 0.2 V t2 C Parameter 8 k Symbol Min. Input Setup Time(1) Data In N t1 250 Input Hold 3. Source current Time(1) Typ. Max. Units ps t2 Note 4. Sink current 1. Refers to positive clock input signal. See Measurement Conventions (Figure 6). Fiber Optics V23814/15-K1306-M230 V23814/15-K1306-M230 Parallel Optical Link: PAROLI® Tx/Rx DC 4 SCI Mode Figure 7. Numbering conventions transmitter P Clock Out N |VID| min. Data Out 1.22 tS tS Parameter Symbol Min. Typ. Max. The numbering conventions for the Tx and Rx modules are the same. Units Input Skew(1) tS § ps §. Maximum Input Skew=(2*Data Rate)­1 ­ 250 ps ­ DCDIN-CLOCK where DCDIN-CLOCK=|(Data Rate)­1­dcd*(1/2 Data Rate)­1|(dcd: see Recommended Operating Conditions). Transmitter Pin Description Pin# Pin Name 1 VCC1 Power supply voltage of laser driver 1. See Measurement Conventions (Figure 6). 2 t.b.l.o. to be left open Reset Timing Diagram 3 Note Level/Logic Description 4 3.6 V 3.0 V 5 VCC 6 LCU LVCMOS Out 7 VEE Ground 8 VEE Ground 9 VCC3 Power supply voltage of digital circuitry and PLL 10 MU LVCMOS Out Module Up High=normal operation Low=laser fault or PLL not locked or -RESET low 11 CIN LVDS In Clock Input, inverted 2.0 V 0.8 V -RESET t3 data valid data invalid Data t2 t1 Parameter -RESET On Delay Symbol Min. Typ. Max. Units Time(1) t1 -RESET Off Delay Time t2 -RESET Low Duration(2) t3 100 50 ms µs 100 µs Laser Controller Up High=laser controller is operational Low=laser fault condition if -RESET is High and VCC is > 3.0 V 12 CIP LVDS In Clock Input, non-inverted 1. Valid after the release of -RESET. (Clock input must first be stable. Keep -RESET low until clock input is at stable frequency.) 13 DI01N DI01N LVDS In Data Input #1, inverted 14 DI01P DI01P LVDS In Data Input #1, non-inverted 2. Only when not used as power-on reset (see start-up procedure for power-on reset). At any failure recovery, -RESET should be brought to low level for at least t3. 15 DI12N DI12N LVDS In Data Input #12, inverted Notes 16 Figure 6. Measurement conventions for LVDS signals DI12P DI12P LVDS In Data Input #12, non-inverted 17 DI02N DI02N LVDS In Data Input #2, inverted 18 DI02P DI02P LVDS In Data Input #2, non-inverted Setup and Hold Times 19 DI13N DI13N LVDS In Data Input #13, inverted P 20 DI13P DI13P LVDS In Data Input #13, non-inverted N 21 DI03N DI03N LVDS In Data Input #3, inverted 22 DI03P DI03P LVDS In Data Input #3, non-inverted 23 DI14N DI14N LVDS In Data Input #14, inverted 24 DI14P DI14P LVDS In 25 VCC3 26 DI04N DI04N LVDS In 27 DI04P DI04P LVDS In 28 VEE Clock |VID| min. Data tSETUP tHOLD Setup and hold times are measured between the cross point of positive and negative clock and the points where rising and falling data edge cross the borders of the V-range. Data Input #14, non-inverted Power supply voltage of digital circuitry and PLL Data Input #4, inverted Data Input #4, non-inverted Ground 29 Fiber Optics DI15N DI15N LVDS In Data Input #15, inverted 30 DI15P DI15P LVDS In Data Input #15, non-inverted V23814/15-K1306-M230 V23814/15-K1306-M230 Parallel Optical Link: PAROLI® Tx/Rx DC 5 Pin# Pin Name Level/Logic Description Pin# Pin Name Level/Logic Description 31 32 DI05N DI05N LVDS In Data Input #5, inverted 67 LE LVCMOS In DI05P DI05P LVDS In Data Input #5, non-inverted 33 DI16N DI16N LVDS In Data Input #16, inverted 34 DI16P DI16P LVDS In Data Input #16, non-inverted 35 DI06N DI06N LVDS In Data Input #6, inverted 36 DI06P DI06P LVDS In Data Input #6, non-inverted 37 DI17N DI17N LVDS In Data Input #17, inverted Laser ENABLE. High=laser array is on if -LE is also active. Low=laser array is off. This input can be used for connection with an Open Fiber Control (OFC) circuit to configure an IEC class 1 link. This input has an internal pull-up, therefore can be left open. 38 DI17P DI17P LVDS In Data Input #17, non-inverted 68 -LE 39 DI07N DI07N LVDS In Data Input #7, inverted LVCMOS In low active 40 DI07P DI07P LVDS In Data Input #7, non-inverted 41 DI18N DI18N LVDS In Data Input #18, inverted 42 DI18P DI18P LVDS In Data Input #18, non-inverted 43 DI08N DI08N LVDS In Data Input #8, inverted 44 DI08P DI08P LVDS In Data Input #8, non-inverted Laser ENABLE. Low=laser array is on if LE is also active. This input can be used for connection with an Open Fiber Control (OFC) circuit to configure an IEC class 1 link. This input has an internal pull-down, therefore can be left open. 45 VEE 69 t.b.l.o. to be left open 46 DI19N DI19N LVDS In Data Input #19, inverted 70 t.b.l.o. to be left open 47 DI19P DI19P LVDS In Data Input #19, non-inverted 71 t.b.l.o. to be left open 48 VCC3 72 VCC1 Power supply voltage of laser driver 49 DI09N DI09N LVDS In 50 DI09P DI09P LVDS In Data Input #9, non-inverted 51 DI20N DI20N LVDS In Data Input #20, inverted Ground Power supply voltage of digital circuitry and PLL Data Input #9, inverted 52 DI20P DI20P LVDS In Data Input #20, non-inverted 53 DI10N DI10N LVDS In Data Input #10, inverted 54 DI10P DI10P LVDS In Data Input #10, non-inverted 55 DI21N DI21N LVDS In Data Input #21, inverted 56 DI21P DI21P LVDS In Data Input #21, non-inverted 57 DI11N DI11N LVDS In Data Input #11, inverted 58 DI11P DI11P LVDS In Data Input #11, non-inverted 59 DI22N DI22N LVDS In Data Input #22, inverted 60 DI22P DI22P LVDS In Data Input #22, non-inverted 61 CLK-SEL LVCMOS In Input Clocking Mode Select High=strobe mode Low=SCI mode This input has an internal pullup resistor. When left open, strobe mode is active. 62 t.b.l.o. to be left open 63 VCC3 Power supply voltage of digital circuitry and PLL 64 -RESET 65 VEE Ground 66 VEE Ground LVCMOS In low active High=normal operation Low=resets module, shuts laser diode array down This input has an internal pulldown resistor to ensure laser safety switch-off in case of unconnected -RESET input. Fiber Optics V23814/15-K1306-M230 V23814/15-K1306-M230 Parallel Optical Link: PAROLI® Tx/Rx DC 6 DESCRIPTION grouped with output channels 12 to 22, i.e. optical data input 1 feeds electrical data outputs 1 and 12; optical data input 2 feeds electrical data outputs 2 and 13, etc. Demultiplexing of a 4B word (with bits #1.#4) takes two data output cycles. During the first cycle, bit #1 is presented at the lower data output (1.11) and bit #2 at the higher data output (12.22). During the second cycle, bits #3 and #4 are presented at the lower and higher outputs, respectively. (Example: Of the 4B word from optical data channel 1, bit #1 is presented at corresponding lower data output 1 and bit #2 is presented at corresponding higher data output 12.) The demultiplexed data bits are presented as 22 parallel outputs together with the output clock signal, the characteristics of which depend on the clocking mode. (See Clocking Modes above.) Receiver V23815-K1306-M230 V23815-K1306-M230 The PAROLI receiver module converts parallel optical input signals (data and frame) into parallel electrical output signals. Figure 8. Receiver block diagram Optical Inputs Data 11 Fibers Frame Fiber Electrical Outputs 11 Pin Diode Array 11 22 22 Data Decoder Outputs AmpliDemultiOutput fier Frame plexer Clock Stage Clock PLL Output ENSD -SD11 -SD11 OE FRAME_DET -RESET LOCK_DET Start-up Procedure CLK_SEL Detailed information can be found in the data sheet of the Paroli Test board AC/DC, part number V23815-S1306-M931 V23815-S1306-M931. · Switch system power supply on and hold -RESET at Low level · Release -RESET when VCC has reached 3.0 V level · Wait for LOCK_DET to become High · Module starts presenting data at the data outputs if OE is High. All electrical data and clock outputs are LVDS compatible. The module also features several LVCMOS compatible control inputs and outputs, which are described in the Receiver Pin Description (table starting on page 10). The module features demultiplexing and decoding of 11 optical data input channels to 22 electrical data output channels. The frame signal is used to control an integrated PLL circuit, which generates internal clock signals for decoding and demultiplexing. The PLL circuit also generates a clock signal at the Receiver output. Transmission delay of the PAROLI system is at a maximum of 4 strobe cycles + 3 ns for the transmitter, 3 strobe cycles + 3 ns for the receiver, and approximately 5 ns per meter for the fiber optic cable. If OE is at a high level or left open during start-up, clock output will start running immediately after release of -RESET. Clock frequency will drift upwards to the operating frequency established by FRAME input when FRAME_DET indicates sufficient input signal level. After PLL has locked (indicated by LOCK_DET high level) data outputs are also enabled. OE can be used for complete LVDS switch-off whenever clock drift during start-up is critical. Clocking Modes The receiver can be operated in one of two output clocking modes: Strobe mode or SCI mode. The mode is selected via CLK_SEL input. In Strobe mode, the rising edges of the noninverted clock signal are centered over the data bits. In SCI mode, High/Low transitions of clock and data signals coincide. In SCI mode the electrical interface complies with the SCI standard. See Timing diagram Figure 10. Decoding and Demultiplexing The input data received from the optical interface are strobed into the input register with the PLL generated internal clock signal. The data are read in relation to FRAME input. The input frequency expected at FRAME is one fifth of square input data frequency, as FRAME transitions indicate 5B word boundaries. FRAME input is expected to change levels simultaneously with data transitions. All eleven input data channels are fed through individual 5B/4B decoders. Decoding is based on an inversion bit which is received at the first position of a 5B word. This bit determines whether the nibble received at bit positions 2, 3, 4 and 5 has to be inverted. An inversion bit High level indicates a nibble which was transmitted uninverted, i.e. this 4B nibble will be directly forwarded to the demultiplexer. If the inversion bit received is Low, the corresponding nibble will be inverted by the decoder before it is demultiplexed. The 4B words from the decoders are then demultiplexed 1:2 to electrical output data channels. Output channels 1 to 11 are Fiber Optics V23814/15-K1306-M230 V23814/15-K1306-M230 Parallel Optical Link: PAROLI® Tx/Rx DC 7 TECHNICAL DATA Receiver Electro-Optical Characteristics Recommended Operating Conditions Parameter Symbol Min. Typ. Max. Units lCC 910 1030 mA P 3.0 3.7 W Parameter Symbol Min. Max. Units Supply Current Power Supply Voltage VCC 3.0 3.6 V Power Consumption Noise on Power Supply(1) NPS1 50 mV NPS2 100 LVDS Output Low Voltage(1, 4) VLVDSOL Noise on Power Supply(2) Differential LVDS Termination Impedance Rt 80 120 LVDS Output High Voltage(1, 4) VLVDSOH LVCMOS Input High Voltage VLVCMOSIH 2.0 VCC V |VOD| 250 400 LVCMOS Input Low Voltage VLVCMOSIL VEE 0.8 LVDS Output Differential Voltage(1, 2, 4) VOS 1125 1275 mV LVCMOS Input Rise/ Fall Time(3) tR, tF LVDS Output Offset Voltage(1, 3, 4) tR, tF 400 ps Optical FRAME Input Frequency fFRAME Clock Output Rise and Fall Time(5) VLVCMOSOL 400 mV Optical Data, FRAME Input Skew(4) LVCMOS Output Voltage Low LVCMOS Output Voltage High VLVCMOSOH 2500 LVCMOS Input Current High/Low ILVCMOSI 500 µA LVCMOS Output Current High(6) ILVCMOSOH 0.5 mA LVCMOS Output Current Low(7) ILVCMOSOL 4.0 Data Rate per channel (output) DR 150 500 Mbit/s Clock Frequency SCI Mode fCLOCK 75 250 MHz Clock Frequency Strobe Mode fCLOCK 150 500 MHz 20 ns 125 MHz tSI ± 0.2 UI Optical Data, FRAME Input Rise/Fall Time(5) tR, tF 400 ps Optical Data, FRAME Input Extinction Ratio ER 5.0 Input Center Wavelength C 820 37.5 dB 860 nm Notes Voltages refer to VEE=0 V. 1. Noise frequency is 1 kHz to 10 MHz. Voltage is peak-to-peak value. 2. Noise frequency is > 10 MHz. Voltage is peak-to-peak value. 3. Measured between 0.8 V and 2.0 V. 4. Measured for all optical data channels with reference to the optical FRAME channel. A link operating distance of 75m at maximum data rate is supported when using a low skew fiber ribbon cable (skew specification < 1.2 ps/m, fiber bandwidth > 160 MHz · km). Longer link distances are supported at lower data rates. 925 mV 1475 ­500 Notes . Level diagram: Figure 9. Output level diagram 5. 20%­80% level, measured using a GBE (Gigabit Ethernet) filter. mV 1475 |VOD| 925 Time 2. |VOD|=|(output voltage of non-inverted output minus output voltage of inverted output)|. 3. VOS=1/2 (output voltage of inverted output + output voltage of noninverted output). 4. LVDS output must be differentially terminated with Rt. 5. 20% - 80% level, measured with a maximum capacitive load of 5 pF . 6. Source current. 7 Sink current . . Fiber Optics V23814/15-K1306-M230 V23814/15-K1306-M230 Parallel Optical Link: PAROLI® Tx/Rx DC 8 Parameter Symbol Min. Sensitivity (Average Power)(1) PIN Saturation (Average Power) PSAT FRAME Detect Assert Level(2) PFDA FRAME Detect Deassert Level(2) PFDD PFDA­ PFDD 1.0 Return Loss of Receiver ARL Units ­16.5 FRAME_DET and -RESET Timing Diagrams ­28.0 FRAME Detect Hysteresis(2) Max. dBm 12 Optical FRAME Input t2 t1 ­6.0 FRAME_DET 2.5 V 0.4 V ­18.0 t3 t4 LOCK_DET 4.0 dB 2.0 V -RESET 0.8 V Notes t5 Optical parameters valid for each channel. Data and Clock out 1. BER=10 ­12 at infinite ER. This means that the sensitivity specification equals -13.7 dBm for an input signal with an ER of 5 dB. Data Low Clock Low valid t6 2. PFDA: Average optical power when FRAME_DET switches from Low to High. PFDD: Average optical power when FRAME_DET switches from High to Low. Figure 10. Timing diagrams t7 2.0 V OE Values are also applicable for SD11 function, except SD11 is low active. valid 0.8 V Data and Clock out Data Low Clock Low valid Strobe Mode t8 P valid t9 Clock Out N Parameter Symbol Max. Units FRAME_DET Deassert time(1) t1 10 µs FRAME_DET Assert Time(1) t2 FRAME_DET Low to LOCK_DET Low Delay t3 20 ns FRAME_DET High to LOCK_DET High Duration(2) t4 50 ms -RESET Low Duration(3) t5 -RESET Off Delay Time t6 20 ns |VOD| min. Data In 1.22 t1 t2 Parameter Symbol Min. Typ. Max. Units Output Setup Time t1 625 ps Output Hold Time t2 SCI Mode P Clock Out N -RESET On Delay 100 µs 50 ms t8 20 ns LVDS Output Enable Time tS t7 LVDS Output Disable Time |VOD| min. Data Out 1.22 tS Time(4) Min. t9 20 Notes 1. Timing also applicable for SD11 function on fiber #12. In this operation mode the clock output is supplied in phase to data outputs. Parameter Symbol Output Skew(1) ts Min. Typ. Max. 810 2. Stable frame input required. -RESET not activated. 3. Except when used as power-on reset. At any failure recovery, -RESET should be brought to low level for at least t3. Units 4. Valid if -RESET is set high when VCC exceeds 3.0 V level and optical FRAME (FRAME_DET=high) and data input are valid. t5 starts when all these conditions are fulfilled. -RESET must be set to Low during power-up. ps Note 1. All data outputs and clock output. Fiber Optics V23814/15-K1306-M230 V23814/15-K1306-M230 Parallel Optical Link: PAROLI® Tx/Rx DC 9 Figure 11. Measurement conventions for LVDS signals Pin# Pin Name Setup and Hold Times 13 DO01P DO01P LVDS Out Data Output #1, non-inverted 14 DO01N DO01N LVDS Out Data Output #1, inverted 15 DO12P DO12P LVDS Out Data Output #12, non-inverted 16 DO12N DO12N LVDS Out Data Output #12, inverted 17 DO02P DO02P LVDS Out Data Output #2, non-inverted 18 DO02N DO02N LVDS Out Data Output #2,inverted 19 DO13P DO13P LVDS Out Data Output #13, non-inverted 20 DO13N DO13N LVDS Out Data Output #13, inverted 21 DO03P DO03P LVDS Out Data Output #3, non-inverted 22 DO03N DO03N LVDS Out Data Output #3, inverted 23 DO14P DO14P LVDS Out Data Output #14, non-inverted 24 DO14N DO14N LVDS Out Data Output #14, inverted 25 VCC4 26 DO04P DO04P LVDS Out Data Output #4, non-inverted 27 DO04N DO04N LVDS Out Data Output #4, inverted 28 VEE 29 DO15P DO15P LVDS Out Data Output #15, non-inverted 30 DO15N DO15N LVDS Out Data Output #15, inverted 31 DO05P DO05P LVDS Out Data Output #5, non-inverted 32 DO05N DO05N LVDS Out Data Output #5, inverted 33 DO16P DO16P LVDS Out Data Output #16, non-inverted Ground 34 DO16N DO16N LVDS Out Data Output #16, inverted DO06P DO06P LVDS Out Data Output #6, non-inverted P Clock N |VOD| min. Data tSETUP tHOLD Setup and hold times are measured between the cross point of positive and negative clock and the points where rising and falling data edge cross the borders of the V-range. Figure 12. Numbering conventions receiver The numbering conventions for the Tx and Rx modules are the same. Receiver Pin Description Pin# Pin Name 1 Level/Logic Description VEE Level/Logic Description Power supply voltage of decoder Ground 2 VCC1 Power supply voltage of preamplifier 35 36 DO06N DO06N LVDS Out Data Output #6, inverted 3 VCC2 Power supply voltage of analog circuitry 37 DO17P DO17P LVDS Out Data Output #17, non-inverted 4 t.b.l.o. to be left open 38 DO17N DO17N LVDS Out Data Output #17, inverted 5 -RESET 39 DO07P DO07P LVDS Out Data Output #7, non-inverted 40 DO07N DO07N LVDS Out Data Output #7, inverted 41 DO18P DO18P LVDS Out Data Output #18, non-inverted 42 DO18N DO18N LVDS Out Data Output #18, inverted 43 DO08P DO08P LVDS Out Data Output #8, non-inverted 44 DO08N DO08N LVDS Out Data Output #8, inverted 45 VEE 46 DO19P DO19P LVDS Out Data Output #19, non-inverted 47 DO19N DO19N LVDS Out Data Output #19, inverted 6 FRAME_ DET LVCMOS in High=receiver is active. low active Low=internal logic is reset and LVDS outputs are set to low. Internal pull- up pulls to high level when this input is left open. LVCMOS Out High=FRAME input signal present (on fiber #1) Low=insufficient FRAME signal. This output can be used for connection with an Open Fiber Control (OFC) circuit to configure an IEC class 1 link Ground 48 VCC4 7 VCC3 Power supply voltage of digital circuitry 49 DO09P DO09P LVDS Out Data Output #9, non-inverted 8 VEE Ground 50 DO09N DO09N LVDS Out Data Output #9, inverted 9 VCC4 Power supply voltage of decoder 51 DO20P DO20P LVDS Out Data Output #20, non-inverted 52 DO20N DO20N LVDS Out Data Output #20, inverted 53 DO10P DO10P LVDS Out Data Output #10, non-inverted 54 DO10N DO10N LVDS Out Data Output #10, inverted 55 DO21P DO21P LVDS Out Data Output #21, non-inverted 56 DO21N DO21N LVDS Out Data Output #21, inverted 10 LOCK_ DET LVCMOS Out High=PLL has successfully locked onto incoming FRAME signal. LOCK_DET being low sets all LVDS data outputs to low; clock output is unaffected by LOCK_DET. Power supply voltage of decoder 11 COP LVDS Out Clock Output, non-inverted 57 DO11P DO11P LVDS Out Data Output #11, non-inverted 12 CON LVDS Out Clock Output, inverted 58 DO11N DO11N LVDS Out Data Output #11, inverted Fiber Optics V23814/15-K1306-M230 V23814/15-K1306-M230 Parallel Optical Link: PAROLI® Tx/Rx DC 10 Pin# Pin Name Level/Logic Description Optical Port 59 DO22P DO22P LVDS Out Data Output #22, non-inverted 60 DO22N DO22N LVDS Out Data Output #22, inverted 61 CLK_SEL LVCMOS In Input Clocking Mode Select High=strobe mode Low=SCI mode This input has an internal pullup resistor. When left open, strobe mode is active. 62 OE LVCMOS In High=enable LVDS outputs Low=set LVDS outputs (data and clock) to static low level. Internal pull-up pulls to high level when input is left open · Designed for the Simplex MT Connector (SMC) · Port outside dimensions: 15.4 mm x 6.8 mm (width x height) · MT compatible (IEC 61754-5) fiber spacing (250 µm) and alignment pin spacing (4600 µm) · Alignment pins fixed in module port · Integrated mechanical keying · Process plug (SMC dimensions) included with every module · Cleaning of port and connector interfaces necessary prior to mating 63 t.b.l.o. VCC4 Power supply voltage of decoder 65 VEE Ground 66 VCC3 Power supply voltage of digital circuitry 67 -SD11 -SD11 (as part of optional PAROLI fiber optic cables) · Uses standardized MT ferrule (IEC 61754-5) · MT compatible fiber spacing (250 µm) and alignment pin spacing (4600 µm) · Snap-in mechanism · Ferrule bearing spring loaded · Integrated mechanical keying to be left open 64 Features of the Simplex MT Connector (SMC) LVCMOS Out low active Signal Detect Optical Data Channel 11 (on fiber #12) Low=signal of sufficient AC power is present on fiber # 12 High=signal on fiber # 12 is insufficient. This output can be used for connection with an Open Fiber Control (OFC) circuit to configure an IEC class 1 link 68 ENSD 69 t.b.l.o. VCC2 Power supply voltage of analog circuitry 71 VCC1 Power supply voltage of preamplifier 72 VEE On the next pages are some figures to assist the customer in designing his printed circuit board (PCB). Figure 13 shows the mechanical dimensions of the PAROLI transmitter and receiver modules and Figures 14 to 16 give the dimensions of the holes and solder pads on a customer PCB that are necessary to mount the modules on this PCB. Keeping the tolerances for the PCB given in Figures 14 to 16 is required to properly attach the PAROLI transmitter and receiver module to the PCB. Attachment to the customer PCB should be done with four M2 screws torqued to 0.25 Nm + 0.05 Nm (see Figure 13, cross section B-B). The screw length a should be 3 to 4 mm plus the thickness b of the customer PCB. Special care must be taken to remove residues from the soldering and washing process which can impact the mechanical function. Avoid the use of aggressive organic solvents like ketones, ethers, etc. Consult the supplier of the PAROLI modules and the supplier of the solder paste and flux for recommended cleaning solvents. The following common cleaning solvents will not affect the module: deionized water, ethanol, and isopropyl alcohol. Air-drying is recommended to a maximum temperature of 150°C. Do not use ultrasonics. During soldering, heat must be applied to the leads only, to ensure that the case temperature never exceeds 150°C. The module must be mounted with a hot-air or hot-bar soldering process using a SnPb solder type, e.g. Sn62Pb36Ag2, in accordance with ISO 9435. to be left open 70 Assembly LVCMOS In Enable Signal Detect High=SD11 and FRAME_DET function enabled. Low=FRAME_DET and SD11 is set to permanent active. PLL is then forced to start lock-on procedure (for test purposes). Internal pull-up pulls to high level when input is left open. Ground Fiber Optics V23814/15-K1306-M230 V23814/15-K1306-M230 Parallel Optical Link: PAROLI® Tx/Rx DC 11 Figure 13. Drawing of the PAROLI transmitter and receiver module Fiber Optics V23814/15-K1306-M230 V23814/15-K1306-M230 Parallel Optical Link: PAROLI® Tx/Rx DC 12 Figure 14. Recommended circuit board layout: transmitter Figure 15. Recommended circuit board layout: receiver No electronic components are allowed on the customer PCB within the area covered by the PAROLI module and the jumper used to attach a ribbon fiber cable. Figure 16. Mounting hole, Detail Y Fiber Optics V23814/15-K1306-M230 V23814/15-K1306-M230 Parallel Optical Link: PAROLI® Tx/Rx DC 13 Figure 17. Applications LVDS SMC Port Link Controller PAROLI Tx module Ribbon Cables PAROLI Rx module Board-to-Board Passive Optical Backplane PAROLI Tx Rx Optical Feed Through I/O Board Backplane PAROLI SMC Port SMC Port Tx module Rx module Ribbon Cable LVDS LVDS Point-to-Point Published by Infineon Technologies AG Warnings © Infineon Technologies AG 2000 All Rights Reserved Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your Infineon Technologies offices. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infineon Technologies is an approved CECC manufacturer. Information For further information on technology, delivery terms and conditions and prices please contact the Infineon Technologies offices or our Infineon Technologies Representatives worldwide - see our web page at www.infineon.com/fiberoptics Infineon Technologies AG · Fiber Optics · Wernerwerkdamm 16 · Berlin D-13623 D-13623, Germany Infineon Technologies, Inc. · Fiber Optics · 1730 North First Street · San Jose, CA 95112, USA Infineon Technologies K.K. · Fiber Optics · Takanawa Park Tower · 20-14, Higashi-Gotanda, 3-chome, Shinagawa-ku · Tokyo 141, Japan