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UniPHY*

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: 10 Gb Ethernet LAN/WAN-PHY and OC-192 OC-192 Framer Decathlon PX-19200 PX-19200 Features · Conforms to the UNI-PHY proposal of the IEEE 802.3ae Task Force combining Serial LAN-PHY and WAN-PHY proposals. · Supports OC-192c SONET/SDH and 10 Gigabit Ethernet transport applications. · Performs 64B/66B 64B/66B encoding and decoding providing ethernet frame delineation. Can optionally disable PCS scrambling. · System side supports 36-bit XGMII at 156.25 MHz clock with DDR data transfer. · Line side support for SFI ... Paxonet Communications
Original
datasheet

2 pages,
232.86 Kb

OC192 repeater HSBGA 388-HSBGA SFI4 SFI-4 OC192c DDR PHY ASIC OC-192 PX-19200 TEXT
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Abstract: deliver a complete memory solution with the High Performance Memory Controller II (HPMC II) and UniPHY ... Altera
Original
datasheet

66 pages,
1224.98 Kb

SV53001-2 HF35-F1152 5SGX RF40-F1517 TEXT
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Abstract: ://www.pmc-sierra.com For corporate information, send email to: S/UNI®, SA TU R N ® and UNI-PHYTM are tradem arks of ... Altera
Original
datasheet

56 pages,
1034.93 Kb

AV-51002-2 TEXT
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Abstract: Memory PMC-970823 PMC-970823 (P2 ) S/UNI®, SATURN® and UNI-PHYTM are trademarks of PMC-Sierra, Inc. This ... OCR Scan
datasheet

2 pages,
211.83 Kb

PM5371 TEXT
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Abstract: self-calibrating ALTMEMPHY megafunction and UniPHY Intellectual Property (IP) core, optimized to take advantage , megafunction and UniPHY IP core provide the total solution for the highest reliable frequency of operation , ALTMEMPHY megafunction and UniPHY IP core instantiate a phase-locked loop (PLL) and PLL reconfiguration , about ALTMEMPHY megafunction and UniPHY IP core support for Arria II GX devices, refer to the External , rules for Arria II GX devices also apply for this implementation. 1 The UniPHY IP core does not use ... Intel
Original
datasheet

478 pages,
1964.29 Kb

xeon e5-2400 i5-750 intel I5-750 intel Sandy Bridge intel xeon e5-2400 Power One PCU-10 Sandy Bridge DRAM Controller Xeon e5 2600 v2 Xeon E5-1600 v3 Sandy Bridge vm 30 cpu E51600/2400/2600/4600 TEXT
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Abstract: with UniPHY in Stratix IV Devices. Implementing Multiple Memory Interfaces Using UniPHY. , the name of the QDR II and QDR II+ SRAM controller with UniPHY. Parameterize QDR II+ SRAM , .0. 3. Type rldram for the name of the RLDRAM II controller with UniPHY. Parameterize a Controller , Section II. UniPHY Design Tutorials 101 Innovation Drive San Jose, CA 95134 www.altera.com , . . . . . . . . . . vii Chapter 1. Using QDR II and QDR II+ SRAM Controller with UniPHY in Arria ... PMC-Sierra
Original
datasheet

2 pages,
35.4 Kb

PM7346 PM6344 PM6341 PM4351 PM4344 PM4341 apc isdn 1207R TEXT
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Abstract: complete memory solution with a High Performance Memory Controller II (HPMC II) and UniPHY MegaCore® IP ... Altera
Original
datasheet

28 pages,
761.1 Kb

EP2AGX45 EP2AGX125 358p UniPHY EP2AGX260 EP2AGX190 EP2AGX65 AIIGX51007-2 TEXT
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