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;: mux_tbuf16.lca (4008PC84-5 4008PC84-5 4008PC84-5 4008PC84-5), ppr Xilinx:ppr:beta-5.2.0a:95/05/24, 1995/05/31 11:07:03 Version 2 Design 4008PC84 4008PC84 4008PC84 4008PC84 Speed -5 Addnet n513 PAD11 PAD11 PAD11 PAD11.I2 TBUF.TG.2.I NProgram n513 TBUF.TG.2.I:col.G.local.8 UG.40.1.7 UG.40.1.12 row.U.local.3:col.G.long.5-S row.K.local.1:col.G.long.5 PAD11 PAD11 PAD11 PAD11.I2:col.G.long.5 Addnet n512 PAD25 PAD25 PAD25 PAD25.I2 TBUF.TP.2.I NProgram n512 TBUF.TP.2.I:col.P.local.8 UP.40.1.7 UP.40.1.37 row.U.local.3:col.O.long.5-S row.K.local.1:col.O.long.5 PAD25 PAD25 PAD25 PAD25.I2:col.O.long.5 Addnet n511 PAD12 PAD12 PAD12 PAD12.I2 TBUF.TF.2.
www.datasheetarchive.com/files/xilinx/bbs/swhlp/synopsys/vhdl/mux_vs_3/mux_tbu1.lca		 Xilinx 31/05/1995 10.61 Kb LCA mux_tbu1.lca
;: mux_tbuf16.lca (4008PC84-5 4008PC84-5 4008PC84-5 4008PC84-5), ppr Xilinx:ppr:beta-5.2.0a:95/05/24, 1995/05/31 11:07:03 Version 2 Design 4008PC84 4008PC84 4008PC84 4008PC84 Speed -5 Addnet n513 PAD11 PAD11 PAD11 PAD11.I2 TBUF.TG.2.I NProgram n513 TBUF.TG.2.I:col.G.local.8 UG.40.1.7 UG.40.1.12 row.U.local.3:col.G.long.5-S row.K.local.1:col.G.long.5 PAD11 PAD11 PAD11 PAD11.I2:col.G.long.5 Addnet n512 PAD25 PAD25 PAD25 PAD25.I2 TBUF.TP.2.I NProgram n512 TBUF.TP.2.I:col.P.local.8 UP.40.1.7 UP.40.1.37 row.U.local.3:col.O.long.5-S row.K.local.1:col.O.long.5 PAD25 PAD25 PAD25 PAD25.I2:col.O.long.5 Addnet n511 PAD12 PAD12 PAD12 PAD12.I2 TBUF.TF.2.
www.datasheetarchive.com/download/61635476-996530ZC/xsi_vhdl.tar		 Xilinx 09/04/1997 12384 Kb TAR xsi_vhdl.tar
;: mux_tbuf16.lca (4008PC84-5 4008PC84-5 4008PC84-5 4008PC84-5), ppr Xilinx:ppr:beta-5.2.0a:95/05/24, 1995/05/31 11:07:03 Version 2 Design 4008PC84 4008PC84 4008PC84 4008PC84 Speed -5 Addnet n513 PAD11 PAD11 PAD11 PAD11.I2 TBUF.TG.2.I NProgram n513 TBUF.TG.2.I:col.G.local.8 UG.40.1.7 UG.40.1.12 row.U.local.3:col.G.long.5-S row.K.local.1:col.G.long.5 PAD11 PAD11 PAD11 PAD11.I2:col.G.long.5 Addnet n512 PAD25 PAD25 PAD25 PAD25.I2 TBUF.TP.2.I NProgram n512 TBUF.TP.2.I:col.P.local.8 UP.40.1.7 UP.40.1.37 row.U.local.3:col.O.long.5-S row.K.local.1:col.O.long.5 PAD25 PAD25 PAD25 PAD25.I2:col.O.long.5 Addnet n511 PAD12 PAD12 PAD12 PAD12.I2 TBUF.TF.2.
www.datasheetarchive.com/download/78754389-996537ZC/xsivnowk.tar		 Xilinx 20/01/1997 9960 Kb TAR xsivnowk.tar