Z16C35 UM011002-0808 CRC-16 680X0 AD15-AD0 A31-A16 16C35 Z8530 Z8030 WR10A - Datasheet Archive

 

ISCC User Manual UM011002-0808 Copyright © 2008 by Zilog®, Inc. All rights reserved. www.zilog.com ISCC User Manual ii

 

Z16C35 Z16C35 ISCC User Manual UM011002-0808 UM011002-0808 Copyright © 2008 by Zilog®, Inc. All rights reserved. www.zilog.com ISCC User Manual ii Warning: DO NOT USE IN LIFE SUPPORT LIFE SUPPORT POLICY ZILOG'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS PRIOR WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF ZILOG CORPORATION. As used herein Life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user. A critical component is any component in a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness. Document Disclaimer ©2008 by Zilog, Inc. All rights reserved. Information in this publication concerning the devices, applications, or technology described is intended to suggest possible uses and may be superseded. ZILOG, INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT. Z I L O G A L S O D O E S N O T A S S U M E L I A B I L I T Y F O R I N T E L L E C T U A L P R O P E RT Y INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. The information contained within this document has been verified according to the general principles of electrical and mechanical engineering. Z8, Z8 Encore!, Z8 Encore! XP, Z8 Encore! MC, Crimzon, eZ80, and ZNEO are trademarks or registered trademarks of Zilog, Inc. All other product or service names are the property of their respective owners. UM011002-0808 UM011002-0808 ISCC User Manual iii Revision History Each instance in Revision History reflects a change to this document from its previous revision. For more details, refer to the corresponding pages and appropriate links in the table below. Date Aug 2008 02 Reformatted with the latest UM template All June 2001 UM011002-0808 UM011002-0808 Revision Level Description 01 Original issue All Page No Revision History Z8 CPU Core User Manual iv Table of Contents General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 2 6 Interfacing the ISCCTM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 BUS INTERFACE UNIT (BIU) DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Non-Multiplexed Bus Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Multiplexed Bus Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Data Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 I/O INTERFACE CAPABILITIES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 DMA Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 REGISTER ACCESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 SCC Cell Register Access, Multiplexed Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 SCC Cell Register Access, Non-Multiplexed Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 SCC Cell Register Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 DMA Cell Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 DMA Register Access, Multiplexed Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 DMA Register Access, Non-Multiplexed Bus Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Notes on Pointer Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 ISCCTM DMA and Ancillary Support Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Receiver DMA Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Transmitter DMA Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 BAUD RATE GENERATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 DATA ENCODING/DECODING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 DIGITAL PHASE-LOCKED LOOP (DPLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 DPLL Operation in the NRZI Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 DPLL Operation in the FM Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 DPLL Operation and Encoding in the Manchester Mode . . . . . . . . . . . . . . . . . . . . . . . 38 CLOCK SELECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 CRYSTAL OSCILLATORS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Data Communication Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 UM011002-0808 UM011002-0808 Table of Contents Z8 CPU Core User Manual v General Description of the Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General Description of the Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ASYNCHRONOUS MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Asynchronous Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Asynchronous Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BYTE-ORIENTED SYNCHRONOUS MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Byte Oriented Synchronous Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Byte-Oriented Synchronous Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmitter/Receiver Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BIT-ORIENTED SYNCHRONOUS MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SDLC Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SDLC Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SDLC LOOP MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SDLC Loop Mode Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SDLC Loop Mode Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 47 49 50 52 54 55 59 68 69 70 74 80 84 84 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 REGISTER DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Write Registers, SCC Cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Read Registers, SCC Cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 DMA Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 SCC CELL REGISTER OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 WRITE REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Write Register 0 (Command Register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Write Register 1 (Transmit/Receive Interrupt and Data Transfer Mode Definition) . . 94 Write Register 2 (Interrupt Vector) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Write Register 3 (Receive Parameters and Control) . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Write Register 4 (Transmit/Receiver Miscellaneous Parameters and Modes) . . . . . . 100 Write Register 5 (Transmit Parameter and Controls) . . . . . . . . . . . . . . . . . . . . . . . . . 103 Write Register 6 (Sync Characters or SDLC Address Field) . . . . . . . . . . . . . . . . . . . 104 Write Register 7 (SYNC Character or SDLC Flag) . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Write Register 8 (Transmit Buffer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Write Register 9 (Master Interrupt Control) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Write Register 10 (Miscellaneous Transmitter/Receiver Control Bits) . . . . . . . . . . . 108 Write Register 11 (Clock Mode Control) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Write Register 12 (Lower Byte of Baud Rate Generator Time Constant) . . . . . . . . . 114 Write Register 13 (Upper Byte of Baud Rate Generator Time Constant) . . . . . . . . . 115 Write Register 14 (Miscellaneous Control Bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Write Register 15 (External/Status Interrupt Control) . . . . . . . . . . . . . . . . . . . . . . . . 118 READ REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Read Register 0 (Transmit/receive buffer Status and External Status) . . . . . . . . . . . . 120 UM011002-0808 UM011002-0808 Table of Contents Z8 CPU Core User Manual vi Read Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Read Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Read Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Read Register 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Read Register 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Read Register 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Read Register 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Read Register 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DMA CELL REGISTER DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Channel Command/Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DMA Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Vector Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DMA Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DMA Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receive DMA Count Registers A, B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmit DMA Count Registers A, B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receive DMA Address Registers A, B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmit DMA Address Registers A, B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bus Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 125 126 127 127 128 128 129 130 130 131 132 133 135 136 137 138 139 140 141 143 145 Customer Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 Application Notes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 UM011002-0808 UM011002-0808 Table of Contents ISCC User Manual 1 Chapter 1 General Description 1.1 INTRODUCTION The Z16C35 Z16C35, ISCC is a CMOS superintegration device with a flexible Bus Interface Unit (BIU) connecting a built-in Direct Memory Access (DMA) cell to the CMOS Serial Communications Control (SCC) cell. The ISCC is a dual-channel, multi-protocol data communications peripheral which easily interfaces to CPU's with either multiplexed or non-multiplexed address and data buses. The advanced CMOS process offers lower power consumption, higher performance, and superior noise immunity. The programming flexibility of the internal registers allow the ISCC to be configured for a wide variety of serial communications applications. The many on-chip features such as streamlined bus interface, four channel DMA, baud rate generators, digital phase-locked loops, and crystal oscillators dramatically reduce the need for external logic. Additional features, including a 10x19 bit status FIFO, are added to support high speed SDLC transfers using on-chip DMA controllers. The ISCC can address up to 4 gigabytes per DMA channel by using the /UAS and /AS signals to strobe out 32-bit multiplexed addresses. The ISCC handles asynchronous formats, synchronous byte-oriented protocols such as IBM Bisync, and synchronous bit-oriented protocols such as HDLC and IBM SDLC. This versatile device supports virtually any serial data transfer application (terminals, printers, diskette, tape drives, etc.). The device can generate and check CRC codes in any synchronous mode and can be programmed to check data integrity in various modes. The ISCC also has facilities for modem controls in both channels. In applications where these controls are not needed, the modem controls can be used for general-purpose I/O. The standard Zilog interrupt daisy chain is supported for interrupt hierarchy control. Internally, the SCC cell has higher interrupt priority than the DMA cell. The DMA cell consists of four DMA channels; one for transmit and one for receive to and from each SCC channel, respectively. The DMA cell adopts a simple fly-by-mode DMA transfer, providing a powerful and efficient DMA access. The cell does not support memory-to-memory transfer. Priorities between the four DMA channels are programmable to custom-fit user applications. Arbitration of Bus prior-ity control signals between the ISCC DMA and other system DMA's should be handled outside the ISCC. The BIU has a universal interface to most system/CPU bus structures and timing. The first write to the ISCC after a hardware reset will configure the bus interface type being implemented. UM011002-0808 UM011002-0808 Page 1 of 316 ISCC User Manual 2 Figure 1­1. Block Diagram 1.2 Features · · · · · · · UM011002-0808 UM011002-0808 Low Power CMOS Technology Software Compatible to the Zilog CMOS SCC Two General-Purpose SCC Channels, Four DMA Channels; and Universal Bus Interface Unit Four DMA Channels; Two Transmit and Two Receive Channels to and from the SCC Four Gigabyte Address Range per DMA Channel Flyby DMA Transfer Mode Programmable DMA Channel Priorities Page 2 of 316 ISCC User Manual 3 · · · · · · · · · 32-Bit Addresses Multiplexed to 16-pin Address/Data Lines · Multi-Protocol Operation under Program Control; Programmable for NRZ, NRZI, or FM Data Encoding. · Asynchronous Mode with Five to Eight Bits and One, One and One-Half, or Two Stop Bits per Character; Programmable Clock Factor; Break Detection and Generation; Parity, Overrun, and Framing Error Detection. · Synchronous Mode with Internal or External Character Synchronization on One or Two Synchronous Characters and CRC Generation and Checking with CRC-16 CRC-16 or CRC-CCITT preset to either 1's or 0's. · SDLC/HDLC Mode with Comprehensive Frame-Level Control, Automatic Zero Insertion and Deletion, I-Field Residue Handling, Abort Generation and Detection, CRC Generation and Checking, and SDLC Loop Mode Operation. · · · · UM011002-0808 UM011002-0808 Independent DMA Register Set Local Loopback and Auto Echo modes A Universal Bus Interface Unit Providing Simple Interface to Most CPUs Multiplexed or Non-Multiplexed Bus; Compatible with 680X0 680X0 and 8X86 CPUs 8-Bit Data Supporting High/Low Byte Swapping 10 MHz Timing 12.5 and 16 MHz Timing Planned 68-Pin PLCC Supports all Zilog CMOS SCC Features: Two Independent, 0 to 4.0 Mbit/Second, Full-Duplex Channels, Each with a Separate Crystal Oscillator, Baud Rate Generator, and Digital Phase-Locked Loop Circuit for Clock Recovery. Supports T1 Digital Trunk Enhanced SDLC 10x19 Status FIFO for DMA Support Full CMOS SCC Register Set Page 3 of 316 ISCC User Manual 4 Figure 1­2. Pin Functions UM011002-0808 UM011002-0808 Page 4 of 316 ISCC User Manual VCC 2 1 68 67 66 65 64 63 62 61 /BUSACK N/C 3 /UAS VCC 4 /WR /RESET 5 R//W /CE 6 /RD A0/SCC//DMA 7 /DS AI/A//B 8 /AS /WAIT//READY 9 /INTACK IEI 5 IEO 10 60 /BUSREQ /INT 11 59 PCLK /SYNCA 12 58 /SYNCB /RTxCA 13 57 /RTxCB GND 14 56 GND VCC 15 55 VCC AD0 16 54 AD8 AD1 17 53 AD9 AD2 18 52 AD10 AD3 19 51 AD11 AD4 20 50 AD12 AD5 21 49 AD13 AD6 22 48 AD14 ISCC Z16C35 Z16C35 AD7 23 47 AD15 GND 24 46 GND VCC 25 45 VCC N/C 26 44 N/C RxDB /TRxCB TxDB /DTRB /RTSB /CTSB GND /DCDB N/C GND /CTSA /DCDA /RTSA /DTRA TxDA /TRxCA RxDA 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 Figure 1­3. Pin Assignments UM011002-0808 UM011002-0808 Page 5 of 316 ISCC User Manual 6 1.3 Pin Description The following section describes the Z16C35 Z16C35 pin functions. Figures 1-2 and 1-3 detail the respective pin functions and pin assignments. All references to DMA are internal. /CTSA, /CTSB. Clear To Send (inputs, active Low). These pins function as transmitter enables if they are programmed for Auto Enables (WR3, D5). If these pins are programmed as Auto Enables, a Low on the inputs enables the respective transmitters. If not programmed as Auto Enables, they may be used as general-purpose inputs. Both inputs are Schmitt-trigger buffered to accommodate slow rise-time inputs. The SCC cell detects transitions on these inputs and can interrupt the CPU on both low to high and high to low transitions. /DCDA, /DCDB. Data Carrier Detect (inputs, active Low). These pins function as receiver enables if they are programmed for Auto Enables (WR3 D5), otherwise they are used as general-purpose input pins. Both pins are Schmitt-trigger buffered to accommodate slow rise time signals. The SCC cell detects transitions on these inputs and can interrupt the CPU on both low to high and high to low transitions. /DTR//REQA, /DTR//REQB. Data Terminal Ready/Request (outputs, active Low). These pins are programmable (WR14, D2) to serve as either general-purpose outputs or as DMA request lines. When programmed for the DTR function these outputs follow the state programmed into the DTR bit of Write Register 5 (WR5, D7). When programmed for the Ready mode, these pins serve as DMA requests for the transmitter. Note that this DMA request is not associated with the on-chip DMA and is intended for use in requesting DMA service from an external DMA. IEI. Interrupt Enable In (input, active High). IEI is used with IEO to form an interrupt daisy chain when there is more than one interrupt driven device. A high IEI indicates that no other higher priority device has an interrupt under service or is requesting an interrupt. IEO. Interrupt Enable Out (output, active High). IEO is High only if IEI is High and the CPU is not servicing the ISCC (SCC or DMA) interrupt or the ISCC is not requesting an interrupt (Interrupt Acknowledge cycle only). IEO is connected to the next lower priority device's IEI input and thus inhibits interrupts from lower priority devices. /INT. Interrupt (output, active Low). This signal is activated when the SCC or DMA requests an interrupt. Note that /INT is pulled high and is not an open-drain output. /INTACK. Interrupt Acknowledge (input, active Low). This is a strobe which indicates that an interrupt acknowledge cycle is in progress. During this cycle, the SCC and DMA interrupt daisy chain is resolved. The device is capable of returning an interrupt vector that may be encoded with the type of interrupt pending during this acknowledge cycle when / RD or /DS become high. /INTACK may be programmed to accept a status acknowledge, a single pulse acknowledge, or a double pulse acknowledge. This is programmed in the Bus UM011002-0808 UM011002-0808 Page 6 of 316 ISCC User Manual 7 Configuration Register (BCR). The double pulse acknowledge is compatible with 8X86 family microprocessors. PCLK. Clock (input). This is the master SCC cell and DMA cell clock used to synchronize internal signals. PCLK is a TTL level signal. PCLK is not required to have any phase relationship with the master system clock. RxDA, RxDB. Receive Data (inputs, active High). These input signals receive serial data at standard TTL levels. /RTxCA, /RTxCB. Receive/Transmit Clocks (inputs, active Low). These pins can be programmed to several modes of operation. In each channel, /RTxC may supply the receive clock, the transmit clock, the clock for the baud rate generator, or the clock for the Digital Phase-Locked Loop. These pins can also be programmed for use with the respective / SYNC pins as a crystal oscillator. The receive clock may be 1, 16, 32, or 64 times the data rate in asynchronous modes. /RTSA, /RTSB. Request To Send (outputs, active Low). When the Request To Send (RTS) bit in Write Register 5 is set, the /RTS signal goes Low. When the RTS bit is reset in the Asynchronous mode and Auto Enable is on, the signal goes High after the transmitter is empty. In Synchronous mode or in Asynchronous mode with Auto Enable off, the /RTS pin strictly follows the state of the RTS bit. Both pins can be used as general-purpose outputs. /SYNCA, /SYNCB. Synchronization (inputs or outputs, active Low). These pins can act either as inputs, outputs, or part of the crystal oscillator circuit. In the Asynchronous Receive mode (crystal oscillator option not selected), these pins are inputs similar to /CTS and /DCD. In this mode, transitions on these lines affect the state of the Sync/Hunt status bits in Read Register 0 but have no other function. In External Synchronization mode with the crystal oscillator not selected, these lines also act as inputs. In this mode, /SYNC must be driven Low two receive clock cycles after the last bit in the synchronous character is received. Character assembly begins on the rising edge of the receive clock immediately preceding the activation of /SYNC. In the Internal Synchronization mode (Monosync and Bi-sync) with the crystal oscillator not selected, these pins act as outputs and are active only during the part of the receive clock cycle in which sync condition is not latched. These outputs are active each time a sync pattern is recognized (regardless of character boundaries). In SDLC mode, the pins act as outputs and are valid on receipt of a flag. The output is active for one receive clock period (refer to Chapter 4). TxDA, TxDB. Transmit Data (outputs, active high). These output signals transmit serial data at standard TTL levels. /TRxCA, /TRxCB. Transmit/Receive Clocks (inputs or outputs, active Low). These pins can be programmed in several different modes of operation. /TRxC may supply the receive clock or the transmit clock in the input mode or supply the output of the Digital UM011002-0808 UM011002-0808 Page 7 of 316 ISCC User Manual 8 Phase-Locked Loop, the crystal oscillator, the baud rate generator, or the transmit clock in the output mode. /CE. Chip Enable (input, active Low). This signal selects the ISCC for a peripheral read or write operation. This signal is ignored when the ISCC is bus master. AD15-AD0 AD15-AD0. Data bus (bidirectional, tri-state). These lines carry data and commands to and from the ISCC. /RD. Read (bidirectional, active Low). When the ISCC is a peripheral (i.e., bus slave), this signal indicates a read operation and when the ISCC is selected, enables the ISCC's bus drivers. As an input, /RD indicates that the CPU wants to read from the ISCC read registers. During the Interrupt Acknowledge cycle, /RD gates the interrupt vector onto the bus if the ISCC is the highest priority device requesting an interrupt. When the ISCC is the bus master, this signal is used to read data. As an output, after the ISCC has taken control of the system buses, /RD indicates a DMA-controlled read from a memory or I/O port address. /WR. Write (bidirectional, active Low). When the ISCC is selected, this signal indicates a write operation. As an input, this indicates that the CPU wants to write control or command bytes to the ISCC write registers. As an output, after the ISCC has taken control of the system buses /WR indicates a DMA-controlled write to a memory or I/O port address. /DS. Data Strobe (bidirectional, active Low). A Low on this signal indicates that the AD15-AD0 AD15-AD0 bus is used for data transfer. When the ISCC is not in control of the system bus and the external system is transferring information to or from the ISCC, /DS is a timing input used by the ISCC to move data to or from the AD15-AD0 AD15-AD0 bus. Data is written into the ISCC by the external system on the High to Low /DS transition. Data is read from the ISCC by the external system while /DS is Low. There are no timing requirements between /DS as an input and ISCC clock; this allows use of the ISCC with a system bus which does not have a bussed clock. During a DMA operation when the ISCC is in control of the system, /DS is an output generated by the ISCC and used by the system to move data to or from the AD15-AD0 AD15-AD0 bus. When the ISCC has bus control, it writes to the external system by placing data on the AD15-AD0 AD15-AD0 bus before the High-to-Low /DS transition and holds the data stable until after the Low-to-High /DS transition; while reading from the external system, the Low-to-High transition of /DS inputs data from the AD15-AD0 AD15-AD0 bus into the ISCC. R//W. Read/Write (bidirectional). Read polarity is High and write polarity is Low. When the ISCC is not in control of the system bus and the external system is transferring information to or from the ISCC, R//W is a status input used by the ISCC to determine if data is entering or leaving on the AD15-AD0 AD15-AD0 bus during /DS time. In such a case, Read (High) indicates that the system is requesting data from the ISCC and Write (Low) indicates that the system is presenting data to the ISCC. The only timing requirements for R//W as an input are defined relative to /DS. When the ISCC is in control of the system bus, R//W is an output generated by the ISCC, with Read (high) indicating that data is being requested UM011002-0808 UM011002-0808 Page 8 of 316 ISCC User Manual 9 from the addressed location or device, and Write (low) indicating that data is being presented to the addressed location or device. /UAS. Upper Address Strobe (Output, active Low). This signal is used if the output address is more than 16-bit. The upper address, A31-A16 A31-A16, can be latched externally by the rising edge of this signal. /UAS is active first before /AS becomes active. This signal and / AS are used by the DMA cell. /AS. Lower Address Strobe (bidirectional, active Low). When the ISCC is bus master, this signal is an output, and is used as a lower address strobe for AD15-AD0 AD15-AD0. It is used in conjunction with /UAS since the address is 32-bits. This signal and /UAS are used by the DMA cell when it is bus master. When ISCC is not bus master, this signal is used in the multiplexed bus modes to latch the address on the AD lines. The /AS signal is not used in the non-multiplexed bus modes and should be tied to VCC through a resistor in these cases. /WAIT//RDY. Wait/Ready (bidirectional, active Low). This signal may be programmed to function either as a Wait signal or Ready signal during the BCR write. When the BCR is written to Channel A (A1/A//B High during the BCR write), this signal functions as a / WAIT and thus supports the READY function of 8X86 microprocessors family. When the BCR writes to Channel B (A1/A//B Low), this signal functions as a /READY and supports the /DTACK function of the 680X0 680X0 microprocessor family. This signal is an output when the ISCC in not bus master. In this case, the /Wait//RDY signal indicates when the data is available during a read cycle; when the device is ready to receive data during a write cycle; and when a valid vector is available during an interrupt acknowledge cycle. When the ISCC is the bus master (the DMA cell has taken control of the bus), the /Wait// RDY signal functions as a /WAIT or /READY input. Slow memories and peripheral devices can assert /WAIT to extend /DS during bus transfers. Similarly, memories and peripherals use /READY to indicate that its output is valid or that it is ready to latch input data. /BUSACK. Bus Acknowledge (input, active Low). Signals the bus has been released to the DMA. If the /BUSACK goes inactive before the DMA transfer is completed, the current DMA transfer is aborted. /BUSREQ. Bus Request (output, active Low). This signal is used by the DMA to obtain the bus from the CPU. A0/SCC//DMA. DMA Channel/SCC Select/DMA Select (bidirectional). When this pin is used as input, a high selects the SCC cell and a low selects the DMA cell, (during BCR Write should be kept Low). When this pin is used as output, the signal on this pin is used in conjunction with A1/A//B pin output to identify which DMA channel is active. This information can be used by the user to determine whether to issue a DMA abort command. A0/SCC//DMA and A1/A//B output encoding is shown on the following page. UM011002-0808 UM011002-0808 Page 9 of 316 ISCC User Manual 10 A1/A//B 1 1 0 0 A0/SCC//DMA 1 0 1 0 DMA channel RxA TxA RxB TxB A1/A//B. DMA Channel/Channel A/Channel B (bidirectional). This signal, when used as input, selects the SCC channel in which the read and write operation occurs. Note that A0/ SCC//DMA pin must be held high to select this feature. When this pin is used as an output, it is used in conjunction with the A0/SCC//DMA pin output to identify which DMA channel is active. During a DMA peripheral access, the A1/A//B pin is ignored. /RESET. (input, active Low). This signal resets the device to a known state. The first write to the ISCC after a reset accesses the BCR to select additional bus options for the device. UM011002-0808 UM011002-0808 Page 10 of 316 ISCC User Manual 11 Chapter 2 Interfacing the ISCCTM 2.1 Introduction This chapter details the interfacing of the 16C35 16C35 ISCC to a system. Covered in this chapter is a description of the Bus Interface Unit (BIU) and information about the ISCC in nonmultiplexed and multiplexed bus operation. The following section entails the ISCC's capabilities for three types of I/O operations: polling, interrupt (vectored or non-vectored), and DMA Transfer modes. Also included in this chapter is information about the ISCC registers and register access. 2.2 BUS INTERFACE UNIT (BIU) DESCRIPTION The ISCCTM contains a flexible bus interface that is compatible with a variety of microprocessors and microcontrollers. The device is designed to work with 8- or 16-bit bus systems and may be used with address/data multiplexed buses or non-multiplexed buses. The bus interface style is selected by certain actions which take place after a hardware reset. The ISCC contains a Bus Configuration Register, the BCR. This register has no address and is only accessible in the first transaction to the ISCC after a hardware reset; this first transaction must be a write with AØ/sec//DMA Low and is automatically directed to the Bus Configuration Register by the ISCC. The Bus Configuration Register contains bits which program the byte swapping feature, the interrupt acknowledge type and other aspects of the bus interface configuration. Refer to Chapter 5 for BCR details. The multiplexed bus is selected for the ISCC if there is an Address Strobe prior to or during the transaction which writes the BCR. If no Address Strobe is present prior to or during the transaction which writes the BCR, a non-multiplexed bus is selected. The address strobe is recognized whether or not the ISCC Chip Enable is active. 2.2.1 Non-Multiplexed Bus Operation When the ISCC is initialized for non-multiplexed operation, register addressing for the ISCC cell is (with the ex-ception of WR0 and RR0), accomplished using an internal pointer accessed via WR0. Accessing internal registers by this means is a two step operation requiring a write to the pointer followed by access of the desired register. This is described in detail in later sections. Note that when the DMA is not used to address the data, the data registers must be accessed by pointing to Register 8. (This is in contrast to the Z8530 Z8530 which allows direct addressing of the data registers through the C/D pin.) When the ISCC is initialized for non-multiplexed operation, register addressing for the DMA cell (with the exception of CSAR) is accomplished in a manner similar to that used in the SCC cell. In this case the pointer is accessed in the Command Status Address Regis- UM011002-0808 UM011002-0808 Page 11 of 316 ISCC User Manual 12 ter (CSAR bits 4 - 0). The SCC cell and DMA cell pointers are independent. Detailed operation is described in a later section. 2.2.2 Multiplexed Bus Operation When the ISCC is initialized for multiplexed bus operation, all registers in the SCC cell are directly addressable with the register address occupying AD5 through AD1, or AD4 through AD0 (Shift Left/Shift Right modes). The A0/SCC //DMA pin controls the SCC cell /DMA selection. The SCC cell channel A/B selection may be controlled either by the A0/A//B pin or by the A/B selection in the address on AD7-AD0 that is strobed into the ISCC with /AS. Use of this re-quires that the unused SCC channel select option to be set to Channel A. That is, if the A0/A//B pin is used to select the channel, then the AD bit for channel selection must select channel A (the actual bit is determined by the Shift Left/ Shift Right mode employed) and conversely, if the AD bus bit is used to select the channel, then the A0/A//B pin must select channel A. Refer to the A0/SCC//DMA and A1/A//B pin descriptions for the encoding of these signals. In the multiplexed bus mode of operation, the register pointer in WR0 of the SCC cell is ignored and has no effect on the accessing of the internal registers. Register access is made solely through the latched address. However, the pointer in the DMA Channel Command/ Address Register functions in the multiplexed bus mode and may be used to access DMA registers in a manner identical to that in the non-multiplexed bus mode. To use the DMA pointer in the multiplexed bus mode, the multiplexed address must always address the CCAR of the DMA even though the actual register access will be made according to the pointer. This requires that in the normal multiplexed mode of operation with register access through the latched address, writes to the DMA CCAR must always write zeros to the pointer field. In the multiplexed bus mode in some host configurations, address A0 may be used for byte transfer control in 16-bit systems. Therefore, it may be necessary to ignore A0 in the register decode. This is accommodated in the ISCC by providing an option to decode the multiplexed address from A1 upwards rather than from A0 upwards. This option is the Shift Left/Shift Right mode. The Shift Left/Shift Right modes for the address decoding for the internal registers (multiplexed bus) are separately programmable for the SCC cell and for the DMA cell. For the SCC cell the programming and operation is identical to that in the SCC; programming is accomplished through Write Register 0 (WR0), bits 1 and 0 (Figure 5-2). The programming of the Shift Left/Shift Right modes for the DMA cell is accomplished in the BCR, bit 0. In this case, the shift function is similar to that for the SCC cell; with Shift left, the internal register addresses are decoded from bits AD5 through AD1 and with Shift Right, the internal register addresses are decoded from bits AD4 through AD0. When the multiplexed bus mode is selected, Write Register 0 (WR0) takes on the form of WR0 in the Z8030 Z8030 (Figure 5-2). UM011002-0808 UM011002-0808 Page 12 of 316 ISCC User Manual 13 2.2.3 Data Transfers All data transfers to and from the ISCC are done in bytes even though the data may at special times occupy the lower or upper byte of the 16-bit bus. Bus transfers as a slave peripheral are done differently than bus transfers when the ISCC is the bus master during DMA transactions. The ISCC is fundamentally an 8-bit peripheral but supports 16-bit buses in the DMA mode. Slave peripheral and DMA transactions are described in the next paragraphs. Data Bus Transfers as a Slave Peripheral: When accessed as a peripheral device (when the ISCC is not a bus master performing DMA transfers), only 8 bits are transferred. When the ISCC registers are read, the byte data present on the lower 8 bits of the bus is replicated on the upper 8 bits of the bus. Data is accepted by the ISCC only on the lower 8 bits of the bus. ISCC DMA Bus Transfers: During DMA transfers, when the ISCC is bus master, only byte data is transferred. However, data may be transferred from the ISCC on the upper 8 bits of the bus or on the lower 8 bits of the bus. Moreover, odd or even byte transfers may be done on the lower or upper 8 bits of the bus. This is programmable and is described below. During DMA transfers to memory from the ISCC, byte data only is transferred and the data appears on the lower 8 bits and is replicated on the upper 8 bits of the bus. Thus the data may be written to an odd or even byte of the system memory by address decoding and strobe generation. During DMA transfers to the ISCC from memory, byte data only is transferred and normally data is accepted only on the lower 8 bits of the bus. However, the byte swapping feature may be used to enable data to be accepted on either the lower or upper 8 bits of the bus. The byte swapping feature is enabled by programming the Byte Swap Enable bit to a 1 in the BCR. The odd/even byte transfer selection is made by programming the Byte Swap Select bit in the BCR. If Byte Swap Select is a 1, then even address bytes (transfers where the DMA address has A0 equal 0) are accepted on the lower 8 bits of the bus and odd address bytes (transfers where the DMA address has A0 equal 1) are accepted on the upper 8 bits of the bus. If Byte Swap Select is a 0, then even address bytes (transfers where the DMA address has A0 equal 0) are accepted on the upper 8 bits of the bus and odd address bytes (transfers where the DMA address has A0 equal 1) are accepted on the lower 8 bits of the bus. UM011002-0808 UM011002-0808 Page 13 of 316 ISCC User Manual 14 Table 2­1. ISCC Bus Access Summary Process Byte Enable Swap Select Lower 8 Bits Action on Bus Upper 8 Bits Read X X data same data Write X X data read data ignored DMA Write 0 X data same data DMA Read 0 X data read data ignored DMA Write 1 X data same data DMA Read 1 0 depends upon A0 (see below) In the DMA Read with Byte Swap enabled: Byte Swap Select A0 ISCC Accepts Data 0 0 Upper 8 Bits of Bus 0 1 Lower 8 Bits of Bus 1 0 Lower 8 Bits of Bus 1 1 Upper 8 Bits of Bus In this table DMA read refers to a DMA controlled transfer from memory to the ISCC and DMA write refers to a DMA controlled transfer from the ISCC to memory. Read refers to a normal peripheral transaction where the CPU reads data from the ISCC and Write refers to a normal peripheral transaction where the CPU writes data to the ISCC. 2.3 I/O INTERFACE CAPABILITIES The ISCC offers the choice of Polling, Interrupt (vectored or non-vectored), and DMA Transfer modes to transfer data, status, and control information to and from the CPU. 2.3.1 Polling In this mode all interrupts and the DMA's are disabled. Three status registers in the SCC are automatically updated whenever any function is performed. For example, end-offrame in SDLC mode sets a bit in one of these status registers. With polling, the CPU must periodically read a status register until the register contents indicate the need for some CPU action to be taken. Only one register in the SCC cell needs to be read; depending on UM011002-0808 UM011002-0808 Page 14 of 316 ISCC User Manual 15 the contents of the register, the CPU either reads data, writes data, or satisfies an error condition. Two bits in the register indicate the need for data transfer. An alternative is to poll the Interrupt Pending register to determine the source of an interrupt. The status for both SCC channels resides in one register. 2.3.2 Interrupts When the ISCC responds to an Interrupt Acknowledge signal (INTACK) from the CPU, an interrupt vector is placed on the data bus. Both the SCC and the DMA contain vector registers. Depending on the source of interrupt, one of these vectors is returned, either unmodified or modified by the interrupt status to indicate the exact cause of the interrupt. Each of the six sources of interrupt in the SCC (Transmit, Receive, and External/Status interrupts in both channels) and each DMA channel has three bits associated with interrupt source: Interrupt Pending (IP), Interrupt Under Service (IUS), and Interrupt Enable (IE). If the IE bit is set for any given source of interrupt, then that source can request interrupts. The only exception to this rule is when the associate Master Interrupt Enable (MIE) bit is reset, then no interrupts are requested. Both the SCC cell and the DMA have an associated MIE bit. The IE bits in the SCC cell are write only, but the IE bits in the DMA are read/ write. The ISCC provides for nesting of interrupt sources with an interrupt daisy chain using the IEI, IEO, and /INTACK pins. As a microprocessor peripheral, the ISCC may request an interrupt only when no higher priority device is requesting one, e.g., when IEI is High. If the device in question requests an interrupt, it enables the /INT signal. The CPU then responds with /INTACK, and the interrupting cell places the vector on the data bus. In the ISCC, the IP bit signals a need for interrupt servicing. When an IP bit is 1 and the IEI input pin is High, the /INT signal is activated, requesting an interrupt. In the SCC cell, if the IE bit is not set, then the IP for that source can never be set. The IP bits in the DMA cell are set independent of the IE bit. The IUS bits signal that an interrupt request is being ser-viced. If an IUS is set, all interrupt sources of lower priority in the ISCC and external to the ISCC are prevented from requesting interrupts. The internal interrupt sources are inhibited by the state of the internal daisy chain, while lower priority devices are inhibited by the IEO output of the ISCC being pulled Low and propagated to subsequent peripherals. Internally, the SCC cell is higher priority than the DMA cell. An IUS bit is set during an Interrupt Acknowledge cycle if there are no higher priority devices requesting interrupts. The IUS bit must be cleared by the CPU. This is usually done at the end of the correspond-ing interrupt service routine. Within the SCC portion of the ISCC there are three types of interrupts: Transmit, Receive, and External/Status. Each interrupt type is enabled under program control with Channel A having higher priority than Channel B, and with Receive, Transmit, and External/Status interrupts prioritized in that order within each channel. When the Transmit interrupt is UM011002-0808 UM011002-0808 Page 15 of 316 ISCC User Manual 16 enabled, the CPU is interrupted when the transmit buffer becomes empty. This implies that data has shifted from the transmit buffer to the transmitter, thus emptying the transmit buffer. When enabled, the receiver interrupts the CPU in one of three ways: 1. Interrupt on First Receive Character or Special Receive Condition 2. Interrupt on All Receive Characters or Special Receive Condition 3. Interrupt on Special Condition Only Interrupt on First Character or Special Condition, and Interrupt on Special Condition Only, are typically used when doing block transfers with the DMA. A Special Receive Condition is one of the following: receiver overrun, framing error in Asynchronous mode, endof-frame in SDLC mode and, optionally, a parity error. The Special Receive Condi-tion interrupt is different from an Ordinary Receive Character Available interrupt only by the status placed in the vector during the Interrupt Acknowledge cycle. In Interrupt on First Receive Character, an interrupt occurs from Special Receive Conditions any time after the First Receive Character interrupt. The main function of the External/Status interrupt is to monitor the signal transitions of the /CTS, /DCD, and /SYNC pins; however, an External/Status interrupt is also caused by a Transmit Underrun condition, or a zero count in the baud rate generator, or by the detection of a Break (Asynchronous mode), Abort (SDLC mode) or EOP (SDLC Loop mode) sequence in the data stream. The interrupt caused by the Abort or EOP has a special feature allowing the ISCC to interrupt when the Abort or EOP sequence is detected or terminated. This feature facilitates the proper termination of the current message, correct initialization of the next message, and the accurate timing of the Abort condition in external logic. 2.3.3 DMA Interrupts Each DMA in the ISCC has two sources of interrupt, which share an IP bit and an IUS bit, but have independent enables: Terminal Count and Abort. The Abort interrupt is generated when an active DMA channel is forced to terminate its transfers because /BUSACK is deasserted during a transfer. The Terminal Count interrupt is generated when the DMA transfer count reaches zero. The DMA channels themselves are prioritized in a fixed order: Receive A, Transmit A, Receive B, and Transmit B. When DMA transfers are used, the on-chip DMA channels transfer data directly to the transmit buffers or directly from the receive buffers. No other transfers are possible (for initialization, for example). The request signals from the receivers and transmitters are hard-wired to the request inputs of the DMA channels internally. Each DMA channel provides a 32-bit address which is either incremented or decremented with a 16-bit transfer length. Whenever a DMA channel receives a request from its associated receiver or transmitter and the DMA channel is enabled, the ISCC activates the /BUSREQ signal. Upon receipt of an active /BUSACK, the DMA channel transfers data between memory and the SCC cell. This transfer continues until the receiver or transmitter stops requesting a trans- UM011002-0808 UM011002-0808 Page 16 of 316 ISCC User Manual 17 fer or until the terminal count is reached, or /BUSACK is deactivated. The four DMA channels operate independently when the Request Per Channel option is selected; otherwise, all requests pending at the time of bus acquisition will be serviced before the bus is released. Each DMA channel is independently enabled and disabled. 2.4 REGISTER ACCESS ISCC registers may be accessed explicitly, directly or indirectly. Explicit addressing occurs only for three registers in the ISCC: these are the Bus Configuration Register (for the first write after a hardware reset), the RDR (Receive Data Register) by a fly-by DMA read, and the TDR (Transmit Data Register) by a fly-by DMA write. In the non-multiplexed bus case, only WR0/RR0 of the SCC cell and only the Channel Command/Address Register of the DMA cell are accessed directly. Other registers are accessed using the pointers in these directly accessed registers. In the multiplexed bus case, all registers (except the WR0, RR0 and CCAR) are accessed through a two step address/read-write bus transaction. In this case there are two options available for address decoding: shift right and shift left. These options are independently selectable for both the SCC cell and the DMA cell. 2.4.1 SCC Cell Register Access, Multiplexed Bus The registers in the ISCC in the multiplexed bus mode are addressed via the address on AD7-AD0 which is latched by the rising edge of /AS. As discussed in the paragraphs below, the address contains a bit to select the SCC cell channel (A or B). Although this selection is in the address, the A1/A//B input remains active and must be set to select Channel A for the selection bit in the AD7-AD0 address to function correctly. Conversely, the A1/A//B pin may also be used to select the channel instead of the bit in the AD7-AD0 address. In this case, the bit in the AD7-AD0 address must be set to select Channel A for the A1/A//B input to function correctly. There are two address decoding modes: shift left and shift right. In shift left mode, the register address is decoded from AD5-AD1. This mode is set by a hardware reset. In the shift left mode, the register address itself is placed on AD4-AD1 and the Channel Select bit, A/B, is decoded from AD5. The register map for this case is shown in Table 2-2. UM011002-0808 UM011002-0808 Page 17 of 316 ISCC User Manual 18 Table 2­2. SCC Cell Address Map, Multiplexed Bus Mode, Shift Left Address AD5-AD1 Write 10000 WR0A 10001 WR1A 10010 WR2 10011 WR3A 10100 WR4A 10101 WR5A 10110 WR6A 10111 WR7A 11000 WR8A 11001 WR9 11010 WR10A WR10A 11011 WR11A WR11A 11100 WR12A WR12A 11101 WR13A WR13A 11110 WR14A WR14A 11111 WR15A WR15A Note: The above table applies to Channel "B" also. Read RR0A RR1A RR2A RR3A (RR0A) (RR1A) (RR2A) (RR3A) RR8A (RR13A RR13A) RR10A RR10A (RR15A RR15A) RR12A RR12A RR13A RR13A (RR10A RR10A) RR15A RR15A In Shift Right Mode, bits 0-1 in WR0A controls which bits will be decoded to form the register address. It is placed in this register to simplify programming when the current state of the Shift Right/Shift Left bit is not known. The register address is decoded from AD4-AD0. The Shift Right/Shift Left bit is written via command to make the software writing to WR0 independent of the state of the Shift Right/Shift Left bit. AD4-AD0 is the actual register address and AD0 determines the channel selection (A//B). The register map is shown in Table 2-3. Because the ISCC SCC Cell does not contain 16 read registers, the decoding of the read registers is not complete; this is indicated in Table 2-2 and Table 2-3 by parentheses around the register name. These addresses may also be used to access the read registers. Note also that in the multiplexed bus mode, only one WR2 and WR9 are shown in the address map; these registers may be written from either SCC cell channel. UM011002-0808 UM011002-0808 Page 18 of 316 ISCC User Manual 19 Table 2­3. SCC Cell Address Map, Multiplexed Bus Mode, Shift Right Address AD4-AD0 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 Write WR0B WR0A WR1B WR1A WR2 WR2 WR3B WR3A WR4B WR4A WR5B WR5A WR6B WR6A WR7B WR7A WR8B WR8A WR9 WR9 WR10B WR10B WR10A WR10A WR11B WR11B WR11A WR11A WR12B WR12B WR12A WR12A WR13B WR13B WR13A WR13A WR14B WR14B WR14A WR14A WR15B WR15B WR15A WR15A Read RR0B RR0A RR1B RR1A RR2B RR2A RR3B RR3A RR0B RR0A (RR1B) (RR1A) RR2B RR2A (RR3B) (RR3A) RR8B RR8A (RR13B RR13B) (RR13A RR13A) RR10B RR10B RR10A RR10A (RR15B RR15B) (RR15A RR15A) RR12B RR12B RR12A RR12A RR13B RR13B RR13A RR13A (RR10B RR10B) (RR10A RR10A) RR15B RR15B RR15A RR15A 2.4.2 SCC Cell Register Access, Non-Multiplexed Bus The registers in the SCC cell in the non-multiplexed bus mode are accessed in a two-step process, using a Register Pointer to perform the addressing. To access a particular register, UM011002-0808 UM011002-0808 Page 19 of 316 ISCC User Manual 20 the pointer bits must be set by writing to WR0 bits 2, 1, and 0 and, if required, using the Point High command to extend the three bit pointer to registers 8 through 15. This write to WR0 to set the pointer bits may be done in either channel. There is only one pointer register and it is used for both A and B channels. After the pointer bits are set, the next read or write cycle to the SCC cell will access the desired register in the channel selected during this read or write cycle. At the conclusion of this read or write cycle, the pointer bits are reset to "0s," so that the next access will be to WR0. The fact that the pointer bits are reset to "0," unless explicitly set otherwise, means that WR0 and RR0 may also be accessed in a single cycle. That is, it is not necessary to write the pointer bits with "0" before accessing WR0 or RR0. There are three pointer bits in WR0, and these allow access to the registers with addresses 0 through 7. Note that a command may be written to WR0 at the same time that the pointer bits are written. To access the registers with addresses 8 through 15, a special command must accompany the pointer bits; WR0(4-3)=001. This precludes concurrently issuing a command when pointing to these registers. The register map for the ISCC in the non-multiplexed bus mode is shown in Table 2-4 below. If, for some reason, the state of the pointer bits is unknown, they may be reset to "0" by performing a read cycle of the SCC cell. Once the pointer bits have been set, the desired channel is selected by the state of the A1/A//B pin during the actual read or write of the desired SCC cell register.) UM011002-0808 UM011002-0808 Page 20 of 316 ISCC User Manual 21 Table 2­4. SCC Cell Register Address Map Using Pointer (Non-multiplexed Bus Mode) Using Null Command A1/A//B 0 0 0 0 Address D2 D1 D0 000 001 010 011 Write Register WR0B WR1B WR2 WR3B Read Register RR0B RR1B RR2B RR3B 0 0 0 0 100 101 110 111 WR4B WR5B WR6B WR7B (RR0B) (RR1B) (RR2B) (RR3B) 1 1 1 1 000 001 010 011 WR0A WR1A WR2 WR3A RR0A RR1A RR2A RR3A 1 1 1 1 100 101 110 111 WR4A WR5A WR6A WR7A (RR0A) (RR1A) (RR2A) (RR3A) Using Point High Command A1/A//B 0 0 0 0 Write Register WR8B WR9 WR10B WR10B WR11B WR11B Read Register RR8B RR13B RR13B RR10B RR10B (RR15B RR15B) 0 0 0 0 100 101 110 111 WR12B WR12B WR13B WR13B WR14B WR14B WR15B WR15B RR12B RR12B RR13B RR13B (RR10B RR10B) RR15B RR15B 1 1 1 1 000 001 010 011 WR8A WR9A WR10A WR10A WR11A WR11A RR8A (RR13A RR13A) RR10A RR10A (RR15A RR15A) 1 1 1 1 UM011002-0808 UM011002-0808 Address D2 D1 D0 000 001 010 011 100 101 110 111 WR12A WR12A WR13A WR13A WR14A WR14A WR15A WR15A RR12A RR12A RR13A RR13A (RR10A RR10A) RR15A RR15A Page 21 of 316 ISCC User Manual 22 2.4.3 SCC Cell Register Reset Table 2-5 lists the contents of the SCC cell registers after a hardware reset and after a channel reset. Table 2­5. SCC Cell Reset Value Register WR0 WR1 WR2 WR3 WR4 Hardware Reset 00000000 00x00x00 xxxxxxxx xxxxxxx0 xxxxx1xx Channel Reset 00000000 00x00x00 xxxxxxxx xxxxxxx0 xxxxx1xx WR5 WR6 WR7 WR9 WR10 0xx0000x xxxxxxxx xxxxxxxx 110000xx 00000000 0xx0000x xxxxxxxx xxxxxxxx xx0xxxxx 0xx00000 WR11 WR12 WR13 WR14 WR15 00001000 xxxxxxxx xxxxxxxx xx100000 11111000 xxxxxxxx xxxxxxxx xxxxxxxx xx1000xx 11111000 RR0 RR1 RR3 RR10 01xxx100 00000110 00000000 00000000 01xxx100 00000110 00000000 00000000 2 2.4.4 DMA Cell Registers The DMA cell contains seventeen registers counting the Bus Configuration Register. All of these registers are read/write exept the Bus Configuration Register (write only), the Channel Command Address Register (write only), the DMA Status Register (read only), the Interrupt Command Register (write only), and the Interrupt Status Register (read only). The reset content of all of the DMA registers identified in the address map is all zeroes. 2.4.5 DMA Register Access, Multiplexed Bus The registers in the ISCC in the multiplexed bus mode are addressed via the address on AD7-AD0 which is latched by the rising edge of /AS. UM011002-0808 UM011002-0808 Page 22 of 316 ISCC User Manual 23 There are two address decoding modes: shift left and shift right. In shift left mode, the register address is decoded from AD5-AD1. This mode is set by a hardware reset. In Shift right mode, the register address is decoded from AD4-AD0. The shift right/shift left selection for the DMA is located in the Bus Configuratin Register, bit D0. When set, this bit programs the Shift Right mode for the DMA and when reset, this bit programs the Shift Left Mode. The address map for the DMA registers is shown in Table 2-6. This Table is also applicable to the non-multiplexed bus mode. UM011002-0808 UM011002-0808 Page 23 of 316 ISCC User Manual 24 Table 2­6. DMA Address Map Address* xxxxx 00000 00000 00001 00010 00011 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 UM011002-0808 UM011002-0808 Name BCR CCAR DSR ICR IVR ICSR ISR I DER DCR RDCRA RDCRA TDCRA TDCRA RDCRB RDCRB TDCRB TDCRB RDARA RDARA RDARA RDARA TDARA TDARA TDARA TDARA RDARB RDARB RDARB RDARB TDARB TDARB TDARB TDARB Description Bus Configuration Register Channel Command/Address Register (Write) DMA Status (Read) Interrupt Control Register Interrupt Vector Register Interrupt Command Register (Write) nterrupt Status Register (Read) DMA Enable/Disable Register DMA Control Register Reserved Address Reserved Address Receive DMA Count Register, Channel A (Low Byte) Receive DMA Count Register, Channel A (High Byte) Transmit DMA Count Register, Channel A (Low Byte) Transmit DMA Count Register, Channel A (High Byte) Receive DMA Count Register, Channel B (Low Byte) Receive DMA Count Register, Channel B (High Byte) Transmit DMA Count Register, Channel B (Low Byte) Transmit DMA Count Register, Channel B (High Byte) Receive DMA Address Register, Channel A (Bits 0-7) Receive DMA Address Register, Channel A (Bits 8-15) Receive DMA Address Register, Channel A (Bits 16-23 Receive DMA Address Register, Channel A (Bits 24-31) Transmit DMA Address Register, Channel A (Bits 0-7) Transmit DMA Address Register, Channel A (Bits 8-15) Transmit DMA Address Register, Channel A (Bits 16-23) Transmit DMA Address Register, Channel A (Bits 24-31) Receive DMA Address Register, Channel B (Bits 0-7) Receive DMA Address Register, Channel B (Bits 8-15) Receive DMA Address Register, Channel B (Bits 16-23) Receive DMA Address Register, Channel B (Bits 24-31) Transmit DMA Address Register, Channel B (Bits 0-7) Transmit DMA Address Register, Channel B (Bits 8-15) Transmit DMA Address Register, Channel B (Bits 16-23) Transmit DMA Address Register, Channel B (Bits 24-31) Page 24 of 316 ISCC User Manual 25 Note: *Address in this Table is AD5-AD1 in the Multiplexed Bus with the Shift Left mode selected, AD4-AD0 in the Multiplexed Bus with the Shift Right mode selected, and D4 -D0 of the Channel Command/Address Register in the Non-multiplexed Bus mode. 2.4.6 DMA Register Access, Non-Multiplexed Bus Mode The registers in the DMA cell in the non-multiplexed bus mode are accessed in a two-step process, using a Register Pointer to perform the addressing. To access a particular register, the pointer bits must be set by writing to the Channel Command /Address Register bits 4 through 0. After the pointer bits are set, the next read or write cycle to the DMA cell will access the desired register. At the conclusion of this read or write cycle, the pointer bits are reset to "0s," so that the next access will be to the Channel Command/Address Register. The fact that the pointer bits are reset to "0," unless explicitly set otherwise, means that the Channel Command/Address Register may be accessed in a single cycle. That is, it is not necessary to write the pointer bits with "0" before accessing the Channel Command/ Address Register. This permits single access DMA enabling and resetting the highest IUS through the encoded DMA Commands. 2.4.7 Notes on Pointer Accesses The non-multiplexed bus accesses are accomplished as described in the preceding paragraphs using the DMA pointer for the DMA cell and the SCC cell pointer for channels A and B. These two pointers are completely independent. If one of these pointers is written to with a pointer value in preparation for a read or write to the selected register, the pointer will hold its value until the corresponding cell is accessed. For example, suppose the SCC cell pointer is written to in preparation to read an SCC cell register in the next (or even subsequent) software program steps. Before this SCC cell read takes place, a DMA interrupt occurs and the program enters the interrupt service routine prior to the SCC register read. In the interrupt service routine, several DMA register accesses are made. When the program exits the interrupt service routine and returns to the interrupted process, the register access to the SCC cell register proceeds correctly; the pointer was left unaltered. A converse situation is true for the DMA cell. It should be clear, however, that if an interrupt routine is invoked between the pointer write and the register access, there can be conflict if the same cell is accessed in the interrupt service routine. Assume in the above example that the interrupt service routine accesses the SCC cell also. Since the pointer has already been written, a second write (the one in the interrupt service routine) will not write to the pointer in WR0 but will write to the pointed to register. Subsequent register access will also be incorrect. This suggests that the pointer write and subsequent register access be an uninterruptable pair and that the SCC Cell and DMA cell or the processor interrupts be disabled during the register access sequence. UM011002-0808 UM011002-0808 Page 25 of 316 ISCC User Manual 26 Chapter 3 ISCCTM DMA and Ancillary Support Circuitry 3.1 INTRODUCTION The most important feature of the ISCC other than SCC cell is the integrated, four channel DMA controller. As in the original SCC, the serial channels of the ISCC are supported by ancillary circuitry for generating clocks and performing data encoding and decoding. This chapter presents a description of these functional blocks. 3.2 DMA The ISCCTM contains four independent DMA Channels, one for each receiver and transmitter. The DMA channels operate in fly-by mode; a 32-bit transfer address is generated along with the bus acquisition signals for executing the DMA transfer. Each DMA consists of a 32-bit address counter, a 16-bit (transfer) counter, and the required sequencing and control circuitry. The DMA is set up by initializing the address resisters with the starting address of the DMA transfer and the count registers for the length of the block. Following this, the option to increment or decrement the address after a transfer is selected. Other DMA selections that must be programmed include the DMA priority, if separate bus requests are to be made for each DMA channel, the programming of the interrupt vector and the option to include interrupt status in the vector. Note that a no vector interrupt option is also possible. Following this, the Interrupt On Abort is programmed as desired, the individual channel interrupt enables are programmed, the Master Interrupt Enable is set (if interrupts are used), and lastly the appropriate DMA channels are enabled. 3.2.1 Receiver DMA Operation Assuming the receiver has been appropriately set up, the DMA request will be made when the receive FIFO contains a byte and will continue to hold the bus and transfer bytes until the FIFO is empty. Once started, the DMA for the channel continues until the FIFO is empty even though a request from a higher priority DMA channel arises. Upon completion of the current DMA channel service, the next highest priority DMA channel commences its operation. The ISCC continues to hold the bus until all pending DMA requests have been served. Note that if the Bus Request Per Channel option has been selected, then the bus will be released and subsequently re-requested for each channel. At the completion of the block transfer (terminal count reached), an interrupt will be generated, if enabled. If selected, the interrupt vector will indicate the interrupt source according to Table 3-1. UM011002-0808 UM011002-0808 Page 26 of 316 ISCC User Manual 27 Table 3­7. DMA Interrupt Vector Modifications IV3 0 0 0 0 1 1 1 1 IV2 0 0 1 1 0 0 1 1 IV1 0 1 0 1 0 1 0 1 Interrupt Source No Interrupt Pending Not Possible Not Possible Not Possible Rx A Interrupt Pending Rx B Interrupt Pending Tx A Interrupt Pending Tx B Interrupt Pending An Interrupt Pending only modifies the interrupt vector if the corresponding Interrupt Enable bit is set. Note that software may have to test status bits to determine if the channel interrupt is due to terminal count or an abort. When the receive DMA enable bit is set, a DMA request is made if the receive FIFO contains a character at the time, or no request will be made until a character enters the receive FIFO. Note that DMA requests will follow the state of the receive FIFO even though the receiver is disabled. Thus, if the receiver is disabled and the DMA is still enabled, the DMA will transfer the previously received data correctly. In this mode the DMA requests directly follow the state of the receive FIFO. This operation is essentially equivalent to the DMA requests following the state of the Receive Character Available bit in the SCC cell in Read Register 0. The SCC cell will not generate a DMA request in the case of a special receive condition in the Receive Interrupt on First Character or Special Condition mode, or the Receive Interrupt on Special Condition Only mode. In these two interrupt modes any receive character with a special receive condition is locked at the top of the FIFO until an Error Reset command is issued. This character in the receive FIFO would ordinarily cause additional DMA Requests after the first time it is read. However, the logic in the SCC cell guarantees no extra DMA transfers by terminating DMA requests after the time the character with the special receive condition is read, and the FIFO locked. DMA requests are held off until after the Error Reset command has been issued. Once the FIFO is locked, it allows the checking of the Receive Error FIFO (RR1) to find the cause of the error. Locking the data FIFO therefore, will stop the error status from popping out of the Receive Error FIFO. Also, since DMA request will become inactive, the interrupt (Special Condition) can be serviced. Once the FIFO is unlocked by the Error Reset command, DMA requests again follow the state of the receive FIFO. UM011002-0808 UM011002-0808 Page 27 of 316 ISCC User Manual 28 3.2.2 Transmitter DMA Operation With the DMA enabled, the status of an empty transmitter FIFO triggers the DMA to request the bus and begin DMA transfer to the transmit FIFO. Once this DMA channel is selected for service, DMA transfers continue until the transmit FIFO is full (or until terminal count is reached if there are not enough bytes remaining to fill the FIFO). Once started, the DMA for the channel continues until the FIFO is full even though a request from a higher priority DMA channel arises. Upon completion of the current DMA channel service, the next highest priority DMA channel commences its operation. The ISCC continues to hold the bus until all pending DMA requests have been served. Note that if the Bus Request Per Channel option has been selected, then the bus will be released and subsequently re-requested for each channel. At the completion of the block transfer (terminal count reached), an interrupt will be generated, if enabled. If selected, the interrupt vector will indicate the interrupt source according to Table 3-1. An Interrupt Pending only modifies the interrupt vector if the corresponding Interrupt Enable bit is set. Note that software may have to test status bits to determine if the channel interrupt is due to terminal count or an abort. Note that the DMA request will follow the state of the transmit FIFO even though the transmitter is disabled. Thus, if the DMA is enabled, the DMA may write data to the SCC cell before the transmitter is enabled. This will not cause a problem in Asynchronous mode but may cause problems in Synchronous mode because the ISCC will send data in preference to flags or sync characters. Thus a data character in the transmit FIFO may get transmitted prior to the frame sync character or opening flag. It may also complicate the CRC initialization, which cannot be done until after the transmitter is enabled. DMA requests essentially follow the Tx Buffer Empty bit in the SCC cell Read Register 0. 3.3 BAUD RATE GENERATOR The Baud Rate Generator (BRG) is essential for asynchronous communications. Each channel in the ISCC contains a programmable baud rate generator. Each generator consists of two 8-bit, time-constant registers forming a 16-bit time constant, a 16-bit down counter, and a flip-flop on the output that makes the output a square wave. On start-up, the flip-flop on the output is set High, so that it starts in a known state, the value in the time-constant register is loaded into the counter, and the counter begins counting down. When a count of zero is reached, the output of the baud rate generator toggles, the value in the time-constant register is loaded into the counter, and the process starts over. A block diagram of the baud rate generator is shown in Figure 3-1. The time-constant can be changed at any time, but the new value does not take effect until the next load of the counter (i.e., after zero count is reached). No attempt is made to synchronize the loading of a new time-constant with the clock used to drive the generator. UM011002-0808 UM011002-0808 Page 28 of 316 ISCC User Manual 29 When the time-constant is to be changed, the generator should be stopped first by writing to an enable bit in WR14. After loading the time constant, the BRG can be started again. This ensures the loading of a correct time constant, but loading will not be taking place until zero count or a re-set occurs. If neither the transmit clock nor the receive clock are programmed to come from the /TRxC pin, the output of the baud rate generator may be made available for external use on the /TRxC pin. The clock source for the baud rate generator is selected by bit D1 of WR14. When this bit is set to "0," the baud rate generator uses the signal on the /RTxC pin as its clock, independent of whether the /RTxC pin is a simple input or part of the crystal oscillator circuit. When this bit is set to "1," the baud rate generator is clocked by PCLK. To avoid metastable problems in the counter, this bit should be changed only while the baud rate generator is disabled, since arbitrarily narrow pulses can be generated at the output of the multiplexer when it changes state. The BRG is enabled while bit DO of WR14 is set to 1 and disabled while this bit is set to 0 and it is disabled after a hardware reset. To prevent metastable problems when the baud rate generator is first enabled, the enable bit is synchronized to the baud rate generator clock. This introduces an additional delay when the baud rate generator is first enabled. This is shown in Figure 3-2. The baud rate generator is disabled immediately when bit D0 of WR14 is set to "0," because the delay is only necessary on start-up. The baud rate generator may be enabled and disabled on the fly, but this delay on start-up must be taken into consideration. Figure 3­4. Baud Rate Generator UM011002-0808 UM011002-0808 Page 29 of 316 ISCC User Manual 30 Figure 3­5. Baud Rate Generator Start-Up The formulas relating the baud rate to the time-constant and vice versa are shown below. The clock mode in the formula is the ratio of the receive clock applied to the ISCC relative to the data rate. The ISCC may be programmed to accept a receive clock that is one, sixteen, thirty-two, or sixty-four times the data rate (refer to the description of WR4 and the descriptions in Chapter 4). Time Constant = Clock Frequency -2 2*(Clock Mode)*(Baud Rate) Clock Frequency Baud Rate = 2*(Clock Mode)*(Time Constant +2) In these formulas, the baud rate generator clock frequency (PCLK or /RTxC) is in Hertz, the desired baud rate in bits/second and the time constant is dimensionless. The example in Table 3-1 assumes a 2.4576 MHz clock (from /RTxC) clock factor of 16 and shows the time constant for a number of popular baud rates. For example: 6 2.4576 × 10 TC = - = 510 2 × 16 × 150 UM011002-0808 UM011002-0808 Page 30 of 316 ISCC User Manual 31 Table 3­8. Baud Rates for 2.4576 MHz Clock and 16x Clock Factor Time Constant Decimal Hex Baud Rate 0 2 6 14 30 62 126 254 510 0000 0002 0006 000E 001E 003E 007E 00FE 01FE 38400 19200 9600 4800 2400 1200 600 300 150 Initializing the baud rate generator is done in three steps. First, the time-constant is determined and loaded into WR12 and WR13. Next, the processor must select the clock source for the baud rate generator by setting bit D1 of WR14. Finally, the baud rate generator is enabled by setting bit D0 of WR14 to "1." Note that the first write to WR14 is not necessary after a hardware reset if the clock source is the /RTxC pin. This is because a hardware reset automatically selects the /RTxC pin as the baud rate generator clock source. 3.4 DATA ENCODING/DECODING The ISCC provides four different data encoding methods, selected by bits D6 and D5 in WR10. An example of these four encoding methods is shown in Figure 3-3. Any encoding method may be used in any X1 mode in the ISCC, asynchronous or synchronous. The data encoding selected is active even though the transmitter or receiver may be idling or disabled. The data encoding methods are shown in Figure 3-3. UM011002-0808 UM011002-0808 Page 31 of 316 ISCC User Manual 32 DATA 1 1 0 0 1 0 NRZ Bit Cell Level: High = 1 Low = 0 No Change = 1 Change = 0 NRZI FM1 (Biphase Mark) FM0 (Biphase Space) MANCHESTER Figure 3­6. Data Encoding Methods In NRZ, encoding a "1" is represented by a HIGH level and a "0" is represented by a LOW level. In this encoding meth-od, only a minimal amount of clocking information is available in the data stream in the form of transitions on bit-cell boundaries. In an arbitrary data pattern, this may not be sufficient to generate a clock for the data from the data itself. In NRZI, encoding a "1" is represented by no change in the level and a "0" is represented by a change in the level. As in NRZ, only a minimal amount of clocking information is available in the data stream, in the form of transitions on bit cell boundaries. In an arbitrary data pattern this may not be sufficient to generate a clock for the data from the data itself. In the case of SDLC, where the number of consecutive "1s" in the data stream is limited, a minimum number of transitions to generate a clock are guaranteed. In FM1 encoding, also known as biphase mark, a transition is present on every bit cell boundary, and an addition transition may be present in the middle of the bit cell. In FM1 a "0" is sent as no transition in the center of the bit cell and a "1" is sent as a transition in the center of the bit cell. FM1 encoded data contains sufficient information to recover a clock from the data. In FM0 encoding, also known as biphase space, a transition is present on every bit cell boundary and an additional transition may be present in the middle of the bit cell. In FM0, a "1" is sent as no transition in the center of the bit cell and a "0" is sent as a transition in the center of the bit cell. FM0 encoded data contains sufficient information to recover a clock from the data. UM011002-0808 UM011002-0808 Page 32 of 316 ISCC User Manual 33 Manchester encoding, which is not directly supported, always produces a transition at the center of the bit cell. If the transition is Low to High, the bit is "0." If the transition is High to Low, the bit is "1." ISCC can be used to decode Manchester (biphase level) data by using the DPLL in the FM mode and programming the receiver for NRZ data. (See section 3.5.3.) The data encoding method should be selected in the initialization procedure before the transmitter and receiver are enabled, but no other restrictions apply. Note, in Figure 3-3, that in NRZ and NRZI the receiver samples the data only on one edge. However, in FM1 and FM0 the receiver samples the data on both edges. Also, as shown in Figure 6-4, the transmitter defines bit cell boundaries by one edge in all cases and uses the other edge in FM1 and FM0 to create the mid-bit transition. 3.5 DIGITAL PHASE-LOCKED LOOP (DPLL) Each channel of the SCC cell contains a digital phase-locked loop that can be used to recover clock information from a data stream with NRZI, FM or NRZ encoding. The DPLL is driven by a clock nominally 32 (NRZI) or 16 (FM) times the data rate. The DPLL uses this clock, along with the data stream, to construct a receive clock for the data. This clock can then be used as the ISCC receive clock, the transmit clock, or both. Figure 3-4 shows a block diagram of the digital phase-locked loop. It consists of a 5-bit counter, an edge detector, and a pair of output decoders. The clock for the DPLL comes from the output of a two-input multiplexer, and the two outputs go to the transmitter and receive clock multiplexers. The DPLL is controlled by the seven commands that are encoded in bits D7, D6 and D5 of WR14. Edge Detector Count Modifier Decode Receive Clock 5-Bit Counter RxD Decode Transmit Clock Figure 3­7. Digital Phase Lock Loop The clock for the DPLL is selected by two of the commands in WR14, that is: WR14 (7-5) = 100 WR14 (7-5) = 101 UM011002-0808 UM011002-0808 BRG Clock Source /RTxC Pin Clock Source Page 33 of 316 ISCC User Manual 34 The first command selects the baud rate generator as the clock source. The other command selects /RTxC pin as the clock source, independent of whether the /RTxC pin is a simple input or part of the crystal oscillator circuit. Initialization of the DPLL may be done at any time during the initialization sequence, but should preferably be done after the clock modes have been selected in WR11, and before the receiver and transmitter are enabled. When initializing the DPLL, the clock source should be selected first, followed by the selection of the operating mode. To avoid metastable problems in the counter, the clock source selection should be made only while DPLL is disabled, since arbitrarily narrow pulses can be generated at the output of the multiplexer when it changes status. The DPLL is enabled by issuing the Enter Search Mode command in WR14; that is WR14 (7-5) = 001. The Enter Search Mode command unlocks the counter, which is held while the DPLL is disabled, and enables the edge detector. If the DPLL is already enabled when this command is issued, the DPLL also enters Search Mode. Enter Search Mode is also used to reset the DPLL to a known state if it is suspected that synchronization has been lost. Note that the DPLL and the receiver are independent, so whether the receiver is disabled or not enabled, DPLL will sample whatever is on the RxD line. DPLL requires a transition in every bit cell, and if this transition is not present in two consecutively sampled bit cells, the DPLL will automatically enter search mode and the DPLL will not provide any clock output. In Search mode, the counter is held at a specific count and no outputs are provided. The DPLL remains in this status until an edge is detected in the receive data stream. This first edge is assumed to occur on a bit cell boundary, and the DPLL will begin providing an output to the receiver that will properly sample the data. From this point on the DPLL will adjust its output to remain in phase with the receive da-ta. If the first edge that the DPLL sees does not occur on a bit cell boundary, the DPLL will eventually lock on to the receive data, but it will take longer to do so. The DPLL may be programmed to operate in either of two modes, as selected by command in WR14. WR14 (7-5) = 111 for NRZI mode and WR14 (7-5) = 110 for FM mode Note that a channel or hardware reset disables the DPLL, selects the /RTxC pin as the clock source for the DPLL, and places it in the NRZI mode. As in the case of the clock source selection, the mode of operation should only be changed while the DPLL is disabled to prevent unpredictable results. In the NRZI mode, the DPLL clock must be 32 times the data rate. In this mode, the transmit and receive clock outputs of the DPLL are identical, and the clocks are phased so that UM011002-0808 UM011002-0808 Page 34 of 316 ISCC User Manual 35 the receiver samples the data in the middle of the bit cell. In NRZI mode, the DPLL does not require a transition in every bit cell, so this mode is useful for recovering the clocking information from NRZ and NRZI data streams. In the FM mode, the DPLL clock must be 16 times the data rate. In this mode the transmit clock output of the DPLL lags the receive clock outputs by 90 degrees to make the transmit and receive bit cell boundaries the same, because the receiver must sample FM data at one-quarter and three-quarters bit time. 3.5.1 DPLL Operation in the NRZI Mode To operate in NRZI mode, the DPLL must be supplied with a clock that is 32 times the data rate. The DPLL uses this clock, along with the receive data, to construct receive and transmit clock outputs that are phased to properly receive and transmit data. To do this, the DPLL divides each bit cell into four regions, and makes an adjustment to the count cycle of the 5-bit counter dependent upon in which region a transition on the receive data input occurred. This is shown in Figure 3-5. Bit Cell Count 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Connection Add One Count No Change Subtract One Count No Change DPLL Out Figure 3­8. DPLL in NRZI Mode Ordinarily, a bit cell boundary will occur between count 15 and count 16, and the DPLL output will cause the data to be sampled in the middle of the bit cell. However, four different situations may happen: The DPLL actually allows the transition marking a bit cell boundary to occur anywhere during the second half of count 15 or the first half of count 16 without making a correction to its count cycle. If the transition marking a bit cell boundary occurs between the middle of count 16 and count 31, the DPLL is sampling the data too early in the bit cell. In response to this, the DPLL extends its count by one during the next 0 to 31 counting cycle, which effectively moves the edge of the clock that samples the receive data closer to the center of the bit cell. UM011002-0808 UM011002-0808 Page 35 of 316 ISCC User Manual 36 If the transition occurs between count 0 and the middle of count 15, the output of the DPLL is sampling the data too late in the bit cell. To correct this, the DPLL shortens its count by one during the next 0 to 31 counting cycle, which effectively moves the edge of the clock that samples the receive data closer to the center of the bit cell. If the DPLL does not see any transition during a counting cycle, no adjustment is made in the following counting cycle. If an adjustment to the counting cycle is necessary, the DPLL modifies count 5, either deleting it or doubling it. Thus, only the LOW time of the DPLL output will be lengthened or shortened. While the DPLL is in search mode, the counter remains at count 16 where the DPLL outputs are both HIGH. The missing clock latches in the DPLL which may be accessed in RR10. They are not used in NRZI mode. An example of the DPLL in operation is shown in Figure 3-6. Receive Data DPLL Output Correction Windows +1 Count Length 32 -1 +1 32 -1 32 +1 -1 31 +1 -1 31 +1 -1 +1 31 -1 33 +1 -1 +1 33 -1 +1 33 Figure 3­9. DPLL Operating Example (NRZI Mode) 3.5.2 DPLL Operation in the FM Modes To operate in FM mode, the DPLL must be supplied with a clock that is 16 times the data rate. The DPLL uses this clock, along with the receive data, to construct receive and transmit clock outputs that are phased to receive and transmit data properly. In FM mode one cycle of the counter in the DPLL is a count from 0 to 31, but now each cycle corresponds to 2-bit cells. To make adjustments to remain in phase with the receive data, the DPLL divides a pair of bit cells into 5 regions, making the adjustment to the UM011002-0808 UM011002-0808 Page 36 of 316 ISCC User Manual 37 counter dependent upon which region the transition on the receive data input occurred. This is shown in Figure 3-7. Bit Cell Count 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Correction +1 Ignored No Change -1 No Change RX DPLL Out TX DPLL Out Figure 3­10. DPLL Operation in the FM Mode In FM mode, the transmit clock and receive clock outputs from the DPLL are not in phase. This is necessary to make the transmit and receive bit cell boundaries coincide, since the receive clock must sample the data one-fourth and three-fourths of the way through the bit cell. Ordinarily, a bit cell boundary will occur between count 15 or count 16, and the DPLL receive output will cause the data to be sampled at one-fourth and three-fourths of the way through the bit cell. However, four variations may happen: 4. The DPLL actually allows the transition marking a bit-cell boundary to occur anywhere during the second half of count 15 or the first half of count 16, without making a correction to its count cycle. 5. If the transition marking a bit cell boundary occurs between the middle of count 16 and the middle of count 19, the DPLL is sampling the data too early in the bit cell. In response to this, the DPLL extends its count by 1 during the next 0 to 31 counting cycle, which effectively moves the receive clock edges closer to where they should be. Any transitions occurring between the middle of count 19 in one cycle and the middle of count 12 during the next cycle are ignored by the DPLL. This is necessary to guarantee that any data transitions in the bit cells will not cause an adjustment to the counting cycle. 6. If no transition occurs between the middle of count 12 and the middle of count 19, the DPLL is probably not locked onto the data properly. When the DPLL misses an edge, the One Clock Missing bit is RR10, it is set to "1" and latched. It will hold this value until a Reset missing Clock command is issued in WR14 or until the DPLL is disabled UM011002-0808 UM011002-0808 Page 37 of 316 ISCC User Manual 38 or programmed to enter the Search mode. Upon missing this one edge, the DPLL takes no other action and does not modify its count during the next counting cycle. 7. If the DPLL does not see an edge between the middle of count 12 and the middle of count 19 in two successive 0 to 31 count cycles, a line error condition is assumed. If this occurs, the Two Clocks Missing bit in RR10 is set to "1" and latched. At the same time, the DPLL enters the Search mode. The DPLL makes the decision to enter Search mode during count 2, where both the receive clock and transmit clock outputs are LOW. This prevents any glitches on the clock outputs when search mode is entered. While in search mode, no clock outputs are provided by the DPLL. The Two Clocks Missing bit in RR10 is latched until a Reset Missing Clock command is issued in WR14, or until the DPLL is disabled or programmed to enter the Search mode. While the DPLL is disabled, the transmit clock output of the DPLL may be toggled by alternately selecting FM and NRZI move in the DPLL. The same is true of the receive clock. While the DPLL is in Search mode, the counter remains at count 16, where the receive output is LOW and the transmit output is LOW. This fact can be used to provide a transmit clock under software control since the DPLL is in Search mode while it is disabled. As in NRZI mode, if an adjustment to the counting cycle is necessary, the DPLL modifies count 5, either deleting it or doubling it. If no adjustment is necessary, the count sequence proceeds normally. From the above discussion, together with an examination of FM0 and FM1 data encoding, it should be obvious that only clock transitions should exist on the receive data pin when the DPLL is programmed to enter search mode. If this is not the case, the DPLL may attempt to lock on to the data transitions. With FM0 encoding this requires continuous "1s" received when leaving Search. In FM1 encoding, it is continuous "0s"; with Manchester encoded data this means alternating "1s" and "0s." With all three of these data encoding methods there will always be at least one transition in every bit cell, and in FM mode the DPLL is designed to expect this transition. 3.5.3 DPLL Operation and Encoding in the Manchester Mode The ISCC can encode Manchester data using the external logic shown in Figure 3-8, and it can decode Manchester data using the DPLL. Recall that Manchester encoded data contains a transition at the center of every bit cell; it is the direction of this transition that distinguishes a "1" from a "0." Hence, for Manchester data, the DPLL should be in FM mode, but the receiver should be set up to accept NRZ data. As with the FM modes, when in the Search Mode the data stream should contain only clock transitions. UM011002-0808 UM011002-0808 Page 38 of 316 ISCC User Manual 39 NRZ 3 b a 1 5 Manchester 4 2 Transmit Clock Transmit Clock NRZ 1 2 3 4 5 Figure 3­11. Encoding Manchester Data UM011002-0808 UM011002-0808 Page 39 of 316 ISCC User Manual 40 3.6 CLOCK SELECTION The ISCC can select several clock sources for internal and external use. Write Register 11 is the Clock Mode Control register for both the receive and transmit clocks. It determines the type of signal on the /SYNC and /RTxC pins and the direction of the /TRxC pin. The ISCC may be programmed to select one of several sources to provide the receive and receive clocks. The source of the receive clock is controlled by bits D6 and D5 of WR11. The receive clock may be programmed to come from the /RTxC pin, the /TRxC pin, the output of the baud rate generator, or the receive output of the DPLL. The source of the transmit clock is controlled by bits D4 and D3 of WR11. The transmit clock may be programmed to come from the /RTxC pin, the /TRxC pin, the output of the baud rate generator, or the transmit output of the DPLL. Ordinarily the /TRxC pin is an input, but it becomes an output if this pin has not been selected as the source for the transmitter or the receiver, and bit D2 of WR11 is set to "1." The selection of the signal provided on the /TRxC output pin is controlled by bits D1 and D0 of WR11. The /TRxC pin may be programmed to provide the output of the crystal oscillator, the output of the baud rate generator, the receive output of the DPLL or the actual transmit clock. If the output of the crystal oscillator is selected, but the crystal oscillator has not been enabled, the /TRxC pin will be driven HIGH. The option of placing the transmit clock signal on the /TRxC pin when it is an output allows access to the transmit output of the DPLL. Figure 3-9 shows a simplified schematic diagram of the circuitry used in the clock multiplexing. It shows the inputs to the multiplexer section, as well as the various signal inversions that occur in the paths to the outputs. UM011002-0808 UM011002-0808 Page 40 of 316 ISCC User Manual 41 OSC RX /SYNC Receiver OSC /RTxC TX /TRxC Transmitter Echo DPLL Baud Rate Generator Out Echo DPPL Tx DPLL Out Rx DPLL Out BRG Baud Rate Generator PCLK Figure 3­12. Clock Multiplexer Selection of the clocking options may be done anywhere in the initialization sequence, but the final values must be selected before the receiver, transmitter, baud rate generator, or DPLL are enabled to prevent problems from arbitrarily narrow clock signals out of the multiplexers. The same is true of the crystal oscillator, in that the output should be allowed to stabilize before it is used as a clock source. Also shown are the edges used by the receiver, transmitter, baud rate generator and DPLL to sample or send data or otherwise change state. For example, the receiver samples data on the falling edge, but since there is an inversion in the clock path between the /RTxC pin and the receiver, a rising edge of the /RTxC pin samples the data for the receiver. UM011002-0808 UM011002-0808 Page 41 of 316 ISCC User Manual 42 /SYNC Pin B R G External Crystal 16x Output TxC RxC /RTxC Pin /TRxC Pin SCC Figure 3­13. Async Transmission, 16x Clock Mode Using External Crystal D7 D6 D5 D4 D3 D2 D1 D0 WR11 1 1 0 1 0 1 1 0 /TRxC Out = BRG Output /TRxC Pin = Output Pin Tx Clock = BRG Output Rx Clock = BRG Output Using External Crystal D1 WR14 0 BRG Clock Source = /RTxC or XTAL Oscillator NRZ Data SYNC Modem TxC RxD Pin 1x /RTxC Pin RxC SCC Figure 3­14. Async Transmission, 1x Clock Rate, NRZ Data Encoding UM011002-0808 UM011002-0808 Page 42 of 316 ISCC User Manual 43 /SYNC Pin B External Crystal /RTxC Pin R G 16x Data Rate Rxc L L RxD Pin D P Txc RxD Figure 3­15. Asynchronous Transmission, 1x Clock Rate, FM Data Encoding Fig 3-10 shows the clock set up for asynchronous transmission, 16x clock mode using the on chip oscillator with an external crystal. The registers involved are WR11 and WR14 and the figure shows the programming in these registers. Figure 3-11 shows asynchronous communication where a 1x clock is obtained from an external MODEM. The data encoding is NRZ. Note: that the BRG is not used under this configuration. The x1 mode in Asynchronous mode is a combination of both synchronous and asynchronous transmission. The data are clocked by a common timing base, but characters are still framed with Start and Stop bits. Because the receiver waits for one clock period after detecting the first High-to-Low transition before beginning to assemble characters, the data and clock must be synchronized externally. The x1 mode is the only mode in which a data encoding method other than NRZ may be used. Figure 3-12 shows the use of the DPLL to derive a 1x clock from the data. In this example: · · UM011002-0808 UM011002-0808 The DPLL clock input = BRG output (x16 the data rate) WR14. The DPLL clock output = RxC (receiver clock) WR11. Page 43 of 316 ISCC User Manual 44 · · Set FM mode WR14. Set FM mode WR10. 3.7 CRYSTAL OSCILLATORS For a given channel, if bit D7 of WR11 is set to 1, the crystal oscillator is enabled and a high-gain amplifier is connected between the /RTxC pin and the /SYNC pin. While the crystal oscillator is enabled, anything that has selected /RTxC as its clock source will automatically be connected to the output of the crystal oscillator. This also makes the /SYNC pin unavailable for other use. In synchronous modes, no sync pulse is output, and the External Sync mode cannot be selected. In asynchronous modes, the state of the Sync/Hunt bit in RR0 is no longer controlled by the /SYNC pin. Instead, the Sync/Hunt bit is forced to "0." The crystal oscillator requires some finite time to stabilize and must be allowed to stabilize before it is used as a clock source. The External Crystal used should operate in parallel resonance. UM011002-0808 UM011002-0808 Page 44 of