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ULTRASPARC-II Datasheet

Part Manufacturer Description PDF Type
UltraSPARC-II Sun Microelectronics UltraSPARC-II CPU Module Original
UltraSPARC-IIi Sun Microelectronics UltraSPARC-IIi CPU Module Original

ULTRASPARC-II

Catalog Datasheet MFG & Type PDF Document Tags

SPARC v9 architecture BLOCK DIAGRAM

Abstract: UltraSPARC ii -Bit Microprocessor With VIS DESCRIPTION The STP1031, UltraSPARC­II, is a high-performance, highly-integrated , , instructions before and after a conditional branch) can be issued in the same group. UltraSPARC-II is part of , technology, the UltraSPARC-II provides a higher clock frequency, multiple SRAM modes and System-to-Processor , software compatibility with existing UltraSPARC-I based systems. UltraSPARC-II also implements the , add FP divide Graphics Unit (GRU) Memory Interface Unit (MIU) UltraSPARC­II Bus Figure 1
Sun Microelectronics
Original
STP1031LGA SPARC v9 architecture BLOCK DIAGRAM UltraSPARC ii Sinak h30 sparc sparc v7 1997AD32 787-P

ultrasparc

Abstract: UltraSPARC " -!! Data Buffer (UDB-II) DATA SHEET D e s c r ip t io n The UltraSPARC-II Data Buffer (UDB-II) consists of two identical ASICs connecting the UltraSPARC-II micro processor and its , . Companion Device for 250/300 MHz UltraSPARC-II Systems Features · Isolates the processor from the system , /300 MHz UltraSPARC-II Systems UDB-II Interface UDB-II Interlace Figure 1. UDB-II Module Block , delivery rates of the E-Cache and that of the interconnect. UltraSPARC-II has a second-level cache of at
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ultrasparc STP1081ABGA SYSDATAJ59 SYSDATAI32 256-P OOOOOOOO60 1V11V
Abstract: DATA SHEET Complete 296 MHz CPU, 2.0 MB E-Cache, UDB-II D e s c r ip t io n The UltraSPARC-II m , the UltraSPARC Port Architecture (UPA) interconnect bus. The m odule consists of one UltraSPARC-II microprocessor, two UltraSPARC-II Data Buffer chips, one 32 K x 36 tag SRAM , four 128k K x 36 data SRAM s, and , frequency.The m odule is available w ith the UltraSPARC-II run­ ning at 296M Hz. The interface to the m odule , The STP5211, UltraSPARC-II CPU M odule consists of the follow ing components: â'¢ UltraSPARC-II -
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STP5212 MC100LVE210 SPARC-11 H-261 STP5212UPA-300 100MH

MCE-100

Abstract: STP1081 E-Cache, UDB-II DESCRIPTION The UltraSPARC-II module is a high performance, SPARC V9 compliant, small , . The module consists of one UltraSPARC-II microprocessor, one UltraSPARC-II Data Buffer (consisting of , available with the UltraSPARC-II running at 248 MHz. The interface to the module is through a high-speed standard edge connector. Features Benefits · High performance UltraSPARC-II CPU Module · , multiprocessing · Range of scalable systems can be built · 1.0 Megabyte E-Cache · UltraSPARC-II pipelined
Sun Microelectronics
Original
STP5211UPA-250 STP1081 MCE-100 MC100LVE111 248MH 128-B

SPARC v9 architecture BLOCK DIAGRAM

Abstract: UltraSPARC ii STP1031 July 1997 UltraSPARCTM-II DATA SHEET DESCRIPTION The STP1031, UltraSPARC­II, is a , . UltraSPARC-II is part of a second generation of UltraSPARC pipeline-based products. In addition to using a new process technology, the UltraSPARC-II provides a higher clock frequency, multiple SRAM modes and , provides software compatibility with existing UltraSPARC-I based systems. UltraSPARC-II also implements the , Interface Unit (MIU) UltraSPARC­II Bus Figure 1. Functional Block Diagram 214 July 1997
Sun Microsystems
Original

instruction set Sun SPARC T3

Abstract: Sun UltraSparc T2 v9 64-Bit Microprocessor With VIS Description The STP1031, UltraSPARC-II, is a high-performance , before and after a conditional branch) can be issued in the same group. UltraSPARC-II is part of a , , the UltraSPARC-II provides a higher clock frequency, multiple SRAM modes and System-to-Processor clock , compatibility with existing UltraSPARC-I based systems. UltraSPARC-II also implements the SPARC-V9 Prefetch , In a single chip implementation, UltraSPARC-II integrates the following components (see Figure 1): â
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instruction set Sun SPARC T3 Sun UltraSparc T2 instruction set Sun SPARC T5 Sun UltraSparc Sun UltraSparc T1

MCE-100

Abstract: ULTRASPARC-II E-Cache, UDB-II DESCRIPTION The UltraSPARC-II module is a high performance, SPARC V9 compliant, small , . The module consists of one UltraSPARC-II microprocessor, two UltraSPARC-II Data Buffer chips, one 32 K , which yields a 3:1 ratio to the UPA frequency.The module is available with the UltraSPARC-II running at , Benefits · High performance UltraSPARC-II CPU Module · Deliver 12.1 SPECint95 (est.), 15.5 SPECfp95 , · 2.0 Megabyte E-Cache · UltraSPARC-II Pipelined E-Cache Interface delivering high performance
Sun Microelectronics
Original
BGA 328 Motherboard socket 754 MCE100 296MH

STP1081

Abstract: 75193 /300 MHz UltraSPARC-II Systems DESCRIPTION The UltraSPARC-II Data Buffer (UDB-II) consists of two identical ASICs connecting the UltraSPARC-II microprocessor and its E-Cache to the system data bus (i.e , UltraSPARCTM-II Data Buffer (UDB-II) Companion Device for 250/300 MHz UltraSPARC-II Systems STP1081 SRAM , the interconnect. UltraSPARC-II has a second-level cache of at minimum 512 Kilobytes. This , 1997 UltraSPARCTM-II Data Buffer (UDB-II) Companion Device for 250/300 MHz UltraSPARC-II Systems
Sun Microsystems
Original
75193 40N20 STP1081ABGA-125 STP1081ABGA-150
Abstract: DATA SHEET Complete 248 MHz CPU, 1.0 MB E-Cache, UDB-II D e s c r ip t io n The UltraSPARC-II m , the UltraSPARC Port Architecture (UPA) interconnect bus. The m odule consists of one UltraSPARC-II microprocessor, one UltraSPARC-II Data Buffer (consisting of two UDB-II m icrochips), one 32 K x 36 tag SRAM , ratio to the UPA frequency.The m odule is available w ith the UltraSPARC-II run­ ning at 248 MHz. The , ultiprocessing â'¢ Range of scalable system s can be built â'¢ 1.0 M egabyte E-Cache â'¢ UltraSPARC-II -
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5211UPA-250

in138

Abstract: SPARC v9 architecture BLOCK DIAGRAM io n The UltraSPARC-II module is a high performance, SPARC V9 compliant, small form factor processor , one UltraSPARC-II microprocessor, two UltraSPARC-II Data Buffer chips, one 32 K x 36 tag SRAM, four , to the UPA frequency.The module is available with the UltraSPARC-II run ning at 296MHz. The interface , E-Cache, UDB-II Features · High performance UltraSPARC-II CPU Module · Programmable UPA bus speed · , Gigabytes/sec · Range of scalable systems can be built · UltraSPARC-II Pipelined E-Cache Interface
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in138 cpu lga

MCE-100

Abstract: MCE100 STP5212 July 1997 UltraSPARCTM-II CPU Module DATA SHEET DESCRIPTION The UltraSPARC-II module , UltraSPARC Port Architecture (UPA) interconnect bus. The module consists of one UltraSPARC-II microprocessor, two UltraSPARC-II Data Buffer chips, one 32 K x 36 tag SRAM, four 128k K x 36 data SRAMs, and an , available with the UltraSPARC-II running at 296MHz. The interface to the module is through a high-speed , UltraSPARC-II CPU Module · Programmable UPA bus speed · SPARC V9 Compliant · Implements Visual Instruction Set
Sun Microsystems
Original
Abstract: , UltraSPARC-II, is a high-perform ance, highly-integrated superscalar processor implementing the SPARC-V9 64 , branch) can be issued in the same group. UltraSPARC-II is part of a second generation of UltraSPARC pipeline-based products. In addition to using a new process technology, the UltraSPARC-II provides a higher , existing UltraSPARC-1 based systems. UltraSPARC-II also im plem ents the SPARC-V9 Prefetch instruction , , UltraSPARC-II integrates the follow ing com ponents (see Figure 1): â'¢ Prefetch, branch prediction and -
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1031LG
Abstract: High-Capacity, Two-Speed Data Transfer D e s c r ip t io n The UltraSPARC-II Data Buffer (UDB-II) consists of two identical integrated circuit microchips connecting the UltraSPARC-II microprocessor and its , of the E-Cache and that of the interconnect. UltraSPARC-II has a second-level cache of at m inim um , Transfer F u n c t io n a l O v e r v ie w Data Buffering UltraSPARC-II supports m ultiple outstanding , data com es from the store buffer of the UltraSPARC-II. The processor m akes successive stores to the -
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ASAM/CCR-232 1081ABG

Sun Enterprise 250

Abstract: MC100LVE210 DESCRIPTION UltraSPARC-II CPU The UltraSPARCTM-II CPU is the second generation in the UltraSPARCTM s-series , E-Cache SME5222AUPA-400 DATA BUFFER DESCRIPTION UltraSPARC-II Data Buffer (UDB-II) The UltraSPARCTM-II module has two UltraSPARC-II data buffers (UDB-II) - each a 256 pin BGA device - for a system bus , clocked with the same clock delivered to UltraSPARC-II (1/2 of the CPU pipeline frequency). EXTERNAL , , 2.0 MB E-Cache SME5222AUPA-400 MODULE COMPONENT OVERVIEW The UltraSPARC-II CPU Module
Sun Microsystems
Original
Sun Enterprise 250 RT0201

BGA 48 "8 x 8" memory micron

Abstract: MC100LVE210 CPU Module 450 MHz CPU, 4.0 MByte E-Cache CPU DESCRIPTION UltraSPARC-II CPU The UltraSPARCTM-II , DESCRIPTION UltraSPARC-II Data Buffer (UDB-II) The UltraSPARCTM-II, 450MHz CPU module has two UltraSPARC-II , the same clock delivered to UltraSPARC-II (1/2 of the CPU pipeline frequency). EXTERNAL CACHE , components: · · · · · · UltraSPARCTM-II, 450MHz CPU UltraSPARC-II Data Buffer (UDB-II) 4.0 , ADDR [17:0] + Control Tag SRAM DATA [24:0] UltraSPARC-II CPU UPA ADDR [35:0] + Control SRAM
Sun Microsystems
Original
SME5224AUPA-450 BGA 48 "8 x 8" memory micron STP2202ABGA 450MH
Abstract: -400 UltraSPARCTM-II CPU Module 400 MHz CPU, 4.0 MB E-Cache CPU DESCRIPTION UltraSPARC-II CPU The UltraSPARCTM-II , UltraSPARC-II Data Buffer (UDB-II) The UltraSPARCTM-II module has two UltraSPARC-II data buffers (UDB-II) - each , system side. The CPU side of the UDB-II is clocked with the same clock delivered to UltraSPARC-II (1/2 of , components: · · · · · · UltraSPARCTM-II CPU at 400 MHz UltraSPARC-II Data Buffer (UDB-II) 4.0 Megabyte , Tag SRAM DATA [24:0] UltraSPARC-II CPU UPA ADDR [35:0] + Control SRAM ADDR [19:0] + Control Tag Sun Microsystems
Original
SME5224AUPA-400 400MH
Abstract: E-Cache CPU DESCRIPTION UltraSPARC-II CPU The UltraSPARCâ"¢-II, 480 MHz CPU is the second generation , '¢ UltraSPARCâ"¢-II, 480 MHz CPU UltraSPARC-II Data Buffer (UDB-II) Eight Megabyte E-cache, made up of eight (512K Î , is illustrated in Figure 1. Tag SRAM ADDR [17:0] + Control Tag SRAM DATA [24:0] UltraSPARC-II , UltraSPARC-II Data Buffer (UDB-II) The UltraSPARCâ"¢-II, 480 MHz CPU module has two UltraSPARC-II data buffers , UltraSPARC-II (1/2 of the CPU pipeline frequency). EXTERNAL CACHE DESCRIPTION The external cache is Sun Microsystems
Original
SME5224BUPA-480

Sun Enterprise 250

Abstract: MC100LVE210 DESCRIPTION UltraSPARC-II CPU The UltraSPARCTM-II CPU is the second generation in the UltraSPARCTM s-series , DESCRIPTION UltraSPARC-II Data Buffer (UDB-II) The UltraSPARCTM-II module has two UltraSPARC-II data buffers , UltraSPARC-II (1/2 of the CPU pipeline frequency). EXTERNAL CACHE DESCRIPTION The external cache (E-cache , UltraSPARC-II CPU at 360 MHz UltraSPARC-II Data Buffer (UDB-II) 4.0 Megabyte E-cache, made up of eight (256K X , DATA [24:0] UltraSPARC-II CPU UPA ADDR [35:0] + Control SRAM ADDR [19:0] + Control SRAM
Sun Microsystems
Original
SME5224AUPA-360

UltraSPARC ii

Abstract: ( UltraSPARC-II Data Bujjer (UDB-II) Data Sh eet O c t o b e r 1 996 STP1081 S un M ic r o e , , Two-Speed Data Transfer D esc r ip tio n The UltraSPARC-II Data Buffer (UDB-II) consists of two identical integrated circuit microchips connecting the UltraSPARC-II m icroprocessor and its E-Cache to the slower , systembus Interlace to the UltraSPARC-II bus B e n e fits · High performance: ease of design * Fully , delivery rates of the E-Cache and that of the interconnect. UltraSPARC-II has a second-level cache of at m
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STP2202ABGA

Abstract: RT0201 -400 UltraSPARCTM-II CPU Module 400 MHz CPU, 4.0 MB E-Cache CPU DESCRIPTION UltraSPARC-II CPU The UltraSPARCTM-II , -400 DATA BUFFER DESCRIPTION UltraSPARC-II Data Buffer (UDB-II) The UltraSPARCTM-II module has two UltraSPARC-II data buffers (UDB-II) - each a 256 pin BGA device - for a UPA Interconnect system bus width of , the same clock delivered to UltraSPARC-II (1/2 of the CPU pipeline frequency). EXTERNAL CACHE , · UltraSPARCTM-II CPU at 400 MHz UltraSPARC-II Data Buffer (UDB-II) 4.0 Megabyte E-cache, made
Sun Microsystems
Original
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