UG388 XC6SLX75 XC6SLX75T CPG196 CSG484 UG416 DS643 DSP48A1 DS162 TQG144 CSG225 - Datasheet Archive

 

Memory Controller User Guide UG388 (v2.1) March 4, 2010 Xilinx is disclosing this user guide, manual, release note, and/or

 

Spartan-6 FPGA Memory Controller User Guide UG388 UG388 (v2.1) March 4, 2010 Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the Documentation in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx. Xilinx expressly disclaims any liability arising out of your use of the Documentation. Xilinx reserves the right, at its sole discretion, to change the Documentation without notice at any time. Xilinx assumes no obligation to correct any errors contained in the Documentation, or to advise you of any corrections or updates. Xilinx expressly disclaims any liability in connection with technical support or assistance that may be provided to you in connection with the Information. THE DOCUMENTATION IS DISCLOSED TO YOU "AS-IS" WITH NO WARRANTY OF ANY KIND. XILINX MAKES NO OTHER WARRANTIES, WHETHER EXPRESS, IMPLIED, OR STATUTORY, REGARDING THE DOCUMENTATION, INCLUDING ANY WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NONINFRINGEMENT OF THIRD-PARTY RIGHTS. IN NO EVENT WILL XILINX BE LIABLE FOR ANY CONSEQUENTIAL, INDIRECT, EXEMPLARY, SPECIAL, OR INCIDENTAL DAMAGES, INCLUDING ANY LOSS OF DATA OR LOST PROFITS, ARISING FROM YOUR USE OF THE DOCUMENTATION. © Copyright 2009­2010 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. PCI, PCI Express, PCIe, and PCI-X are trademarks of PCI-SIG. All other trademarks are the property of their respective owners. Revision History The following table shows the revision history for this document. Date Version Revision 05/28/09 1.0 Initial Xilinx release. 08/18/09 1.1 · Removed references to MCB per-bit deskew calibration. · Chapter 1: · Added XC6SLX75 XC6SLX75 and XC6SLX75T XC6SLX75T devices and CPG196 CPG196, CSG484 CSG484, and FG(G)900 packages to Table 1-2, page 13. · Chapter 2: · In Figure 2-2, page 18, changed Configuration 5 to 128-bit bidirectional. · Added note regarding board design requirements under Table 2-9, page 30. · Chapter 3: · Updated first paragraph in Supported Memory Devices, page 35. · Added note to Clocking, page 37. · Added subsection Additional Board Design Requirements, page 42. · Chapter 4: · Moved Note 1 from Figure 4-1, page 44 to below the figure. · Added Note 2 about calibration logic. · Appendix A: · Updated JEDEC specification links in Memory Standards, page 63. Spartan-6 FPGA Memory Controller www.xilinx.com UG388 UG388 (v2.1) March 4, 2010 Date Version Revision 12/02/09 2.0 · Moved Chapter 3, "Getting Started," and Chapter 6, "Debugging MCB Designs," and to UG416 UG416, Spartan-6 FPGA Memory Interface Solutions User Guide. · Changed introduction in About This Guide, page 7. · Chapter 1: · Revised Note 1 in Table 1-1, page 12 to refer to the data sheet for specific values. · Added Note 2 to Table 1-2, page 13. · Chapter 2: · In Table 2-3, changed the description and values of the C_MC_CALIBRATION_MODE attribute on page 25. · Appended two sentences to exception (a) on page 30. · Chapter 3: · Replaced text regarding the speed of the calibration clock, calib_clk, on page 38. · Chapter 4: · Rephrased Note 1 under Figure 4-1, page 44. · In the third paragraph after the Notes on page 44, removed the sentence about calibration logic. · Added note after first paragraph of Calibration, page 45. · Removed portion of sentence about calibration logic in first paragraph of Phase 2: DQS Centering, page 46. · Added paragraph above Figure 4-13, page 56. · Added note on page 59 before Table 4-5. 01/05/10 2.0.1 03/04/10 2.1 Revised document hyperlinks. Chapter 1: In the Features and Benefits section, added bullet for input termination automatic calibration to section. In Table 1-1, added parameters in Data Rate Minimum column and updated table note 2. In Table 1-2, revised table note 1. Chapter 2: In Table 2-2, added "THREEQUARTERS" as a possible value for the Memory Drive Strength attribute, and modified the description for Memory Burst Length attribute, indicating that DDR3 is always set to 8. In the Clock, Reset, and Calibration Signals section, added calibration to the heading name, introductory text, and caption of Table 2-4. In Table 2-4, changed the signal name BUFPLL to BUFPLL_MCB, changed the signal name sys_rst to async_rst, and added signals mcb_drp_clk and calib_done. In the Memory Device Interface section, modified descriptive text related to RZG and ZIO pins. Added clarifying text in Note (page 30) relating to unused pins from an active MCB reverting to general-purpose I/O. In Table 2-9, modified descriptions for the rzq and zio signals. Chapter 3: In Table 3-1, removed memory devices MT41K128M8xx-25 and MT41K256M4xx-25. In the Clocking section, added text related to MIG/EDK generation of clocking infrastructure. Clarified text related to location of externally driven PLL. Revised text related to calibration clock. In Figure 3-3, changed signal name from calib_clk to mcb_drp_clk. Changed the end of the first sentence after Figure 3-3. Changed the first sentence about the calibration related clock on page 38. Under Figure 3-4, added clarifying text related to using bank1 MCB pins as BPI pins. In the Additional Board Design Requirements section on page 42, clarified requirements for pull-down resistors on the RESET, CKE, and ODT signals. Added Simultaneous Switching Output Considerations section. Chapter 4: In the Phase 1: Input Termination section, added clarifying text related to input termination of the RZQ and ZIO pins. In the Addressing section, added clarifying text related to offsetting the starting address location using the write data mask inputs. Added the Read Latency and Suspend sections. Appendix A: Updated JEDEC URLs. UG388 UG388 (v2.1) March 4, 2010 www.xilinx.com Spartan-6 FPGA Memory Controller Spartan-6 FPGA Memory Controller www.xilinx.com UG388 UG388 (v2.1) March 4, 2010 Table of Contents Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Preface: About This Guide Guide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Additional Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Additional Support Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Chapter 1: Memory Controller Block Overview Scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Features and Benefits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Device Family Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Supported Memory Configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Software and Tool Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Chapter 2: MCB Functional Description Architecture Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Port Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Selecting a Port Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Programmability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Interface Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 User (Fabric Side) Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock, Reset, and Calibration Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Command Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write Datapath . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Read Datapath . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Self-Refresh Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory Device Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 25 26 27 28 29 30 Chapter 3: Designing with the MCB Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 CORE Generator Tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Supported Memory Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Resource Utilization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Migration and Banking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Spartan-6 FPGA Memory Controller UG388 UG388 (v2.1) March 4, 2010 www.xilinx.com 35 36 37 37 39 5 PCB Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 General Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data, Data Mask, and Data Strobe Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Address, Control and Clock Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Additional Board Design Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Simultaneous Switching Output Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 41 41 42 42 Chapter 4: MCB Operation Startup Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Phase 1: Input Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Phase 2: DQS Centering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Phase 3: Continuous DQS Tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Command Path Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write Path Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Read Path Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 48 49 50 51 52 Simple Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Simple Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Read Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Self Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Suspend Mode without DRAM Data Retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Suspend Mode with DRAM Data Retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Additional Suspend Mode Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Byte Address to Memory Address Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Transaction Ordering and Coherency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Appendix A: References Memory Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 PCB Layout and Signal Integrity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 6 www.xilinx.com Spartan-6 FPGA Memory Controller UG388 UG388 (v2.1) March 4, 2010 Preface About This Guide This document describes the Spartan®-6 FPGA memory controller block (MCB). Complete and up-to-date documentation of the Spartan-6 family of FPGAs is available on the Xilinx website at http://www.xilinx.com/products/spartan6/index.htm. To implement an MCB based memory interface, one of the two supported design tool flows must be followed: 1. Memory Interface Generator (MIG) For traditional (non-embedded) FPGA designs, refer to UG416 UG416, Spartan-6 FPGA Memory Interface Solutions User Guide for information on implementing an MCB based memory interface using the MIG tool within the CORE GeneratorTM software. This document also contains information on debugging MCB interfaces. 2. Embedded Development Kit (EDK) For embedded designs, refer to DS643 DS643, Multi-Port Memory Controller (MPMC) for details on how the MCB is used to implement the MPMC within the EDK environment. Guide Contents This manual contains the following chapters: · Chapter 1, Memory Controller Block Overview, introduces the Spartan-6 FPGA MCB. · Chapter 2, MCB Functional Description, describes the architecture, signal interface, and possible configurations of the MCB. · Chapter 3, Designing with the MCB, provides details on how to incorporate the MCB into a Spartan-6 design, with specifics on how to customize the block for a given application. · Chapter 4, MCB Operation, explains how the MCB functions in various operational modes: startup, calibration, refresh, precharge, standard read/write transactions, etc. · Appendix A, References, contains links to additional documentation relevant to memory interface design. Additional Documentation The following documents are also available for download at http://www.xilinx.com/products/spartan6/index.htm. · Spartan-6 Family Overview This overview outlines the features and product selection of the Spartan-6 family. Spartan-6 FPGA Memory Controller UG388 UG388 (v2.1) March 4, 2010 www.xilinx.com 7 Preface: About This Guide · Spartan-6 FPGA Data Sheet: DC and Switching Characteristics This data sheet contains the DC and Switching Characteristic specifications for the Spartan-6 family. · Spartan-6 FPGA Packaging and Pinout Specifications This specification includes the tables for device/package combinations and maximum I/Os, pin definitions, pinout tables, pinout diagrams, mechanical drawings, and thermal specifications. · Spartan-6 FPGA Configuration User Guide This all-encompassing configuration guide includes chapters on configuration interfaces (serial and parallel), multi-bitstream management, bitstream encryption, boundary-scan and JTAG configuration, and reconfiguration techniques. · Spartan-6 FPGA SelectIO Resources User Guide This guide describes the SelectIOTM resources available in all Spartan-6 devices. · Spartan-6 FPGA Clocking Resources User Guide This guide describes the clocking resources available in all Spartan-6 devices, including the DCMs and the PLLs. · Spartan-6 FPGA Block RAM Resources User Guide This guide describes the Spartan-6 device block RAM capabilities. · Spartan-6 FPGA Configurable Logic Block User Guide This guide describes the capabilities of the configurable logic blocks (CLBs) available in all Spartan-6 devices. · Spartan-6 FPGA GTP Transceivers User Guide This guide describes the GTP transceivers available in Spartan-6 LXT FPGAs. · Spartan-6 FPGA DSP48A1 DSP48A1 Slice User Guide This guide describes the architecture of the DSP48A1 DSP48A1 slice in Spartan-6 FPGAs and provides configuration examples. · Spartan-6 FPGA PCB Design Guide This guide provides information on PCB design for Spartan-6 devices, with a focus on strategies for making design decisions at the PCB and interface level. Additional Support Resources To find additional documentation, see the Xilinx website at: . To search the Answer Database of silicon, software, and IP questions and answers, or to create a technical support WebCase, see the Xilinx website at: http://www.xilinx.com/support. 8 www.xilinx.com Spartan-6 FPGA Memory Controller UG388 UG388 (v2.1) March 4, 2010 Chapter 1 Memory Controller Block Overview Scope This chapter provides an overview of the Spartan®-6 FPGA memory controller block (MCB). It contains the following sections: · Introduction · Features and Benefits · Block Diagram · Performance · Device Family Support · Supported Memory Configurations · Software and Tool Support Introduction The MCB is a dedicated embedded block multi-port memory controller that greatly simplifies the task of interfacing Spartan-6 devices to the most popular memory standards. The MCB provides significantly higher performance, reduced power consumption, and faster development times than equivalent IP implementations. The embedded block implementation of the MCB conserves valuable FPGA resources and allows the user to focus on the more unique features of the FPGA design. Features and Benefits The key features and benefits of the Spartan-6 FPGA memory controller block are: · DDR, DDR2, DDR3, and LPDDR (Mobile DDR) memory standards support · Up to 800 Mb/s (400 MHz double data rate) performance · Up to four MCB cores in a single Spartan-6 device. Each MCB core supports: · · Memory densities up to 4 Gb · · 4-bit, 8-bit, or 16-bit single component memory interface Up to 12.8 Gb/s aggregate bandwidth Configurable dedicated multi-port user interface to FPGA logic · 1 to 6 ports per MCB depending on configuration · 32-, 64-, or 128-bit data bus options · Bidirectional (R/W) or unidirectional (W only or R only) port options Spartan-6 FPGA Memory Controller UG388 UG388 (v2.1) March 4, 2010 www.xilinx.com 9 Chapter 1: Memory Controller Block Overview · Memory Bank Management · · Up to eight memory banks open simultaneously for greater controller efficiency Embedded controller and physical interface (PHY), providing: · · Low power · · Predictable timing Guaranteed performance Predefined pinouts (I/O locations) for each MCB · · · Simplified board design Predefined I/Os not used in an MCB interface become general-purpose I/Os (see page 30 for details). Common memory device options and attributes support · · On-Die Termination (ODT) · CAS latency · Self refresh (including partial array) · Refresh interval · · Programmable drive strength Write recovery time Automatic delay calibration of memory strobe and read data inputs · Adjusts DQS (strobe) to DQ (data) timing relationship for optimal read performance · Optional automatic calibration of FPGA on-chip input termination for optimal signal integrity · Supported by Xilinx® CORE GeneratorTM and Embedded Development Kit (EDK) design tools · Memory Interface Generator (MIG) tool within the CORE Generator software simplifies the MCB design flow · Embedded designs can also access the MCB via the multi-port memory controller (MPMC) IP in the EDK tool Block Diagram The block diagram in Figure 1-1 shows the major architectural components of the MCB core. Throughout this document, the MCB is described as provided to the user by the memory IP tools within the CORE Generator software or EDK environment. These tools typically produce top-level "wrapper" files that incorporate the embedded block memory controller primitive and any necessary soft logic and port mapping required to deliver the complete solution. For example, in Figure 1-1, the physical interface of the MCB uses the capabilities of the general I/O block (IOB) to implement the external interface to the memory. General I/O clock network resources are also used. 10 www.xilinx.com Spartan-6 FPGA Memory Controller UG388 UG388 (v2.1) March 4, 2010 Block Diagram X-Ref Target - Figure 1-1 Spartan-6 FPGA IP Wrapper CMD FIFO 0 CMD FIFO 1 CMD FIFO 2 Arbiter Controller CMD FIFO 3 CMD FIFO 4 CMD FIFO 5 32-Bit Unidirectional Datapath IOB 32-Bit Bidirectional Memory Dedicated Routing 32-Bit Bidirectional I/O Clocking Network User Logic PHY DDR DDR2 DDR3 LPDDR 32-Bit Unidirectional 32-Bit Unidirectional Calibration Logic 32-Bit Unidirectional UG388 UG388_c1_01_050409 Figure 1-1: Spartan-6 FPGA Memory Controller Block (IP Wrapper View) The single data rate (SDR) user interface to the MCB inside the FPGA can be configured for one to six ports, with each port consisting of a command interface and a read and/or write data interface. The two 32-bit bidirectional and four 32-bit unidirectional hardware-based ports inside the MCB can be grouped to create five different port configurations. Other major components of the MCB include: · Arbiter Determines which port currently has priority for accessing the memory device. · Controller Primary control block that converts the simple requests made at the user interface into the necessary instructions and sequences required to communicate with the memory. · Datapath Handles the flow of write and read data between the memory device and the user logic. · Physical Interface (PHY) Converts the controller instructions into the actual timing relationships and DDR signaling necessary to communicate with the memory device. · Calibration Logic Calibrates the PHY for optimal performance and reliability. Spartan-6 FPGA Memory Controller UG388 UG388 (v2.1) March 4, 2010 www.xilinx.com 11 Chapter 1: Memory Controller Block Overview Performance The dedicated MCB cores in Spartan-6 devices enable significantly higher performance levels than equivalent IP solutions implemented in the FPGA logic. Because memory bandwidth is often the bottleneck in overall system performance, the MCB cores were specifically engineered for users looking to maximize memory performance in a low-cost, low-power FPGA device. Each MCB core supports the memory interface data rates and total memory bandwidth specifications shown in Table 1-1. Peak bandwidth for a single MCB memory interface is calculated for the three supported interface widths. Table 1-1: Memory Interface Data Rates and Peak Bandwidth for Each MCB Memory Type Data Rate: Mb/s DDR (MHz Clock) Peak Bandwidth per MCB Interface (Gb/s) Minimum Maximum(1) 4-Bit 8-Bit 16-Bit DDR 167 Mb/s(2) (83.3 MHz) 400 Mb/s (200 MHz) 1.6 Gb/s 3.2 Gb/s 6.4 Gb/s DDR2 250 Mb/s(2) (125 MHz) 800 Mb/s (400 MHz) 3.2 Gb/s 6.4 Gb/s 12.8 Gb/s DDR3 606 Mb/s(2) (303 MHz) 800 Mb/s (400 MHz) 3.2 Gb/s 6.4 Gb/s 12.8 Gb/s LPDDR 20 Mb/s(2) (10 MHz) 400 Mb/s (200 MHz) 1.6 Gb/s 3.2 Gb/s 6.4 Gb/s Notes: 1. The maximum MCB data rate shown does not apply to all speed grades. Refer to DS162 DS162, Spartan-6 FPGA Data Sheet: DC and Switching Characteristics, for performance by speed grade. 2. The minimum frequency requirement of the MCB is dictated by the minimum frequency specification for the memory standard. See Memory Standards in Appendix A for links to the relevant JEDEC specifications. 12 www.xilinx.com Spartan-6 FPGA Memory Controller UG388 UG388 (v2.1) March 4, 2010 Device Family Support Device Family Support The number of MCBs available in a given Spartan-6 device is determined by the density range that the device falls within. The smallest device (XC6SLX4) contains no MCBs, midrange density devices contain two MCBs, and the largest devices contain four MCBs. Table 1-2 shows the number of MCBs supported in each device/package combination. Note: The MCB is designed to interface to a single x4, x8, or x16 memory component. Multiple component interfaces to a single MCB (for example, two x8 memories interfacing to an MCB in x16 mode) are not supported. Table 1-2: . MCB Support by Device / Package Combination Package Device TQG144 TQG144 CPG196 CPG196 CSG225 CSG225 XC6SLX4 0 0 0 XC6SLX9 0 0 2(1) 2 2 0 2(1) 2 2 2 2 2 2 2 2 2 XC6SLX75 XC6SLX75 2(2) 2(2) 4 XC6SLX100 XC6SLX100 2(2) 2(2) 4 XC6SLX150 XC6SLX150 2(2) 2(2) 4 XC6SLX16 XC6SLX16 XC6SLX25 XC6SLX25 XC6SLX45 XC6SLX45 FT(G)256 CSG324 CSG324 FG(G)484 CSG484 CSG484 FG(G)676 FG(G)900 4 XC6SLX25T XC6SLX25T 2 2 XC6SLX45T XC6SLX45T 2 2 2 XC6SLX75T XC6SLX75T 2(2) 2(2) 4 XC6SLX100T XC6SLX100T 2(2) 2(2) 4 4 XC6SLX150T XC6SLX150T 2(2) 2(2) 4 4 Notes: 1. For devices in the CSG225 CSG225 package, the MCBs support only the x4 and x8 memory interface width options, meaning LPDDR devices cannot be supported. In addition, there are only 13 MCB address bits available in this package, which limits the maximum memory density to 256 Mb for DDR2 and 512 Mb for DDR and DDR3. 2. For devices with four MCBs, only two MCBs are bonded out in the FGG484 FGG484 and CSG484 CSG484 packages. Spartan-6 FPGA Memory Controller UG388 UG388 (v2.1) March 4, 2010 www.xilinx.com 13 Chapter 1: Memory Controller Block Overview Supported Memory Configurations The Spartan-6 FPGA MCB supports a wide range of common memory types, configurations, and densities, as shown in Table 1-3. Table 1-3: Supported Memory Configurations Memory Type Memory Density Width (# DQ bits) LPDDR DDR 128 Mb x16 X X x8 256 Mb DDR3 X x4 DDR2 X X X X X X X X X X x4 X X X X X X x8 X X X x4 X X X x16 X X x8 X X x4 4 Gb X x8 2 Gb X x4 1 Gb X x8 512 Mb x16 X X x16 x16 X X X x16 X Software and Tool Support The Spartan-6 FPGA MCB is supported by standard software and tool flows like other soft and embedded IP blocks offered by Xilinx. For conventional (i.e., non-embedded) FPGA designs, the MCB can be integrated into a design using the Memory Interface Generator (MIG) tool, available in the CORE Generator tool. The MIG tool is used to generate memory interfaces for all Xilinx FPGAs. It produces the necessary RTL design files, user constraints files (UCFs), and script files for simulation and implementation of memory solutions offered by Xilinx. The Getting Started chapter in UG416 UG416, Spartan-6 FPGA Memory Interface Solutions User Guide, contains detailed step-by-step instructions on how to use the MIG tool to implement memory interfaces based on the MCB. For embedded designs (e.g., MicroBlazeTM processor designs), the IP configurator GUI found in the Xilinx Platform Studio tool within the EDK environment can be used to specify the memory interface characteristics. In this flow, the MCB serves as the underlying hardware implementation of the MPMC IP block, available in the EDK library. In addition to setting up the controller and memory attributes, the tool generates the necessary soft bridges to the PLB bus, Xilinx Cache Link (XCL), LocalLink (LL), or other specified interface for connecting EDK peripherals to the resulting memory controller ports. 14 www.xilinx.com Spartan-6 FPGA Memory Controller UG388 UG388 (v2.1) March 4, 2010 Chapter 2 MCB Functional Description This chapter provides a detailed functional description of the Spartan®-6 FPGA MCB. It contains the following sections: · Architecture Overview · Port Configurations · Arbitration · Programmability · Interface Details Architecture Overview The MCB provides a simple, reliable means of interfacing to a single component memory device. The MCB User Interface removes the complexities of DDR memory interfacing so that more engineering resources can be directed to the unique aspects of the FPGA design. The MCB can operate at speeds considerably faster than a comparable "soft" solution implemented in the FPGA logic. With data rates up to 800 Mb/s, the MCB more than doubles the performance of prior generation low-cost FPGA memory interface solutions, allowing higher levels of bandwidth and/or narrower memory buses. This provides the significant benefit of conserving valuable FPGA logic and I/O resources that are otherwise required to communicate with the memory device. Figure 2-1 expands on the MCB block diagram introduced in Chapter 1 to show the major signals associated with the User Interface internal to the FPGA as well as the I/O signals connected to the external memory device. While the User Interface can be configured to support up to six ports, for simplicity, Figure 2-1 shows only the signals for a single bidirectional port. Spartan-6 FPGA Memory Controller UG388 UG388 (v2.1) March 4, 2010 www.xilinx.com 15 Chapter 2: MCB Functional Description X-Ref Target - Figure 2-1 Spartan-6 FPGA Memory IP Wrapper p0_cmd_clk p0_cmd_en p0_cmd_bl p0_cmd_instr p0_cmd_addr p0_cmd_full p0_cmd_empty p0_rd_data p0_rd_empty p0_rd_full p0_rd_overflow p0_rd_count p0_rd_error p0_wr_clk p0_wr_en p0_wr_data p0_wr_mask Controller 32-Bit Bidirectional 32-Bit Bidirectional 32-Bit Unidirectional Dedicated Routing p0_rd_clk p0_rd_en Arbiter I/O Clock Network CMD FIFO 0 CMD FIFO 1 CMD FIFO 2 CMD FIFO 3 CMD FIFO 4 CMD FIFO 5 P H Y I O B Datapath 32-Bit Unidirectional mcbx_dram_clk mcbx_dram_clk_n mcbx_dram_cke mcbx_dram_ras_n mcbx_dram_cas_n mcbx_dram_we_n mcbx_dram_odt mcbx_dram_ddr3_rst mcbx_dram_ba mcbx_dram_addr mcbx_dram_dq mcbx_dram_dqs mcbx_dram_dqs_n mcbx_dram_udm mcbx_dram_ldm 32-Bit Unidirectional 32-Bit Unidirectional p0_wr_empty p0_wr_full p0_wr_underrun p0_wr_count p0_wr_error Spartan-6 FPGA Memory Controller Block UG388 UG388_c3_01_050409 Figure 2-1: MCB Architecture with Major Internal and I/O Signals There are three basic types of ports that can be established at the User Interface: · Read port (unidirectional) · Write port (unidirectional) · Read and Write port (bidirectional) Each port contains a command path and a datapath. For a unidirectional port, a command path is paired with a single read-only or a single write-only datapath. However, for a bidirectional port, a single command path is shared by both the read and write datapaths associated with that port. FIFOs are used at the User Interface of the command path and datapath to queue up memory requests and to manage the transfer from the user clock domain to the memory controller clock domain. The command path signals for a port are used to issue requests to the command FIFOs. The command FIFOs have a user-programmable depth up to four. They store the instruction type (read, write, refresh, etc.), address, and burst length associated with a requested memory transaction. The command path also includes full and empty status flag outputs from the command FIFOs, indicating whether new requests can be accepted. There are six command FIFOs available in hardware; the port configuration determines how many are accessible to the User Interface (see Port Configurations). For more details on the command path signals, refer to Interface Details, page 25. 16 www.xilinx.com Spartan-6 FPGA Memory Controller UG388 UG388 (v2.1) March 4, 2010 Port Configurations In the datapath, the underlying hardware contains six 32-bit ports, two of which are inherently bidirectional. The other four ports are inherently unidirectional but can be combined to create bidirectional ports as well. There are five possible port configurations that combine these six hardware ports to implement the desired User Interface (see Port Configurations). The width of the read and write data word fields of the User Interface are naturally determined by the chosen configuration. The datapath FIFOs are 64 deep, allowing for burst lengths of up to 64 data words from a given start address. In addition to the data word field, the write path FIFOs contain mask bit fields that allow optional masking of write data on a per byte basis. Full, empty, underrun, count, and error outputs indicate the current status of the write data FIFOs. The read data FIFOs have a similar set of status outputs. For more details on the read and write datapath signals, refer to Interface Details, page 25. The arbiter inside the MCB uses a time slot based arbitration mechanism to determine which of the one to six ports of the User Interface currently has access to the memory. There are also methods for allowing some ports greater priority, and thus frequent access to the memory, as discussed in Arbitration. Bank management logic in the MCB allows up to eight memory banks to be open simultaneously, allowing the controller to maintain high efficiency levels when accessing data spread across multiple banks. In addition, read and write requests to the memory can include an optional auto-precharge to automatically close a bank upon completion of the transaction to improve the efficiency of random data accesses within a bank. The MCB does not perform any reordering of transactions. Port Configurations The five possible port configurations for the User Interface are shown in Figure 2-2. In Configuration 1, the user ports essentially map directly to the underlying six physical hardware ports. For the other configurations, the diagram shows how the physical ports are concatenated to create different user port combinations. As shown in Figure 2-2, the MIG tool always sequentially numbers ports for the User Interface starting from 0, regardless of the underlying physical port numbers. In all five port configurations, the command path, write datapath, and read datapath within a given port all have separate clocks and therefore can be connected to independent clock domains. However, it is recommended that all paths related to a given port be kept on a single clock domain to simplify the interface requirements. Spartan-6 FPGA Memory Controller UG388 UG388 (v2.1) March 4, 2010 www.xilinx.com 17 Chapter 2: MCB Functional Description X-Ref Target - Figure 2-2 Configuration 1 Configuration 3 2 32-Bit Bidirectional 4 32-Bit Unidirectional Configuration 2 4 32-Bit Bidirectional User Port 0 32-Bit R/W User Port 1 User Port 1 32-Bit R/W Configuration 4 Configuration 5 2 64-Bit Bidirectional 1 128-Bit Bidirectional User Port 0 32-Bit R/W 1 64-Bit Bidirectional 2 32-Bit Bidirectional 32-Bit R/W User Port 0 User Port 0 64-Bit R/W 64-Bit R/W User Port 0 User Port 2 32-Bit R or W User Port 3 User Port 2 32-Bit R/W 32-Bit R/W 32-Bit R or W User Port 1 64-Bit R/W User Port 4 32-Bit R or W User Port 5 128-Bit R/W User Port 1 User Port 3 User Port 2 32-Bit R/W 32-Bit R/W 32-Bit R or W UG388 UG388_c3_02_072809 Figure 2-2: Possible Port Configurations for the User Interface Selecting a Port Configuration The MIG tool in the CORE GeneratorTM tool provides a simple graphical interface for setting up the number and type of ports required for a specific application. For designs that require less than the full width or functionality of the User Interface, unused ports can simply be disabled through the MIG interface. In the event that additional ports are required beyond the six ports provided in the MCB, port bridges with additional arbitration mechanisms can be implemented in the FPGA logic to expand the MCB port capabilities. Arbitration The arbiter inside the MCB uses a time slot based arbitration mechanism to determine which port of the User Interface currently has access to the memory. There are 12 time slots in the arbitration table as shown in Table 2-1. Each time slot corresponds to a single memory clock cycle. The order of port priority in a given time slot is determined by the port numbers entered into the Priority 1 through 6 columns moving from left to right across the table. Table 2-1 shows the case where the User Interface is configured for the maximum six ports. If the MCB is configured to have fewer than six ports, the arbitration table automatically adjusts to have priority columns only for the selected number of ports. 18 www.xilinx.com Spartan-6 FPGA Memory Controller UG388 UG388 (v2.1) March 4, 2010 Arbitration Table 2-1: MCB Arbitration Table with Round Robin Configuration Time Slot Priority 1 Priority 2 Priority 3 Priority 4 Priority 5 Priority 6 0 0 1 2 3 4 5 1 1 2 3 4 5 0 2 2 3 4 5 0 1 3 3 4 5 0 1 2 4 4 5 0 1 2 3 5 5 0 1 2 3 4 6 0 1 2 3 4 5 7 1 2 3 4 5 0 8 2 3 4 5 0 1 9 3 4 5 0 1 2 10 4 5 0 1 2 3 11 5 0 1 2 3 4 During a given clock cycle, the arbiter determines which port to service in that time slot. It moves left to right across the priority columns to find the first port in that row that has a command pending in its command FIFO. That port is then serviced with execution of the pending command, and the arbiter moves on to the next time slot on the following clock cycle. If no port has a command pending for that row, no action occurs for that time slot and a clock cycle is lost. The order of port priorities in the arbitration table is fully programmable. The MIG tool provides a default round-robin scheme as illustrated in Table 2-1, where all ports are given the highest priority in 2 of the 12 available time slots. However, the MIG tool also provides a custom option where the user can define any arbitration table. This allows for some ports to be given greater overall access to the memory device. However, care should be exercised when using this option to ensure that the assigned priorities do not prevent any active ports from receiving access to the memory device. It is possible to configure the User Interface to have five ports (two 32-bit bidirectional ports and three 32-bit unidirectional ports, with one 32-bit unidirectional port disabled). In this case, the arbitration table is reduced to 10 time slots. When the number of time slots is evenly divisible by the number of ports, each port is ensured to receive equal access to the memory device, if desired. Spartan-6 FPGA Memory Controller UG388 UG388 (v2.1) March 4, 2010 www.xilinx.com 19 Chapter 2: MCB Functional Description Programmability The MCB is highly configurable through a set of memory device and controller attributes, allowing it to support multiple memory standards and configurations. The MIG tool within the CORE Generator tool and the IP Configurator in the Xilinx Platform Studio tool within the EDK environment provide a simple means of configuring the MCB attributes to implement the desired memory interface (for example, see the "Getting Started" chapter in UG416 UG416, Spartan-6 FPGA Memory Interface Solutions User Guide). Table 2-2 and Table 2-3 list the memory device and controller attributes, respectively, supported by the MCB. The specific HDL parameter names, possible values, and descriptions associated with each of the attributes are provided. In general, the MIG tool or IP Configurator tools are responsible for setting all parameter values, so the values should not be modified directly. Memory timing parameters are taken from the vendor data sheets, and are automatically assigned by the tools when a supported device is selected. Timing parameters can be specified when creating a custom device (see the "Setting Controller Options" section in the Spartan-6 FPGA Memory Interface Solutions User Guide). Table 2-2: Memory Device Attributes Memory Attributes Memory Type Parameter Name(s) C_MEM_TYPE Description / Possible Values This attribute sets the memory standard implemented by the MCB. Possible values: DDR, DDR2, DDR3, LPDDR. Memory Data Bus Width C_NUM_DQ_PINS This attribute sets the bit width of the DQ bus. Possible values: "4", "8", "16". Memory Address Bus Width C_MEM_ADDR_WIDTH This attribute sets the memory address bus width (the total number of address bits). Possible values: Based on device selection in the MIG tool. Memory Bank Address Bus Width C_MEM_BANKADDR_WIDTH This attribute sets the number of bank address bits. Possible values: Based on device selection in the MIG tool. Memory Column Address Bus Width C_MEM_NUM_COL_BITS This attribute sets the number of column address bits. Possible values: Based on device selection in the MIG tool. Memory Burst Length C_MEM_BURST_LEN This attribute sets the memory burst length to be used. The MIG tool determines the value based on the memory standard, port configuration, and interface width. DDR3 will always be set to 8. Possible values: "4", "8". 20 www.xilinx.com Spartan-6 FPGA Memory Controller UG388 UG388 (v2.1) March 4, 2010 Programmability Table 2-2: Memory Device Attributes (Cont'd) Memory Attributes Parameter Name(s) DDR, DDR2, LPDDR: C_MEM_CAS_LATENCY Memory CAS Latency Description / Possible Values This attribute sets the CAS latency (the delay in clock cycles between the READ command and the first output data) for memory. DDR3 has separate Read and Write CAS latency values. DDR3: C_MEM_DDR3_CAS_LATENCY, C_MEM_DDR3_CAS_WR_LATENCY Possible values: 2, 3, 4, 5, 6, 7, 8, 9, 10, depending on memory type. Partial Array Self-Refresh Size C_MEM_MOBILE_PA_SR For LPDDR: This attribute sets the array size for self-refresh operation. Possible values: LPDDR: Full, Half Memory Drive Strength DDR, DDR2: C_MEM_DDR1_2_ODS DDR3: C_MEM_DDR3_ODS LPDDR: C_MEM_MDDR_ODS This attribute sets output drive strength of memory device. Possible values: DDR/DDR2: "FULL", "REDUCED" DDR3: "DIV6" (RZQ/6), "DIV7" (RZQ/7) LPDDR: "FULL", "THREEQUARTERS", "HALF", "QUARTER" Memory Termination Value (ODT) DDR2: C_MEM_DDR2_RTT DDR3: C_MEM_DDR3_RTT This attribute sets on-die termination resistance of the memory device. Possible values: DDR2: "OFF", "50OHMS 50OHMS", "75OHMS 75OHMS", "150OHMS 150OHMS" DDR3: "OFF", "DIV2" (RZQ/2), "DIV4" (RZQ/4), "DIV6" (RZQ/6), "DIV8" (RZQ/8), "DIV12 DIV12" (RZQ/12 RZQ/12) Note: RZQ = 240 Memory Differential DQS Enable C_MEM_DDR2_DIFF_DQS_EN Enables differential DQS strobe use. This attribute is always enabled for DDR3; it is set to "YES" for DDR2 at frequencies above 200 MHz. Possible values: DDR2: "YES", "NO" Memory Auto Self Refresh C_MEM_DDR3_AUTO_SR For DDR3 only: Auto self-refresh allows memory to determine the best refresh interval based on device temperature. If auto selfrefresh is not used, the operating temperature range must be indicated using the hightemperature self-refresh register. Possible values: "ENABLED", "MANUAL" Memory High Temperature Self Refresh C_MEM_DDR2_3_HIGH_TEMP_SR For DDR2 and DDR3: Memory can be put in high-temperature self-refresh mode to decrease refresh interval time. Possible values: DDR2/DDR3: "NORMAL" (0­85°C), "EXTENDED" (> 85°C) Spartan-6 FPGA Memory Controller UG388 UG388 (v2.1) March 4, 2010 www.xilinx.com 21 Chapter 2: MCB Functional Description Table 2-2: Memory Device Attributes (Cont'd) Memory Attributes Memory Dynamic Output Driver Termination Parameter Name(s) C_MEM_DDR3_DYN_WRT_ODT Description / Possible Values For DDR3: Determines the value of the dynamic output driver termination. Possible values: DDR3: "OFF", "DIV2" (RZQ/2), "DIV4" (RZQ/4) Memory tRAS Value C_MEM_TRAS Minimum Active to Precharge period for memory. Possible values (in picoseconds): Based on device selection in the MIG tool. Memory tRCD Value C_MEM_TRCD Minimum Active to the Read or Write command delay for memory. Possible values (in picoseconds): Based on device selection in the MIG tool. Memory tREFI Value C_MEM_TREFI Average Periodic Refresh Interval for memory. This attribute is the rate at which the MCB refreshes the memory, not the self-refresh interval. Possible values (in picoseconds): Based on device selection in the MIG tool. Memory tRFC Value C_MEM_TRFC Minimum Auto-Refresh to Active or AutoRefresh command period for memory. Possible values (in picoseconds): Based on device selection in the MIG tool. Memory tRP Value C_MEM_TRP Minimum Precharge command period for memory. Possible values (in picoseconds): Based on device selection in the MIG tool. Memory tWR Value C_MEM_TWR Minimum Write Recovery time for memory. Possible values (in picoseconds): Based on device selection in the MIG tool. Memory tRTP Value C_MEM_TRTP Minimum Read to Precharge command delay for memory. Typically, this parameter is only found in DDR2 and DDR3 devices. Possible values (in picoseconds): Based on device selection in the MIG tool. Memory tWTR Value C_MEM_TWTR Minimum Write to Read command delay for memory. Possible values (in picoseconds): Based on device selection in the MIG tool. 22 www.xilinx.com Spartan-6 FPGA Memory Controller UG388 UG388 (v2.1) March 4, 2010 Programmability Table 2-3: Controller Attributes Controller Attributes Controller Clock Period Parameter Name(s) C_MEMCLK_PERIOD Description / Possible Values This attribute converts memory timing parameters between clock cycles and picoseconds. Possible values (in picoseconds): Based on frequency selection in the MIG tool. Controller Port Configuration C_PORT_CONFIG This attribute sets the port configuration of the User Interface. It determines the port direction (B = Bidirectional, W = Unidirectional Write, R = Unidirectional Read) and data bus width (32, 64, or 128 bits). Possible Values: "B32_B32_W32_W32_W32_W32" "B32_B32_W32_W32_W32_R32" "B32_B32_W32_W32_R32_W32" "B32_B32_W32_W32_R32_R32" "B32_B32_W32_R32_W32_W32" "B32_B32_W32_R32_W32_R32" "B32_B32_W32_R32_R32_W32" "B32_B32_W32_R32_R32_R32" "B32_B32_R32_W32_W32_W32" "B32_B32_R32_W32_W32_R32" "B32_B32_R32_W32_R32_W32" "B32_B32_R32_W32_R32_R32" "B32_B32_R32_R32_W32_W32" "B32_B32_R32_R32_W32_R32" "B32_B32_R32_R32_R32_W32" "B32_B32_R32_R32_R32_R32" "B32_B32_B32_B32" "B64_B32_B32" "B64_B64" "B128" Port Data Bus Width (Ports 0 and 1) C_P0_DATA_PORT_SIZE C_P1_DATA_PORT_SIZE Ports 0 and 1 of the User Interface can vary in data bus width depending on the port configuration selected (Ports 3 through 5, if available, are always 32 bits wide). These parameters set the Port 0 and 1 data width. Possible Values: "32", "64", "128" Port Data Mask Width (Ports 0 and 1) C_P0_MASK_SIZE C_P1_MASK_SIZE This attribute sets the number of mask bits for Ports 0 and 1, depending on the data bus width as determined by the port configuration. Possible Values: "4", "8", "16" Spartan-6 FPGA Memory Controller UG388 UG388 (v2.1) March 4, 2010 www.xilinx.com 23 Chapter 2: MCB Functional Description Table 2-3: Controller Attributes (Cont'd) Controller Attributes Controller Port Enable Parameter Name(s) Description / Possible Values C_PORT_ENABLE This six-bit value determines which of the 6 underlying 32-bit hardware ports are used in a given port configuration. Possible Values: For example, 6'b001111 = ports 0 to 3 enabled Address Mapping Order C_MEM_ADDR_ORDER This attribute determines how the byte address presented to the User Interface maps to the physical memory bank, row, and column address bits. This attribute is based on a system addressing scheme. This value should be set to take the most advantage of MCB open bank management capabilities. Possible Values: "BANK_ROW_COLUMN", "ROW_BANK_COLUMN" Arbitration Time Slot Count C_ARB_NUM_TIME_SLOTS This attribute sets the number of time slots in the arbitration table. Most port configurations have 12 time slots, but port configurations with 5 active ports have 10 time slots in the arbitration table to ensure equal arbitration. Possible Values: "12", "10" Arbitration Time Slot Values C_ARB_TIME_SLOT[0:11] These 6-digit octal (18-bit) values set the port priority for each time slot. Possible Values: For example, C_ARB_TIME_SLOT0 = 18'o012345 (sets Port 0 with the highest priority down to Port 5 with the lowest priority). Controller Calibration Bypass (Simulation) C_MC_CALIB_BYPASS Directs the MIG tool to set up simulation files to skip the controller calibration sequence for faster simulation. Note: This parameter is for simulation only. Possible Values: "YES", "NO" Reserved Calibration Address Space C_MC_CALIBRATION_RA C_MC_CALIBRATION_BA C_MC_CALIBRATION_CA Defines the starting row, bank, and column address reserved for calibration. This attribute is used for training pattern data during recalibration to avoid overwrite of application data. Possible Values (any valid address is okay): Examples: C_MC_CALIBRATION_RA = 15'h0000 C_MC_CALIBRATION_BA = 3'h0 C_MC_CALIBRATION_CA = 12'h000 24 www.xilinx.com Spartan-6 FPGA Memory Controller UG388 UG388 (v2.1) March 4, 2010 Interface Details Table 2-3: Controller Attributes (Cont'd) Controller Attributes Parameter Name(s) C_MC_CALIBRATION_MODE Calibration Mode Description / Possible Values This attribute determines whether the MCB executes precise alignment and real-time voltage/temperature compensation of the DQS strobe (recommended) or simply uses a fixed ratio of the bit period to offset DQS into the data window. Possible Values: "CALIBRATION" (precise DQS alignment with voltage/temperature compensation), "NOCALIBRATION" (fixed DQS offset delay) DQS Offset Delay Value C_MC_CALIBRATION_DELAY This attribute sets the fixed DQS offset delay as a ratio of the bit period when C_MC_CALIBRATION_MODE = "NO CALIBRATION". Possible Values: "QUARTER", "HALF", "THREEQUARTER", "FULL" Interface Details As shown in the architecture block diagram of Figure 2-1, page 16, the MCB has two basic interfaces: the internal User Interface to the FPGA logic and the external interface to the memory device via the predefined I/O pins. The following subsections discuss the details of all signals related to these two interfaces. As in the rest of this document, all descriptions refer to the interface of the IP wrapper delivered by the CORE Generator or EDK tool flows, not the interface of the underlying memory controller block primitive. User (Fabric Side) Interface The User Interface contains all the necessary signals for the user logic in the FPGA logic to interact with the command path and datapath of the MCB ports. It also includes the general clock and reset signals for the MCB as well as signals related to calibration, debug, and self-refresh operation. The User Interface can be configured to have anywhere from one to six ports as shown in Port Configurations, page 17. Clock, Reset, and Calibration Signals Table 2-4 shows the clock, reset, and calibration related signals of the MCB User Interface. Table 2-4: Clock, Reset, and Calbration Signals Signal Name Direction async_rst Input calib_done Output This active-High signal indicates the completion of all phases of calibration during the start-up sequence of the MCB. See Calibration in Chapter 4 for more information. Input This clock synchronizes the soft calibration module to the sysclk_2x domain. It must be generated by the same PLL as sysclk_2x to ensure that it is phase-synchronized to that domain. See Clocking in Chapter 3 for more information. mcb_drp_clk Spartan-6 FPGA Memory Controller UG388 UG388 (v2.1) March 4, 2010 Description Main system reset for the MCB. www.xilinx.com 25 Chapter 2: MCB Functional Description Table 2-4: Clock, Reset, and Calbration Signals (Cont'd) Signal Name Direction Description pll_ce_0 Input I/O clock enable strobe from BUFPLL_MCB. This signal pulses High on every other clock cycle of sysclk_2x. It is used for double data rate transfers in the I/O blocks. pll_ce_90 Input I/O clock enable strobe from BUFPLL_MCB. This signal pulses High on every other clock cycle of sysclk_2x_180. It is used for double data rate transfers in the I/O blocks. pll_lock Input Lock signal from the PLL block. sysclk_2x Input Main system clock for the MCB. This signal is generated by the Spartan-6 FPGA PLL block and is rebuffered by the BUFPLL_MCB driver to the I/O clock network. It operates at two times the memory clock frequency (for example, 800 MHz for a 400 MHz memory interface). sysclk_2x_180 Input This input is the phase-shifted clock with the same frequency as sysclk_2x. It is generated by the same PLL/BUFPLL_MCB resources. Command Path Table 2-5 defines the signals related to the command path of the MCB User Interface. All port signal names have the prefix pX, where X represents the port number (for example, port 0 signals are prefixed with p0, port 1 with p1, and so forth). Table 2-5: Command Path Signals Signal Name Direction Description Byte start address for current transaction. Addresses must be aligned to port size: pX_cmd_addr[29:0] Input 32-bit ports: Lower two bits must be 0s. 64-bit ports: Lower three bits must be 0s. 128-bit ports: Lower four bits must be 0s. pX_cmd_bl[5:0] pX_cmd_clk Input User clock for the Command FIFO. FIFO signals are captured on the rising edge of this clock. pX_cmd_empty Output pX_cmd_en 26 Input Burst length in number of user words for the current transaction. Burst length is encoded as 0 to 63, representing 1 to 64 user words (for example, 6'b00011 is a burst length 4 transaction). The user word width equals the port width (for example, a burst length of 3 on a 64-bit port transfers 3 x 64-bit user words = 192 bits total). Input This active-High empty flag for the Command FIFO indicates no commands are queued in FIFO, although there might be commands in flight. This active-High signal is the write-enable signal for the Command FIFO. This signal is covered in more detail in Chapter 4. www.xilinx.com Spartan-6 FPGA Memory Controller UG388 UG388 (v2.1) March 4, 2010 Interface Details Table 2-5: Command Path Signals (Cont'd) Signal Name Direction Description pX_cmd_error Output This output indicates a Command Port error occurred because the FIFO pointers were unsynchronized. pX_cmd_full Output This active-High output is the full flag for the Command FIFO. It indicates the FIFO cannot accept any more commands and blocks writes to the Command FIFO. Command code for the current instruction. Bit 0 represents the READ/WRITE select, Bit 1 is Auto Precharge enable, and Bit 2 represents Refresh, which always takes priority: Write: 3'b000 pX_cmd_instr[2:0] Input Read: 3'b001 Write with Auto Precharge: 3'b010 Read with Auto Precharge: 3'b011 Refresh: 3'b1xx This signal is covered in more detail in Chapter 4. Write Datapath Table 2-6 shows all signals related to the write datapath of the MCB User Interface. All port signal names have the prefix pX, where X represents the port number (for example, port 0 signals are prefixed with p0, port 1 with p1, and so forth). Table 2-6: Write Datapath Signals Signal Name Direction pX_wr_clk Input pX_wr_count[6:0] Output pX_wr_data[PX_SIZE-1:0] Input pX_wr_empty Output Spartan-6 FPGA Memory Controller UG388 UG388 (v2.1) March 4, 2010 www.xilinx.com Description This signal is the user clock for the Write Data FIFO. Count value for Write Data FIFO. This output indicates how many user words are in the FIFO (from 1 to 64). A count value of 0 indicates the FIFO is empty. This signal has a longer latency than the pX_wr_empty flag. Therefore, the FIFO could be empty or experience an underrun even when the count is not 0. Write Data value to be loaded into Write Data FIFO and sent to memory. PX_SIZE can be 32, 64, or 128 bits, depending on port configuration. This active-High signal is the empty flag for the Write Data FIFO. It indicates there is no valid data in the FIFO. 27 Chapter 2: MCB Functional Description Table 2-6: Write Datapath Signals (Cont'd) Signal Name Direction Description pX_wr_en Input This active-High signal is the write enable for the Write Data FIFO. It indicates that the value on pX_wr_data is valid for loading into the FIFO. Data is loaded on the rising edge of pX_wr_clk when pX_wr_en = 1 and pX_wr_full = 0. pX_wr_error Output This signal indicates a Write Data FIFO error occurred because the FIFO pointers were unsynchronized. Output This active-High signal is the full flag for the Write Data FIFO. When this signal is high, it prevents data from being loaded into the FIFO. Input Data mask bits for Write Data. This mask is loaded into the FIFO coincident with the associated Write Data (pX_wr_data). One mask bit is associated with each byte of data. When a pX_wr_mask bit is High, the corresponding byte of data is masked (that is, not written to the memory). Output This active-High signal is the underrun flag. It indicates there was not enough data in Write Data FIFO to complete the transaction. The last valid data word is written continuously to finish the burst. To prevent underrun, make sure there is enough data in the FIFO when issuing a Write instruction to the Command FIFO. The sys_rst signal must be asserted to reset this flag and recover from this condition. pX_wr_full pX_wr_mask[PX_MASKSIZE-1:0] pX_wr_underrun Read Datapath Table 2-7 shows all signals related to the read datapath of the MCB User Interface. All port signal names have the prefix pX, where X represents the port number (for example, port 0 signals are prefixed with p0, port 1 with p1, and so forth). Table 2-7: Read Datapath Signals Signal Name Direction Description pX_rd_clk Input This input is the user clock for the Read Data FIFO. Input This active-High signal is the read enable for the Read Data FIFO. Read Data is clocked out of the FIFO on the rising edge of pX_rd_clk when pX_rd_en = 1 and pX_rd_empty = 0. Output Read Data value returning from memory. This signal is driven by the output of the Read Data FIFO into FPGA logic. PX_SIZE can be 32, 64, or 128 bits, depending on the port configuration. pX_rd_en pX_rd_data[PX_SIZE-1:0] 28 www.xilinx.com Spartan-6 FPGA Memory Controller UG388 UG388 (v2.1) March 4, 2010 Interface Details Table 2-7: Read Datapath Signals (Cont'd) Signal Name Direction Description pX_rd_full Output This active-High signal is the full flag for the Read Data FIFO. When High, this signal prevents additional data returning from the memory from being loaded into the FIFO. pX_rd_empty Output This active-High signal is the empty flag for the Read Data FIFO. It indicates there is no valid data in the FIFO. Output Count value for Read Data FIFO. This signal indicates how many user words are in the FIFO (from 1 to 64). A count value of 0 indicates the FIFO is empty. This signal has a longer latency than the pX_rd_full flag. Therefore, the FIFO could be full or experience overflow even when the count is less than 64. pX_rd_count[6:0] This active-High signal is the overflow flag. It indicates that data was lost due to Read Data continuing to return from the memory after the Read Data FIFO was full. To prevent overflow: pX_rd_overflow Output · Make sure there is enough room to store the requested Read Data in the FIFO before issuing a Read instruction to the Command FIFO. · Be sure to account for any transactions in flight. The sys_rst signal must be asserted to reset this flag and recover from this condition. pX_rd_error This signal indicates a Read Data FIFO error occurred because the FIFO pointers were unsynchronized. Output Self-Refresh Signals Table 2-8 shows the self-refresh signals accessible through the user interface. Self-refresh is covered in more detail in Chapter 4. Table 2-8: Self-Refresh Signals Signal Name Direction Description selfrefresh_enter Input This input is rising-edge sensitive. When asserted, the MCB requests the memory device to enter selfrefresh mode. The signal must remain asserted until the selfrefresh_mode signal goes active. selfrefresh_mode Output This active-High signal indicates the memory device is in self-refresh mode. Spartan-6 FPGA Memory Controller UG388 UG388 (v2.1) March 4, 2010 www.xilinx.com 29 Chapter 2: MCB Functional Description Memory Device Interface The Memory Device Interface contains all the necessary signals to communicate with the external memory device. All these signals (Table 2-9) have predefined pin locations in Spartan-6 devices. See Spartan-6 FPGA Packaging and Pinout Specification for detailed MCB pinout information for each device/package combination. In addition, the soft calibration module generated by MIG requires allocation of an additional pin (RZQ) for all MCB designs. RZQ is a required pin, but its location can be moved within the MCB bank. When Calibrated Input Termination is selected in the MIG tool, a ZIO pin is also generated for use with the soft calibration module. The ZIO location can also be moved but must placed on a bonded I/O (i.e., a valid package pin) within the MCB bank. See the "Setting FPGA Options" section in UG416 UG416, Spartan-6 FPGA Memory Interface Solutions User Guide, for more information on the RZQ and ZIO pins. Note: All predefined pins revert to general-purpose I/Os when an MCB is unused. In addition, unused pins from an active MCB also revert to general-purpose I/Os. This includes higher order address or bank address pins not needed for a particular density device, DQ data bits not needed for a particular interface width, the reset and ODT signals when not needed for a memory standard, and the UDQS / UDQS_n strobes for x4 or x8 interfaces. All other interface pins are required for all MCB based designs. In addition, there are two exceptions to the general-purpose I/O recovery rules: a. Data mask pins are paired such that if only LDM is used, UDM is lost as a general I/O. The data mask pins are required in all MCB designs to support variable burst length requests at the user interface. Therefore, both LDM and UDM are unavailable as general I/Os whenever the MCB is used. b. Data strobe pins are paired such that if only DQS is used (single-ended strobe), DQS_n is lost as a general I/O. The same is true for UDQS and UDQS_n. Table 2-9: Memory Device Interface Signals Signal Name Direction Description mcbx_dram_addr [C_MEM_ADDR_WIDTH­1:0] Output Address bus to the memory device. C_MEM_ADDR_WIDTH is set by the MIG tool depending on the memory device configuration (the maximum value is 15). mcbx_dram_ba[2:0] Output Bank Address bus to the memory device. The MCB supports up to eight banks in a memory device. mcbx_dram_cas_n Output This signal is the active-Low column address strobe to the memory device. mcbx_dram_cke Output This active-High signal is the clock enable to the memory device. mcbx_dram_clk Output This output is the differential clock (p output) to the memory device. mcbx_dram_clk_n Output This output is the differential clock (n output) to the memory device. mcbx_dram_ddr3_rst Output This signal is the DDR3 reset to the memory device. Bidir Bidirectional data bus to memory device. C_NUM_DQ_PINS is set by the MIG tool depending on the memory device configuration (valid values are 4, 8, and 16). mcbx_dram_dq [C_NUM_DQ_PINS­1:0] 30 www.xilinx.com Spartan-6 FPGA Memory Controller UG388 UG388 (v2.1) March 4, 2010 Interface Details Table 2-9: Memory Device Interface Signals (Cont'd) Signal Name Direction mcbx_dram_dqs Bidir Bidirectional data strobe for DQ[7:0]. This signal is an input during Read transactions and an output during Write transactions. mcbx_dram_dqs_n Bidir Bidirectional complementary data strobe for DQ[7:0]. This signal is an input during Read transactions and an output during Write transactions. mcbx_dram_ldm Output This output is the data mask for the lower data byte (DQ[7:0]) for x16, x8, or x4 configurations. mcbx_dram_odt Output This output is the on-die termination signal. ODT is supported for DDR2 and DDR3. mcbx_dram_ras_n Output This active-Low signal is the row address strobe to the memory device. mcbx_dram_udm Output This output is the data mask for the upper data byte (DQ[15:8]) when interfacing to a x16 device. mcbx_dram_udqs Bidir Bidirectional data strobe for DQ[15:8]. This signal is an input during Read transactions and an output during Write transactions. mcbx_dram_udqs_n Bidir Bidirectional complementary data strobe for DQ[15:8]. This signal is an input during Read transactions and an output during Write transactions. mcbx_dram_we_n Output This signal is the active-Low write enable to the memory device. Bidir Required pin for all MCB designs. When Calibrated Input Termination is selected in the MIG tool, the RZQ pin should have a resistor of value 2R from the pin to ground, where R is the desired input termination value. In all other cases, the RZQ pin should be left as a no-connect pin. The RZQ pin can be moved to any valid package pin within the MCB bank. Bidir No Connect signal used with the soft calibration module when Calibrated Input Termination is selected. ZIO must be placed on a valid package pin within the MCB bank, and there should be no board trace attached to this pin (i.e., no connect). ZIO is not generated for designs that do not use Calibrated Input Termination. rzq zio Description Note: Refer to PCB Layout Considerations in Chapter 3 for board design requirements related to the CS#, ODT, and CKE pins of the memory device. Spartan-6 FPGA Memory Controller UG388 UG388 (v2.1) March 4, 2010 www.xilinx.com 31 Chapter 2: MCB Functional Description 32 www.xilinx.com Spartan-6 FPGA Memory Controller UG388 UG388 (v2.1) March 4, 2010 Chapter 3 Designing with the MCB This chapter provides detailed information on how to design with the Spartan®-6 FPGA MCB. It contains the following sections: · Design Flow · Supported Memory Devices · Simulation · Resource Utilization · Clocking · Migration and Banking · PCB Layout Considerations Design Flow There are two supported design flows for the MCB: · Non-embedded design flow · · · Conventional FPGA design with the Xilinx® ISE® tool flow MIG tool is used within the CORE GeneratorTM tool for MCB designs Embedded design flow · Processor-based FPGA system design with EDK tool flow · IP Configurator in Xilinx Platform Studio (XPS) is used within the EDK environment for MCB designs Both tool flows provide a simple method for developing a reliable interface to external memory devices. A step-by-step GUI driven flow allows an MCB based design to be configured and parameterized to meet the precise needs of the application. The MIG tool flow actually has two "wrapper" levels: a lower-level wrapper (mcb_raw_wrapper.v) and the top-level wrapper (for example, memc3_wrapper.v). The lower-level wrapper incorporates all of the necessary silicon blocks (MCB, I/O, etc.) and soft logic (soft calibration module), required for the solution. It also provides access to all signals associated with the underlying hardware implementation of the User Interface ports and calibration logic. The top-level wrapper handles signal reassignment, tying off lower-level wrapper signals, as needed, and passing down the parameter values to the lower wrapper based on the user selections in the MIG tool. The top-level wrapper presents a clean interface of only those signals needed to implement the MCB-based design as configured during the MIG tool flow. For example, while the lower-level wrapper always shows all 6 of the native 32-bit ports on the User Interface, the top-level wrapper reassigns signals, ties off unused ports, and concatenates buses to Spartan-6 FPGA Memory Controller UG388 UG388 (v2.1) March 4, 2010 www.xilinx.com 33 Chapter 3: Designing with the MCB present the port interface the user expects, such as a single 64-bit port. The top-level wrapper is the one that is subsequently integrated into the larger FPGA design. The lower-level wrapper (mcb_raw_wrapper.v) is documented throughout this User Guide. The parameter and signal lists in Chapter 2, for example, are all described with respect to this lower-level wrapper. This wrapper does not change based on the choices made in the MIG tool GUI flow, whereas the top-level wrapper is customized as a result of the user selections. In addition, the embedded design flow (EDK) uses the same lower-level wrapper as the foundation for creating the Multi-Port Memory Controller (MPMC) peripheral. The IP configurator in XPS allows the user to add the necessary soft bridges on top of the lowerlevel wrapper to create the desired peripheral interfaces, such as: · PLB interface · Xilinx Cache Link (XCL) interface · Local Link (LL) interface · Other Personality Interface Modules (PIMs) supported by EDK Figure 3-1 illustrates how the lower-level wrapper is used for both the non-embedded (MIG) and embedded (EDK) design flows. X-Ref Target - Figure 3-1 Top-level Wrapper (MIG) Top-level Wrapper (EDK) Soft Bridges Lower-level Wrapper Port Grouping Top-level User Interface Signal Tie Off PLB Ports MCB I/O Top-level User Interface XCL Lower-level Wrapper Ports MCB I/O LL Soft Calibration Module Soft Calibration Module Non-embedded Design (MIG/CORE Generator Tool) Embedded Design (EDK / XPS) UG388 UG388_c4_01_050409 Figure 3-1: Common Lower-Level Wrapper for Non-embedded and Embedded Design CORE Generator Tool Figure 3-2 shows the high-level design flow for integrating an MCB based memory interface into a non-embedded (conventional) FPGA design. The "Getting Started" chapter in UG416 UG416, Spartan-6 FPGA Memory Interface Solutions User Guide, provides a detailed step-by-step guide to Phase 1 of this design flow. Phase 2 and Phase 3 are outside the scope of this document, but detailed instructions on the ISE tool flow can be found elsewhere in the Xilinx Documentation Library. 34 www.xilinx.com Spartan-6 FPGA Memory Controller UG388 UG388 (v2.1) March 4, 2010 Supported Memory Devices X-Ref Target - Figure 3-2 Phase 1 Phase 2 Phase 3 Launch MIG Tool from Inside the CORE Generator Tool Integrate MIG UCF Constraints into Overall Design Constraints File Implement Design Synthesis, MAP, PAR Make MIG selections for FPGA/Memory Parameters Import MIG RTL and Build Options into ISE Tool Project Perform Timing Simulation on Completed Design Perform Functional Simulation with MIG Design Integrated Verify Design in Hardware Generate RTL and UCF Files Perform Functional Simulation on MIG Example Design (optional) UG388 UG388_c4_02_050409 Figure 3-2: MCB Design Flow for Non-embedded (Conventional) FPGA Applications Supported Memory Devices Table 3-1 provides a list of memory devices to be verified to operate with the MCB on a Xilinx hardware verification platform. These devices can be selected in the MIG tool (or EDK) GUI flow from the drop-down list of supported devices. Xilinx will add devices to the MIG drop-down supported device list in future releases, but these devices will receive "simulation only" verification. Additionally, custom devices can be created by the user in the MIG tool; however, these do not have simulation or hardware verification by Xilinx. See the "Setting Controller Options" section in UG416 UG416, Spartan-6 FPGA Memory Interface Solutions User Guide, for more information. Table 3-1: Supported Memory Devices for the MCB Standard Vendor Part Number Width Density DDR3 Micron MT41J64M16xx-187E 16 1 Gb DDR3 Micron MT41J256M8xx-187E 8 2 Gb DDR3 Micron MT41J128M8xx-187E 8 1 Gb DDR3 Micron MT41J256M4xx-187E 4 1 Gb DDR3 Micron MT41J512M4xx-187E 4 2 Gb DDR2 Micron MT47H256M4xx-25E 4 1 Gb DDR2 Micron MT47H64M8xx-25E-IT 8 512 Mb DDR2 Micron MT47H128M8xx-25 8 1 Gb DDR2 Micron MT47H128M16xx-3 16 2 Gb DDR2 Micron MT47H256M4xx-3 4 1 Gb DDR2 Micron MT47H16M16xx-3 16 256 Mb DDR2 Micron MT47H32M16xx-37E 16 512 Mb DDR2 Micron MT47H32M8xx-37E 8 256 Mb Spartan-6 FPGA Memory Controller UG388 UG388 (v2.1) March 4, 2010 www.xilinx.com 35 Chapter 3: Designing with the MCB Table 3-1: Supported Memory Devices for the MCB (Cont'd) Standard Vendor Part Number Width Density DDR2 Micron MT47J64M16xx-3 16 1 Gb DDR2 Micron MT47J256M4xx-37E 4 1 Gb DDR2 Micron MT47J128M8xx-3 8 1 Gb DDR2 Elpida EDE1116ACBG-8E EDE1116ACBG-8E 16 1 Gb DDR2 Elpida EDE5116AJBG-8E EDE5116AJBG-8E 16 512 Mb DDR2 Hynix HYB18TC512160B2F-2 HYB18TC512160B2F-2.5 16 512 Mb DDR Micron MT46V32M16xx-5B-IT 16 512 Mb DDR Micron MT46V32M8xx-5B 8 256 Mb DDR Micron MT46V64M4xx-5B 4 256 Mb LPDDR Micron MT46H32M16xxxx-5 16 512 Mb LPDDR Micron MT46H16M16xxxx-6-IT 16 256 Mb LPDDR Micron MT46H16M16xxxx-75-IT 16 256 Mb LPDDR Micron MT46H64M16xxxx-5L-IT 16 1 Gb LPDDR Micron MT46H64M16xxxx-6L-IT 16 1 Gb Simulation The simulation model of the underlying MCB contained within the MIG (or EDK) wrapper is encrypted as specified in Verilog LRM-IEEE Std 1364-2005. This is similar to other IP offered by Xilinx, such as the GTP transceiver and Integrated Endpoint blocks for PCI Express® designs. Xilinx supports the following simulators for this encryption methodology: · ModelSim 6.4b and above The encrypted model of the MCB is automatically compiled when the usual COMPXLIB script is run, provided the appropriate version of the simulator is available on the computer. When running a simulation for a Verilog based design, the following library must be referenced: secureip. For most simulators, this can be done by using the -L switch as an argument to the simulator, such as -L secureip. Note: If VHDL is used as the design entry language, a mixed-language license is required for ModelSim to simulate designs that include the MCB. For more information on simulating IP blocks using the secureip methodology, see UG626 UG626, Synthesis and Simulation Design Guide. 36 www.xilinx.com Spartan-6 FPGA Memory Controller UG388 UG388 (v2.1) March 4, 2010 Resource Utilization Resource Utilization The MIG (or EDK) wrapper produced by the GUI design flow incorporates all of the device resources required for implementation of an MCB based memory interface. For the most part, the wrapper files are simply managing signal name reassignment and connectivity between the silicon resources (for example, MCB to I/O block connections), and thus do not consume any measurable FPGA logic. However, the soft calibration module contained within the wrapper does consume a small amount of FPGA logic resources. In addition, there are specific clocking requirements for the MCB (see Clocking) that result in use of some general clocking resources. Table 3-2 shows the resource utilization associated with an MCB design, excluding any logic required in the user design to control the User Interface ports. This table uses a DDR3 interface with eight banks, differential strobes, and data masking to calculate a maximum pin count. Other memory standards and configurations use fewer pins. Table 3-2: Resource Utilization for Each MCB Based Memory Interface Memory Interface Width Resource x4 x8 x16 Memory Controller Block (MCB) 1 1 1 Predefined I/O Pins: Address, Data, Control, etc. 35 39 50 Soft Calibration Module Logic < 100 Slices < 100 Slices < 100 Slices PLL Block 1 1 1 BUFPLL_MCB Buffer 1 1 1 Clocking This section describes the clocking requirements for implementing a memory interface based on the MCB. The MIG (or EDK) tool automatically generates a clocking infrastructure that fully complies with these requirements. The MCB requires three basic types of clocks: · MCB system clocks determine the operating frequency of the memory controller and physical interface to the external memory device. · Calibration clock determines the operating frequency of the calibration logic. · User clocks determine the operating frequency of the User Interface ports. These clocks can be completely asynchronous to the system and calibration clocks. The Command and Data Path FIFOs handle the necessary clock domain transfer from the User Interface to the internal controller logic. Figure 3-3 shows the recommended clock distribution scheme for the MCB system and calibration clocks. The MCBs are located in the I/O regions on the left and right side of the device, and must therefore be driven by the I/O clock network. The I/O clock network is designed for significantly higher frequencies than the global clock network, allowing memory interfaces to operate at up to 800 Mb/s. Note: CLKOUT0 and CLKOUT1 are the only outputs of the PLL that can be connected to the BUFPLL_MCB driver. These connections must be made exactly as shown in Figure 3-3. Spartan-6 FPGA Memory Controller UG388 UG388 (v2.1) March 4, 2010 www.xilinx.com 37 Chapter 3: Designing with the MCB X-Ref Target - Figure 3-3 SERDESSTROBE0 PLL CLK CLKIN1 CLKB CLKOUT0 CLKOUT1 PLLIN0 MIG Wrapper pll_ce_0 IOCLK0 PLLIN1 I/O Clock Network IOCLK1 sysclk_2x sysclk_2x_180 IBUFGDS pll_ce_90 SERDESSTROBE1 BUFPLL_MCB mcb_drp_clk CLKOUT2 pll_lock LOCKED CLKFB IN CLKFB OUT To second MCB on same side of device (if available) UG388 UG388_c4_03_021510 Figure 3-3: Recommended System and Calibration Clock Distribution To create the desired system clock frequency on the I/O clock network, an external clock source drives one of the PLLs in the center column of the device. The external clock frequency is not critical as long as the PLL can synthesize the desired MCB system clocks from it. The PLL generates two system clock outputs, sysclk_2x and sysclk_2x_180, that are twice the frequency of the desired memory clock (for example, for a 800 Mb/s DDR2 interface with a memory clock equal to 400 MHz, the system clocks are set to 800 MHz) and 180 degrees out of phase from each other. Only two clock lines are available on each side of the device to drive the I/O clock network from the PLLs. The pair of system clocks uses these two clock lines to connect to the MCBs on the left or right side of the device. Thus for devices with four MCBs, the two MCBs on the same side of the device must share the same system clock pair and therefore must run at the same data rate, although the memory standard implemented can be different. DCMs do not have access to the I/O clock network and cannot, therefore, be used to drive MCBs. When the pair of system clocks reaches the I/O clock network, they are rebuffered by a BUFPLL_MCB driver. This driver also creates clock enable strobes required by the MCB: pll_ce_0 and pll_ce_90. The attributes of the BUFPLL_MCB primitive should be set as follows to create the necessary clock enable strobe behavior for the MCBs: · LOCK_SRC = "LOCK_TO_0" · DIVIDE = 2 The rebuffered full rate system clocks (2X clocks) are used in the PHY layer of the interface to create the necessary double data rate (DDR) signaling at the I/O pins (for example, an 800 MHz clock is used to generate an effective 800 Mb/s DDR signal at the I/O). A divide-by-two circuit in the MCB creates what is traditionally considered the memory clock frequency (for example, 400 MHz for an 800 Mb/s DDR interface). These 1X clocks drive the controller, arbiter, and other single data rate (SDR) logic. The calibration related clock, mcb_drp_clk, must be generated by the PLL and must be phase-synchronized (i.e., in phase) with the sysclk_2x domain.The calibration clock rate is limited by normal static timing analysis, with a typical achievable frequency of 100 MHz. In general, a calibration clock frequency of at least 50 MHz should be used to allow the MCB to complete calibration operations in a reasonable period of time. 38 www.xilinx.com Spartan-6 FPGA Memory Controller UG388 UG388 (v2.1) March 4, 2010 Migration and Banking A set of user clocks is associated with each of the User Interface ports (port number X = 0 to 5) used in a given design, as follows: · pX_cmd_clk: Command FIFO user clock for clocking in the Address, Instruction, and Burst Length from the FPGA logic into the FIFO. · pX_wr_clk: Write Data FIFO user clock for loading write data from the FPGA logic into the FIFO in preparation for a burst to memory. · pX_rd_clk: Read Data FIFO user clock for clocking out data returning from the memory into the FPGA logic. The user clocks are completely asynchronous from the system and calibration clocks and therefore they can operate at any frequency dictated by the FPGA logic portion of the design. The FIFOs inside the MCB handle the necessary clock domain transfer. For best utilization of the available memory bandwidth, the user clocks should be set at or above the frequency determined by the ratio of the User Interface to the external Memory Device interface. For example: · For a DDR3 800 Mb/s interface with the memory clock = 400 MHz and a x8 bit memory device: The result is 16 bits of data transfer per clock cycle (8 bits on each clock edge) · For a x64 bit User interface: The user clock should be set at or above (16/64) * 400 MHz = 100 MHz While not technically required, it is also highly recommended that all three user clocks for a port (pX_cmd_clk, pX_wr_clk, and pX_rd_clk) be driven by the same clock source from the FPGA logic to avoid complex timing and synchronization issues in the user design. Migration and Banking The MCB located on the left side (for devices with two MCBs) or lower-left side (for devices with four MCBs) of the device is the most flexible to design with in most situations (see Figure 3-4). The predefined pins for the MCB in this location have the fewest number of "multipurpose" pin functions, while the MCBs on the right side of the device tend to have pins with more shared functionality. X-Ref Target - Figure 3-4 MCB 4 MCB 3 MCB 1 Two MCB Devices MCB 5 MCB 3 MCB 1 Four MCB Devices UG388 UG388_c4_04_050409 Figure 3-4: Spartan-6 FPGA Memory Controller UG388 UG388 (v2.1) March 4, 2010 MCB3 is the Preferred Location for Migration and Pin Flexibility www.xilinx.com 39 Chapter 3: Designing with the MCB For example, some bank 1 MCB pins are shared with the Byte-wide Peripheral Interface (BPI) pins that can be used to configure the Spartan-6 device from a parallel flash device. These dual-purpose pins can be used for a BPI or an MCB interface, but not both. Thus, it is necessary to consider what other components will be in the system, and how they will interface to the Spartan-6 device when planning the MCB interfaces. The MCBs on both sides of the device have pins that are shared with global clock (GCLK) pins and PCI pins, but overall the left (or lower left) side MCB has the fewest restrictions related to pin usage. In addition, it is possible to migrate between Spartan-6 family members in the same package type (for example, migrate from an LX16 device to an LX25 device in the same CSG324 CSG324 package) while maintaining the same MCB predefined pin locations. This applies to all MCB locations. In general, any particular device can migrate up or down at least one device density in the same package type. Refer to the Spartan-6 Family Overview for more details on available devices and package types. PCB Layout Considerations This section lists PCB layout considerations, which should be reviewed before beginning board design for an MCB based memory interface. The Spartan-6 FPGA PCB Designer's Guide should also be consulted for information regarding proper device decoupling, overall power distribution system design, and other general PCB guidelines. Additional references for PCB layout and signal integrity analysis of DDR memory interfaces can be found in Appendix A, References. All trace length calculations assume an average 165 ps of electrical delay per inch of signal trace. General Guidelines · · Top or bottom layer routing can be considered for routing to external termination resistors (if used) when placed in a fly-by mode after the memory component. · Memory interfaces without external terminations should have a maximum of two vias. · Memory interfaces with external terminations should have a maximum of three vias. · Once a signal is broken out to an internal signal layer, it must complete its routing on that layer. Terminating the signal to a via permits final routing to the component pad via and connection at the top or bottom layer of the board. PCB layer hopping is not allowed. · Overall trace length should be minimized. Traces should be 3 inches or less. · Trace widths should be 3 to 5 mils. · Trace spacing should be three times the trace width. · Signals must not be routed over splits or voids. · Routing of differential pairs adjacent to noisy signal lines or high-speed switching devices such as clock chips should be avoided. · 40 Only internal PCB layers should be used to route memory interface signals between the FPGA and memory devices. Breakout vias to connect component balls are excluded from this requirement. The spacing between differential clocks/strobes and other signals on the same PCB layer should be 20 mil. The 20 mil spacing should be maintained when using serpentine routing for length matching. www.xilinx.com Spartan-6 FPGA Memory Controller UG388 UG388 (v2.1) March 4, 2010 PCB Layout Considerations · Differential clocks/strobes are to be routed as 100 differential signals. The clock pairs must be routed on the same PCB layer with no layer changes or hops after the initial pad to via breakout. · Series terminations (if used) should be as close to the FPGA as possible. · Parallel terminations (if used) should be as close to the DRAM as possible. · Parallel termination resistors should be placed on a top or bottom layer VTT island. · Board designers should ensure that clock lines are routed differentially and correct trace widths or clearances maintained to achieve the target differential impedance. Routing the signals differentially reduces the flight time of the clocks when compared to the single-ended signals. Because of this, most DDR2 design guides recommend that clock signals be routed at the same length or longer than the address, control, and command signals to compensate for this timing variation. Data, Data Mask, and Data Strobe Guidelines The Data (DQ), Data Mask (DM), and Data Strobe (DQS) signals should receive the highest priority (that is, routed first), because they are the highest speed DDR signals. · DQ, DM, and DQS signals should be routed in a data group (per byte). Each group should have similar loading and routing to maintain timing and signal integrity. · The provided spacing should be 20 mil between a data group and any other signals. · DQS signals should be isolated from other signals by 20 mil to avoid crosstalk. · There should be a maximum of ±25 ps electrical delay (±150 mil) between any DQ/DM and its associated DQS strobe. · A data group should be referenced to a GROUND plane. · DQ bit swapping at the memory interface is permitted to facilitate layout. Swapping should only be done within a data group. · DQS to DQS_N trace lengths should be matched (±10 mil). · Memory terminations (if external terminations are used) should be placed after the associated memory component in a fly-by fashion. · For 16-bit DDR devices, the LDQS/LDQS_N and UDQS/UDQS_N trace lengths should be matched within ±25 ps of the electrical delay (±150 mil). Address, Control and Clock Guidelines When the data groups have been routed, the next highest priority is the differential clock (CK / CK_N). The clock should be routed first because all address and control trace length matching must be referenced to the differential clock PCB trace length, which might need to be adjusted as the layout task proceeds. · CK to CK_N trace lengths must be matched (±10 mil). · CK and DQS trace lengths must be matched (±250 mil) to maximize setup and hold margins. · There must be a maximum ±50 ps electrical delay (±300 mil) between any address/control signals and the associated CK and CK_N differential clock FPGA output. · Address and control signals can be referenced to a POWER plane if a GROUND plane is not next to this group of signals in the PCB stack-up. Spartan-6 FPGA Memory Controller UG388 UG388 (v2.1) March 4, 2010 www.xilinx.com 41 Chapter 3: Designing with the MCB · To avoid crosstalk, address and command signals should be kept on a different routing layer from DQ, DQS, and DM. · Differential clock terminations (if external terminations are used) must be located as close as possible to the load, after the clock pads of the PCB. PCB trace lengths used in trace length matching must exclude the CLINE length of the PCB trace from memory ball to terminating resistor. · Memory terminations should be placed (if external terminations are used) after the associated memory component in a fly-by fashion. Additional Board Design Requirements In addition to the PCB layout guidelines detailed in this section, these board design requirements must be implemented: · The active-Low Chip Select (CS#) pin of the target memory device should be connected to ground on the board. Because the MCB only supports connections to a single memory component, it does not provide a signal to control the CS# input. Contact your memory vendor for more information, if needed. · For DDR3 memory devices, the RESET and CKE signals should each have a 4.7 k resistor to ground to ensure that these signals are Low during memory initialization. · For DDR2 memory devices, the ODT and CKE signals should each have a 4.7 k resistor to ground to ensure that these signals are Low during memory initialization. Simultaneous Switching Output Considerations As noted in Block Diagram in Chapter 1, the MCB utilizes the general I/O blocks (IOBs) associated with the predefined pin locations to create the external interface to the memory device. The MIG tool automatically configures these IOB locations to implement the required I/O standard for the selected memory type (e.g., SSTL18 SSTL18 for DDR2, SSTL15 SSTL15 for DDR3). Hardware characterization of MCB based memory interfaces indicates there are no Simultaneous Switching Output (SSO) related restrictions when using the predefined IOB locations up to their maximum extent (i.e., the maximum number of data and address pins in the interface). Refer to DS162 DS162, Spartan-6 FPGA Data Sheet: DC and Switching Characteristics and UG361 UG361, Spartan-6 FPGA SelectIO Resources User Guide for more information on SSO characteristics. When placing signals on any remaining pins in the bank, it is recommended that they are used as follows: Single-ended output with the low drive strength, unterminated standards LVCMOS 4 mA or LVCMOS 2mA 42 www.xilinx.com Spartan-6 FPGA Memory Controller UG388 UG388 (v2.1) March 4, 2010 Chapter 4 MCB Operation This chapter provides detailed information on the operation of the Spartan®-6 FPGA MCB. It contains these sections: · Startup Sequence · Calibration · Instructions · Addressing · Command Path Timing · Write Path Timing · Read Path Timing · Memory Transactions · Self Refresh · Suspend · Byte Address to Memory Address Conversion · Transaction Ordering and Coherency Startup Sequence Figure 4-1 shows the startup procedure for the MCB. After the FPGA has been fully configured and the PLL providing the system clocks has locked, a number of initialization and calibration steps are automatically performed by the MCB to prepare it for normal operation. Spartan-6 FPGA Memory Controller UG388 UG388 (v2.1) March 4, 2010 www.xilinx.com 43 Chapter 4: MCB Operation X-Ref Target - Figure 4-1 FPGA Configuration and PLL Lock Phase 2 Calibration Phase 1 Calibration Normal Operation Begins DQS Centering Input Termination Phase 3 Calibration Continuous DQS Tuning Memory Device Mode Registers Loaded UG388 UG388_c5_01_021910 Figure 4-1: MCB Startup Sequence Notes relevant to Figure 4-1: 1. The soft calibration module implements some aspects of Phases 1, 2, and 3 of calibration. 2. The MCB hard calibration logic does NOT perform individual per-bit deskew of the DQ data bus. Follow the guidelines in PCB Layout Considerations, page 40 to ensure that DQ/DQS board traces are properly length matched. The first major operation is Phase 1 of calibration. In this step, the soft calibration module measures the value of an external resistor on the RZQ pin to determine the desired on-chip Input Termination value for several of the pre-defined MCB pins (e.g., DQ bus). This only occurs if the user selects the Calibrated Input Termination option in the MIG GUI flow (see the "Setting FPGA Options" section in UG416 UG416, Spartan-6 FPGA Memory Interface Solutions User Guide). Otherwise an approximate uncalibrated on-chip termination or external termination is assumed, and this startup step is skipped. The second major step of the startup sequence is to load the memory device mode registers with the desired parameters. After the memory device has been configured, Phase 2 of calibration occurs. This phase adds delay to the input path of the DQS strobes entering the FPGA. The goal is to shift the DQS strobes into the center of what becomes the Read Data capture window. Once all of the operations in the startup sequence have completed, the MCB enters normal operation. Commands and Data can be loaded into the User Interface FIFOs while the startup sequence is in progress, but no commands are executed until calibration completes and the block enters normal operation. During normal operation, the soft calibration module continuously monitors the tap delay values of the IDELAY element used to delay the DQS input paths (for more information on IDELAY, see the Spartan-6 FPGA SelectIOTM Resources User Guide). The intent is to measure any change in the per tap delay value due to voltage or temperature variations during operation. If a shift in tap delay value is detected, the tap delay count on the DQS strobe input paths can be adjusted to keep them centered in the Read Data capture window. The update to the IDELAY values is done during memory REFRESH operations to avoid impacting normal data operations and controller efficiency. Phase 3 of calibration is known as continuous DQS tuning. See Calibration for more details on all phases of calibration. 44 www.xilinx.com Spartan-6 FPGA Memory Controller UG388 UG388 (v2.1) March 4, 2010 Calibration Calibration To achieve optimum signal integrity and maximum timing margin (hence, highest performance) for the memory interface, the MCB automatically performs several forms of calibration as briefly outlined in Startup Sequence, page 43. T