UG366 FF484 FF784 FF1156 FF1759 8B/10B DSP48E1 XC6VLX760 64B/66B 64B/67B - Datasheet Archive

 

GTX Transceivers User Guide [optional] UG366 (v1.0) June 24, 2009 [optional] Xilinx is disclosing this user guide, manual,

 

Virtex-6 FPGA GTX Transceivers User Guide [optional] UG366 UG366 (v1.0) June 24, 2009 [optional] Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the Documentation in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx. Xilinx expressly disclaims any liability arising out of your use of the Documentation. Xilinx reserves the right, at its sole discretion, to change the Documentation without notice at any time. Xilinx assumes no obligation to correct any errors contained in the Documentation, or to advise you of any corrections or updates. Xilinx expressly disclaims any liability in connection with technical support or assistance that may be provided to you in connection with the Information. THE DOCUMENTATION IS DISCLOSED TO YOU "AS-IS" WITH NO WARRANTY OF ANY KIND. XILINX MAKES NO OTHER WARRANTIES, WHETHER EXPRESS, IMPLIED, OR STATUTORY, REGARDING THE DOCUMENTATION, INCLUDING ANY WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NONINFRINGEMENT OF THIRD-PARTY RIGHTS. IN NO EVENT WILL XILINX BE LIABLE FOR ANY CONSEQUENTIAL, INDIRECT, EXEMPLARY, SPECIAL, OR INCIDENTAL DAMAGES, INCLUDING ANY LOSS OF DATA OR LOST PROFITS, ARISING FROM YOUR USE OF THE DOCUMENTATION. © 2009 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. PCI, PCI Express, PCIe, and PCI-X are trademarks of PCI-SIG. All other trademarks are the property of their respective owners. Revision History The following table shows the revision history for this document. Date Version 06/24/09 1.0 Revision Initial Xilinx release. Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com UG366 UG366 (v1.0) June 24, 2009 Table of Contents Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Preface: About This Guide Guide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Additional Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Additional Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Chapter 1: Transceiver and Tool Overview Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port and Attribute Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Virtex-6 FPGA GTX Transceiver Wizard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ports and Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SIM_GTXRESET_SPEEDUP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SIM_RECEIVER_DETECT_PASS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SIM_RXREFCLK_SOURCE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SIM_TXREFCLK_SOURCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SIM_VERSION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SIM_TX_ELEC_IDLE_LEVEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 15 28 29 29 30 31 32 32 32 33 33 Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FF484 FF484 Package Placement Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FF784 FF784 Package Placement Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FF1156 FF1156 Package Placement Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FF1759 FF1759 Package Placement Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 34 36 39 44 Chapter 2: Shared Transceiver Features Reference Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Ports and Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Single External Reference Clock Use Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Ports and Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 PLL Settings for Common Protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ports and Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Generic Power-Down Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLL Power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TX and RX Power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-Down Features for PCI Express Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Virtex-6 FPGA GTX Transceivers User Guide UG366 UG366 (v1.0) June 24, 2009 www.xilinx.com 64 64 65 65 65 66 3 Power-Down Transition Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Ports and Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Dynamic Reconfiguration Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Ports and Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Chapter 3: Transmitter TX Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 FPGA TX Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interface Width Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TXUSRCLK and TXUSRCLK2 Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ports and Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 72 73 74 TX Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Ports and Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 TX 8B/10B 8B/10B Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8B/10B 8B/10B Bit and Byte Ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . K Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Running Disparity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ports and Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Enabling and Disabling 8B/10B 8B/10B Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 76 77 77 78 79 TX Gearbox . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ports and Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Enabling the TX Gearbox . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TX Gearbox Bit and Byte Ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TX Gearbox Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Sequence Counter Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Sequence Counter Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 80 80 81 82 83 85 TX Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ports and Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Using the TX Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Using the TX Buffer for Oversampling Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 88 88 88 TX Buffer Bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ports and Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Using the TX Phase-Alignment Circuit to Bypass the Buffer . . . . . . . . . . . . . . . . . . . . Using the TX Phase Alignment Circuit to Minimize TX Lane-to-Lane Skew . . . . . . . 89 89 91 92 TX Pattern Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Ports and Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Use Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 TX Oversampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Ports and Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 4 www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide UG366 UG366 (v1.0) June 24, 2009 TX Polarity Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Ports and Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Using TX Polarity Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 TX Clock Divider Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Serial Clock Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Parallel Clock Divider and Selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Ports and Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 PCI Express Clocking Use Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 TX Configurable Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ports and Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Use Modes ­ TX Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCIe Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Customizable User Presets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Use Mode ­ Resistor Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 102 107 107 107 107 107 TX Receiver Detect Support for PCI Express Designs . . . . . . . . . . . . . . . . . . . . . . . 108 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Ports and Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 TX Out-of-Band Signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Ports and Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Chapter 4: Receiver RX Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 RX Analog Front End . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ports and Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Use Modes ­ RX Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Use Mode ­ Resistor Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 113 114 119 RX Out-of-Band Signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Ports and Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 RX Equalizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Ports and Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Use Mode ­ Continuous Time RX Linear Equalizer . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 RX CDR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Ports and Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 RX Clock Divider Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Clock Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel Clock Divider and Selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ports and Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 129 130 130 RX Margin Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Horizontal Eye Margin Scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Virtex-6 FPGA GTX Transceivers User Guide UG366 UG366 (v1.0) June 24, 2009 www.xilinx.com 5 Ports and Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 RX Polarity Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Ports and Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Using RX Polarity Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 RX Oversampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Feature Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Ports and Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 RX Pattern Checker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Ports and Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 Use Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 RX Byte and Word Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Enabling Comma Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuring Comma Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Activating Comma Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Alignment Status Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Alignment Boundaries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ports and Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 139 139 140 140 140 141 RX Loss-of-Sync State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 Ports and Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 RX 8B/10B 8B/10B Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 8B/10B 8B/10B Decoder Bit and Byte Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 RX Running Disparity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 RX Buffer Bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 Ports and Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Using the RX Phase Alignment Circuit to Bypass the Buffer . . . . . . . . . . . . . . . . . . . 149 RX Elastic Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 Ports and Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 Using the RX Elastic Buffer for Channel Bonding or Clock Correction . . . . . . . . . . . 154 RX Clock Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ports and Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Using RX Clock Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Enabling Clock Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Setting RX Elastic Buffer Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Setting Clock Correction Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Correction Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Monitoring Clock Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 155 158 158 159 159 160 160 RX Channel Bonding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ports and Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Using RX Channel Bonding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Enabling Channel Bonding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Channel Bonding Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Connecting Channel Bonding Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 www.xilinx.com 160 161 164 164 164 165 Virtex-6 FPGA GTX Transceivers User Guide UG366 UG366 (v1.0) June 24, 2009 Setting Channel Bonding Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 Setting the Maximum Skew . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 Precedence between Channel Bonding and Clock Correction . . . . . . . . . . . . . . . . . . . 169 RX Gearbox . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ports and Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Enabling the RX Gearbox . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RX Gearbox Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RX Gearbox Block Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 170 170 171 172 RX Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 Ports and Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 FPGA RX Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interface Width Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RXUSRCLK and RXUSRCLK2 Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ports and Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 177 178 179 Chapter 5: Board Design Guidelines Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 Pin Description and Design Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 GTX Transceiver Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Termination Resistor Calibration Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Managing Unused GTX Transceivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Analog Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Unused Quad Column . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Partially Unused Quad Column . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Partially Used Quad . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Quad Usage Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 182 184 184 185 185 186 187 Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reference Clock Checklist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reference Clock Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LVDS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LVPECL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Coupled Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Unused Reference Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reference Clock Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 189 190 190 190 190 191 191 Power Supply and Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Supply Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Linear vs. Switching Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Linear Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Switching Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Supply Distribution Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Staged Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Supply Decoupling Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Printed Circuit Board Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Board Stackup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GTX Transceiver Power Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signal BGA Breakout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Virtex-6 FPGA GTX Transceivers User Guide UG366 UG366 (v1.0) June 24, 2009 www.xilinx.com 191 191 192 192 192 193 193 193 194 194 195 197 7 Crosstalk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 SelectIO Usage Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 Appendix A: 8B/10B 8B/10B Valid Characters 8 www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide UG366 UG366 (v1.0) June 24, 2009 Preface About This Guide This document shows how to use the GTX transceivers in Virtex®-6 FPGAs. In this document: · Virtex-6 FPGA GTX transceiver is abbreviated as GTX transceiver. · GTXE1 is the name of the instantiation primitive that instantiates one Virtex-6 FPGA GTX transceiver. · A Quad or Q is a cluster or set of four GTX transceivers that share two differential reference clock pin pairs and analog supply pins. Guide Contents This manual contains the following chapters: · Chapter 1, "Transceiver and Tool Overview" · Chapter 2, "Shared Transceiver Features" · Chapter 3, "Transmitter" · Chapter 4, "Receiver" · Chapter 5, "Board Design Guidelines" · Appendix A, "8B/10B 8B/10B Valid Characters" Additional Documentation The following documents are also available for download at http://www.xilinx.com/6. · Virtex-6 Family Overview The features and product selection of the Virtex-6 family are outlined in this overview. · Virtex-6 FPGA Data Sheet: DC and Switching Characteristics This data sheet contains the DC and Switching Characteristic specifications for the Virtex-6 family. · Virtex-6 FPGA Packaging and Pinout User Guide This specification includes the tables for device/package combinations and maximum I/Os, pin definitions, pinout tables, pinout diagrams, mechanical drawings, and thermal specifications. · Virtex-6 FPGA Configuration User Guide This all-encompassing configuration guide includes chapters on configuration interfaces (serial and SelectMAP), bitstream encryption, boundary-scan and JTAG Virtex-6 FPGA GTX Transceivers User Guide UG366 UG366 (v1.0) June 24, 2009 www.xilinx.com 9 Preface: About This Guide configuration, reconfiguration techniques, and readback through the SelectMAP and JTAG interfaces. · Virtex-6 FPGA SelectIO Resources User Guide This guide describes the SelectIOTM resources available in all Virtex-6 devices. · Virtex-6 FPGA Clocking Resources User Guide This guide describes the clocking resources available in all Virtex-6 devices, including the MMCM and PLLs. · Virtex-6 FPGA Memory Resources User Guide The functionality of the block RAM and FIFO are described in this user guide. · Virtex-6 FPGA Configurable Logic Blocks User Guide This guide describes the capabilities of the configurable logic blocks (CLBs) available in all Virtex-6 devices. · Virtex-6 FPGA DSP48E1 DSP48E1 Slice User Guide This guide describes the DSP48E1 DSP48E1 slice available in all Virtex-6 FPGAs. · Virtex-6 FPGA Embedded Tri-Mode Ethernet MACs User Guide This guide describes the dedicated Tri-Mode Ethernet Media Access Controller available in all Virtex-6 FPGAs except the XC6VLX760 XC6VLX760. · Virtex-6 FPGA System Monitor User Guide The System Monitor functionality available in all Virtex-6 devices is outlined in this guide. · Virtex-6 FPGA PCB Designer's Guide This guide provides information on PCB design for Virtex-6 FPGA GTX transceivers, with a focus on strategies for making design decisions at the PCB and interface level. Additional Resources To find additional documentation, see the Xilinx website at: . To search the Answer Database of silicon, software, and IP questions and answers, or to create a technical support WebCase, see the Xilinx website at: http://www.xilinx.com/support. 10 www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide UG366 UG366 (v1.0) June 24, 2009 Chapter 1 Transceiver and Tool Overview Overview The Virtex®-6 FPGA GTX transceiver is a power-efficient transceiver. The GTX transceiver is highly configurable and tightly integrated with the programmable logic resources of the FPGA. It provides the following features to support a wide variety of applications: · Current Mode Logic (CML) serial drivers/buffers with configurable termination, voltage swing · Programmable TX pre-emphasis/post-emphasis, RX equalization, and linear and decision feedback equalization (DFE) for optimized signal integrity. · Line rates from 750 Mb/s to 6.5 Gb/s, with optional 5X digital oversampling required for rates between 150 Mb/s and 750 Mb/s. · Optional built-in PCS features, such as 8B/10B 8B/10B encoding, comma alignment, channel bonding, and clock correction. · Fixed latency modes for minimized, deterministic datapath latency. · Beacon signaling for PCI Express® designs and Out-of-Band signaling including COM signal support for SATA designs. · RX/TX Gearbox provides header insertion and extraction support for 64B/66B 64B/66B and 64B/67B 64B/67B (Interlaken) protocols. · Receiver eye scan Horizontal eye scan in the time domain for testing purposes The first-time user is recommended to read High-Speed Serial I/O Made Simple, which discusses high-speed serial transceiver technology and its applications. The Xilinx® CORE GeneratorTM tool includes a Wizard to automatically configure GTX transceivers to support configurations for different protocols or perform custom configuration (see "Virtex-6 FPGA GTX Transceiver Wizard," page 28). The GTX transceiver offers a data rate range and features that allow physical layer support for various protocols. Figure 1-1 illustrates a block view of the Virtex-6 FPGA GTX transceiver. Virtex-6 FPGA GTX Transceivers User Guide UG366 UG366 (v1.0) June 24, 2009 www.xilinx.com 11 Chapter 1: Transceiver and Tool Overview X-Ref Target - Figure 1-1 TX TX OOB Driver and PCIe TX Gearbox TX Pre/ Post emp PISO Pattern Generator FPGA TX Interface Phase Adjust FIFO & Oversampling Polarity TX PIPE Control 8B/ 10B PLL PCIe Beacon SATA OOB TX-PMA TX-PCS To RX Parallel Data (Near-End PCS Loopback) PLL RX EQ DFE From RX Parallel Data (Far-End PMA Loopback) Pattern Checker Polarity RX CDR From RX Parallel Data (Far-End PCS Loopback) Loss of Sync RX PIPE Control Comma Detect and Align RX Status Control RX OOB FPGA RX Interface RX Gearbox Elastic Buffer Oversampling SIPO 10B /8B RX-PMA RX-PCS UG366 UG366_c1_01_051509 Figure 1-1: Virtex-6 FPGA GTX Transceiver Simplified Block Diagram Details about the different functional blocks of the transmitter and receiver including their use models are described in Chapter 3, "Transmitter," and Chapter 4, "Receiver." Figure 1-2 shows the GTX transceiver placement in an example Virtex-6 device (XC6VLX75T XC6VLX75T). Additional information on the functional blocks in Figure 1-2 is available in the following locations: 12 www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide UG366 UG366 (v1.0) June 24, 2009 Overview · The Virtex-6 FPGA Configuration User Guide provides more information on the Configuration and Clock, MMCM, and I/O blocks. · The Virtex-6 FPGA Embedded Tri-Mode Ethernet MACs User Guide provides detailed information on the Ethernet MAC. Figure 1-2 illustrates the location of the GTX transceiver inside the Virtex-6 XC6VLX75T XC6VLX75T FPGA. X-Ref Target - Figure 1-2 Virtex-6 FPGA (XC6VLX75T XC6VLX75T) GTXE1 Column GTXE1_ X0Y11 X0Y11 MMCM Ethernet MAC GTXE1_ X0Y10 X0Y10 Ethernet MAC GTXE1_ X0Y9 GTXE1_ X0Y8 GTXE1_ X0Y7 I/O Column MMCM GTXE1_ X0Y6 I/O Column Integrated Block for PCI Express Operation Configuration I/O Column GTXE1_ X0Y5 GTXE1_ X0Y4 GTXE1_ X0Y3 GTXE1_ X0Y2 Ethernet MAC GTXE1_ X0Y1 Ethernet MAC MMCM GTXE1_ X0Y0 UG366 UG366_c1_02_051509 Figure 1-2: GTX Transceiver Inside the Virtex-6 XC6VLX75T XC6VLX75T FPGA GTX transceivers are clustered together in a set of four called a Quad or Q. Figure 1-3 illustrates the clustering of four GTX transceivers to a Quad. Refer to "Implementation," page 33 for placement information and the mapping of each transceiver into a specific Quad. Virtex-6 FPGA GTX Transceivers User Guide UG366 UG366 (v1.0) June 24, 2009 www.xilinx.com 13 Chapter 1: Transceiver and Tool Overview X-Ref Target - Figure 1-3 From/To Adjacent Quad TX-P2S To FPGA Logic PCS TX0 CLKs TX PLL From FPGA Logic RX DFE, CDR, S2P RX0 CLKs RX PLL TX-P2S To FPGA Logic PCS TX1 CLKs TX PLL From FPGA Logic RX DFE, CDR, S2P RX1 CLKs RX PLL MGTREFCLK0 MGTREFCLK1 TX-P2S To FPGA Logic PCS TX2 CLKs TX PLL From FPGA Logic RX DFE, CDR, S2P RX2 CLKs RX PLL TX-P2S To FPGA Logic PCS TX3 CLKs TX PLL From FPGA Logic RX DFE, CDR, S2P RX3 CLKs RX PLL From/To Adjacent Quad UG366 UG366_c1_03_051509 Figure 1-3: 14 Quad Configuration www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide UG366 UG366 (v1.0) June 24, 2009 Port and Attribute Summary This cluster of four GTX transceivers share two differential reference clock pin pairs and clock routing. Chapter 2, "Shared Transceiver Features," discusses details about reference clock sources and the routing. Port and Attribute Summary The ports and attributes are grouped in tables for each functionality group (e.g., reference clock selection). If a port or attribute appears in multiple chapters, it is listed in the group of its first appearance. Table 1-1 summarizes the ports and attributes according to functionality group. Table 1-1: Port and Attribute Summary Port/Attribute Section, Page Simulation Attributes: · · · · · · SIM_GTXRESET_SPEEDUP SIM_RECEIVER_DETECT_PASS SIM_RXREFCLK_SOURCE SIM_TX_ELEC_IDLE_LEVEL SIM_TXREFCLK_SOURCE SIM_VERSION page 30 page 30 page 31 page 31 page 31 page 31 Clocking Ports: · · · · · · · · · · · GREFCLKRX GREFCLKTX MGTREFCLKRX[1:0] MGTREFCLKTX[1:0] NORTHREFCLKRX[1:0] NORTHREFCLKTX[1:0] PERFCLKRX PERFCLKTX SOUTHREFCLKRX[1:0] SOUTHREFCLKTX[1:0] TXPLLREFSELDY[2:0] page 56 page 56 page 56 page 56 page 56 page 56 page 56 page 56 page 56 page 57 page 57 Attributes: · PMA_CAS_CLK_EN · SIM_RXREFCLK_SOURCE[2:0] · SIM_TXREFCLK_SOURCE[2:0] Virtex-6 FPGA GTX Transceivers User Guide UG366 UG366 (v1.0) June 24, 2009 www.xilinx.com page 57 page 57 page 57 15 Chapter 1: Transceiver and Tool Overview Table 1-1: Port and Attribute Summary (Cont'd) Port/Attribute Section, Page PLL Ports: · · · · · · · · page 61 page 61 page 61 page 61 page 61 page 61 page 61 page 61 PLLTXRESET PLLRXRESET TXPLLLKDET RXPLLLKDET TXPLLLKDETEN RXPLLLKDETEN TXPLLPOWERDOWN RXPLLPOWERDOWN Attributes: · · · · · · · · · · · · · · · · · page 61 page 61 page 61 page 61 page 61 page 61 page 61 page 61 page 61 page 61 page 61 page 61 page 61 page 61 page 61 page 61 page 61 TX_CLK_SOURCE TX_TDCC_CFG TXPLL_COM_CFG RXPLL_COM_CFG TXPLL_CP_CFG RXPLL_CP_CFG TXPLL_DIVSEL_FB RXPLL_DIVSEL_FB TXPLL_DIVSEL_OUT RXPLL_DIVSEL_OUT TXPLL_DIVSEL_REF RXPLL_DIVSEL_REF TXPLL_DIVSEL45 DIVSEL45_FB RXPLL_DIVSEL45 DIVSEL45_FB TXPLL_LKDET_CFG RXPLL_LKDET_CFG TXPLL_SATA Power Down Ports: · · · · · RXPLLPOWERDOWN RXPOWERDOWN[1:0] TXPDOWNASYNCH TXPLLPOWERDOWN TXPOWERDOWN[1:0] page 64 page 64 page 64 page 64 page 64 Attributes: · · · · · 16 POWER_SAVE TRANS_TIME_FROM_P2 TRANS_TIME_NON_P2 TRANS_TIME_RATE TRANS_TIME_TO_P2 www.xilinx.com page 64 page 64 page 65 page 65 page 65 Virtex-6 FPGA GTX Transceivers User Guide UG366 UG366 (v1.0) June 24, 2009 Port and Attribute Summary Table 1-1: Port and Attribute Summary (Cont'd) Port/Attribute Section, Page Loopback Attributes: · LOOPBACK[2:0] page 68 DRP Ports: · · · · · · · DADDR[6:0] DCLK DEN DI[15:0] DO[15:0] DRDY DWE page 68 page 68 page 68 page 68 page 68 page 69 page 69 FPGA TX Interface Ports: · · · · · · MGTREFCLKFAB[1:0] TXCHARDISPMODE[3:0] TXCHARDISPVAL[3:0] TXDATA[31:0] TXUSRCLK TXUSRCLK2 page 74 page 74 page 74 page 74 page 74 page 74 Attributes: · GEN_TXUSRCLK · TX_DATA_WIDTH page 75 page 75 TX Initialization Ports: · · · · · · · GTXTEST[12:0] GTXTXRESET PLLTXRESET TSTIN[19:0] TXDLYALIGNRESET TXRESET TXRESETDONE page 75 page 75 page 75 page 75 page 75 page 76 page 76 Attributes: · TX_EN_RATE_RESET_BUF Virtex-6 FPGA GTX Transceivers User Guide UG366 UG366 (v1.0) June 24, 2009 www.xilinx.com page 76 17 Chapter 1: Transceiver and Tool Overview Table 1-1: Port and Attribute Summary (Cont'd) Port/Attribute Section, Page TX Encoder Ports: · · · · · · · TXBYPASS8B10B TXBYPASS8B10B[3:0] TXCHARDISPMODE[3:0] TXCHARDISPVAL[3:0] TXCHARISK[3:0] TXENC8B10BUSE TXENC8B10BUSE TXKERR[3:0] TXRUNDISP[3:0] page 78 page 78 page 78 page 79 page 79 page 79 page 79 TX Gearbox Ports: · · · · page 80 page 80 page 80 page 80 TXGEARBOXREADY TXHEADER[2:0] TXSEQUENCE[6:0] TXSTARTSEQ Attributes: · GEARBOX_ENDEC · TXGEARBOX_USE page 80 page 80 TX Buffer Ports: · TXBUFSTATUS[2:0] · TXRESET page 88 page 88 Attributes: · TX_BUFFER_USE · TX_OVERSAMPLE_MODE page 88 page 88 TX Buffer Bypass Ports: · · · · · · · · · · · 18 TXDLYALIGNDISABLE TXDLYALIGNMONITOR[7:0] TXDLYALIGNOVERRIDE TXDLYALIGNRESET TXDLYALIGNUPDSW TXENPMAPHASEALIGN TXOUTCLK TXPLLLKDET TXPLLLKDETEN TXPMASETPHASE TXUSRCLK www.xilinx.com page 89 page 89 page 89 page 89 page 89 page 89 page 89 page 89 page 89 page 89 page 89 Virtex-6 FPGA GTX Transceivers User Guide UG366 UG366 (v1.0) June 24, 2009 Port and Attribute Summary Table 1-1: Port and Attribute Summary (Cont'd) Port/Attribute Section, Page Attributes: · · · · · · · · · · TX_BUFFER_USE TX_BYTECLK_CFG[5:0] TX_DATA_WIDTH TX_DLYALIGN_CTRINC TX_DLYALIGN_LPFINC TX_DLYALIGN_MONSEL TX_DLYALIGN_OVRDSETTING TX_PMADATA_OPT TX_XCLK_SEL TXOUTCLK_CTRL page 90 page 90 page 90 page 90 page 90 page 90 page 90 page 90 page 90 page 90 TX Pattern Generator Ports: · TXENPRBSTST[2:0] · TXPRBSFORCEERR page 94 page 94 Attributes: · RXPRBSERR_LOOPBACK page 95 TX Oversampling Attributes: · PMA_RX_CFG · TX_OVERSAMPLE_MODE page 96 page 96 TX Polarity Control Ports: · TXPOLARITY page 97 TX Clock Divider Control Ports: · · · · · · · · MGTREFCLKFAB[0] O ODIV2 PHYSTATUS TXOUTCLK TXOUTCLKPCS TXRATE TXRATEDONE page 99 page 99 page 99 page 100 page 100 page 100 page 100 page 100 Attributes: · · · · TRANS_TIME_RATE TX_EN_RATE_RESET_BUF TXOUTCLK_CTRL TXPLL_DIVSEL_OUT Virtex-6 FPGA GTX Transceivers User Guide UG366 UG366 (v1.0) June 24, 2009 www.xilinx.com page 100 page 100 page 101 page 101 19 Chapter 1: Transceiver and Tool Overview Table 1-1: Port and Attribute Summary (Cont'd) Port/Attribute Section, Page TX Configurable Driver Ports: · · · · · · · · · · · page 102 page 102 page 103 page 103 page 103 page 103 page 104 page 104 page 105 page 105 page 105 TXBUFDIFFCTRL[2:0] TXDEEMPH TXDIFFCTRL[3:0] TXELECIDLE TXINHIBIT TXMARGIN[2:0] TXPDOWNASYNCH TXPOSTEMPHASIS[4:0] TXPREEMPHASIS[3:0] TXP TXN TXSWING Attributes: · · · · · · · · · · · · · page 105 page 105 page 106 page 106 page 106 page 106 page 106 page 106 page 106 page 106 page 107 page 107 page 107 TX_DEEMPH_0[4:0] TX_DEEMPH_1[4:0] TX_DRIVE_MODE TX_MARGIN_FULL_0[6:0] TX_MARGIN_FULL_1[6:0] TX_MARGIN_FULL_2[6:0] TX_MARGIN_FULL_3[6:0] TX_MARGIN_FULL_4[6:0] TX_MARGIN_LOW_0[6:0] TX_MARGIN_LOW_1[6:0] TX_MARGIN_LOW_2[6:0] TX_MARGIN_LOW_3[6:0] TX_MARGIN_LOW_4[6:0] TX Receiver Detect Support for PCI Express Designs Ports: · · · · · PHYSTATUS RXPOWERDOWN[1:0] TXPOWERDOWN[1:0] RXSTATUS[2:0] TXDETECTRX page 108 page 109 page 109 page 109 page 109 TX OOB Ports: · · · · · 20 TXCOMINIT TXCOMSAS TXCOMWAKE TXELECIDLE[1:0] TXPOWERDOWN[1:0] www.xilinx.com page 110 page 110 page 110 page 110 page 110 Virtex-6 FPGA GTX Transceivers User Guide UG366 UG366 (v1.0) June 24, 2009 Port and Attribute Summary Table 1-1: Port and Attribute Summary (Cont'd) Port/Attribute Section, Page Attributes: · COM_BURST_VAL · TXPLL_SATA page 110 page 110 RX AFE Ports: · RXN · RXP page 113 page 113 Attributes: · · · · · · AC_CAP_DIS CM_TRIM[1:0] RCV_TERM_GND RCV_TERM_VTTRX TERMINATION_CTRL[4:0] TERMINATION_OVRD page 113 page 113 page 114 page 114 page 114 page 114 RX OOB Ports: · · · · · · page 120 page 120 page 120 page 120 page 120 page 120 COMINITDET COMSASDET COMWAKEDET RXELECIDLE RXSTATUS[2:0] RXVALID Attributes: · · · · · · · · · · SAS_MAX_COMSAS SAS_MIN_COMSAS SATA_BURST_VAL SATA_IDLE_VAL SATA_MAX_BURST SATA_MAX_INIT SATA_MAX_WAKE SATA_MIN_BURST SATA_MIN_INIT SATA_MIN_WAKE Virtex-6 FPGA GTX Transceivers User Guide UG366 UG366 (v1.0) June 24, 2009 page 120 page 120 page 120 page 120 page 121 page 121 page 121 page 121 page 121 page 121 www.xilinx.com 21 Chapter 1: Transceiver and Tool Overview Table 1-1: Port and Attribute Summary (Cont'd) Port/Attribute Section, Page RX Equalizer Ports: · · · · · · · · · · · · · · · DFECLKDLYADJ[5:0] DFECLKDLYADJMON[5:0] DFEDLYOVRD DFEEYEDACMON[4:0] DFESENSCAL[2:0] DFETAP1[4:0] DFETAP1MONITOR[4:0] DFETAP2[4:0] DFETAP2MONITOR[4:0] DFETAP3[3:0] DFETAP3MONITOR[3:0] DFETAP4[3:0] DFETAP4MONITOR[3:0] DFETAPOVRD RXEQMIX[9:0] page 124 page 124 page 124 page 124 page 124 page 124 page 124 page 124 page 124 page 124 page 125 page 125 page 125 page 125 page 125 Attributes: · DFE_CAL_TIME[4:0] · DFE_CFG[7:0] · RX_EN_IDLE_HOLD_DFE page 125 page 125 page 125 RX CDR Ports: · RXCDRRESET · RXRATE[1:0] page 127 page 127 Attributes: · · · · · · · · 22 CDR_PH_ADJ_TIME PMA_CDR_SCAN PMA_RX_CFG RX_EN_IDLE_HOLD_CDR RX_EN_IDLE_RESET_FR RX_EN_IDLE_RESET_PH RX_EYE_SCANMODE RXPLL_DIVSEL_OUT www.xilinx.com page 128 page 128 page 128 page 128 page 128 page 128 page 128 page 128 Virtex-6 FPGA GTX Transceivers User Guide UG366 UG366 (v1.0) June 24, 2009 Port and Attribute Summary Table 1-1: Port and Attribute Summary (Cont'd) Port/Attribute Section, Page RX Clock Divider Control Ports: · · · · · · · · page 130 page 130 page 130 page 131 page 131 page 131 page 131 page 131 MGTREFCLKFAB[1] O ODIV2 PHYSTATUS RXRATE RXRATEDONE RXRECCLK RXRECCLKPCS Attributes: · · · · RX_EN_RATE_RESET_BUF RXPLL_DIVSEL_OUT RXRECCLK_CTRL TRANS_TIME_RATE page 131 page 131 page 131 page 131 RX Margin Analysis Ports: · RXDATA[31:0] page 133 Attributes: · RX_EYE_OFFSET · RX_EYE_SCANMODE page 134 page 134 RX Polarity Control Ports: · RXPOLARITY page 134 RX Oversampling Ports: · RXENSAMPLEALIGN · RXOVERSAMPLER page 136 page 136 Attributes: · PMA_RX_CFG · RX_OVERSAMPLE_MODE page 136 page 136 RX Pattern Checker Ports: · PRBSCNTRESET · RXENPRBSTST[2:0] · RXPRBSERR page 137 page 137 page 137 Attributes: · RX_PRBS_ERR_CNT · RXPRBSERR_LOOPBACK Virtex-6 FPGA GTX Transceivers User Guide UG366 UG366 (v1.0) June 24, 2009 www.xilinx.com page 137 page 137 23 Chapter 1: Transceiver and Tool Overview Table 1-1: Port and Attribute Summary (Cont'd) Port/Attribute Section, Page RX Byte and Word Alignment Ports: · · · · · · RXBYTEISALIGNED RXBYTEREALIGN RXCOMMADET RXCOMMADETUSE RXENMCOMMAALIGN RXENPCOMMAALIGN page 141 page 141 page 141 page 142 page 142 page 142 Attributes: · ALIGN_COMMA_WORD · COMMA_10B_ENABLE · COMMA_DOUBLE page 142 page 142 page 142 RX Loss-of-Sync State Machine Ports: · RXLOSSOFSYNC page 144 Attributes: · RX_LOS_INVALID_INCR · RX_LOS_THRESHOLD · RX_LOSS_OF_SYNC_FSM page 144 page 144 page 144 RX Buffer Bypass Ports: · · · · · · · · · · · · 24 RXDLYALIGNDISABLE RXDLYALIGNMONITOR[7:0] RXDLYALIGNOVERRIDE RXDLYALIGNRESET RXDLYALIGNSWPPRECURB RXDLYALIGNUPDSW RXENPMAPHASEALIGN RXPLLLKDET RXPLLLKDETEN RXPMASETPHASE RXRECCLK RXUSRCLK www.xilinx.com page 147 page 147 page 147 page 147 page 147 page 147 page 147 page 147 page 147 page 148 page 148 page 148 Virtex-6 FPGA GTX Transceivers User Guide UG366 UG366 (v1.0) June 24, 2009 Port and Attribute Summary Table 1-1: Port and Attribute Summary (Cont'd) Port/Attribute Section, Page Attributes: · · · · · · · · · · RX_BUFFER_USE RX_DATA_WIDTH RX_DLYALIGN_CTRINC RX_DLYALIGN_EDGESET RX_DLYALIGN_LPFINC RX_DLYALIGN_MONSEL RX_DLYALIGN_OVRDSETTING RX_XCLK_SEL RXRECCLK_CTRL RXUSRCLK_DLY page 148 page 148 page 148 page 148 page 148 page 148 page 148 page 148 page 149 page 149 RX Elastic Buffer Ports: · RXBUFRESET · RXBUFSTATUS[2:0] page 153 page 153 Attributes: · · · · · · RX_BUFFER_USE RX_EN_IDLE_RESET_BUF RX_FIFO_ADDR_MODE RX_IDLE_HI_CNT RX_IDLE_LO_CNT RX_XCLK_SEL page 153 page 153 page 153 page 153 page 154 page 154 RX Clock Correction Ports: · RXBUFRESET · RXBUFSTATUS[2:0] · RXCLKCORCNT[2:0] Virtex-6 FPGA GTX Transceivers User Guide UG366 UG366 (v1.0) June 24, 2009 page 155 page 155 page 156 www.xilinx.com 25 Chapter 1: Transceiver and Tool Overview Table 1-1: Port and Attribute Summary (Cont'd) Port/Attribute Section, Page Attributes: · · · · · · · · · · · · · · · · · · · · · · CLK_COR_ADJ_LEN CLK_COR_DET_LEN CLK_COR_INSERT_IDLE_FLAG CLK_COR_KEEP_IDLE CLK_COR_MAX_LAT CLK_COR_MIN_LAT CLK_COR_PRECEDENCE CLK_COR_REPEAT_WAIT CLK_COR_SEQ_1_1 CLK_COR_SEQ_1_2 CLK_COR_SEQ_1_3 CLK_COR_SEQ_1_4 CLK_COR_SEQ_1_ENABLE CLK_COR_SEQ_2_1 CLK_COR_SEQ_2_2 CLK_COR_SEQ_2_3 CLK_COR_SEQ_2_4 CLK_COR_SEQ_2_ENABLE CLK_COR_SEQ_2_USE CLK_CORRECT_USE RX_DATA_WIDTH RX_DECODE_SEQ_MATCH page 156 page 156 page 156 page 156 page 156 page 157 page 157 page 157 page 157 page 157 page 157 page 157 page 157 page 158 page 158 page 158 page 158 page 158 page 158 page 158 page 158 page 158 RX Channel Bonding Ports: · · · · · · · · · 26 RXCHANBONDSEQ RXCHANISALIGNED RXCHANREALIGN RXCHBONDI[3:0] RXCHBONDO[3:0] RXCHBONDLEVEL[2:0] RXCHBONDMASTER RXCHBONDSLAVE RXENCHANSYNC www.xilinx.com page 161 page 161 page 161 page 161 page 162 page 162 page 162 page 162 page 162 Virtex-6 FPGA GTX Transceivers User Guide UG366 UG366 (v1.0) June 24, 2009 Port and Attribute Summary Table 1-1: Port and Attribute Summary (Cont'd) Port/Attribute Section, Page Attributes: · · · · · · · · · · · · · · · · · · CHAN_BOND_1_MAX_SKEW CHAN_BOND_2_MAX_SKEW CHAN_BOND_KEEP_ALIGN CHAN_BOND_SEQ_1_1 CHAN_BOND_SEQ_1_2 CHAN_BOND_SEQ_1_3 CHAN_BOND_SEQ_1_4 CHAN_BOND_SEQ_1_ENABLE CHAN_BOND_SEQ_2_1 CHAN_BOND_SEQ_2_2 CHAN_BOND_SEQ_2_3 CHAN_BOND_SEQ_2_4 CHAN_BOND_SEQ_2_ENABLE CHAN_BOND_SEQ_2_CFG CHAN_BOND_SEQ_2_USE CHAN_BOND_SEQ_LEN PCI_EXPRESS_MODE RX_DATA_WIDTH page 162 page 162 page 162 page 163 page 163 page 163 page 163 page 163 page 163 page 163 page 163 page 163 page 163 page 163 page 163 page 163 page 164 page 164 RX Gearbox Ports: · · · · · page 170 page 170 page 170 page 170 page 170 RXDATAVALID RXGEARBOXSLIP RXHEADER[2:0] RXHEADERVALID RXSTARTOFSEQ Attributes: · GEARBOX_ENDEC · RXGEARBOX_USE page 170 page 170 RX Initialization Ports: · · · · · · · · · GTXRXRESET GTXTEST[12:0] PLLRXRESET RXBUFRESET RXCDRRESET RXDLYALIGNRESET RXRESET RXRESETDONE TSTIN[19:0] Virtex-6 FPGA GTX Transceivers User Guide UG366 UG366 (v1.0) June 24, 2009 page 175 page 175 page 175 page 175 page 175 page 175 page 175 page 175 page 175 www.xilinx.com 27 Chapter 1: Transceiver and Tool Overview Table 1-1: Port and Attribute Summary (Cont'd) Port/Attribute Section, Page Attributes: · · · · · · · · · · · page 176 page 176 page 176 page 176 page 176 page 176 page 176 page 176 page 176 page 176 page 176 CDR_PH_ADJ_TIME[4:0] RX_EN_IDLE_HOLD_CDR RX_EN_IDLE_HOLD_DFE RX_EN_IDLE_RESET_BUF RX_EN_IDLE_RESET_PH RX_EN_IDLE_RESET_FR RX_EN_MODE_RESET_BUF RX_EN_RATE_RESET_BUF RX_EN_REALIGN_RESET_BUF RX_IDLE_HI_CNT[3:0] RX_IDLE_LO_CNT[3:0] FPGA RX Interface Ports: · · · · · · page 179 page 179 page 179 page 179 page 179 page 179 MGTREFCLKFAB[1:0] RXCHARISK[3:0] RXDATA[31:0] RXDISPERR[3:0] RXUSRCLK RXUSRCLK2 Attributes: · GEN_RXUSRCLK · RX_DATA_WIDTH page 179 page 179 Virtex-6 FPGA GTX Transceiver Wizard The Virtex-6 FPGA GTX Transceiver Wizard is the preferred tool to generate a wrapper to instantiate a GTX transceiver primitive called GTXE1. The Wizard can be found in the Xilinx CORE GeneratorTM tool. Be sure to download the most up-to-date IP Update before using the Wizard. Details on how to use this Wizard can be found in Virtex-6 FPGA GTX T ransceiver Getting Started Guide. 1. Start the Xilinx CORE Generator tool. 2. Locate the GTX Transceiver Wizard in the taxonomy tree under: /FPGA Features & Design/IO Interfaces See Figure 1-4. 28 www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide UG366 UG366 (v1.0) June 24, 2009 Simulation X-Ref Target - Figure 1-4 UG366 UG366_c1_04_051509 Figure 1-4: 3. Virtex-6 FPGA GTX Transceiver Wizard Double-click V6 GTX Wizard to launch the Wizard. Simulation Functional Description Simulations using GTX transceivers have specific prerequisites that the simulation environment and the test bench must fulfill. The Synthesis and Simulation Design Guide explains how to set up the simulation environment for supported simulators depending on the used Hardware Description Language (HDL). This design guide can be downloaded from the Xilinx website. The prerequisites for simulating a design with GTX transceivers are: · Simulator with support for SecureIP models, which are encrypted versions of the Verilog HDL used for implementation of the modeled block. SecureIP is a new IP encryption methodology. To support SecureIP models, a Verilog LRM - IEEE Std 1364-2005 encryption compliant simulator is required. Virtex-6 FPGA GTX Transceivers User Guide UG366 UG366 (v1.0) June 24, 2009 www.xilinx.com 29 Chapter 1: Transceiver and Tool Overview · Mixed-language simulator for VHDL simulation. SecureIP models use a Verilog standard. To use them in a VHDL design, a mixedlanguage simulator is required. The simulator must be capable of simulating VHDL and Verilog simultaneously. · Installed GTX SecureIP model. · Correct setup of the simulator for SecureIP use (initialization file, environment variable(s). · Running COMPXLIB (which compiles the simulation libraries (e.g. UNISIM, SIMPRIMS, etc.) in the correct order. · Correct simulator resolution (Verilog) · The user guide of the simulator and the Synthesis and Simulation Design Guide provide a detailed list of settings for SecureIP support. Ports and Attributes There are no simulation-only ports. The GTXE1 primitive has attributes intended only for simulation. Table 1-2 lists the simulation-only attributes of the GTXE1 primitive. The names of these attributes start with SIM_. Table 1-2: GTXE1 Simulation-Only Attributes Attribute SIM_GTXRESET_SPEEDUP Type Integer Description This attribute shortens the time it takes to finish the GTXRESET sequence and lock the TX PMA PLL and RX PMA PLL during simulation. 0: The GTXRESET sequence is simulated with its original duration (standard initialization is approximately 160 µs). 1: Shorten the GTXRESET cycle time (fast initialization is approximately 300 ns). SIM_RECEIVER_DETECT_PASS Boolean This attribute simulates the TXDETECTRX feature in the GTX transceiver. TRUE: Simulates an RX connection to the TX serial ports. TXDETECTRX initiates receiver detection, and RXSTATUS[2:0] = 011 reports that an RX port is connected. FALSE (default): Simulates a disconnected TX port. TXDETECTRX initiates receiver detection, and RXSTATUS[2:0] = 000 reports that an RX port is not connected. 30 www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide UG366 UG366 (v1.0) June 24, 2009 Simulation Table 1-2: GTXE1 Simulation-Only Attributes (Cont'd) Attribute Type SIM_RXREFCLK_SOURCE Description 3-Bit Binary This attribute selects the reference clock source used to drive the RX PMA PLL in simulation for designs where the RX PMA PLL is always driven by the same reference clock source. The RXPLLREFSELDY port must be set to 000 for this attribute to select the reference clock source. For multi-rate designs that require the reference clock source to be changed on the fly, the RXPLLREFSELDY port is used to dynamically select the source instead. 000: Selects the MGTREFCLKRX[0] port as the source 001: Selects the MGTREFCLKRX[1] port as the source 010: Selects the NORTHREFCLKRX[0] port as the source 011: Selects the NORTHREFCLKRX[1] port as the source 100: Selects the SOUTHREFCLKRX[0] port as the source 101: Selects the SOUTHREFCLKRX[1] port as the source 110: Reserved 111: Selects a clock from the FPGA logic which can be either port GREFCLKRX or PERFCLKRX as the source SIM_TX_ELEC_IDLE_LEVEL 1-Bit Binary This attribute sets the value of TXN and TXP during simulation of electrical idle. This attribute can be set to 0, 1, x, or z. The default for this attribute is x. SIM_TXREFCLK_SOURCE 3-Bit Binary This attribute selects the reference clock source used to drive the TX PMA PLL in simulation for designs where the TX PMA PLL is always driven by the same reference clock source. The TXPLLREFSELDY port must be set to 000 for this attribute to select the reference clock source. For multi-rate designs that require the reference clock source to be changed on the fly, the TXPLLREFSELDY port is used to dynamically select the source instead. 000: Selects the MGTREFCLKTX[0] port as the source 001: Selects the MGTREFCLKTX[1] port as the source 010: Selects the NORTHREFCLKTX[0] port as the source 011: Selects the NORTHREFCLKTX[1] port as the source 100: Selects the SOUTHREFCLKTX[0] port as the source 101: Selects the SOUTHREFCLKTX[1] port as the source 110: Selects the RX recovered clock from the RX channel as the source 111: Selects a clock from the FPGA logic that can be either the GREFCLKTX or the PERFCLKTX port as the source SIM_VERSION Real This attribute selects the simulation version to match different steppings of silicon. The default for this attribute is 1.0. SIM_GTXRESET_SPEEDUP The SIM_GTXRESET_SPEEDUP attribute can be used to shorten the simulated lock time of the TX PMA PLL and the RX PMA PLL. Virtex-6 FPGA GTX Transceivers User Guide UG366 UG366 (v1.0) June 24, 2009 www.xilinx.com 31 Chapter 1: Transceiver and Tool Overview If TXOUTCLK or RXRECCLK is used to generate clocks in the design, these clocks occasionally flatline while the GTX transceiver is locking. If an MMCM is used to divide TXOUTCLK or RXRECCLK, the final output clock is not ready until both the GTX transceiver and the MMCM have locked. Equation 1-1 provides an estimate of the time required before a stable source from TXOUTCLK or RXRECCLK is available in simulation, including the time required for any MMCMs used. Equation 1-1 t USRCLKstable t GTXRESETsequence + t locktimeMMCM If the MMCM is not used, the term can be removed from the lock time equation. SIM_RECEIVER_DETECT_PASS The GTX transceiver includes a TXDETECTRX feature that allows the transmitter to detect whether its serial ports are currently connected to a receiver by measuring rise time on the TXP/TXN differential pin pair (see "TX Receiver Detect Support for PCI Express Designs," page 108). The GTXE1 SecureIP model includes an attribute for simulating TXDETECTRX called SIM_RECEIVER_DETECT_PASS. This attribute allows TXDETECTRX to be simulated for the GTX transceiver without modeling the measurement of rise time on the TXP/TXN differential pin pair. By default, SIM_RECEIVER_DETECT_PASS is set to FALSE. When FALSE, the attribute models a disconnected receiver and TXDETECTRX operations indicate a receiver is disconnected. To model a connected receiver, SIM_RECEIVER_DETECT_PASS for the transceiver is set to TRUE. SIM_RXREFCLK_SOURCE The GTXE1 SecureIP model includes an attribute to select the reference clock source used to drive the RX PMA PLL in simulation called SIM_RXREFCLK_SOURCE. This attribute is to be used in designs where the RX PMA PLL's clock input is always driven by the same reference clock source. Reference clock sources include the dedicated clock pins of the Quad that the transceiver belongs to, the north-running reference clocks, the south-running reference clocks, and a clock from the FPGA logic. Table 1-2, page 30 shows the possible settings for this attribute. For multi-rate designs requiring the reference clock source driving the RX PMA PLL to be changed on the fly, the RXPLLREFSELDY port is used to dynamically select the reference clock source instead. SIM_TXREFCLK_SOURCE The GTXE1 SecureIP model includes an attribute to select the reference clock source used to drive the TX PMA PLL in simulation called SIM_TXREFCLK_SOURCE. This attribute is to be used in designs where the TX PMA PLL's clock input is always driven by the same reference clock source. Reference clock sources include the dedicated clock pins of the Quad that the transceiver belongs to, the north-running reference clocks, the south-running reference clocks, and a clock from the FPGA logic. Table 1-2, page 30 shows the possible settings for this attribute. For multi-rate designs requiring the reference clock source driving the TX PMA PLL to be changed on the fly, the TXPLLREFSELDY port is used to dynamically select the reference clock source instead. 32 www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide UG366 UG366 (v1.0) June 24, 2009 Implementation SIM_VERSION The SIM_VERSION attribute selects the simulation version to match different steppings of silicon. The default for this attribute is 1.0. SIM_TX_ELEC_IDLE_LEVEL The SIM_TX_ELEC_IDLE_LEVEL attribute sets the value of the transceiver's differential transmitter output pair TXN and TXP during simulation of electrical idle. This attribute can be set to 0, 1, x, or z. The default for this attribute is x. Implementation Functional Description This section provides the information needed to map Virtex-6 FPGA GTX transceivers instantiated in a design to device resources, including: · The location of the GTX transceiver on the available device and package combinations. · The pad numbers of external signals associated with each GTX transceiver. · How GTX transceiver and clocking resources instantiated in a design are mapped to available locations with a user constraints file (UCF). It is a common practice to define the location of GTX transceivers early in the design process to ensure correct usage of clock resources and to facilitate signal integrity analysis during board design. The implementation flow facilitates this practice through the use of location constraints in the UCF. While this section describes how to instantiate GTX clocking components, the details of the different GTX transceiver clocking options are discussed in "Reference Clock Selection," page 53. The position of the GTX transceiver is specified by an XY coordinate system that describes the column number and its relative position within that column. In current members of the Virtex-6 platform, all GTX transceivers are located in a single column along one side of the die. The transceiver with the coordinates "X0Y0" is for a given device/package combination always located at the lowest position of the lowest available bank. For the combination of a package with a large pin count (for example, 1759) and a smaller device (for example, XC6VLX240T XC6VLX240T), transceivers at higher or lower banks are not available. There are two ways to create a UCF for designs that utilize the GTX transceiver. The preferred method is to use the Virtex-6 FPGA GTX Transceiver Wizard (see "Virtex-6 FPGA GTX Transceiver Wizard," page 28). The Wizard automatically generates UCF templates that configure the transceivers and contain placeholders for GTX placement information. The UCFs generated by the Wizard can then be edited to customize operating parameters and placement information for the application. The second approach is to create the UCF by hand. When using this approach, the designer must enter both configuration attributes that control transceiver operation as well as tile location parameters. Care must be taken to ensure that all of the parameters needed to configure the GTX transceiver are correctly entered. Virtex-6 FPGA GTX Transceivers User Guide UG366 UG366 (v1.0) June 24, 2009 www.xilinx.com 33 Chapter 1: Transceiver and Tool Overview Figure 1-5, page 34 through Figure 1-23, page 52 provide the GTX transceiver position information for all available device and package combinations along with the pad numbers for the external signals associated with each GTX transceiver. FF484 FF484 Package Placement Diagrams Figure 1-5 through Figure 1-6 show the placement diagrams for the FF484 FF484 package. X-Ref Target - Figure 1-5 B1 MGTRXP3_115 B2 MGTRXN3_115 D1 MGTTXP3_115 D2 MGTTXN3_115 C3 MGTRXP2_115 C4 MGTRXN2_115 F1 MGTTXP2_115 F2 MGTTXN2_115 J4 MGTREFCLK1P_115 J3 MGTREFCLK1N_115 L4 MGTREFCLK0P_115 L3 MGTREFCLK0N_115 E3 MGTRXP1_115 E4 MGTRXN1_115 H1 MGTTXP1_115 H2 MGTTXN1_115 G3 MGTRXP0_115 G4 MGTRXN0_115 K1 MGTTXP0_115 K2 MGTTXN0_115 LX75T LX75T: GTXE1_X0Y7 LX130T LX130T: GTXE1_X0Y15 X0Y15 LX75T LX75T: GTXE1_X0Y6 LX130T LX130T: GTXE1_X0Y14 X0Y14 QUAD_115 LX75T LX75T: GTXE1_X0Y5 LX130T LX130T: GTXE1_X0Y13 X0Y13 LX75T LX75T: GTXE1_X0Y4 LX130T LX130T: GTXE1_X0Y12 X0Y12 UG366 UG366_c1_05_051509 Figure 1-5: 34 Placement Diagram for the FF484 FF484 Package (1 of 2) www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide UG366 UG366 (v1.0) June 24, 2009 Implementation X-Ref Target - Figure 1-6 W3 MGTRXP3_114 W4 MGTRXN3_114 M1 MGTTXP3_114 M2 MGTTXN3_114 Y1 MGTRXP2_114 Y2 MGTRXN2_114 P1 MGTTXP2_114 P2 MGTTXN2_114 R4 MGTREFCLK1P_114 R3 MGTREFCLK1N_114 U4 MGTREFCLK0P_114 U3 MGTREFCLK0N_114 LX75T LX75T: GTXE1_X0Y3 LX130T LX130T: GTXE1_X0Y11 X0Y11 LX75T LX75T: GTXE1_X0Y2 LX130T LX130T: GTXE1_X0Y10 X0Y10 QUAD_114 AA3 MGTRXP1_114 AA4 MGTRXN1_114 T1 MGTTXP1_114 T2 MGTTXN1_114 AB1 MGTRXP0_114 AB2 MGTRXN0_114 V1 MGTTXP0_114 V2 MGTTXN0_114 LX75T LX75T: GTXE1_X0Y1 LX130T LX130T: GTXE1_X0Y9 LX75T LX75T: GTXE1_X0Y0 LX130T LX130T: GTXE1_X0Y8 UG366 UG366_c1_06_051509 Figure 1-6: Virtex-6 FPGA GTX Transceivers User Guide UG366 UG366 (v1.0) June 24, 2009 Placement Diagram for the FF484 FF484 Package (2 of 2) www.xilinx.com 35 Chapter 1: Transceiver and Tool Overview FF784 FF784 Package Placement Diagrams Figure 1-7 through Figure 1-9 show the placement diagrams for the FF784 FF784 package. X-Ref Target - Figure 1-7 A3 MGTRXN3_116 D1 MGTTXP3_116 MGTTXN3_116 B1 MGTRXP2_116 B2 MGTRXN2_116 F1 MGTTXP2_116 F2 MGTTXN2_116 G4 MGTREFCLK1P_116 G3 MGTREFCLK1N_116 J4 MGTREFCLK0P_116 J3 MGTREFCLK0N_116 C3 MGTRXP1_116 C4 MGTRXN1_116 H1 MGTTXP1_116 H2 MGTTXN1_116 E3 MGTRXP0_116 E4 MGTRXN0_116 K1 MGTTXP0_116 K2 LX75T LX75T: GTXE1_X0Y10 X0Y10 LX130T LX130T: GTXE1_X0Y18 X0Y18 LX195T LX195T: GTXE1_X0Y18 X0Y18 LX240T LX240T: GTXE1_X0Y18 X0Y18 A4 D2 LX75T LX75T: GTXE1_X0Y11 X0Y11 LX130T LX130T: GTXE1_X0Y19 X0Y19 LX195T LX195T: GTXE1_X0Y19 X0Y19 LX240T LX240T: GTXE1_X0Y19 X0Y19 MGTRXP3_116 MGTTXN0_116 QUAD_116 LX75T LX75T: GTXE1_X0Y9 LX130T LX130T: GTXE1_X0Y17 X0Y17 LX195T LX195T: GTXE1_X0Y17 X0Y17 LX240T LX240T: GTXE1_X0Y17 X0Y17 LX75T LX75T: GTXE1_X0Y8 LX130T LX130T: GTXE1_X0Y16 X0Y16 LX195T LX195T: GTXE1_X0Y16 X0Y16 LX240T LX240T: GTXE1_X0Y16 X0Y16 UG366 UG366_c1_07_051509 Figure 1-7: 36 Placement Diagram for the FF784 FF784 Package (1 of 3) www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide UG366 UG366 (v1.0) June 24, 2009 Implementation X-Ref Target - Figure 1-8 L3 MGTRXN3_115 M1 MGTTXP3_115 MGTTXN3_115 N3 MGTRXP2_115 N4 MGTRXN2_115 P1 MGTTXP2_115 P2 MGTTXN2_115 P6 MGTREFCLK1P_115 P5 MGTREFCLK1N_115 T6 MGTREFCLK0P_115 T5 MGTREFCLK0N_115 R3 MGTRXP1_115 R4 MGTRXN1_115 T1 MGTTXP1_115 T2 MGTTXN1_115 U3 MGTRXP0_115 U4 MGTRXN0_115 V1 MGTTXP0_115 V2 LX75T LX75T: GTXE1_X0Y6 LX130T LX130T: GTXE1_X0Y14 X0Y14 LX195T LX195T: GTXE1_X0Y14 X0Y14 LX240T LX240T: GTXE1_X0Y14 X0Y14 L4 M2 LX75T LX75T: GTXE1_X0Y7 LX130T LX130T: GTXE1_X0Y15 X0Y15 LX195T LX195T: GTXE1_X0Y15 X0Y15 LX240T LX240T: GTXE1_X0Y15 X0Y15 MGTRXP3_115 MGTTXN0_115 QUAD_115 LX75T LX75T: GTXE1_X0Y5 LX130T LX130T: GTXE1_X0Y13 X0Y13 LX195T LX195T: GTXE1_X0Y13 X0Y13 LX240T LX240T: GTXE1_X0Y13 X0Y13 LX75T LX75T: GTXE1_X0Y4 LX130T LX130T: GTXE1_X0Y12 X0Y12 LX195T LX195T: GTXE1_X0Y12 X0Y12 LX240T LX240T: GTXE1_X0Y12 X0Y12 UG366 UG366_c1_08_051509 Figure 1-8: Virtex-6 FPGA GTX Transceivers User Guide UG366 UG366 (v1.0) June 24, 2009 Placement Diagram for the FF784 FF784 Package (2 of 3) www.xilinx.com 37 Chapter 1: Transceiver and Tool Overview X-Ref Target - Figure 1-9 AC3 MGTRXN3_114 Y1 MGTTXP3_114 MGTTXN3_114 AE3 MGTRXP2_114 AE4 MGTRXN2_114 AB1 MGTTXP2_114 AB2 LX75T LX75T: GTXE1_X0Y2 LX130T LX130T: GTXE1_X0Y10 X0Y10 LX195T LX195T: GTXE1_X0Y10 X0Y10 LX240T LX240T: GTXE1_X0Y10 X0Y10 AC4 Y2 LX75T LX75T: GTXE1_X0Y3 LX130T LX130T: GTXE1_X0Y11 X0Y11 LX195T LX195T: GTXE1_X0Y11 X0Y11 LX240T LX240T: GTXE1_X0Y11 X0Y11 MGTRXP3_114 MGTTXN2_114 W4 MGTREFCLK1P_114 W3 MGTREFCLK1N_114 AA4 MGTREFCLK0P_114 AA3 MGTREFCLK0N_114 AG3 MGTRXP1_114 AG4 MGTRXN1_114 AD1 MGTTXP1_114 AD2 MGTTXN1_114 AH1 MGTRXP0_114 AH2 MGTRXN0_114 AF1 MGTTXP0_114 AF2 MGTTXN0_114 QUAD_114 LX75T LX75T: GTXE1_X0Y0 LX130T LX130T: GTXE1_X0Y9 LX195T LX195T: GTXE1_X0Y9 LX240T LX240T: GTXE1_X0Y9 LX75T LX75T: GTXE1_X0Y0 LX130T LX130T: GTXE1_X0Y8 LX195T LX195T: GTXE1_X0Y8 LX240T LX240T: GTXE1_X0Y8 UG366 UG366_c1_09_051509 Figure 1-9: 38 Placement Diagram for the FF784 FF784 Package (3 of 3) www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide UG366 UG366 (v1.0) June 24, 2009 Implementation FF1156 FF1156 Package Placement Diagrams Figure 1-10 through Figure 1-14 show the placement diagrams for the FF1156 FF1156 package. X-Ref Target - Figure 1-10 B5 B6 MGTRXN3_116 A3 MGTTXP3_116 MGTTXN3_116 D5 MGTRXP2_116 D6 MGTRXN2_116 B1 MGTTXP2_116 B2 MGTTXN2_116 F6 MGTREFCLK1P_116 F5 MGTREFCLK1N_116 H6 MGTREFCLK0P_116 H5 MGTREFCLK0N_116 E3 MGTRXP1_116 E4 MGTRXN1_116 C3 MGTTXP1_116 C4 MGTTXN1_116 G3 MGTRXP0_116 G4 MGTRXN0_116 D1 MGTTXP0_116 D2 LX130T LX130T: GTXE1_X0Y18 X0Y18 LX195T LX195T: GTXE1_X0Y18 X0Y18 LX240T LX240T: GTXE1_X0Y18 X0Y18 LX365T LX365T: GTXE1_X0Y18 X0Y18 SX315T SX315T: GTXE1_X0Y18 X0Y18 SX475T SX475T: GTXE1_X0Y26 X0Y26 MGTRXP3_116 A4 LX130T LX130T: GTXE1_X0Y19 X0Y19 LX195T LX195T: GTXE1_X0Y19 X0Y19 LX240T LX240T: GTXE1_X0Y19 X0Y19 LX365T LX365T: GTXE1_X0Y19 X0Y19 SX315T SX315T: GTXE1_X0Y19 X0Y19 SX475T SX475T: GTXE1_X0Y27 X0Y27 MGTTXN0_116 QUAD_116 LX130T LX130T: GTXE1_X0Y17 X0Y17 LX195T LX195T: GTXE1_X0Y17 X0Y17 LX240T LX240T: GTXE1_X0Y17 X0Y17 LX365T LX365T: GTXE1_X0Y17 X0Y17 SX315T SX315T: GTXE1_X0Y17 X0Y17 SX475T SX475T: GTXE1_X0Y25 X0Y25 LX130T LX130T: GTXE1_X0Y16 X0Y16 LX195T LX195T: GTXE1_X0Y16 X0Y16 LX240T LX240T: GTXE1_X0Y16 X0Y16 LX365T LX365T: GTXE1_X0Y16 X0Y16 SX315T SX315T: GTXE1_X0Y16 X0Y16 SX475T SX475T: GTXE1_X0Y24 X0Y24 UG366 UG366_c1_10_051509 Figure 1-10: Virtex-6 FPGA GTX Transceivers User Guide UG366 UG366 (v1.0) June 24, 2009 Placement Diagram for the FF1156 FF1156 Package (1 of 5) www.xilinx.com 39 Chapter 1: Transceiver and Tool Overview X-Ref Target - Figure 1-11 J3 J4 MGTRXN3_115 F1 MGTTXP3_115 MGTTXN3_115 K5 MGTRXP2_115 K6 MGTRXN2_115 H1 MGTTXP2_115 H2 MGTTXN2_115 M6 MGTREFCLK1P_115 M5 MGTREFCLK1N_115 P6 MGTREFCLK0P_115 P5 MGTREFCLK0N_115 L3 MGTRXP1_115 L4 MGTRXN1_115 K1 MGTTXP1_115 K2 MGTTXN1_115 N3 MGTRXP0_115 N4 MGTRXN0_115 M1 MGTTXP0_115 M2 LX130T LX130T: GTXE1_X0Y14 X0Y14 LX195T LX195T: GTXE1_X0Y14 X0Y14 LX240T LX240T: GTXE1_X0Y14 X0Y14 LX365T LX365T: GTXE1_X0Y14 X0Y14 SX315T SX315T: GTXE1_X0Y14 X0Y14 SX475T SX475T: GTXE1_X0Y22 X0Y22 MGTRXP3_115 F2 LX130T LX130T: GTXE1_X0Y15 X0Y15 LX195T LX195T: GTXE1_X0Y15 X0Y15 LX240T LX240T: GTXE1_X0Y15 X0Y15 LX365T LX365T: GTXE1_X0Y15 X0Y15 SX315T SX315T: GTXE1_X0Y15 X0Y15 SX475T SX475T: GTXE1_X0Y23 X0Y23 MGTTXN0_115 QUAD_115 LX130T LX130T: GTXE1_X0Y13 X0Y13 LX195T LX195T: GTXE1_X0Y13 X0Y13 LX240T LX240T: GTXE1_X0Y13 X0Y13 LX365T LX365T: GTXE1_X0Y13 X0Y13 SX315T SX315T: GTXE1_X0Y13 X0Y13 SX475T SX475T: GTXE1_X0Y21 X0Y21 LX130T LX130T: GTXE1_X0Y12 X0Y12 LX195T LX195T: GTXE1_X0Y12 X0Y12 LX240T LX240T: GTXE1_X0Y12 X0Y12 LX365T LX365T: GTXE1_X0Y12 X0Y12 SX315T SX315T: GTXE1_X0Y12 X0Y12 SX475T SX475T: GTXE1_X0Y20 X0Y20 UG366 UG366_c1_11_051509 Figure 1-11: 40 Placement Diagram for the FF1156 FF1156 Package (2 of 5) www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide UG366 UG366 (v1.0) June 24, 2009 Implementation X-Ref Target - Figure 1-12 R3 R4 MGTRXN3_114 P1 MGTTXP3_114 MGTTXN3_114 U3 MGTRXP2_114 U4 MGTRXN2_114 T1 MGTTXP2_114 T2 MGTTXN2_114 T6 MGTREFCLK1P_114 T5 MGTREFCLK1N_114 V6 MGTREFCLK0P_114 V5 MGTREFCLK0N_114 W3 MGTRXP1_114 W4 MGTRXN1_114 V1 MGTTXP1_114 V2 MGTTXN1_114 AA3 MGTRXP0_114 AA4 MGTRXN0_114 Y1 MGTTXP0_114 Y2 LX130T LX130T: GTXE1_X0Y10 X0Y10 LX195T LX195T: GTXE1_X0Y10 X0Y10 LX240T LX240T: GTXE1_X0Y10 X0Y10 LX365T LX365T: GTXE1_X0Y10 X0Y10 SX315T SX315T: GTXE1_X0Y10 X0Y10 SX475T SX475T: GTXE1_X0Y18 X0Y18 MGTRXP3_114 P2 LX130T LX130T: GTXE1_X0Y11 X0Y11 LX195T LX195T: GTXE1_X0Y11 X0Y11 LX240T LX240T: GTXE1_X0Y11 X0Y11 LX365T LX365T: GTXE1_X0Y11 X0Y11 SX315T SX315T: GTXE1_X0Y11 X0Y11 SX475T SX475T: GTXE1_X0Y19 X0Y19 MGTTXN0_114 QUAD_114 LX130T LX130T: GTXE1_X0Y9 LX195T LX195T: GTXE1_X0Y9 LX240T LX240T: GTXE1_X0Y9 LX365T LX365T: GTXE1_X0Y9 SX315T SX315T: GTXE1_X0Y9 SX475T SX475T: GTXE1_X0Y17 X0Y17 LX130T LX130T: GTXE1_X0Y8 LX195T LX195T: GTXE1_X0Y8 LX240T LX240T: GTXE1_X0Y8 LX365T LX365T: GTXE1_X0Y8 SX315T SX315T: GTXE1_X0Y8 SX475T SX475T: GTXE1_X0Y16 X0Y16 UG366 UG366_c1_12_051509 Figure 1-12: Virtex-6 FPGA GTX Transceivers User Guide UG366 UG366 (v1.0) June 24, 2009 Placement Diagram for the FF1156 FF1156 Package (3 of 5) www.xilinx.com 41 Chapter 1: Transceiver and Tool Overview X-Ref Target - Figure 1-13 AC3 AC4 MGTRXN3_113 AB1 MGTTXP3_113 MGTTXN3_113 AE3 MGTRXP2_113 AE4 MGTRXN2_113 AD1 MGTTXP2_113 AD2 MGTTXN2_113 AB6 MGTREFCLK1P_113 AB5 MGTREFCLK1N_113 AD6 MGTREFCLK0P_113 AD5 MGTREFCLK0N_113 AF5 MGTRXP1_113 AF6 MGTRXN1_113 AF1 MGTTXP1_113 AF2 MGTTXN1_113 AG3 MGTRXP0_113 AG4 MGTRXN0_113 AH1 MGTTXP0_113 AH2 LX130T LX130T: GTXE1_X0Y6 LX195T LX195T: GTXE1_X0Y6 LX240T LX240T: GTXE1_X0Y6 LX365T LX365T: GTXE1_X0Y6 SX315T SX315T: GTXE1_X0Y6 SX475T SX475T: GTXE1_X0Y14 X0Y14 MGTRXP3_113 AB2 LX130T LX130T: GTXE1_X0Y7 LX195T LX195T: GTXE1_X0Y7 LX240T LX240T: GTXE1_X0Y7 LX365T LX365T: GTXE1_X0Y7 SX315T SX315T: GTXE1_X0Y7 SX475T SX475T: GTXE1_X0Y15 X0Y15 MGTTXN0_113 QUAD_113 LX130T LX130T: GTXE1_X0Y5 LX195T LX195T: GTXE1_X0Y5 LX240T LX240T: GTXE1_X0Y5 LX365T LX365T: GTXE1_X0Y5 SX315T SX315T: GTXE1_X0Y5 SX475T SX475T: GTXE1_X0Y13 X0Y13 LX130T LX130T: GTXE1_X0Y4 LX195T LX195T: GTXE1_X0Y4 LX240T LX240T: GTXE1_X0Y4 LX365T LX365T: GTXE1_X0Y4 SX315T SX315T: GTXE1_X0Y4 SX475T SX475T: GTXE1_X0Y12 X0Y12 UG366 UG366_c1_13_051509 Figure 1-13: 42 Placement Diagram for the FF1156 FF1156 Package (4 of 5) www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide UG366 UG366 (v1.0) June 24, 2009 Implementation X-Ref Target - Figure 1-14 AJ3 AJ4 MGTRXN3_112 AK1 MGTTXP3_112 MGTTXN3_112 AL3 MGTRXP2_112 AL4 MGTRXN2_112 AM1 MGTTXP2_112 AM2 MGTTXN2_112 AH6 MGTREFCLK1P_112 AH5 MGTREFCLK1N_112 AK6 MGTREFCLK0P_112 AK5 MGTREFCLK0N_112 AM5 MGTRXP1_112 AM6 MGTRXN1_112 AN3 MGTTXP1_112 AN4 MGTTXN1_112 AP5 MGTRXP0_112 AP6 MGTRXN0_112 AP1 MGTTXP0_112 AP2 LX130T LX130T: GTXE1_X0Y2 LX195T LX195T: GTXE1_X0Y2 LX240T LX240T: GTXE1_X0Y2 LX365T LX365T: GTXE1_X0Y2 SX315T SX315T: GTXE1_X0Y2 SX475T SX475T: GTXE1_X0Y10 X0Y10 MGTRXP3_112 AK2 LX130T LX130T: GTXE1_X0Y3 LX195T LX195T: GTXE1_X0Y3 LX240T LX240T: GTXE1_X0Y3 LX365T LX365T: GTXE1_X0Y3 SX315T SX315T: GTXE1_X0Y3 SX475T SX475T: GTXE1_X0Y11 X0Y11 MGTTXN0_112 QUAD_112 LX130T LX130T: GTXE1_X0Y1 LX195T LX195T: GTXE1_X0Y1 LX240T LX240T: GTXE1_X0Y1 LX365T LX365T: GTXE1_X0Y1 SX315T SX315T: GTXE1_X0Y1 SX475T SX475T: GTXE1_X0Y9 LX130T LX130T: GTXE1_X0Y0 LX195T LX195T: GTXE1_X0Y0 LX240T LX240T: GTXE1_X0Y0 LX365T LX365T: GTXE1_X0Y0 SX315T SX315T: GTXE1_X0Y0 SX475T SX475T: GTXE1_X0Y8 UG366 UG366_c1_14_051509 Figure 1-14: Virtex-6 FPGA GTX Transceivers User Guide UG366 UG366 (v1.0) June 24, 2009 Placement Diagram for the FF1156 FF1156 Package (5 of 5) www.xilinx.com 43 Chapter 1: Transceiver and Tool Overview FF1759 FF1759 Package Placement Diagrams Figure 1-15 through Figure 1-23 show the placement diagrams for the FF1759 FF1759 package. X-Ref Target - Figure 1-15 A5 A6 MGTRXN3_118 B3 MGTTXP3_118 MGTTXN3_118 B7 MGTRXP2_118 B8 MGTRXN2_118 C1 MGTTXP2_118 C2 LX240T LX240T: Not available LX365T LX365T: Not available LX550T LX550T: GTXE1_X0Y34 X0Y34 SX315T SX315T: Not available SX475T SX475T: GTXE1_X0Y34 X0Y34 MGTRXP3_118 B4 LX240T LX240T: Not available LX365T LX365T: Not available LX550T LX550T: GTXE1_X0Y35 X0Y35 SX315T SX315T: Not available SX475T SX475T: GTXE1_X0Y35 X0Y35 MGTTXN2_118 A10 MGTREFCLK1P_118 A9 MGTREFCLK1N_118 C10 MGTREFCLK0P_118 C9 MGTREFCLK0N_118 C5 MGTRXP1_118 C6 MGTRXN1_118 D3 MGTTXP1_118 D4 MGTTXN1_118 D7 MGTRXP0_118 D8 MGTRXN0_118 E1 MGTTXP0_118 E2 MGTTXN0_118 QUAD_118 LX240T LX240T: Not available LX365T LX365T: Not available LX550T LX550T: GTXE1_X0Y33 X0Y33 SX315T SX315T: Not available SX475T SX475T: GTXE1_X0Y33 X0Y33 LX240T LX240T: Not available LX365T LX365T: Not available LX550T LX550T: GTXE1_X0Y32 X0Y32 SX315T SX315T: Not available SX475T SX475T: GTXE1_X0Y32 X0Y32 UG366 UG366_c1_15_051509 Figure 1-15: 44 Placement Diagram for the FF1759 FF1759 Package (1 of 9) www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide UG366 UG366 (v1.0) June 24, 2009 Implementation X-Ref Target - Figure 1-16 E5 E6 MGTRXN3_117 F3 MGTTXP3_117 MGTTXN3_117 F7 MGTRXP2_117 F8 MGTRXN2_117 G1 MGTTXP2_117 G2 LX240T LX240T: GTXE1_X0Y22 X0Y22 LX365T LX365T: GTXE1_X0Y22 X0Y22 LX550T LX550T: GTXE1_X0Y30 X0Y30 SX315T SX315T: GTXE1_X0Y22 X0Y22 SX475T SX475T: GTXE1_X0Y30 X0Y30 MGTRXP3_117 F4 LX240T LX240T: GTXE1_X0Y23 X0Y23 LX365T LX365T: GTXE1_X0Y23 X0Y23 LX550T LX550T: GTXE1_X0Y31 X0Y31 SX315T SX315T: GTXE1_X0Y23 X0Y23 SX475T SX475T: GTXE1_X0Y31 X0Y31 MGTTXN2_117 E10 MGTREFCLK1P_117 E9 MGTREFCLK1N_117 G10 MGTREFCLK0P_117 G9 MGTREFCLK0N_117 G5 MGTRXP1_117 G6 MGTRXN1_117 H3 MGTTXP1_117 H4 MGTTXN1_117 H7 MGTRXP0_117 H8 MGTRXN0_117 J1 MGTTXP0_117 J2 MGTTXN0_117 QUAD_117 LX240T LX240T: GTXE1_X0Y21 X0Y21 LX365T LX365T: GTXE1_X0Y21 X0Y21 LX550T LX550T: GTXE1_X0Y29 X0Y29 SX315T SX315T: GTXE1_X0Y21 X0Y21 SX475T SX475T: GTXE1_X0Y29 X0Y29 LX240T LX240T: GTXE1_X0Y20 X0Y20 LX365T LX365T: GTXE1_X0Y20 X0Y20 LX550T LX550T: GTXE1_X0Y28 X0Y28 SX315T SX315T: GTXE1_X0Y20 X0Y20 SX475T SX475T: GTXE1_X0Y28 X0Y28 UG366 UG366_c1_16_051509 Figure 1-16: Virtex-6 FPGA GTX Transceivers User Guide UG366 UG366 (v1.0) June 24, 2009 Placement Diagram for the FF1759 FF1759 Package (2 of 9) www.xilinx.com 45 Chapter 1: Transceiver and Tool Overview X-Ref Target - Figure 1-17 J5 J6 MGTRXN3_116 K3 MGTTXP3_116 MGTTXN3_116 L5 MGTRXP2_116 L6 MGTRXN2_116 L1 MGTTXP2_116 L2 MGTTXN2_116 K8 MGTREFCLK1P_116 K7 MGTREFCLK1N_116 M8 MGTREFCLK0P_116 M7 MGTREFCLK0N_116 N5 MGTRXP1_116 N6 MGTRXN1_116 M3 MGTTXP1_116 M4 MGTTXN1_116 P7 MGTRXP0_116 P8 MGTRXN0_116 N1 MGTTXP0_116 N2 LX240T LX240T: GTXE1_X0Y18 X0Y18 LX365T LX365T: GTXE1_X0Y18 X0Y18 LX550T LX550T: GTXE1_X0Y26 X0Y26 SX315T SX315T: GTXE1_X0Y18 X0Y18 SX475T SX475T: GTXE1_X0Y26 X0Y26 MGTRXP3_116 K4 LX240T LX240T: GTXE1_X0Y19 X0Y19 LX365T LX365T: GTXE1_X0Y19 X0Y19 LX550T LX550T: GTXE1_X0Y27 X0Y27 SX315T SX315T: GTXE1_X0Y19 X0Y19 SX475T SX475T: GTXE1_X0Y27 X0Y27 MGTTXN0_116 QUAD_116 LX240T LX240T: GTXE1_X0Y17 X0Y17 LX365T LX365T: GTXE1_X0Y17 X0Y17 LX550T LX550T: GTXE1_X0Y25 X0Y25 SX315T SX315T: GTXE1_X0Y17 X0Y17 SX475T SX475T: GTXE1_X0Y25 X0Y25 LX240T LX240T: GTXE1_X0Y16 X0Y16 LX365T LX365T: GTXE1_X0Y16 X0Y16 LX550T LX550T: GTXE1_X0Y24 X0Y24 SX315T SX315T: GTXE1_X0Y16 X0Y16 SX475T SX475T: GTXE1_X0Y24 X0Y24 UG366 UG366_c1_17_051509 Figure 1-17: 46 Placement Diagram for the FF1759 FF1759 Package (3 of 9) www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide UG366 UG366 (v1.0) June 24, 2009 Implementation X-Ref Target - Figure 1-18 R5 R6 MGTRXN3_115 P3 MGTTXP3_115 P4 MGTTXN3_115 MGTRXP2_115 U6 MGTRXN2_115 R1 MGTTXP2_115 R2 MGTTXN2_115 T8 MGTREFCLK1P_115 T7 MGTREFCLK1N_115 V8 MGTREFCLK0P_115 V7 MGTREFCLK0N_115 V3 MGTRXP1_115 V4 MGTRXN1_115 T3 MGTTXP1_115 T4 MGTTXN1_115 W5 MGTRXP0_115 W6 MGTRXN0_115 U1 MGTTXP0_115 U2 LX240T LX240T: GTXE1_X0Y14 X0Y14 LX365T LX365T: GTXE1_X0Y14 X0Y14 LX550T LX550T: GTXE1_X0Y22 X0Y22 SX315T SX315T: GTXE1_X0Y14 X0Y14 SX475T SX475T: GTXE1_X0Y22 X0Y22 MGTRXP3_115 U5 LX240T LX240T: GTXE1_X0Y15 X0Y15 LX365T LX365T: GTXE1_X0Y15 X0Y15 LX550T LX550T: GTXE1_X0Y23 X0Y23 SX315T SX315T: GTXE1_X0Y15 X0Y15 SX475T SX475T: GTXE1_X0Y23 X0Y23 MGTTXN0_115 QUAD_115 LX240T LX240T: GTXE1_X0Y13 X0Y13 LX365T LX365T: GTXE1_X0Y13 X0Y13 LX550T LX550T: GTXE1_X0Y21 X0Y21 SX315T SX315T: GTXE1_X0Y13 X0Y13 SX475T SX475T: GTXE1_X0Y21 X0Y21 LX240T LX240T: GTXE1_X0Y12 X0Y12 LX365T LX365T: GTXE1_X0Y12 X0Y12 LX550T LX550T: GTXE1_X0Y20 X0Y20 SX315T SX315T: GTXE1_X0Y12 X0Y12 SX475T SX475T: GTXE1_X0Y20 X0Y20 UG366 UG366_c1_18_051509 Figure 1-18: Virtex-6 FPGA GTX Transceivers User Guide UG366 UG366 (v1.0) June 24, 2009 Placement Diagram for the FF1759 FF1759 Package (4 of 9) www.xilinx.com 47 Chapter 1: Transceiver and Tool Overview X-Ref Target - Figure 1-19 Y3 Y4 MGTRXN3_114 W1 MGTTXP3_114 MGTTXN3_114 AA5 MGTRXP2_114 AA6 MGTRXN2_114 AA1 MGTTXP2_114 AA2 LX240T LX240T: GTXE1_X0Y10 X0Y10 LX365T LX365T: GTXE1_X0Y10 X0Y10 LX550T LX550T: GTXE1_X0Y18 X0Y18 SX315T SX315T: GTXE1_X0Y10 X0Y10 SX475T SX475T: GTXE1_X0Y18 X0Y18 MGTRXP3_114 W2 LX240T LX240T: GTXE1_X0Y11 X0Y11 LX365T LX365T: GTXE1_X0Y11 X0Y11 LX550T LX550T: GTXE1_X0Y19 X0Y19 SX315T SX315T: GTXE1_X0Y11 X0Y11 SX475T SX475T: GTXE1_X0Y19 X0Y19 MGTTXN2_114 Y8 MGTREFCLK1P_114 Y7 MGTREFCLK1N_114 AB8 MGTREFCLK0P_114 AB7 MGTREFCLK0N_114 AB3 MGTRXP1_114 AB4 MGTRXN1_114 AC1 MGTTXP1_114 AC2 MGTTXN1_114 AC5 MGTRXP0_114 AC6 MGTRXN0_114 AE1 MGTTXP0_114 AE2 MGTTXN0_114 QUAD_114 LX240T LX240T: GTXE1_X0Y9 LX365T LX365T: GTXE1_X0Y9 LX550T LX550T: GTXE1_X0Y17 X0Y17 SX315T SX315T: GTXE1_X0Y9 SX475T SX475T: GTXE1_X0Y17 X0Y17 LX240T LX240T: GTXE1_X0Y8 LX365T LX365T: GTXE1_X0Y8 LX550T LX550T: GTXE1_X0Y16 X0Y16 SX315T SX315T: GTXE1_X0Y8 SX475T SX475T: GTXE1_X0Y16 X0Y16 UG366 UG366_c1_19_051509 Figure 1-19: 48 Placement Diagram for the FF1759 FF1759 Package (5 of 9) www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide UG366 UG366 (v1.0) June 24, 2009 Implementation X-Ref Target - Figure 1-20 AD3 AD4 MGTRXN3_113 AG1 MGTTXP3_113 MGTTXN3_113 AE5 MGTRXP2_113 AE6 MGTRXN2_113 AH3 MGTTXP2_113 AH4 MGTTXN2_113 AD8 MGTREFCLK1P_113 AD7 MGTREFCLK1N_113 AF8 MGTREFCLK0P_113 AF7 MGTREFCLK0N_113 AF3 MGTRXP1_113 AF4 MGTRXN1_113 AJ1 MGTTXP1_113 AJ2 MGTTXN1_113 AG5 MGTRXP0_113 AG6 MGTRXN0_113 AK3 MGTTXP0_113 AK4 LX240T LX240T: GTXE1_X0Y6 LX365T LX365T: GTXE1_X0Y6 LX550T LX550T: GTXE1_X0Y14 X0Y14 SX315T SX315T: GTXE1_X0Y6 SX475T SX475T: GTXE1_X0Y14 X0Y14 MGTRXP3_113 AG2 LX240T LX240T: GTXE1_X0Y7 LX365T LX365T: GTXE1_X0Y7 LX550T LX550T: GTXE1_X0Y15 X0Y15 SX315T SX315T: GTXE1_X0Y7 SX475T SX475T: GTXE1_X0Y15 X0Y15 MGTTXN0_113 QUAD_113 LX240T LX240T: GTXE1_X0Y5 LX365T LX365T: GTXE1_X0Y5 LX550T LX550T: GTXE1_X0Y13 X0Y13 SX315T SX315T: GTXE1_X0Y5 SX475T SX475T: GTXE1_X0Y13 X0Y13 LX240T LX240T: GTXE1_X0Y4 LX365T LX365T: GTXE1_X0Y4 LX550T LX550T: GTXE1_X0Y12 X0Y12 SX315T SX315T: GTXE1_X0Y4 SX475T SX475T: GTXE1_X0Y12 X0Y12 UG366 UG366_c1_20_051509 Figure 1-20: Virtex-6 FPGA GTX Transceivers User Guide UG366 UG366 (v1.0) June 24, 2009 Placement Diagram for the FF1759 FF1759 Package (6 of 9) www.xilinx.com 49 Chapter 1: Transceiver and Tool Overview X-Ref Target - Figure 1-21 AJ5 AJ6 MGTRXN3_112 AL1 MGTTXP3_112 MGTTXN3_112 AL5 MGTRXP2_112 AL6 MGTRXN2_112 AM3 MGTTXP2_112 AM4 MGTTXN2_112 AH8 MGTREFCLK1P_112 AH7 MGTREFCLK1N_112 AK8 MGTREFCLK0P_112 AK7 MGTREFCLK0N_112 AM7 MGTRXP1_112 AM8 MGTRXN1_112 AN1 MGTTXP1_112 AN2 MGTTXN1_112 AN5 MGTRXP0_112 AN6 MGTRXN0_112 AP3 MGTTXP0_112 AP4 LX240T LX240T: GTXE1_X0Y2 LX365T LX365T: GTXE1_X0Y2 LX550T LX550T: GTXE1_X0Y10 X0Y10 SX315T SX315T: GTXE1_X0Y2 SX475T SX475T: GTXE1_X0Y10 X0Y10 MGTRXP3_112 AL2 LX240T LX240T: GTXE1_X0Y3 LX365T LX365T: GTXE1_X0Y3 LX550T LX550T: GTXE1_X0Y11 X0Y11 SX315T SX315T: GTXE1_X0Y3 SX475T SX475T: GTXE1_X0Y11 X0Y11 MGTTXN0_112 QUAD_112 LX240T LX240T: GTXE1_X0Y1 LX365T LX365T: GTXE1_X0Y1 LX550T LX550T: GTXE1_X0Y9 SX315T SX315T: GTXE1_X0Y1 SX475T SX475T: GTXE1_X0Y9 LX240T LX240T: GTXE1_X0Y0 LX365T LX365T: GTXE1_X0Y0 LX550T LX550T: GTXE1_X0Y8 SX315T SX315T: GTXE1_X0Y0 SX475T SX475T: GTXE1_X0Y8 UG366 UG366_c1_21_051509 Figure 1-21: 50 Placement Diagram for the FF1759 FF1759 Package (7 of 9) www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide UG366 UG366 (v1.0) June 24, 2009 Implementation X-Ref Target - Figure 1-22 AP7 AP8 MGTRXN3_111 AR1 MGTTXP3_111 MGTTXN3_111 AR5 MGTRXP2_111 AR6 MGTRXN2_111 AT3 MGTTXP2_111 AT4 MGTTXN2_111 AT8 MGTREFCLK1P_111 AT7 MGTREFCLK1N_111 AU10 MGTREFCLK0P_111 AU9 MGTREFCLK0N_111 AU5 MGTRXP1_111 AU6 MGTRXN1_111 AU1 MGTTXP1_111 AU2 MGTTXN1_111 AV7 MGTRXP0_111 AV8 MGTRXN0_111 AV3 MGTTXP0_111 AV4 LX240T LX240T: Not available LX365T LX365T: Not available LX550T LX550T: GTXE1_X0Y6 SX315T SX315T: Not available SX475T SX475T: GTXE1_X0Y6 MGTRXP3_111 AR2 LX240T LX240T: Not available LX365T LX365T: Not available LX550T LX550T: GTXE1_X0Y7 SX315T SX315T: Not available SX475T SX475T: GTXE1_X0Y7 MGTTXN0_111 QUAD_111 LX240T LX240T: Not available LX365T LX365T: Not available LX550T LX550T: GTXE1_X0Y5 SX315T SX315T: Not available SX475T SX475T: GTXE1_X0Y5 LX240T LX240T: Not available LX365T LX365T: Not available LX550T LX550T: GTXE1_X0Y4 SX315T SX315T: Not available SX475T SX475T: GTXE1_X0Y4 UG366 UG366_c1_22_051509 Figure 1-22: Virtex-6 FPGA GTX Transceivers User Guide UG366 UG366 (v1.0) June 24, 2009 Placement Diagram for the FF1759 FF1759 Package (8 of 9) www.xilinx.com 51 Chapter 1: Transceiver and Tool Overview X-Ref Target - Figure 1-23 AW5 AW6 MGTRXN3_110 AW1 MGTTXP3_110 MGTTXN3_110 AY7 MGTRXP2_110 AY8 MGTRXN2_110 AY3 MGTTXP2_110 AY4 LX240T LX240T: Not available LX365T LX365T: Not available LX550T LX550T: GTXE1_X0Y2 SX315T SX315T: Not available SX475T SX475T: GTXE1_X0Y2 MGTRXP3_110 AW2 LX240T LX240T: Not available LX365T LX365T: Not available LX550T LX550T: GTXE1_X0Y3 SX315T SX315T: Not available SX475T SX475T: GTXE1_X0Y3 MGTTXN2_110 AW10 MGTREFCLK1P_110 AW9 MGTREFCLK1N_110 BA10 MGTREFCLK0P_110 BA9 MGTREFCLK0N_110 BA5 MGTRXP1_110 BA6 MGTRXN1_110 BA1 MGTTXP1_110 BA2 MGTTXN1_110 BB7 MGTRXP0_110 BB8 MGTRXN0_110 BB3 MGTTXP0_110 BB4 MGTTXN0_110 QUAD_110 LX240T LX240T: Not available LX365T LX365T: Not available LX550T LX550T: GTXE1_X0Y1 SX315T SX315T: Not available SX475T SX475T: GTXE1_X0Y1 LX240T LX240T: Not available LX365T LX365T: Not available LX550T LX550T: GTXE1_X0Y0 SX315T SX315T: Not available SX475T SX475T: GTXE1_X0Y0 UG366 UG366_c1_23_051509 Figure 1-23: 52 Placement Diagram for the FF1759 FF1759 Package (9 of 9) www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide UG366 UG366 (v1.0) June 24, 2009 Chapter 2 Shared Transceiver Features Reference Clock Selection Functional Description GTX transceivers provide several available reference clock inputs. Clock selection and availability changed slightly across the first three generations of Virtex® FPGA transceivers. The Virtex-6 FPGA GTX transceiver significantly enhances reference clock capabilities by adding dedicated clock routing and multiplexer resources. Architecturally, the concept of a Quad (or Q), contains a grouping of four GTXE1 primitives, two dedicated reference clock pin pairs, and dedicated reference clock routing. The term Quad in this document describes the reference clocking architecture of the Virtex-6 FPGA GTX transceivers. Reference clock features include: · Clock routing for north and south bound clocks. · Clock inputs available per GTX PLL. · Static or dynamic selection of the reference clock for the transmitter and receiver PLLs. Figure 2-1 shows the Quad architecture with four GTX transceivers, two dedicated reference clock pin pairs, and dedicated north/south reference clock routing. Each GTX transceiver in a Quad has seven clock inputs available: · Two local reference clock pin pairs, MGTREFCLK[0/1] · Two reference clock pin pairs from the Quads above, SOUTHREFCLK[0/1] · Two reference clocks pin pairs or below, NORTHREFCLK[0/1] · Internal to each GTX transceiver, the clock from the receiver can be forwarded to the transmit PLL reference clock, CAS_CLK. CAS_CLK must only be used for diagnostics purposes. Virtex-6 FPGA GTX Transceivers User Guide UG366 UG366 (v1.0) June 24, 2009 www.xilinx.com 53 Chapter 2: Shared Transceiver Features X-Ref Target - Figure 2-1 MGTREFCLK0[P/N] MGTREFCLK1[P/N] TX PLL PERFCLK CAS_CLK GREFCLK RX PLL NA GTX0 Q(n+1)NorthClk1 Q(n+1)NorthClk0 Q(n+1)SouthClk1 Q(n+1)SouthClk0 Q(n+1)RefClk1 Q(n+1)RefClk0 Q (n+1) Q (n) TX PLL Controlled by Software 1 0 CAS_CLK 0 1 RX PLL NA GTX3 MGTREFCLK0[P/N] GTX2 GTX1 NORTHREFCLK1 SOUTHREFCLK1 SOUTHREFCLK0 MGTREFCLK1 PERFCLK GREFCLK GREFCLK MGTREFCLK0 PERFCLK NORTHREFCLK0 MGTREFCLK1[P/N] TX PLL CAS_CLK RX PLL NA Q(n)NorthClk1 Q(n)NorthClk0 Q(n)SouthClk1 Q(n)SouthClk0 Q(n)RefClk1 Q(n)RefClk0 GTX0 Q (n-1) TX PLL Controlled by Software 1 0 CAS_CLK 0 1 RX PLL NA GTX3 MGTREFCLK0[P/N] MGTREFCLK1[P/N] PERFCLK GREFCLK UG366 UG366_c2_01_051509 Figure 2-1: 54 Conceptual View of GTX Transceiver Reference Clocking www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide UG366 UG366 (v1.0) June 24, 2009 Reference Clock Selection Figure 2-2 shows the detailed view of the reference clock multiplexer structure within a single GTXE1 primitive. The TXPLLREFSELDY and RXPLLREFSELDY ports are required when multiple reference clocks are used. A single reference clock is most commonly used. In this case, the TXPLLREFSELDY and RXPLLREFSELDY ports can be connected to 000, and the Xilinx software tools handle the complexity of the multiplexers and associated routing. See "Single External Reference Clock Use Model" for more information. X-Ref Target - Figure 2-2 GTX Transceiver TXPLLREFSELDY[2:0] MGTREFCLKTX[0] MGTREFCLKTX[1] NORTHREFCLKTX[0] NORTHREFCLKTX[1] SOUTHREFCLKTX[0] 0 1 2 3 4 5 6 SOUTHREFCLKTX[1] GREFCLKTX PERFCLKTX 0 1 Out CORECLK Out TX PLL REFCLK TX PLL 7 See Note 1 CAS_CLK RXPLLREFSELDY[2:0] MGTREFCLKRX[0] MGTREFCLKRX[1] NORTHREFCLKRX[0] NORTHREFCLKRX[1] SOUTHREFCLKRX[0] SOUTHREFCLKRX[1] 0 1 2 3 4 5 6 GREFCLKRX 0 PERFCLKRX 1 Out CORECLK See Note 1 Out RX PLL RX PLL REFCLK 7 NC(2) Default Configuration UG366 UG366_c2_02_051509 Notes: 1. The CORECLK multiplexer is controlled by software. If GREFCLK is connected, software configures the multiplexer to use GREFCLK. If the PERFCLK is connected, software configures the multiplexer to use PERFCLK. There is no user-controllable attribute to switch the multiplexer. Only one of the inputs can be connected at a time. 2. The CAS_CLK input to the RX PLL is not used or configured. Figure 2-2: GTX Transceiver Detailed Diagram The four GTX transceivers that make up a Quad share two dedicated reference clock pin pairs. The user design accesses these reference clocks by instantiating IBUFDS or IBUFDS_GTXE1 primitives. These reference clocks can be used locally by any of the four Virtex-6 FPGA GTX Transceivers User Guide UG366 UG366 (v1.0) June 24, 2009 www.xilinx.com 55 Chapter 2: Shared Transceiver Features GTX transceivers within the Quad. In addition, they can be routed to the GTX transceivers in the north or south neighboring Quads using the dedicated reference clock routing shown in Figure 2-1. Each GTX transceiver can also select reference clocks from the Quad below (Q(n-1) sourced from the NORTHREFCLKTX[0/1] and NORTHREFCLKRX[0/1] ports; reference clocks from the Quad above (Q(n+1) sourced from the SOUTHREFCLKTX[0/1] and SOUTHREFCLKRX[0/] ports; reference clocks from the FPGA logic sourced from PERFCLKTX and PERFCLKRX, or GREFCLKTX and GREFCLKRX. The Xilinx software tools handle the complexity of the multiplexers and associated routing for designs that require a single reference clock per GTX transceiver PLL. If dynamic switching of reference clocks is required, the user must set the reference clock multiplexers using the GTX TXPLLREFSELDY and RXPLLREFSELDY ports. The dedicated reference clock routing between Quads is set by the Xilinx software tools in both single and multiple reference clock modes. Internal clock nets of the FPGA can provide reference clocks for the GTX transceiver by connecting the output of a global clocking resource to the GTX PERFCLK or GREFCLK port. Only one of these inputs can be connected at a time. These reference clock ports have the lowest performance of the available clocking methods because FPGA clocking resources can introduce jitter for operation at high data rates. Use of PERFCLK and GREFCLK is reserved for internal test purposes only. Ports and Attributes Table 2-1 defines the GTX clocking ports. Table 2-1: GTX Clocking Ports Port Dir Clock Domain GREFCLKRX In Clock Internal FPGA logic clock. Reserved for internal testing purposes only. GREFCLKTX In Clock Internal FPGA logic clock. Reserved for internal testing purposes only. MGTREFCLKRX[1:0] In Clock External jitter stable clock driven by IBUFDS_GTXE1 for the RX PLL MGTREFCLKTX[1:0] In Clock External jitter stable clock driven by IBUFDS_GTXE1 for the TX PLL NORTHREFCLKRX[1:0] In Clock North-bound clocks from the Quad below NORTHREFCLKTX[1:0] In Clock North-bound clocks from the Quad below PERFCLKRX In Clock Internal FPGA logic clock. Reserved for internal testing purposes only. PERFCLKTX In Clock Internal FPGA logic clock. Reserved for internal testing purposes only. SOUTHREFCLKRX[1:0] In Clock South-bound clocks from the Quad above 56 Description www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide UG366 UG366 (v1.0) June 24, 2009 Single External Reference Clock Use Model Table 2-1: GTX C