UG229 FF665 FF1738 DSP48E FF1136 XCF32P AFX-FF665-500 AFX-FF1136-500 - Datasheet Archive

 

FPGA Prototype Platform LXT/SXT/FXT FPGA Prototype User Guide [optional] UG229 (v3.0.1) May 21, 2008 [optional] R P/N 0402534-03

 

Virtex-5 LXT/SXT/FXT FPGA Prototype Platform LXT/SXT/FXT FPGA Prototype User Guide [optional] UG229 UG229 (v3.0.1) May 21, 2008 [optional] R P/N 0402534-03 R Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the Documentation in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx. Xilinx expressly disclaims any liability arising out of your use of the Documentation. Xilinx reserves the right, at its sole discretion, to change the Documentation without notice at any time. Xilinx assumes no obligation to correct any errors contained in the Documentation, or to advise you of any corrections or updates. Xilinx expressly disclaims any liability in connection with technical support or assistance that may be provided to you in connection with the Information. THE DOCUMENTATION IS DISCLOSED TO YOU "AS-IS" WITH NO WARRANTY OF ANY KIND. XILINX MAKES NO OTHER WARRANTIES, WHETHER EXPRESS, IMPLIED, OR STATUTORY, REGARDING THE DOCUMENTATION, INCLUDING ANY WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NONINFRINGEMENT OF THIRD-PARTY RIGHTS. IN NO EVENT WILL XILINX BE LIABLE FOR ANY CONSEQUENTIAL, INDIRECT, EXEMPLARY, SPECIAL, OR INCIDENTAL DAMAGES, INCLUDING ANY LOSS OF DATA OR LOST PROFITS, ARISING FROM YOUR USE OF THE DOCUMENTATION. © 2006­2008 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, the Brand Window, and other designated brands included herein are trademarks of Xilinx, Inc. All other trademarks are the property of their respective owners. Revision History The following table shows the revision history for this document. Date Version Revision 12/04/06 1.0 Initial Xilinx release. 02/16/07 2.0 Updated title and added support for Virtex-5 FPGA SXT devices. 05/13/08 3.0 Added support for Virtex-5 FPGA FXT devices and RocketIO GTX transceivers. Added the supported Platforms to "Overview," page 9. Updated "Features," page 9. Removed CD ROM Contents section. Added "Additional Information," page 10. Updated Figure 1, page 11. Added "Related Xilinx Documents," page 12. Revised "1. Power Switch," page 13. Updated FF665 FF665 labels A13 and A14 in Table 13, page 26. Added "23. Configuration Mode Pins," page 29. Added "References," page 30. Miscellaneous typographical edits. 05/21/08 3.0.1 Updated link to FF1738 FF1738 platform product page in "Additional Information." Virtex-5 LXT/SXT/FXT FPGA Prototype Platform www.xilinx.com UG229 UG229 (v3.0.1) May 21, 2008 Table of Contents Preface: About This Guide Additional Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Additional Support Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Typographical Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Online Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Virtex-5 LXT/SXT/FXT FPGA Prototype Platform Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Package Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Additional Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Related Xilinx Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1. Power Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2. Power Supply Jacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3. Configuration Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4. JTAG Chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5. JTAG Termination Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6. Upstream/Downstream Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7. Prototyping Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8. VCCO-Enable Supply Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9. VBATT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10. Oscillator Sockets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11. Differential Clock Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12. DUT Socket . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13. Pin Breakout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14. User LEDs (Active-High) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15. PROGRAM Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16. RESET Switch (Active-Low) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17. DONE LED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18. INIT LED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19. Platform Flash ISPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20. SPI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21. BPI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22. GTP/GTX Transceiver Clocks to SMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23. Configuration Mode Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 15 16 17 17 18 20 20 20 21 21 22 22 23 24 24 24 24 24 25 26 28 29 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Virtex-5 LXT/SXT/FXT FPGA Prototype Platform UG229 UG229 (v3.0.1) May 21, 2008 www.xilinx.com 3 R 4 www.xilinx.com Virtex-5 LXT/SXT/FXT FPGA Prototype Platform UG229 UG229 (v3.0.1) May 21, 2008 R Preface About This Guide This user guide describes the features and operation of the Virtex®-5 LXT/SXT/FXT FPGA prototype platform and provides instructions to configure chains of FPGAs and serial PROMs. Complete and up-to-date documentation for the Virtex-5 LXT/SXT/FXT FPGA prototype platform is available on the Xilinx website at http://www.xilinx.com/onlinestore/v5_boards.htm. Additional Documentation The following documents are also available for download at http://www.xilinx.com/virtex5. · Virtex-5 Family Overview The features and product selection of the Virtex-5 family are outlined in this overview. · Virtex-5 FPGA Data Sheet: DC and Switching Characteristics This data sheet contains the DC and Switching Characteristic specifications for the Virtex-5 family. · Virtex-5 FPGA User Guide Chapters in this guide cover the following topics: Clock Management Technology (CMT) Phase-Locked Loops (PLLs) Block RAM Configurable Logic Blocks (CLBs) SelectIOTM Resources SelectIO Logic Resources · Clocking Resources Advanced SelectIO Logic Resources Virtex-5 FPGA RocketIO GTP Transceiver User Guide This guide describes the RocketIOTM GTP transceivers available in the Virtex-5 LXT and SXT platforms. · Virtex-5 FPGA RocketIO GTX Transceiver User Guide This guide describes the RocketIO GTX transceivers available in the Virtex-5 FXT platform. Virtex-5 LXT/SXT/FXT FPGA Prototype Platform UG229 UG229 (v3.0.1) May 21, 2008 www.xilinx.com 5 R Preface: About This Guide · Virtex-5 FPGA Tri-Mode Ethernet Media Access Controller This guide describes the dedicated Tri-Mode Ethernet Media Access Controller available in the Virtex-5 LXT, SXT, and FXT platforms. · Virtex-5 FPGA Integrated Endpoint Block User Guide for PCI Express Designs This guide describes the integrated Endpoint blocks in the Virtex-5 LXT, SXT, and FXT platforms used for PCI Express® designs. · XtremeDSP Design Considerations This guide describes the XtremeDSPTM slice and includes reference designs for using the DSP48E DSP48E slice. · Virtex-5 FPGA Configuration Guide This all-encompassing configuration guide includes chapters on configuration interfaces (serial and SelectMAP), bitstream encryption, Boundary-Scan and JTAG configuration, reconfiguration techniques, and readback through the SelectMAP and JTAG interfaces. · Virtex-5 FPGA System Monitor User Guide The System Monitor functionality available in all the Virtex-5 devices is outlined in this guide. · Virtex-5 FPGA Packaging and Pinout Specifications This specification includes the tables for device/package combinations and maximum I/Os, pin definitions, pinout tables, pinout diagrams, mechanical drawings, and thermal specifications. · Virtex-5 FPGA PCB Designer's Guide This guide provides information on PCB design for Virtex-5 devices, with a focus on strategies for making design decisions at the PCB and interface level. Additional Support Resources To search the database of silicon and software questions and answers, or to create a technical support case in WebCase, see the Xilinx website at: http://www.xilinx.com/support Typographical Conventions This document uses the following typographical conventions. An example illustrates each convention. Convention Italic font Meaning or Use Example See the Virtex-5 FPGA References to other documents Configuration User Guide for more information. Emphasis in text Underlined Text 6 The address (F) is asserted after clock event 2. Indicates a link to a web page. http://www.xilinx.com/virtex5 www.xilinx.com Virtex-5 LXT/SXT/FXT FPGA Prototype Platform UG229 UG229 (v3.0.1) May 21, 2008 R Typographical Conventions Online Document The following conventions are used in this document: Convention Meaning or Use Example See the section "Additional Support Resources" for details. Blue text Cross-reference link to a location in the current document Red text Cross-reference link to a location in another document See Figure 2 in the Virtex-5 FPGA Data Sheet Blue, underlined text Hyperlink to a website (URL) Go to http://www.xilinx.com for the latest documentation. Virtex-5 LXT/SXT/FXT FPGA Prototype Platform UG229 UG229 (v3.0.1) May 21, 2008 www.xilinx.com Refer to "Clock Management Technology" in Chapter 2 for details. 7 R Preface: About This Guide 8 www.xilinx.com Virtex-5 LXT/SXT/FXT FPGA Prototype Platform UG229 UG229 (v3.0.1) May 21, 2008 R Virtex-5 LXT/SXT/FXT FPGA Prototype Platform Overview The Virtex-5 FPGA prototype platform and demonstration boards enable designers to investigate and experiment with the features of Virtex-5 FPGAs. This user guide describes the features and operation of the Virtex-5 LXT/SXT/FXT prototype platform ("the board"), including how to configure chains of FPGAs and serial PROMs. This user guide covers the following platforms: · FF665 FF665, FF1136 FF1136, and FF1738 FF1738 Caution! To protect the Virtex-5 board from damage caused by electrostatic discharge (ESD), follow standard ESD prevention measures when handling the board. Note: Prototype platforms are intended strictly for evaluating the functionality of Virtex-5 FPGA features and are not intended for A/C characterization or high-speed I/O evaluation. Features · Independent power supply jacks for VCCINT, VCCO, and VCCAUX · Selectable VCCO-enable pins for each SelectIOTM bank · Configuration port for use with Parallel Cable III and Parallel Cable IV cables · 36 clock inputs 4 differential clock pairs 4 LVTTL-type oscillator sockets 20 breakout clock pins 2 pairs of RocketIOTM GTP/GTX transceiver clock inputs · Power indicator LEDs · Onboard Platform Flash ISPROM (32 Mb) for configuration · Onboard power supplies for the Platform Flash ISPROM · JTAG port for reprogramming the XCF32P XCF32P series reconfigurable ISPROM and the user FPGA, also known as the device under test (DUT) · Upstream and downstream System ACETM interface and configuration interface connectors · Serial Peripheral Interface (SPI) Serial Flash programming · Byte-wide Peripheral Interface (BPI) programming · SPI port for reprogramming the SPI Serial Flash Virtex-5 LXT/SXT/FXT FPGA Prototype Platform UG229 UG229 (v3.0.1) May 21, 2008 www.xilinx.com 9 R Overview · Onboard battery holder · One low-voltage, 14-pin, DIP crystal oscillator The kit contains headers that can be soldered to the breakout area, if desired. These headers are useful with certain types of oscilloscope probes for either connecting function generators or wiring pins to the prototype area. The Virtex-5 LXT/SXT/FXT FPGA prototype platform (the board) contains a DUT FPGA, one SPI, one BPI, and one In-System Programmable Configuration PROM (ISPROM). The ISPROM can hold up to 33,554,432 bits. The SPI Serial Flash holds up to 64 Mb. The BPI holds up to 256 Mb. The DUT can be configured from any one of the following: · ISPROM · SPI device · BPI device · Configuration ports (Parallel Cable III/IV cable) In addition to the ISPROM and the configuration ports, there are upstream connectors and downstream connectors. The upstream connectors can be connected to configure the DUT by using the System ACE configuration solution or by chaining another board. The downstream connectors can be used to connect to another board in a chain for serial configuration. A maximum of two boards can be chained together. Package Contents · Virtex-5 LXT/SXT/FXT prototype platform board · User guide · Device vacuum tool · Headers for test points · One low-voltage, 14-pin, dual-inline package (DIP) crystal oscillator · Four SMA-to-SMA cables Additional Information Additional information and support material is located at: · FF665 FF665: AFX-FF665-500 AFX-FF665-500 platform · FF1136 FF1136: AFX-FF1136-500 AFX-FF1136-500 platform · FF1738 FF1738: AFX-FF1738-500 AFX-FF1738-500 platform This information includes: · Current version of this user guide in PDF format · Full schematics in PDF format and ViewDraw schematic format · PC board layout in Allegro format · Gerber files for the PC board (Many free or shareware Gerber file viewers are available on the Internet for viewing and printing these files.) For information about the Virtex-5 family of FPGA devices, including product highlights, data sheets, user guides, and application notes, see the Virtex-5 website at www.xilinx.com/virtex5. Additional information is available from the data sheets and application notes from the component manufacturers. 10 www.xilinx.com Virtex-5 LXT/SXT/FXT FPGA Prototype Platform UG229 UG229 (v3.0.1) May 21, 2008 R Overview Block Diagram Figure 1 shows a block diagram of the board. X-Ref Target - Figure 1 2x Diff Pair 2x Diff Pair Clocks GTP/GTX Clocks Upstream Interface Connector Upstream System ACE Interface Connector 2x LVTTL SMA SMA SMA SMA Configuration Platform Flash, SPI, BPI, JTAG System Monitor To Test Points on All Pins Virtex-5 DUT User LEDs PROGRAM User RESET VBATT Downstream System ACE Interface Connector Downstream Interface Connector LVTTL 2x DONE LED SMA INIT LED SMA 2x Diff Pair Clocks Power Bus and Switches 5V Jack -or- GTP/GTX Transceiver Power Supply 5V Brick VCCO VCCINT VCCO VCCAUX VCC3 AVCCPLL VCC Jack AVTTTX VCCO Jack AVCC VCCAUX Jack AVTTRX VCC1V8 NOTE: The GTP/GTX transceiver power supply names might have the prefix MGT in other Xilinx documentation. Names with and without the MGT prefix are synonymous to each other. UG229 UG229_01_051208 Figure 1: Virtex-5 LXT/SXT/FXT FPGA Prototype Platform Block Diagram Virtex-5 LXT/SXT/FXT FPGA Prototype Platform UG229 UG229 (v3.0.1) May 21, 2008 www.xilinx.com 11 R Overview Related Xilinx Documents Prior to using the FF665 FF665, FF1136 FF1136, or FF1738 FF1738 prototype platform, users should be familiar with Xilinx resources. See "References" for direct links to Xilinx documentation. See the following locations for additional documentation on Xilinx tools and solutions: · EDK: www.xilinx.com/edk · ISE: www.xilinx.com/ise · Answer Browser: www.xilinx.com/support · Intellectual Property: www.xilinx.com/ipcenter 12 www.xilinx.com Virtex-5 LXT/SXT/FXT FPGA Prototype Platform UG229 UG229 (v3.0.1) May 21, 2008 R Detailed Description Detailed Description The Virtex-5 LXT/SXT/FXT FPGA prototype platform board is shown in Figure 2. The numbered sections on the pages following the figures contain details on each feature. Note: The image might not reflect the current revision of the board. X-Ref Target - Figure 2 6c 6a 22 3 10 13 10 1 11 9 19 23 13 8 13 12 4 20 2 18 7 17 13 21 22 15 16 5 6d 6b 14 UG229 UG229_02_022008 Figure 2: Detailed Description of Virtex-5 LXT/SXT/FXT FPGA Prototype Platform Components 1. Power Switch The board has an onboard power supply and an ON|OFF power switch (SW3). The green LED (DS19) lights up to indicate power from the power brick connector or the 5V jack (J32). On Position In the ON position, the power switch enables delivery of all power to the board by way of voltage regulators situated on the backside of the board. These regulators feed off a 5V external power brick or the 5V power supply jack (J32). The voltage regulators deliver fixed voltages. The maximum current range for each supply varies. Table 1, page 14 shows the maximum voltage and maximum current for each onboard power supply. If the current exceeds maximum ratings, use the power jacks to supply power to the DUT. Virtex-5 LXT/SXT/FXT FPGA Prototype Platform UG229 UG229 (v3.0.1) May 21, 2008 www.xilinx.com 13 R Detailed Description Table 1: Voltage Ranges Label Maximum Voltage Maximum Current VCCINT 1.0V 7A VCCO 2.5V 4A VCCAUX 2.5V 3A VCC1V8 1.8V 3A AVCC(1) 1.0V 1.5A 1.0V, 1.2V 1.5A AVTTTX(1) 1.2V 1.5A AVTTRX(1) 1.2V 1.5A AVCCPLL (1,2) Notes: 1. This GTP/GTX transceiver power supply name might have the prefix MGT in other Xilinx documentation. Names with and without the MGT prefix are synonymous to each other. 2. The maximum voltage for AVCCPLL is 1.0V for FXT devices; 1.2V for LXT and SXT devices. Off Position In the OFF position, the power switch disables all modes of powering the DUT. Table 2: Power Enable Jumpers Header Description These headers are in each power supply and are marked REG ENABLE. J19 J20 J21 Placement of jumpers on these headers enables delivery of all power from the onboard regulators. Removing all jumpers allows the user to provide power from the three power supply jacks marked VCCINT, VCCO, and VCCAUX. Note: If using an external bench top power supply, 5V must be applied to the 5V jack, J32, for proper operation. This header provides GTP/GTX transceiver power. J36 If J36 is a 2-pin header, install jumper for proper operation. If J36 is a 3-pin header, install jumper on pins 2-3 for proper operation. J37 These headers provide GTP/GTX transceiver power. J38 Pins 2-3 are marked for onboard regulation. Keep jumpers on these pins enabled for proper operation. J39 14 www.xilinx.com Virtex-5 LXT/SXT/FXT FPGA Prototype Platform UG229 UG229 (v3.0.1) May 21, 2008 R Detailed Description AVCCPLL The J84 header adjusts AVCCPLL to 1.2V for LXT/SXT devices and 1.0V for FXT devices (Figure 3). Header J84 is located directly above header J36 in the upper left quadrant of the board. However, if your board does not contain header J84, you can ignore Figure 3. X-Ref Target - Figure 3 LXT/SXT Devices FXT Devices J84 J84 1 1 2 2 3 3 UG229 UG229_03_050407 Figure 3: Power Jumper Setting for LXT, SXT, and FXT Devices Note: If your board contains the J84 header, be sure to place a jumper on J84 before powering up the board for proper operation. 2. Power Supply Jacks One method of delivering power to the DUT is by way of the power supply jacks: VCCINT (J33), VCCO (J31), and VCCAUX (J30). See Virtex-5 FPGA Data Sheet: DC and Switching Characteristics [Ref 1] for the maximum voltage rating for each device. The power supply jacks are: · VCCINT · Supplies voltage to the VCCINT of the DUT VCCO · Supplies I/O voltages to the DUT Each bank can be powered from one of two sources (VCCO, VCCINT) by appropriate placement of jumpers on the header VCCAUX Supplies voltage to the VCCAUX DUT pins Virtex-5 LXT/SXT/FXT FPGA Prototype Platform UG229 UG229 (v3.0.1) May 21, 2008 www.xilinx.com 15 R Detailed Description 3. Configuration Ports The configuration port header (J17) supports all Virtex-5 device configuration modes. For use with a Parallel Cable III or Parallel Cable IV cable, the header supports Slave Serial and JTAG configuration modes. Table 3 shows Serial mode connectivity between the configuration port header and a Parallel Cable III or Parallel Cable IV flying-wire cable. Table 3: Serial Mode Configuration Port Header Parallel Cable III/IV Pins VCC3 VCC GND GND CCLK CCLK DONE D/P DIN DIN PROG PROG INIT Table 4 shows JTAG mode connectivity between the configuration port header and a Parallel Cable III or Parallel Cable IV flying-wire cable. Table 4: JTAG Mode Configuration Port Header Parallel Cable III Pins Parallel Cable IV Pins VCC3V3 VCC VCC GND GND GND TMS TMS TMS TDI TDI TDI TDO TDO TDO TCK TCK TCK INIT INIT PC4 JTAG Configuration Interface The JTAG configuration port (J1) for the board allows for device programming and FPGA debug. This interface can be used with a Parallel Cable III or Parallel Cable IV cable for JTAG programming and debugging via the JTAG configuration port. 16 www.xilinx.com Virtex-5 LXT/SXT/FXT FPGA Prototype Platform UG229 UG229 (v3.0.1) May 21, 2008 R Detailed Description 4. JTAG Chain J41 is a 2 x 3 header (Figure 4) that allows users to select either the ISPROM or the FPGA or both devices in the JTAG chain. Table 5 shows the jumper settings for the JTAG chain header. X-Ref Target - Figure 4 J41 PROM_TDO TDI 1 2 3 5 4 6 FPGA_TDO ON_BOARD_TDO UG229 UG229_04_050407 Figure 4: Table 5: JTAG Chain Jumper J41 Jumper Settings J41 Pin Jumpers PROM JTAG 1-3 Enable 3-5 FPGA JTAG Disable 2-4 Enable 4-6 Disable 5. JTAG Termination Header When connecting another board to the downstream System ACE interface connector (P3) or the downstream interface connector (P4), jumper pins 1-2 on the JTAG termination header (J22); otherwise jumper pins 2-3 for on-board termination. The TCK and TMS pins are parallel feedthrough connections from the upstream System ACE interface connector to the downstream System ACE interface connector and drive the TCK and TMS pins of the onboard PROM and the DUT. Note: The termination jumper must be in place on the last board in the chain to connect the TDO pin of the final device to the TDO feedback chain. Virtex-5 LXT/SXT/FXT FPGA Prototype Platform UG229 UG229 (v3.0.1) May 21, 2008 www.xilinx.com 17 R Detailed Description 6. Upstream/Downstream Connectors 6a. Upstream System ACE Interface Connector The upstream System ACE interface connector (P1) can be used to configure the DUT (Figure 5). Any JTAG configuration stream can source this connector. For example, a System ACE controller with a CompactFlash card can be used to generate very large JTAG streams for configuring multiple Virtex-5 FPGA prototype platforms using the downstream System ACE interface connector. X-Ref Target - Figure 5 GND UPSTREAM_TDI GND UPSTREAM_TMS NC UPSTREAM_TDO GND UPSTREAM_TCK GND VCC_TMP 19 17 15 13 11 9 7 5 3 1 20 18 16 14 12 10 8 6 4 2 VCC3_EN VCC3_EN VCC3_EN VCC3_EN GND VCC_TMP VCC_TMP VCC_TMP VCC_TMP GND Figure 5: UG229 UG229_05_050407 Upstream System ACE Interface Connector (20-Pin Female) 6b. Downstream System ACE Interface Connector The downstream System ACE interface connector (P3) is used to pass configuration information to a DUT in a downstream prototype platform board from sources such as a Parallel Cable III cable or an upstream System ACE interface connector (Figure 6). X-Ref Target - Figure 6 GND VCC_TMP VCC_TMP VCC_TMP VCC_TMP GND VCC3_EN VCC3_EN VCC3_EN VCC3_EN 20 18 16 14 12 10 8 6 4 2 19 17 15 13 11 9 7 5 3 1 VCC_TMP GND DOWNSTREAM_TCK GND DOWNSTREAM_TDO NC DOWNSTREAM_TMS GND DOWNSTREAM_TDI GND UG229 UG229_06_050407 Figure 6: 18 Downstream System ACE Interface Connector (20-Pin Male) www.xilinx.com Virtex-5 LXT/SXT/FXT FPGA Prototype Platform UG229 UG229 (v3.0.1) May 21, 2008 R Detailed Description 6c. Upstream Interface Connector The upstream interface connector (P2) is used to configure the DUT in select map or slaveserial mode (Figure 7). This connector can be sourced by a downstream interface connector of another prototype platform board. X-Ref Target - Figure 7 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 GND GND GND NC AFX_M2 AFX_M1 AFX_M0 NC NC NC CS_B B1 NC NC NC NC NC NC NC NC INIT PROG RW_B A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 GND GND GND GND NC NC NC GND NC NC NC DIN D1 D2 D3 D4 D5 D6 D7 DONE CCLK DOUT_BUSY UG229 UG229_07_051506 Figure 7: Virtex-5 LXT/SXT/FXT FPGA Prototype Platform UG229 UG229 (v3.0.1) May 21, 2008 Upstream Interface Connector (44-Pin Female) www.xilinx.com 19 R Detailed Description 6d. Downstream Interface Connector The downstream interface connector (P4) passes serial configuration information to the DUT in the downstream prototype platform board (Figure 8). X-Ref Target - Figure 8 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 NC CLK DONE NC NC NC NC NC NC NC DOUT_BUSY A1 GND NC NC GND GND GND GND GND GND GND GND B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 NC PROG INIT NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC GND GND GND UG229 UG229_08_050407 Figure 8: Downstream Interface Connector (44-Pin Male) 7. Prototyping Area The prototyping area accommodates 0.10-inch spaced ICs. The kit contains headers that can be soldered to the breakout area, if desired. Power and ground buses are located at the top and bottom edges, respectively, of the prototyping area. 8. VCCO-Enable Supply Jumpers Virtex-5 FPGAs have 9 to 33 SelectIO banks (J44 and J45), labeled VCCO_0 to VCCO_34, each with a VCCO-enable supply jumper. The VCCO-enable supply jumpers can connect each bank to one of the two onboard supplies, the VCCINT or VCCO supplies. These jumpers must be installed for the Virtex-5 device to function normally. 9. VBATT An onboard battery holder (B1) is connected to the VBATT pin of the DUT. If an external power supply is used, the associated jumper must be removed; instead, use a 12-mm lithium coin battery (3V). 20 www.xilinx.com Virtex-5 LXT/SXT/FXT FPGA Prototype Platform UG229 UG229 (v3.0.1) May 21, 2008 R Detailed Description 10. Oscillator Sockets The board has four crystal oscillator sockets (X1, X2, X3, X4), all wired for standard LVTTL-type oscillators. These sockets connect to the DUT clock pads (Table 6). Onboard termination resistors can be changed by the user. The oscillator sockets accept both halfand full-sized oscillators and are powered by the DUT VCCO power supply. Table 6: Oscillator Socket Clock Pin Connections Pin Number Label Clock Name FF665 FF665 FF1136 FF1136 FF1738 FF1738 OSC Socket Top 1 IO_L1P_CC_GC_3 D16 K17 M26 OSC Socket Top 2 IO_L1N_CC_GC_3 E16 L18 L27 OSC Socket Bottom 1 IO_L8P_CC_GC_4 AC17 AF18 AL27 OSC Socket Bottom 2 IO_L8N_CC_GC_4 AB16 AE18 AL26 11. Differential Clock Inputs In addition to the oscillator sockets, there are eight 50 SMA connectors (J5, J6, J7, J8, J9, J10, J11, J12) that allow connection to an external function generator. These connect to the DUT clock pads (Table 7). They can also be used as differential clock inputs. The differential clock pairings (differential pairs) are as shown in Table 7. Table 7: SMA Clock Pin Connections Pin Number Label Clock Name FF665 FF665 FF1136 FF1136 FF1738 FF1738 P IO_L0P_CC_GC_3 D15 H17 J16 N IO_L0N_CC_GC_3 E15 H18 J15 P IO_L9P_GC_3 F20 H19 K30 N IO_L9N_GC_3 G21 H20 L30 P IO_L9P_CC_GC_4 AB15 AH18 AP16 N IO_L9N_CC_GC_4 AC16 AG17 AP15 P IO_L6P_GC_4 AC18 AG18 AM27 N IO_L6N_GC_4 AB17 AF19 AM26 Virtex-5 LXT/SXT/FXT FPGA Prototype Platform UG229 UG229 (v3.0.1) May 21, 2008 www.xilinx.com 21 R Detailed Description 12. DUT Socket The DUT socket (U1) contains the user FPGA. The DUT must be oriented using the P1 indicator on the board. Caution! Failure to insert the device to the proper orientation can damage the device. To avoid pin damage, always use the vacuum tool provided when inserting or removing the Virtex-5 device. When using BGA packages, do not apply pressure to the device while activating the socket. Doing so can damage the socket and/or the device. 13. Pin Breakout The pin breakout area is used to monitor or apply signals to each of the DUT pins. Headers can be soldered to the breakout area to use with certain types of oscilloscope probes, for either connecting function generators or wiring pins to the pin breakout area. Table 8 shows the clocks in the pin breakout area that connect to the DUT clock pads. Table 8: Breakout Clock Pin Connections Pin Number Label Clock Name FF1738 FF1738 D14 G15 J17 IO_L2N_GC_VRP_3 D13 G16 K17 IO_L3P_GC_3 E17 K18 M27 IO_L3N_GC_3 D18 J19 M28 IO_L4P_GC_3 E13 J16 L17 IO_L4N_GC_VREF_3 E12 J17 M17 IO_L5P_GC_3 E18 L19 L29 IO_L5N_GC_3 F19 K19 K28 IO_L6P_GC_3 F12 H14 L16 IO _L6N _GC_3 E11 H15 L15 IO_L7P_GC_3 E20 J20 K29 IO _L7N _GC _3 E21 J21 J30 IO_L8P_GC_3 E10 J14 L14 IO_L8N_GC_3 F10 H13 K15 IO_L4P_GC_4 AB19 AG21 AP27 IO_L4N_GC_VREF_4 AC19 AG20 AN28 IO_L5P_GC_4 AC12 AH15 AM16 IO_L5N_GC_4 AC13 AG15 AM17 IO_L7P_GC_VRN_4 AB14 AH17 AN15 IO_L7N_GC_VRP_4 22 FF1136 FF1136 IO_L2P_GC_VRN_3 Breakout Area FF665 FF665 AC14 AG16 AN16 www.xilinx.com Virtex-5 LXT/SXT/FXT FPGA Prototype Platform UG229 UG229 (v3.0.1) May 21, 2008 R Detailed Description 14. User LEDs (Active-High) There are 16 active-High user LEDs on the board. Before configuration, the LEDs reflect the status of the configuration mode pins. During configuration, the LEDs are in a highimpedance condition. After configuration, the LEDs are available to the user and reflect the status of pins D0-D7 and D24-D31 D24-D31 (corresponding to LED 0- LED 15). Table 9 shows the LED assignments. Table 9: LED Assignments and Corresponding I/O Pin Number For Package Type LED FF665 FF665 FF1136 FF1136 FF1738 FF1738 0 E25 A33 G42 1 E26 B32 F42 2 G26 C33 G41 3 F25 B33 F41 4 G25 D32 J41 5 H26 C32 H41 6 G24 D34 K42 F24 C34 J42 K21 H33 Y40 9 E23 G32 L40 10 F22 E34 M41 11 F23 F33 L42 12 H22 E33 N41 13 G22 E32 M42 14 J23 F34 P40 15 H23 G33 N40 7 8 After Configuration Available as user LEDs Virtex-5 LXT/SXT/FXT FPGA Prototype Platform UG229 UG229 (v3.0.1) May 21, 2008 www.xilinx.com 23 R Detailed Description 15. PROGRAM Switch This active-Low PROGRAM switch (SW1) grounds the DUT's PROG pin when pressed. This action clears the DUT. 16. RESET Switch (Active-Low) The RESET switch (SW2) connects to a standard I/O pin on the DUT, allowing the user, after configuration, to reset the logic within the DUT. When pressed, this switch grounds the pin. Table 10 shows the INIT pin locations for the available DUT package types. Table 10: User Hardware and Corresponding I/O Pins Pin Number For Package Type Label FF665 FF665 FF1136 FF1136 FF1738 FF1738 RESET J21 J32 W40 Notes: Refer to the readme.txt file for implementation of these user pins. 17. DONE LED The DONE LED (DS2) indicates the status of the DONE pin on the DUT. This LED lights up when DONE is High or if power is applied to the board without a part in the socket. 18. INIT LED The INIT LED (DS1) lights when the DUT has successfully powered up and completed its internal power-on process. 19. Platform Flash ISPROM A 32-Mb Platform Flash ISPROM (U4) is provided on the board for configuration (Table 11). Refer to the Platform Flash ISPROM data sheet [Ref 2] for a detailed description. Table 11: Platform Flash ISPROM Configuration Label Description J42 Provides power to the ISPROM. These jumpers must be installed for proper operation of the ISPROM. J43 Sets the design revision control for the ISPROM. J24 Enables or disables the ISPROM by placing the address counter in reset and DATA output lines in high-impedance state. J27 Sets the ISPROM for serial or select map configuration. Selects one of two modes of CCLK operation: J3 24 · ISPROM provides CCLK (PROM CLKOUT) · FPGA provides CCLK (FPGA CCLK) www.xilinx.com Virtex-5 LXT/SXT/FXT FPGA Prototype Platform UG229 UG229 (v3.0.1) May 21, 2008 R Detailed Description 20. SPI Interface The SPI interface is a four-wire, synchronous serial data bus configuration. The interface utilizes a 64-Mb STMicroelectronics low-voltage, serial Flash memory device (U10), part number M25P64 M25P64, which can be used for FPGA configuration or to hold user data. A SPI system typically consists of a master device and at least one slave device. For Virtex-5 FPGA configuration, the FPGA is the SPI master and the SPI Flash PROM is the slave device. The SPI interface uses four signals (Table 12) to communicate between the FPGA and the Flash PROM device. Table 12: SPI Pins Pin Number For Package Type Label FF665 FF665 FF1136 FF1136 FF1738 FF1738 Serial Clock (C) J11 N15 AH14 Serial Data Out (Q) J10 P15 R15 Chip Select (S_N) Y12 AE14 AL14 Serial Data In (D) AA12 AF14 AM13 The J2 connector allows users to connect a Parallel Cable IV ribbon cable to configure the SPI device. For SPI programming, refer to the latest version of Xilinx iMPACT software tool documentation [Ref 6]. To set the Mode pins for SPI configuration, see the Virtex-5 FPGA Configuration User Guide [Ref 3]. The PROGRAM pin must be held Low when configuring the SPI device. After configuring the SPI device, the PROGRAM pin must be released to configure the FPGA from the SPI device. Virtex-5 LXT/SXT/FXT FPGA Prototype Platform UG229 UG229 (v3.0.1) May 21, 2008 www.xilinx.com 25 R Detailed Description 21. BPI Interface The BPI interface is a x16 asynchronous bus configuration. The BPI device is a 256-Mb Intel Strata Flash (U18), part number JS28F256P30 JS28F256P30. Table 13 shows the pin mapping from the BPI device to the FPGA. Table 13: BPI Pins Pin Number For Package Type Label FF665 FF665 FF1738 FF1738 DQ0 AA15 AD19 AJ26 DQ1 Y15 AE19 AK27 DQ2 W14 AE17 AM14 DQ3 Y13 AF16 AN14 DQ4 W16 AD20 AK29 DQ5 Y16 AE21 AK28 DQ6 AA14 AE16 AP13 DQ7 AA13 AF15 AN13 DQ8 AB12 AH13 AL16 DQ9 AC11 AH14 AL15 DQ10 AB20 AH19 AP28 DQ11 AB21 AH20 AN29 DQ12 AB11 AG13 AL17 DQ13 AB10 AH12 AK17 DQ14 AA20 AH22 AP30 DQ15 Y21 AG22 AN30 A1 H9 K12 P13 A2 G10 K13 N13 A3 H21 H23 M29 A4 G20 G23 N30 A5 H11 H12 M13 A6 G11 J12 M14 A7 H19 K22 N29 A8 H18 K23 N28 A9 G12 K14 N14 A10 F13 L14 N15 A11 26 FF1136 FF1136 G19 H22 P28 www.xilinx.com Virtex-5 LXT/SXT/FXT FPGA Prototype Platform UG229 UG229 (v3.0.1) May 21, 2008 R Detailed Description Table 13: BPI Pins (Cont'd) Pin Number For Package Type Label FF665 FF665 FF1136 FF1136 FF1738 FF1738 A12 F18 G22 P27 A13 F14 J15 N16 A14 F15 K16 M16 A15 F17 K21 N26 A16 G17 J22 P26 A17 G14 L16 P17 A18 H13 L15 P18 A19 G16 L20 P25 A20 G15 L21 N25 A21 Y18 AE23 AM29 A22 AA18 AE22 AL30 A23 Y11 AG12 AK14 A24 AA10 AF13 AK15 WE_N AA17 AF20 AM28 WP_N Y5 M5 AA6 ADV_N Y6 M6 AA7 RST_N K7 U7 N6 CE_N Y12 AE14 AL14 WAIT K6 T8 N5 CLK U5 J7 U6 OE_N AA12 AF14 AM13 J47 is a three-pin header that allows users to connect the OE signal to VCC or to an FPGA pin. Jumper pin 1 to 2 connects the OE signal to VCC. Jumper pin 2 to 3 connects the OE signal to an FPGA IOB. Table 13 shows the corresponding FPGA pin. J54 allows users to connect the revision select (RS) signals to the highest address lines of the BPI device. Jumper pins 1 to 3 and pins 2 to 4 connect address 23 and address 24 to FPGA IOBs. Jumper pins 3 to 5 and pins 4 to 6 connect RS0 and RS1 to the highest address lines of the BPI device. See the Virtex-5 FPGA Configuration User Guide [Ref 3] for more information on how the RS signals can be applied in a user's application. Virtex-5 LXT/SXT/FXT FPGA Prototype Platform UG229 UG229 (v3.0.1) May 21, 2008 www.xilinx.com 27 R Detailed Description 22. GTP/GTX Transceiver Clocks to SMA GTP/GTX Transceiver Clock Inputs The Virtex-5 FPGA prototype platform provides a high-speed differential clock input used to clock the input and output serial data from the GTP/GTX transceivers. Table 14 shows GTP/GTX transceiver clocks and their corresponding FPGA pins. The GTP/GTX transceivers are looped back and are not connected to test points or SMA connectors. See the Virtex-5 FPGA RocketIO GTP Transceiver User Guide [Ref 4] and the Virtex-5 FPGA RocketIO GTX Transceiver User Guide [Ref 5] for more information on GTP/GTX transceiver operation. Table 14: GTP/GTX Transceiver Clock Pins Pin Number For Package Type LABEL FF665 FF665 FF1136 FF1136 FF1738 FF1738 REFCLKN_116 D3 H3 M3 REFCLKP_116 D4 H4 M4 REFCLKN_118 AB3 AF3 AK3 REFCLKP_118 AB4 AF4 AK4 Notes: 1. These GTP/GTX clock pin names might have the prefix MGT in other Xilinx documentation. Names with and without the MGT prefix are synonymous to each other. 28 www.xilinx.com Virtex-5 LXT/SXT/FXT FPGA Prototype Platform UG229 UG229 (v3.0.1) May 21, 2008 R Detailed Description 23. Configuration Mode Pins The three jumpers on J17 control the configuration mode pins M0-M2. These pins set the configuration mode for the FPGA and determine the direction of CCLK (Table 15 and Figure 9). A jumper across both columns of J17 for each mode pin sets logic 0; removing the jumper sets logic 1. The default value 000 corresponds to the Master Serial configuration mode. Table 15: Configuration Mode Pin Jumper Settings Configuration Mode M2 M1 M0 CCLK Direction Master Serial 0 0 0 Output Master SPI 0 0 1 Output Master BPI-Up 0 1 0 Output Master BPI-Down 0 1 1 Output Master SelectMAP 1 0 0 Output JTAG 1 0 1 Input (TCK) Slave SelectMAP 1 1 0 Input Slave Serial 1 1 1 Input X-Ref Target - Figure 9 J17 (HDR_2x29) M2 M1 M0 UG229 UG229_09_041108 Figure 9: Virtex-5 LXT/SXT/FXT FPGA Prototype Platform UG229 UG229 (v3.0.1) May 21, 2008 Default Configuration Mode Jumper Settings www.xilinx.com 29 R References References 1. DS202 DS202, Virtex-5 FPGA Data Sheet: DC and Switching Characteristics 2. DS123 DS123, Platform Flash ISPROM 3. UG191 UG191, Virtex-5 FPGA Configuration User Guide 4. UG196 UG196, Virtex-5 FPGA RocketIO GTP Transceiver User Guide 5. 6. UG198 UG198, Virtex-5 FPGA RocketIO GTX Transceiver User Guide iMPACT Software Tool Documents supporting Virtex-5 devices: 1. DS100 DS100, Virtex-5 Family Overview 2. DS202 DS202, Virtex-5 FPGA Data Sheet: DC and Switching Characteristics. 3. UG190 UG190, Virtex-5 FPGA User Guide. 4. UG196 UG196, Virtex-5 FPGA RocketIO GTP Transceiver User Guide. 5. UG198 UG198, Virtex-5 FPGA RocketIO GTX Transceiver User Guide. 6. UG194 UG194, Virtex-5 FPGA Tri-Mode Ethernet Media Access Controller User Guide. 7. UG197 UG197, Virtex-5 FPGA Integrated Endpoint Block User Guide for PCI Express Designs. 8. UG193 UG193, XtremeDSP Design Considerations. 9. UG191 UG191, Virtex-5 FPGA Configuration User Guide. 10. UG192 UG192, Virtex-5 FPGA System Monitor User Guide. 11. UG195 UG195, Virtex-5 FPGA Packaging and Pinout Specification. 30 www.xilinx.com Virtex-5 LXT/SXT/FXT FPGA Prototype Platform UG229 UG229 (v3.0.1) May 21, 2008