U-153 UC3855A/B UDG-95151 UC3855 UDG-95152 UDG-95153 DIL-20 UDG-94001-2 - Datasheet Archive

 

UNITRODE CORPORATION UC3855A/B HIGH PERFORMANCE POWER FACTOR PREREGULATOR James P. Noon New Product Applications Engineer

 

U-153 U-153 UNITRODE CORPORATION UC3855A/B UC3855A/B HIGH PERFORMANCE POWER FACTOR PREREGULATOR James P. Noon New Product Applications Engineer INTRODUCTION The trend in power converters is towards increasingly higher power densities. Usually, the method to achieve this is to increase the switching frequency, which allows a reduction in the filter component's size. Raising the switching frequency however, significantly increases the system switching losses which generally precludes operating at switching frequencies greater than 100kHz. In order to increase the switching frequency while maintaining acceptable efficiency, several soft switching techniques have been developed [1,2,3]. Most of these resonant techniques increase the semiconductor current and/or voltage stress, leading to larger devices and increased conduction losses due to greater circulating current. A new class of converters has been developed [4], however, that allow an increase in switching frequency without the associated increase in switching losses, while overcoming most of the disadvantages of the resonant techniques. Zero voltage transition (ZVT) converters operate at a fixed frequency while achieving zero voltage turn-on of the main switch and zero current turn-off of the boost diode. This is accomplished by employing resonant operation only during switch transitions. During the rest of the cycle, the resonant network is essentially removed from the circuit and converter operation is identical to its nonresonant counterpart. This technique allows a improvement in efficiency over the traditional boost converter, as well as operating the boost diode with reduced stress (due to controlled di/dt at turn-off). Soft-switching of the diode also reduces EMI, an important system consideration. Active power factor correction programs the input current of the converter to follow the line voltage and power factors of 0.999 with THD of 3% are possible. The Unitrode UC3855A/B UC3855A/B IC incorporates power factor correction control circuitry capable of providing high power factor with several enhancements relating to current sensing and ZVT operation of the power stage. UDG-95151 UDG-95151 Figure 1. Boost Converter with ZVT Power Stage U-153 U-153 APPLICATION NOTE diode D1 is ramping down. When the diode current reaches zero the diode turns off (i.e. soft switching of D1). In the practical circuit some reverse recovery of the diode will occur since the diode needs time to remove the junction charge. The voltage across the ZVT inductor is VO, and therefore the time required to ramp up to Iin is: IIN t01 = _ VO Lr The UC3855 UC3855 incorporates all of the control functions required to design a ZVT power stage with average current mode control. Average current mode control has been chosen for its ability to accurately program the input current while avoiding the slope compensation and poor noise immunity of other methods [5,6]. ZVT TECHNIQUE ( ZVT Boost Converter Power Stage The ZVT boost converter operates the same as a conventional boost converter throughout its switching cycle except during the switch transitions. Figure 1 shows the ZVT boost power stage. The ZVT network, consisting of QZVT , D2, Lr, and Cr, provides active snubbing of the boost diode and main switch. The ZVT circuit operation has been described in [4, 7, 8] and will be reviewed here for completeness. Referring to Figure 2, the following timing intervals can be defined: ) t1 - t2 At t1, the Lr current has reached IIN and Lr and Cr will begin to resonate. This resonant cycle discharges Cr until its voltage equals zero. The dv/dt of the drain voltage is controlled by Cr (Cr is the combination of the external CDS and Coss). The current through Lr continues to increase while Cr discharges. The time required for the drain voltage to reach zero is 1/4 of the resonant period. At the end of this period the body diode of the main switch turns on. t12 = · LrCr 2 ZVT Timing t0 - t1 During the time prior to t0, the main switch is off and diode D1 is conducting the full load current. At t0, the auxiliary switch (QZVT) is turned on. With the auxiliary switch on, the current in Lr ramps up linearly to IIN. During this time the current in t2 - t3 At the beginning of this interval the switch drain voltage has reached 0V and the body diode is turned on. The current through the body diode is being driven by the ZVT inductor. The voltage VGSMAIN VGSZVT VO VDS lin IQMAIN ILr Iin VO VDl lin ID t0 t1 t 2 t 3 t4 t5 t6 t0 UDG-95152 UDG-95152 Figure 2. ZVT Timing Diagram 2 U-153 U-153 APPLICATION NOTE across the inductor is zero and therefore the current freewheels. At this time, the main switch can be turned on to achieve zero voltage switching. age (2.5V), the ZVT gate drive signal is terminated and the main switch gate drive goes high. The control waveforms are shown in Figure 3. The switching period begins when the oscillator begins to discharge, and the ZVT gate drive goes high at the beginning of the discharge period. The ZVT signal will stay high until the ZVS pin senses the zero voltage condition or until the discharge period is over (the oscillator discharge time is the maximum ZVT pulse width). This allows the ZVT switch to be on only for as long as necessary. At t3, the UC3855 UC3855 senses that the drain t3 - t4 voltage of QMAIN has fallen to zero and turns on the MAIN switch while turning off the ZVT switch. After the ZVT switch turns off, the energy in Lr is discharged linearly through D2 to the load. t4 - t5 At t4, the current in D2 goes to zero. When this occurs, the circuit is operating like a conventional boost converter. In a practical circuit however, Lr will resonate with Coss of the ZVT switch driving the node at the anode of D1 negative (since the opposite end of Lr is clamped to zero). This effect will be discussed in the ZVT circuit design section. t5 - t6 This stage is also exactly like a conventional boost converter. The main switch turns off. The QMAIN drain-to-source node capacitance charges to VO and the main diode begins to supply current to the load. Since the node capacitance initially holds the drain voltage to zero, the turn off losses are significantly reduced. It can be seen through the above description that the operation of the converter differs from the conventional boost only during the turn-on switch transitions. The main power stage components experience no more voltage or current stress than normal, and the switch and diode both experience soft switching transitions. Having significantly reduced the switching losses, the operating frequency can be increased without an efficiency penalty. The diode also operates with much lower losses and therefore will operate at a lower temperature, increasing reliability. The soft switching transitions also reduce EMI, primarily caused by hard turn-off of the boost diode. Control Circuit Requirements UDG-95153 UDG-95153 In order to maintain zero voltage switching for the main switch, the ZVT switch must be on until the voltage on Cr resonates to zero. This can be accomplished by using a fixed delay equal to tZVT at low line and maximum load. I L tZVT = INp · r VO + · 2 Figure 3. ZVT Control Waveforms CONTROL CIRCUIT OPERATION AND DESIGN Figure 4 shows the UC3855A/B UC3855A/B block diagram (pin numbers correspond to DIL-20 DIL-20 packages). It shows a controller which incorporates the basic PFC circuitry, including average current mode control, and the drive circuitry to facilitate ZVT operation. The IC also has current waveform synthesizer circuitry to simplify current sensing, as well as overvoltage and overcurrent protection. In the following sections the control IC will be broken down into functional blocks and individually reviewed. Lr · Cr However, this would give a longer than necessary delay at lighter load or higher line conditions, and therefore would increase the ZVT circuit conduction loss and increase the peak current stress. The UC3855 UC3855 allows for a variable tZVT by sensing when the QMAIN drain voltage has fallen to zero. Once the voltage falls below the ZVS pin threshold volt- 3 U-153 U-153 APPLICATION NOTE Pin numbers refer to DIL-20 DIL-20 package only. UDG-94001-2 UDG-94001-2 Figure 4. UC3855 UC3855 Controller Block Diagram Comparison with UC3854A/B UC3854A/B Oscillator The PFC section of the UC3855A/B UC3855A/B is identical to the UC3854A/B UC3854A/B. Several common design parameters are highlighted below to illustrate the similarities. The oscillator contains an internal current source and sink and therefore only requires an external timing capacitor (CT) to set the frequency. The nominal charge current is set to 500µA and the discharge current is 8mA. The discharge time is approximately 6% of the total period, which defines the maximum ZVT time. CT is calculated by: 1 CT = 11200 · FS FUNCTION UC3854A/B UC3854A/B UC3855A/B UC3855A/B Dedicated pin Incorporated into OVP 1.5V - 4.7V 1.5V - 4.7V VREF for VA 3V 3V Max. VA Output Voltage 6V 6V Offset Voltage at IAC 0.5V 0.7V Multiplier Gain IAC(VA - 1.5) IAC(VA - 1.5) Enable Design Range for VRMS VRMS 2 · IMO VRMS2 ZVT Control Circuit As stated in the ZVT Technique section, the UC3855A/B UC3855A/B provides the control logic to ensure ZVT operation over all line and load conditions without using a fixed delay. The ZVS pin senses the MOSFET drain voltage and is an input to the ZVT drive comparator. The other comparator input is internally biased to 2.5V. When the ZVS input is above 2.5V (and the PWM clock signal is present) the ZVT drive signal can go high. Pulling the ZVS pin low will terminate the ZVT drive signal and turn on the main switch output (recall that the maximum ZVT output signal is equal to the oscillator discharge time). The network used to sense the node voltage is shown in Figure 5. R12 pulls up the pin to a maximum of 7.5V, and C6 provides filtering. · IMO New features incorporated into the UC3855A/B UC3855A/B include: ZVT control circuitry Overvoltage protection Current Synthesizer 4 U-153 U-153 APPLICATION NOTE are only three parameters (VVRMS, IIAC, and RIMO) that need to be defined to properly set up the IC. VRMS The multiplier programs the line current and therefore effects the power drawn from the line. The VRMS pin is programmed by looking at the system power limits. Referring to the block diagram (Figure 4), the multiplier output equation is: I · (V - 1.5) IIMO = IAC 2 EA V VRMS The power limit function is set by the maximum output voltage of the voltage loop error amplifier, VEA (6V). The power limiting function is easily explained by looking at what happens for a given value of VEA . If the AC line decreases by a factor of two, the feedforward voltage decreases by one fourth. This increases multiplier output current (and therefore line current) by two. The power drawn from the line has therefore remained constant. Conversely, if the load increases and the line stays constant, VEA will increase, causing more line current to be drawn. It can be seen then, that VEA is a voltage proportional to input power. UDG-95154 UDG-95154 Figure 5. ZVS Sensing Circuit The RC time constant should be fast enough to reach 2.5V at maximum duty cycle. The drain voltage is limited by the node capacitance which slows down the dv/dt across the main MOSFET, which reduces the high speed requirement on the ZVS circuit. The maximum ZVS pin voltage should be limited to VREF, otherwise the ZVS circuitry can become latched and will not operate properly. Normally the multiplier is set to limit maximum power at low line, corresponding to maximum error amplifier output voltage. The multiplier equation can be solved for the feedforward voltage that corresponds to maximum error amplifier voltage and maximum multiplier current (internally limited to 2 times IIAC). IIAC · (VEA - 1.5) V2VRMS = 2 · (IIAC) An alternative method for ZVS operation, is to sense the drain voltage through a simple voltage divider. This voltage will still have to be filtered (and clamped) however, so as not to inject noise into the ZVS pin. VVRMS = 1.5V Refer back to Figure 3 for the timing waveforms. Knowing the VRMS voltage at low line defines the voltage divider from the line to VRMS pin. This feedforward voltage must be relatively free of ripple in order to reduce the amount of second order harmonic that is present at the multiplier input (which in turn would cause 3rd order harmonics in the input current) [9]. The filtering will produce a dc voltage at the VRMS pin. Since the input voltage is defined in terms of its RMS value, the dc to RMS factor (0.9) must be taken into account [9]. For example, if the low line voltage is 85V, the attenuation required is: GATE DRIVES The main drive can source 1.5APK and the ZVT drive is 0.75APK 75APK. The main switch drive impedance requirements are reduced due to ZVT operation. At turn-on the drain voltage is at zero volts and therefore the Miller capacitance effect is not an issue, and during turn-off, the dv/dt is limited by the resonant capacitor. Since the ZVT MOSFET is generally at least two die sizes smaller than the main switch, its drive requirements are met with a lower peak current capability. 85VRMS 85VRMS · (0.9) = 51:1 1.5 · VDC Multiplier / Divider Circuit At a high line of 270V, this will correspond to VVRMS = 4.76V. The common mode range of the VRMS input is 0V to 5.5V. The calculated range is therefore within the accepted limits. The multiplier section of the UC3855A/B UC3855A/B is identical to the UC3854A/B UC3854A/B. It incorporates input voltage feedforward (through the VRMS input) to eliminate loop gain dependence on the input voltage. There 5 U-153 U-153 APPLICATION NOTE should be kept below 1mA to stay within the linear region of the multiplier. This corresponds to a total resistance of approximately 766k from the line to IAC pin. RIMO The multiplier output resistor can be calculated by recognizing that at low line and maximum load current, the multiplier output voltage will equal 1V (in order to stay below the undercurrent trip point). This will also correspond to the maximum sense voltage of the current transformer. The multiplier current under this condition is equal to 1V / RIMO, and can be equated with the multiplier equation which yields: I · (V - 1.5) 1V = IAC 2 EA V VRMS RIMO At low line IIAC will equal 156µA (if low line = 85V and IIAC was set to 500µA at 270V), VEA will be at its maximum of 6V, and VVRMS will be 1.5V. Therefore RIMO equals 3.2k. UDG-95155 UDG-95155 Figure 6. VRMS Circuit Current Synthesizer A two pole filter is recommended to provide adequate attenuation without degrading the feedforward transient response. A single pole filter will require a pole at too low of a frequency to still allow VRMS to respond quickly enough to changes in line voltage. Current sensing is simplified due to the current synthesis function built into the UC3855A/B UC3855A/B. Switch current is the same as inductor current when the switch is on and can be sensed using a single current transformer. The current synthesizer charges a capacitor (CI) with a current proportional to the switch current when the switch is on. During the switch off-time, the inductor current waveform is reconstructed by the controller. To get an accurate measure of the inductor current then, all that is required is to reconstruct the down slope of the inductor current, which is given by: The filter poles can be calculated once the distortion contribution from VRMS is determined. If the feedforward circuit's contribution to the total distortion is limited to 1.5%, the required attenuation of the filter can be calculated. Recall that the percentage of 2nd harmonic in a full wave rectified sinewave is approximately 66.7% of the dc value. The percentage of second harmonic will translate to the same percent 3rd harmonic distortion in the input current waveform [9]. Therefore, the filter attenuation required is: V - VAC i = OUT L t Discharging CI with a current proportional to VOUT - VAC will allow reconstruction of the inductor current waveform. The capacitor down slope is : I v = DIS t CI 1.5% = 0.0025 66.7% The individual stages should have an attenuation of 0.0225 or 0.15. For a single stage filter: f AV = c fc = 120Hz (0.15) = 18Hz f The UC3855A/B UC3855A/B develops IDIS by subtracting IIAC/4, from a current proportional to VOUT. The voltage at the RVS pin is regulated at 3V and therefore picking the RVS resistor will set the current proportional to VOUT. Referring to Figure 6 the components correspond to R9A = R9B = 390k, R10 = 120k, and R11 = 18k with C4 = 0.082µF and C5 = 0.47µF. IDIS = IIAC The value of IIAC is chosen to be 500µA at high line. This value is somewhat arbitrary, however it 3V - RRVS IIAC 4 The ratio of the current in RRVS to IIAC/4 should equal the ratio of VOUT to VAC. Therefore if 6 U-153 U-153 APPLICATION NOTE IIAC / 4 is 125µA, the current through RRVS should be set to 130µA. RRVS = ly, and this is most efficiently done with a current sense transformer. Resistive sensing at this power level would result in excessive power dissipation. 3V = 23k, use 22k 130µA Several issues should be kept in mind when implementing the current transformer. At frequencies of a couple hundred kilohertz, core reset needs to be addressed. Contributing to the difficulty is the very high duty cycles inherent in a power factor correction circuit. In addition, the ZVT circuit can complicate the sensing/reset function. When the ZVT circuit turns on, it draws current from the line. In order to minimize line current distortion, this current should be measured. Placing the resonant inductor after the current transformer will ensure that the ZVT circuit current is measured. Similarly, when the main switch turns off, current will continue to flow into the resonant capacitor. While it is important to measure this current, if the capacitor is connected to the drain of the MOSFET, below the current transformer, this current will "eat" into the minimal reset time available at line zero crossings, where duty cycles are approaching 100%. This configuration is shown in Figure 7a. If the current transformer does not have enough time to reset, it can begin to saturate and lose accuracy, even if complete saturation is avoided, causing distortion at the zero crossings. A better configuration is shown in Figure 7b. In this circuit, the capacitor current will be measured when it discharges during the ZVT circuit on time. Since this occurs at the beginning of the switching cycle, the current transformer doesn't lose any of its reset time. Connecting Cr above the current transformer will not adversely affect the MOSFET dv/dt control. Since the IC is controlling average current, it doesn't matter whether the capacitor current is measured at the beginning or end of the switching cycle. Equating inductor current slope with capacitor voltage slope, and recognizing that maximum slope occurs when VAC equals zero, CI can be solved for: 3· L· N CI = RRVS · VOUT · RS where N is the current transformer (CT) turns ratio, (Ns / Np) and RS is the current sense resistor. The current synthesizer has approximately 20mV of offset. This offset can cause distortion at the zero crossing of the line current. To null out this offset, a resistor can be connected between VREF and the IMO pin. The resistor value is calculated based on RIMO and the offset at the output of the synthesizer. For a 20mV offset and RIMO = 3.3k a resistor from VREF to IMO of 1.2M will cancel the offset. Current Sensing Current Transformer As was seen in the previous section, synthesizing inductor current with the UC3855A/B UC3855A/B is quite simple. Only switch current needs to be sensed direct- Figure 7 also shows that filtering is added to the transformer secondary in order to reduce noise filtering. The bandwidth of this filter should be low enough to reduce switching noise without degrading the switch current waveform. 7a. UDG-95156 UDG-95156 In addition to position and reset considerations, actual current transformer construction must be considered. Using current transformers that have been designed and manufactured for operation at 20kHz will not give good performance at switching frequencies of 100kHz and greater. Low frequency designs generally have too much leakage inductance to be used for high frequency operation and can cause inaccurate sensing and/or noise problems. Resistive Sensing 7b. Resistive sensing is still possible with the UC3855A/B UC3855A/B. Since both inputs to the current error amplifier are available to the user, resistive sensing UDG-95157 UDG-95157 Figure 7. Current Transformer Sensing. 7 U-153 U-153 APPLICATION NOTE UDG-95159 UDG-95159 a. Current Error Amplifier Clamp Circuit UDG-95158 UDG-95158 Figure 8. Resistive Sensing is easy to implement. Figure 8 shows the typical configuration. The common mode range of the current error amplifier is -0.3V to 5.0V. The RIMO value will remain the same as was calculated above if the maximum signal level remains at 1V. This will also allow the resistively sensed signal to be fed into ION and used for peak current limiting. It is recommended that the RVS resistor still be connected and a resistor connected from CS to ground in order to eliminate the possibility of noise being injected into these high impedance nodes. UDG-95160 UDG-95160 b. Clamp circuit with input voltage compensation Figure 9. Clamp Circuit In addition, if the current transformer saturates, the current limiting function will be lost. For these reasons it is recommended that the output of the current amplifier be clamped externally, to limit the maximum duty cycle. Figure 9 shows a typical clamp circuit. Current Error Amplifier The current error amplifier ensures that the input current drawn from the line follows the sinusoidal reference. The positive input to the amplifier is the multiplier output. The negative input is connected to the output of the current synthesizer (CS) through a resistor (usually the same value as RIMO). The output of the current error amplifier is compared to the sawtooth waveform at the PWM comparator and terminates the duty cycle accordingly. At zero crossings of the line, the duty cycle will be at its maximum. Since the duty cycle is approaching 100%, proper reset of the current transformer will become increasingly difficult. Standard PWM controllers terminate the duty cycle during the oscillator discharge time, however, due to the ZVT operation, the UC3855A/B UC3855A/B is capable of achieving 100% on-time. If the duty cycle is allowed to approach 100%, the current transformer will begin to saturate and cause the current error amplifier to "believe" that less current is being drawn from the line than is being commanded. This will cause the current amplifier to overcompensate, causing line current distortion at the zero crossings. The clamp circuit in Figure 9a will perform quite well (see Table 1), however if better performance is required, or if it's required to operate over a wide line range, the circuit in Figure 9b can be used. This circuit adjusts the clamp voltage to be inversely proportional to line voltage. The procedure for setting the clamp voltage is quite easy. If during initial startup the current amplifier clamp is set to a relatively low value ( 4V) the system will operate but with excessive zero crossing distortion. Once the system is operating, the clamp voltage can be increased until the current transformer is not saturating, and line current has an acceptable level of THD. Once the clamp voltage is set, operation with other ICs will be repeatable. In the experimental breadboard built for universal line operation and 500W output, the single stage clamp was set to 5.6V (at low line and maximum load) and an acceptable level (< 10%) of THD was measured over all line and load conditions. The clamp volt- 8 U-153 U-153 APPLICATION NOTE age is being set below the peak of the PWM comparator ramp (nominally 6.5V) to limit DMAX. Setting the clamp voltage too low will cause excess zero crossing distortion due to the amplifier not being able to command enough line current. 10c shows the effect of clamping the amplifier output voltage too low (top waveform is line current, bottom is VCAO). Setting the clamp too high will have the same effect as having no clamp. The procedure for setting the two stage clamp circuit is the same except that the voltage contribution from the line must be factored in. The line voltage will only have to contribute 100mV to 200mV of clamp voltage for line compensation. Figures 10a and 10b show the current amplifier operation with and without the clamp, while Figure At very light or no load conditions, the average current drawn from the line is lower than can normally be commanded by the current error amplifier. To prevent an overvoltage condition from occurring, the IC goes into a pulse skipping mode if the output voltage of the error amplifier goes below 1V. Pulse skipping can also occur at high line and low load conditions. When CAO goes below 1V, the pulse skipping comparator is activated. The output of the comparator goes to an input of an OR gate in the OVP/ENABLE circuit, causing the output of that OR gate to go high. This signal prevents the ZVT and main gate drives from going high. a. Without Clamp The procedure for compensating the current error amplifier will be covered in the Design Procedure section (IV). Voltage Error Amplifier The output voltage is sensed by the VSENSE input to the voltage error amplifier and compared to an internally generated reference of 3V. The output of the amplifier, VEA, (at a given input voltage) will vary proportionally with output power. The output voltage range for the voltage error amplifier is approximately 0.1V to 6V. The output of the amplifier is one of the multiplier inputs, and an input voltage below 1.5V will inhibit the multiplier output. The design procedure for compensating the voltage loop will be outlined in the Design Procedure section. b. With Clamp Protection Circuitry OVP/ENABLE The UC3855A/B UC3855A/B combines the enable and OVP function into one pin. It requires a minimum of 1.8V to enable the IC, and below this voltage, the reference is held low and the oscillator is disabled. A voltage above 7.5V will interrupt the gate drive. The resistor divider should be sized for 7.5V when an over voltage condition is reached, this will allow startup at a reasonable line voltage. For example, if an overvoltage condition is defined as an output voltage exceeding 450V, then the voltage divider from VOUT to the OVP pin is 60:1. This divider will allow startup at a line voltage of 76VRMS 76VRMS (108VPK 108VPK). c. Too Much Clamp Figure 10. C/A Clamp Circuit Effects on I Line 9 U-153 U-153 APPLICATION NOTE Current Limit 1. Power Stage Design The UC3855A/B UC3855A/B has pulse by pulse current limiting. The multiplier power limit determines the maximum average power drawn from the line. However, during transients or overload conditions, a peak current limiting function is necessary. This function is implemented by sensing the switch current and feeding this value into ION, to a current limiting comparator that terminates the gate drive signal if the switch current signal exceeds 1.5V (nominal). Inductor Design The power stage inductor design in a ZVT converter is identical to the conventional boost converter. The inductance required is determined by the amount of switching ripple desired, and allowing more ripple will reduce the inductor value. The worst case for peak current occurs at low line, maximum load. Peak power is equal to twice the average power and VPK is 2 VRMS. To calculate input current, assume an efficiency of 95%. Soft Start In order to ensure a smooth, controlled startup, the UC3855A/B UC3855A/B provides a soft-start (SS) function. The SS pin sources 1.5µA into an external capacitor. This capacitor limits the supply voltage to the voltage loop error amplifier, which effectively limits the output voltage of the amplifier and therefore the maximum commanded output voltage. This allows the output voltage to ramp up in a controlled fashion. IPK = 2 · VINmin 2· = 500 ( 0.95 ) 85 = 8.7A (60Hz component) A good compromise between current ripple and peak current is to allow a 20% ripple to average ratio. This will also keep the peak switch current less than 10A. Undervoltage Lockout IL = 0.2 · (8.7A) = 1.7App The UC3855A UC3855A has a 15.5V (nominal) turn-on threshold with 6V of hysteresis while the UC3855B UC3855B turns on at 10.5V with 0.5V of hysteresis. Rearranging the conversion ratio for the boost converter to solve for D yields : 410 - 2 · 85 VO - VIN D= = = 0.71 410 VO TYPICAL APPLICATION A typical application will be designed in order to illustrate the design procedure and highlight the design parameters that need to be defined. The design specifications are: · · · · · · · 2 · PIN We can now calculate the required inductance. VIN · D · TS I = 200µH L= VIN = 85 - 270 VAC VO = 410 VDC Pomax = 500W FS = 250kHz Eff > 95% Pf > 0.993 THD < 12% = 2 · 85V · (0.71 · 4µs) 1.7A Output Capacitor Selection The value of output capacitor effects both hold-up time and output voltage ripple. If hold up time (tH) is the main criteria, the following equation will give a value for CO: 2 · PO · tH CO = VO2 - V2MIN The above specifications represent a common universal input voltage, medium power application. The switching frequency of 250kHz is now possible due to the soft switching, zero voltage transitions. The Pf and THD numbers correspond to achievable line correction with the UC3855 UC3855. In this example a compromise between holdup time and capacitor size was made and a capacitor value of 440µF was selected. The capacitor bank consists of two 220µF, 450V DC capacitors in parallel. Design Procedure Power MOSFET & Diode Selection The main MOSFET selected is an Advanced Power Technology's APT5020BN APT5020BN (or equivalent). This is a This design procedure is a summary of what was presented in [8]. However, several values have been changed in order to consolidate component values and/or specify more readily available parts. 10 U-153 U-153 APPLICATION NOTE 500V, 23A device, with RDS(on) = 0.20 (25°C) and COSS 500pF in a TO-247 package. A 5.1 resistor is placed in series with the gate to damp any parasitic oscillations at turn-on with a Schottky diode and 2.7 resistor in parallel with the resistor to speed up turn-off. A Schottky is also placed from GTOUT to ground to prevent the pin from being driven below ground, and should be placed as close to the IC as possible. as such, the inductor is designed to provide soft turn off of the diode. The ZVT capacitor is selected to provide soft switching of the MOSFET. The resonant inductor controls the di/dt of the diode by providing an alternate current path for the boost inductor current. When the ZVT switch turns on, the input current is diverted from the boost diode to the ZVT inductor. The inductor value can be calculated by determining how fast the diode can be turned off. The diode's turn-off time is given by its reverse recovery time. Calculating an exact value for Lr is difficult due to the variation in reverse recovery characteristics within the actual circuit as well as variations in how reverse recovery is specified from manufacturer to manufacturer. An example of circuit conditions effecting the reverse recovery is the natural snubbing action of the resonant capacitor, which limits the dv/dt at the anode of the diode. A good initial estimate is to allow the inductor current to ramp up to the diode current within three times the diode's specified reverse recovery time. One constraint on the maximum inductance value is its affect on the minimum duty cycle. As was shown in the diode selection section, the L-C time constant effects DMIN and therefore VOmin. Making Lr too large will also increase the conduction time of the ZVT MOSFET, increasing the resonant circuit conduction losses. As the value of Lr is reduced, the diode will experience more reverse recovery current, and the peak current through the inductor and ZVT MOSFET will increase. As the peak current is increased, the amount of energy stored in the inductor will also increase (E = 1/2 · L · I2). This energy should be kept to a minimum in order to reduce the amount of parasitic ringing in this node at turn-off. The boost diode selected is the International Rectifier HFA15TB60 HFA15TB60, a 15A, 600V ultrafast diode (or equivalent). Recall that a converter employing ZVT benefits from soft switching of the diode. With ZVT, the boost diode has a negligible impact on switching losses, and therefore a slower diode could potentially be used. However, there are still valid reasons for using an ultra fast diode in this application. The ZVT inductor is sized according to the recovery time of the diode, and a slower diode will require a larger inductor. This will require a correspondingly longer QZVT on-time, which increases conduction loss. A larger inductor will also require a longer time to discharge. To ensure complete discharge of the resonant inductor, the main switch minimum ontime should be approximately equal to the ZVT circuit on-time. This yields: t +t +t DMIN = 01 12 rr T DMIN effects the minimum allowable output voltage for the boost converter to continue operating. The ZVT circuit on-time is a strong function of trr, and therefore choosing an ultra fast diode will keep the resonant circuit losses to a minimum and cause the least impact on the output voltage. The effective system duty cycle is primarily a function of the main switch on-time, since for a large portion of the resonant circuit's on-time, the voltage at the anode of the boost diode is held up by the resonant capacitor. The reverse recovery of the diode is partially a function of its turn-off di/dt. If a controlled di/dt is assumed, the reverse recovery time of this diode can be estimated to be approximately 60ns. If the inductor limits the rise time to 180ns (3 · trr), the inductance can be calculated. IINp di = = 53A/µs dt 3 · trr These considerations suggest a diode with a recovery time less than 75ns. Average output current in this design is less than 1.2A with a peak current of 9.2A. The conduction loss associated with the diode is approximately 2.2W. IINp = Ipk + 1 I 2 While an ultra fast diode is being used, the diode is operating with significantly reduced switching losses. This will increase the overall system efficiency and reduce the peak stress of the diode. Lr = VO 410V = = 7.7µH 53A/µs di dt The inductor design is limited by core loss and resultant temperature rise, not saturating flux density. This is due to the high AC current component and the relatively high operating frequency. A good design procedure is outlined in [10] and is beyond 2. ZVT Circuit Design Resonant Inductor The ZVT circuit design is straightforward. The circuit is performing an active snubber function and, 11 U-153 U-153 APPLICATION NOTE the scope of this review. Several points will be mentioned however. The core material should be a good high frequency, low loss material such as gapped ferrite or molypermalloy powder (MPP). Powder iron cores will generally not be acceptable in this application. The less expensive Magnetics Kool Mu material, although exhibiting higher losses than the MPP material, can also be used. The higher loss material will actually tend to damp the resonant ringing at the turn off of the ZVT switch. The inductor winding construction is also optimized by keeping interwinding capacitance to a minimum. This reduces the node capacitance at turn off and reduces the amount of damping required. The resonant circuit's impact on the output voltage can now be calculated. Recall that to ensure discharge of the resonant inductor at high line: DMIN = Lr Cr ,= (2) Substituting (1) into (2) and solving for VO produces: (Lr · IINp + VINp · T VOMIN = (3) T - trr - · Lr · Cr 2 ( ) Equation (3) can be solved using the previously established values and yields a minimum output voltage of 405V. This suggests a design value of 410V for VO. ZVT Switch and Rectifier Selection 1 The ZVT switch also experiences minimal turn-on loss due to the discharge of its drain-to-source capacitance. However, it doesn't experience high current and voltage overlap since the turn-on current is limited by the resonant inductor. The switch does experience turn-off and conduction losses however. Although the peak switch current is actually higher than the main switch current, the duty cycle is small, keeping conduction losses low. The ZVT switch will be one or two die sizes smaller than the main switch due to the low average drain current. The ZVT switch on-time is : I · Lr tZVT = INp + · LrCr 2 VO Lr · Cr The peak current then is equal to IIN plus the output voltage divided by the resonant circuit's characteristic impedance. Decreasing Lr or increasing Cr will increase the peak current. The inductor was designed using a Magnetics, Inc. MPP core 55209 with 33 turns for an inductance of 8µH. The inductor should be constructed with Litz wire or several strands of small magnet wire to minimize high frequency effects. Resonant Capacitor The resonant capacitor is sized to ensure a controlled dv/dt of the main switch. The effective resonant capacitor is the sum of the MOSFET capacitance and the external node capacitance. The APT5020BN APT5020BN has approximately 500pF of output capacitance, and an external capacitance of 500pF was added across the device. This capacitor limits the dv/dt at turn-off and consequently reduces the Miller effect. In addition, it reduces turn-off losses since the switch current is diverted to the capacitor. The capacitor must be a good high frequency capacitor, and low ESR and ESL are required. It must also be capable of handling the relatively large charging current at turn-off. Two good choices are polypropolene film or a ceramic material. The peak ZVT switch current is equal to the peak ZVT inductor current. A conservative approximation of the switch RMS current is made by assuming a square wave signal. The RMS of the current is approximated by: IRMS ILrpk · tZVT T This corresponds to a peak of approximately 14A at maximum load and maximum ZVT on-time, however, the RMS is only 3.9A. An appropriate device in this application is the Motorola MTP8N50E MTP8N50E, a 500V, 8A device with an RDS(ON) of 0.8. As with the main MOSFET, a 5.1 resistor is placed in series with the gate to damp any parasitic oscillations at turn on and a Schottky diode and resistor is placed in parallel with the resistor to speed up turn-off. A Schottky is also placed from ZVTOUT to ground to This combination of L and C yields a resonant quarter cycle of: 2 (1) and for a boost converter: VINpk VOMIN = 1 - DMIN The inductor current can by found by analyzing the resonant circuit formed by Lr and Cr and recognizing that the resonant cycle begins when the current reaches IIN. VO · sint ILr = IIN + Zn where Zn = t01 + t12 + trr T Lr · Cr = 140ns 12 U-153 U-153 APPLICATION NOTE prevent the pin from being driven below ground. This diode should be placed as close to the IC as possible. age is at VOUT (since D2 is conducting). As the inductor current passes through zero, the voltage rings negative since the opposite end of the inductor is clamped to 0V through the main switch body diode. The anode voltage can easily ring negatively to twice the output voltage. This increases the reverse voltage stress on the diode to three times the output voltage! Keeping the energy in the node capacitance to a minimum and using fast recovery diodes will reduce the ringing and improve the circuit performance. The rectifiers needed for the ZVT circuit also experience relatively low RMS current. Diode D2 returns the energy stored in the resonant inductor during tZVT to the load. D2 should be an ultra-fast recovery diode and is usually chosen to be of similar speed as D1. The diode selected for D2 is a Motorola MURH860 MURH860; a 600V device with a trr 35ns. Diode D3 blocks current from flowing up through the QZVT body diode when the inductor resets, it sees the same peak and RMS current as QZVT. D3 should be a fast recovery diode to decouple the drain to source capacitance of QZVT from the resonant inductor. Energy stored in the D3 anode node capacitance will resonate with the ZVT inductor when the ZVT switch turns off. Minimizing this effect will reduce the amount of snubbing required at this node. The diode chosen here was the MUR460 MUR460. This is a 600V, 4 amp device with trr 75ns. Several methods of damping this oscillation have been proposed [4,7]. In this circuit two methods, the saturable reactor and resistive damping were investigated. A 51, 10W noninductive resistor was connected through a diode from ground to the anode of D2. The saturable reactor was placed in series with the resonant inductor and implemented with 8 turns on a Toshiba saturable core SA 14 x 8 x 4.5. The resistive damping method prevents the node from oscillating. However, it does not prevent current from flowing in D2 while D1 is conducting (due to the dv/dt across Lr when QMAIN turns off). If current flows through D2 during this time it will experience reverse recovery current when QZVT turns on. The saturable reactor prevents this current flow due to its high impedance. LS also decouples Lr from the node capacitance, which prevents the node from oscillating. To summarize, both diodes in the ZVT circuit experience low RMS current. The main selection criteria in addition to the blocking voltage (in both cases equal to VO) is reverse recovery time. Choosing devices with fast recovery times will reduce parasitic oscillations, losses, and EMI. ZVT Snubber Circuit The ZVT circuit requires some method for damping the parasitic oscillations that occur after the ZVT inductor current goes to zero. Figure 10a shows the ZVT inductor current and diode D2 anode voltage without adequate damping. The figure shows that as the inductor current begins to discharge (when QZVT turns off) to the output, the anode volt- The saturable reactor works well without the resistive damping and was the method chosen in this design. With the saturable reactor damping the circuit properly, the resistive damping can be eliminated. However, since LS is designed to saturate each switching cycle, the core loss is largely material dependent and can cause significant temperature a. Waveforms Without Damping b. Waveforms with Proper Damping Figure 11. ZVT Ringing Waveforms 13 U-153 U-153 APPLICATION NOTE rise of the core. In this circuit, heatsinking of the core was required. An alternative design was also tried using the larger MS 18 x 12 x 4.5 which ran cooler although it also required heatsinking. Optimization of this circuit can significantly reduce the losses in the ZVT circuit. In this design, damping network losses were approximately 2W. Figure 10b shows the same circuit condition with the node damped with LS. In order to consolidate capacitor values C4 could be chosen to be 0.1µF without degrading the system performance. Calculate the IAC resistor: Set IIAC = 500µA at high line. 2 · 270V R= = 764k 500µA Use 2, 390k resistors in series to reduce voltage stress. ZVS Circuit The ZVS circuit components are chosen next. In this example, a 1k resistor is used to pull up the ZVS pin. The capacitor chosen is 500pF. This combination will require approximately 200ns to charge up to the 2.5V threshold. 1-VTHRESHOLD t = -R · C · In VREF ( Calculate RIMO: At low line IIAC = 156µA and the output of the multiplier should equal 1V. With low line and maximum load, VEA will be at its maximum of 6V, therefore, using the multiplier output equation: ) 3. Oscillator Frequency RIMO = Calculate CT: The switching frequency selected is 250kHz. 1 CT = = 357pF, use 330pF 11200 · 250kHz Calculate the VRMS resistor divider: Set VRMS = 1.5V at low line (85VRMS 85VRMS) 85VRMS 85VRMS · 0.9 divider = = 51:1 1.5 VDC 5. Current Synthesizer First, chose a turns ratio for the current transformer. The current transformer is designed to produce 1V at peak input current. This allows sufficient margin before the current limit trip point (1.4V) is reached. If IPK = 9.5A a turns ratio of 50 : 1 would be appropriate. This turns ratio will keep the sense network losses less than 150mW and allow the use of a 1/4 watt resistor. Solving for the sense resistor yields: The voltage divider can be solved if one of the resistors is defined (since there are two equations and three unknowns). Letting the lower resistor in the divider = 18k: RTOTAL = 18k · 51 = 918k Letting R10 = 120k, gives: RS = R9 = 918k - 120k - 18k = 780k R9 is split into two resistors (each 390k) to reduce their voltage stress. = 1 2 · 18Hz · 18k = 0.49µF, use 0.47µF C4 = 1 = 2 · fP · Req 1V 1V = 5.1 Isw 9.5 50 N Recall from the previous current synthesizer section that RVS = 22k. The current synthesizer capacitor can now be calculated: 3· L· N CI = RVS · VOUT · Rs Calculate the capacitor values to place the filter poles at 18Hz: 1 2 · fP · R11 2 1.5 = 3.2k, use 3.3k µA · (6 - 1.5) 156 A 1000pF capacitor is placed in parallel with RIMO for noise filtering. Since the voltage across RIMO is the output of the multiplier and is the reference for the current error amplifier, the RC pole frequency should be placed well above the 120Hz multiplier signal. 4. Multiplier/Divider Circuit C5 = IIAC · (VEA - 1.5) VVRMS2 1V = RIMO = 1 2 · 18Hz · 117k 3 · 200µH · 50 = 633pF, use 680pF 22k · 410V · 5.1 6. Control Loop Design Small Signal Model The small signal model of the ZVT PFC boost converter is similar to the standard PFC boost converter model. The two converters operate exactly the = 75nF, use 0.082µF where Req = R9||(R10 + R11) = 117k 14 U-153 U-153 APPLICATION NOTE including the current sense network is given below. This model does not include the sampling effect at one half the switching frequency [12] but is a good approximation at the frequencies of interest. VO · RSENSE Gid (s) = s · L · VSE a. Current Loop Error Amplifier UDG-95161 UDG-95161 b. Current Amplifier Gain Plot The UC3855A/B UC3855A/B has an oscillator ramp of 5.2Vpp (VSE). The RSENSE term, is the attenuation from actual input current to sensed current (i.e. it includes the current transformer turns ratio). Using the previously determined component values and solving for the power stage gain at fc yields a gain of 0.63 at 10kHz. In order to have a gain of 1 at fc, the error amplifier must have a gain of 1/0.63 at 10kHz. The error amplifier is shown in Figure 12a with the frequency response in Figure 12b. The resistor Ri is equal to 3.3k so the feedback resistor is chosen to be 5.6k. A zero is placed at the cross over frequency to give a phase margin of 45 degrees. To reduce switching noise a pole is placed at one-half the switching frequency. The following summarizes the design procedure. 410V · 0.10 = 0.63 1. |Gid(s)| = 2 · · 10kHz · 200µH · 5.2 UDG-95162 UDG-95162 2. GEA = Figure 12. Current Error Amplifier Schematic Rf = same throughout most of the switching cycle and only during the switching transitions is there any difference. This allows the design of the control loops to proceed following the standard techniques outlined in [9]. Rf 1 = 1.58 Av = Ri |Gid(s)| Ri 5.6k |Gid(s)| 1 3. fz = fc = 2 · · Rf · Cz CZ = Current Loop Design Excellent references on the current loop design are found in [5,9,11]. The design of the average current mode control loop begins with choosing a crossover frequency. In this example the switching frequency is 250kHz, so the unity gain cross over frequency could be chosen to be as high as 40kHz (1/6 of the switching frequency). In this circuit however, the cross over is chosen to be 10kHz. Since the main job of the current loop is to track the line current, a 10kHz bandwidth is quite adequate for this application. 1 2200pF 2 · · 10kHz · 5.6k 1 1 = 2 · · Rf · Cp 2 · · Rf. Cz · Cp Cz + Cp 1 Cp = 220pF 2 · · 5.6k · 125kHz 4. fp = ( ) Voltage Loop Design The design of the voltage loop follows the procedure given in [5]. The first step is to determine the amount of ripple on the output capacitor. Once the cross over frequency (fc) is known, the next thing to do is calculate the gain of the power stage. The small signal model of the power stage vOpk = PIN · XCo VO 15 U-153 U-153 APPLICATION NOTE grator function of Cf and Ri. This network has a single pole role off and the capacitor value is easily found to give the desired gain at 120Hz. 525 = 4.14VPK 14VPK 2 · · 120 · 410µ · 410 = 8.3Vpp vOpk = Cf = In order to meet the 3% THD specification, the distortion due to output ripple voltage feeding through the voltage error amplifier will be limited to 0.75%. This allows 1.5% from the multiplier and 0.75% from miscellaneous sources. A 1.5% second harmonic on the error amplifier will result in 0.75% 3 rd harmonic distortion at the input. At full load, the peak error amplifier ripple voltage allowed is: Cf = 1 2 · · f · GVEA · R i 1 2 · · 120Hz · 0.009 · 1.36M 0.1µF The crossover frequency can now be calculated recognizing that a pole (due to the combination of Cf and Rf) will be placed at the cross over frequency to provide adequate phase margin. The pole placement will determine the phase margin since the power stage has a single pole response with the associated 90 degree phase lag. If the error amplifier pole is placed at the crossover frequency, the overall loop gain will have a 45 degree phase margin. The power stage gain is given by: Vo PIN GPS(s) = V = VEA · Vo · (s · Co) VEA VEApk = % ripple · VVEA = 0.015 · (6 - 1) = 0.075V The error amplifier gain at 120Hz is the allowable error amplifier ripple voltage divided by the output ripple voltage, or 0.009 (-41 dB ). The error amplifier input resistor was chosen to be 1.36M to keep power dissipation low and allow a small value for the compensation capacitor. Two 681k resistors in series are used to reduce the voltage stress. The voltage error amplifier schematic is shown in Figure 13, with the 120Hz gain determined by the inte- The voltage loop gain (TV) is the product of the power stage gain and the error amplifier gain. To find the cross over frequency, solve for f and set equal to 1. TV = 1 = GPS(s) · GVEA(s) The error amplifier gain is: GVEA = TV = 1 = -j 2 · · f · Ri · Cf -j · 92.6 f · = -j · 1.17 f ( -j · f1.17 ) = 108 f2 The cross over frequency then is approximately 11Hz, so the resistor, Rf, can be calculated to place the pole at fc. UDG-95163 UDG-95163 Rf = a. Voltage Loop Error Amplifier 1 2 · · 11Hz · 0.1µF 140k Finally, the resistor RD (10k) sets the DC output voltage to 410V. 7. OVP/ENABLE b. Voltage Amplifier Gain Plot An output voltage exceeding 450V is defined as an overvoltage condition. To trip the OVP comparator at 450V requires a divider of: 7.5V = 60:1 450V Letting the lower resistor in the divider = 33k, the top resistor then is 2M, two 1M resistors are UDG-95164 UDG-95164 Figure 13. Voltage Error Amplifier 16 U-153 U-153 APPLICATION NOTE Efficiency ZVT vs. Conventional 97 96 ZVT Conventional Efficiency in Percent 95 94 93 92 91 90 89 88 100 150 200 250 300 350 Vin (DC) Figure 14. Efficiency Data used in series to reduce the voltage stress. A 10nF capacitor is placed in parallel with the 33k resistor for noise filtering. tional converter at low line. At higher line voltages the advantage is reduced until the two power stages converge at high line. This is understandable and consistent with the other reported data [4,13]. At low line, the higher input current contributes to higher switching losses in the conventional converter. The ZVT converter however, does not experience increased switching losses (conduction losses increase for both converters at low line). With this divider the converter will start at 76VRMS 76VRMS, which will allow startup well below low line. EXPERIMENTAL RESULTS The example converter was constructed to demonstrate circuit performance. The circuit performed well and was tested over the full line and load ranges. Figure 14 shows efficiency data for the ZVT vs. a conventional boost converter, which was derived by simply removing the ZVT components. The conventional circuit needed to be cooled with a fan in order to stabilize the power semiconductor temperatures. It can be seen from the data that the ZVT circuit has a significant advantage over the conven- Figure 15 shows the ZVT and main switch gate drives as well as the main switch drain to source voltage. The ZVT gate drive goes high prior to the main switch and drives the drain voltage to zero before the main switch turns on. It should also be noted that the drain to source voltage waveform is very clean with no overshoot or ringing, which will reduce EMI and voltage stress on the device. The ZVT circuit waveforms are shown in Figure 16. Current in Lr is shown in the top trace. The wave- Figure 15. Power Stage Waveforms Figure 16. ZVT Waveforms 17 U-153 U-153 APPLICATION NOTE Figure 17. Current Synthesizer Waveforms Figure 18. Line Current forms are well damped with a peak current of approximately 6A. The current synthesizer waveforms are shown in Figure 17. The top waveform is the reconstructed waveform at CI and the bottom waveform is inductor current. The waveforms show good agreement. Any error between the reconstructed and actual waveform will be greatest at high line and is primarily caused by slight offset voltage errors in the synthesizer circuit. Figure 18 shows the input line current at low line and maximum load, the THD and power factor are well within acceptable limits. Table 1 gives THD and pf measurements for several line and load conditions with the single stage current error amplifier clamp circuit. Table 2 shows THD and pf with the two stage clamp circuit shown in Figure 9B. Line(VAC) % THD Pf Line(VAC) % THD Pf 100 6.3 0.998 100 4.95 0.999 120 4.5 0.999 120 5.30 0.998 200 8.9 0.996 200 5.45 0.998 230 10 0.995 230 5.83 0.998 Table 2 THD and Pf vs. line, with two stage error amplifier clamp circuit. Table 1 THD and Pf vs. line, with single stage error amplifier clamp circuit. 18 U-153 U-153 APPLICATION NOTE UDG-95165 UDG-95165 Figure 19. UC3855A/B UC3855A/B Typical Application 19 U-153 U-153 APPLICATION NOTE POWER STAGE COMPONENT VENDORS [6] L. H. Dixon, "Average Current Mode Control of Switching Power Supplies," Unitrode Power Supply Design Seminar Manual SEM700 SEM700, 1990 (Republished in subsequent Manuals) [7] J. Bazinet and J. O'Connor, "Analysis and Design of a Zero Voltage Transition Power Factor Correction Circuit," IEEE Applied Power Electronics Conference, February 1994 [8] J. P. Noon, "A 250kHz, 500W Power Factor Correction Circuit Employing Zero Voltage Transitions," Unitrode Power Supply Design Seminar Manual SEM1000 SEM1000, 1994 [9] L1,L2 L. H. Dixon, "High Power Factor Switching Preregulator Design Optimization," Unitrode Power Supply Design Seminar Manual SEM800 SEM800, 1991 Magnetics, Butler, PA (412) 282-8282 Spike Killer Toshiba, Westboro, MA (508) 836-3939 QMAIN APT, Bend, OR (503) 382-8028 D1 International Rectifier, El Segundo, CA (310) 322-3331 QZVT, Motorola, Phoenix, AZ D2, D3, D4 (602) 244-3550 REFERENCES [1] K. H. Liu and F. C. Lee, "Resonant Switches a Unified Approach to Improved Performance of Switching Converters," Proceedings of the International Telecommunications Energy Conference, November 1984 [2] W. A. Tabisz and F. C. Lee, "Zero-Voltage Switching Multi-Resonant Technique A Novel Approach to Improve Performance of High Frequency Quasi-Resonant Converters," IEEE Power Electronics Specialists Conference 1988 [3] K. H. Liu and F. C. Lee, "Zero-Voltage Switching Techniques in DC/DC Converter Circuits," Proceedings of the Power Electronics Specialists Conference, June 1986 [4] G. C. Hua, C. S. Leu, Y. M. Jiang, and F. C. Lee, "Novel Zero-Voltage -Transition PWM Converters," IEEE Power Electronics Specialist Conference, 1992 [5] [10] L. H. Dixon, "Design of Flyback Transformers and Filter Inductors," Unitrode Power Supply Design Seminar Manual SEM400 SEM400, 1985 (Republished in subsequent Manuals) L. H. Dixon, "High Power Factor Preregulators for Off-Line Power Supplies," Unitrode Power Supply Design Seminar Manual SEM600 SEM600, 1988 (Republished in subsequent Manuals) [11] C. Zhou and M. M. Jovanovic, "Design TradeOffs in Continuous Current-Mode Controlled Boost Power Factor Correction Circuits", High Frequency Power Conversion Conference, May 1992 [12] W. Tang, R. B. Ridley and F. C. Lee, "Small Signal Modeling of Average Current-Mode Control," IEEE Applied Power Electronics Conference, February 1992 [13] M. M. Jovanovic, C. Zhou, and P. Liao, "Evaluation of Active and Passive Snubber Techniques for Applications in Power Factor correction Boost Converters" 6th International Conference on Power Semiconductors and their Applications (ELECTRONICA `92), Munich, Germany, 1992 UNITRODE CORPORATION 7 CONTINENTAL BLVD. · MERRIMACK, NH 03054 TEL. 603-424-2410 · FAX 603-424-3460 20 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. 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