U632H0604 M3015 D-01109 D-01101 - Datasheet Archive

 

Advanced Information PowerStore 64 x 4 nvSRAM Features F F F F F F F F F F F High-performance CMOS nonvolatile static RAM 64 x 4

 

U632H0604 U632H0604 Advanced Information PowerStore 64 x 4 nvSRAM Features F F F F F F F F F F F High-performance CMOS nonvolatile static RAM 64 x 4 bits 25 and 45 ns Access Times 12 and 25 ns Output Enable Times ICC = 10 mA at 200 ns Cycle Time Unlimited Read and Write to SRAM Automatic STORE to EEPROM on Power Down Hardware or Software initiated STORE (STORE Cycle Time < 4 ms) Automatic STORE Timing 105 STORE cycles to EEPROM 10 year data retention in EEPROM Automatic RECALL on Power Up Hardware or Software RECALL Initiation (RECALL Cycle Time < 10 µs) Unlimited RECALL cycles from EEPROM Single 5 V ± 10 % Operation Operating temperature ranges 0 to 70 °C -40 to 85 °C CECC 90000 Quality Standard ESD characterization according MIL STD 883C M3015 M3015.7-HBM Package: SOP18 (330 mil) The U632H0604 U632H0604 has two separate modes of operation: SRAM mode and nonvolatile mode. In SRAM mode, the memory operates as an ordinary static RAM. In nonvolatile operation, data is transferred in parallel from SRAM to EEPROM or from EEPROM to SRAM. In this mode SRAM functions are disabled. The U632H0604 U632H0604 is a fast static RAM (25, 35, 45 ns), with a nonvolatile electrically erasable PROM (EEPROM) element incorporated in each static memory cell. The SRAM can be read and written an unlimited number of times, while independent nonvolatile data resides in EEPROM. Data transfers from the SRAM to the EEPROM (the STORE operation) take place automatically upon power down using charge stored in an external 33 µF capacitor. Transfers from the EEPROM to the SRAM (the RECALL operation) take place automatically on power up. Pin Configuration VCAP A4 A3 A2 A1 A0 E VSS STORE 1 18 2 17 3 16 4 15 PDIP 5 14 SOP 6 13 7 12 8 11 9 10 The U632H0604 U632H0604 combines the high performance and ease of use of a fast SRAM with nonvolatile data integrity. STORE cycles also may be initiated under user control via a software sequence or via a single pin (STORE). Once a STORE cycle is initiated, further input or output are disabled until the cycle is completed. Because a sequence of addresses is used for STORE initiation, it is important that no other read or write accesses intervene in the sequence or the sequence will be aborted. RECALL cycles may also be initiated by a software sequence or by a RECALL pin. Internally, RECALL is a two step procedure. First, the SRAM data is cleared and second, the nonvolatile information is transferred into the SRAM cells. The RECALL operation in no way alters the data in the EEPROM cells. The nonvolatile data can be recalled an unlimited number of times. Logic Block Diagram VCCX B A5 DQ3 DQ2 DQ1 DQ0 W RECALL EEPROM Array A5 SRAM Array 2 Rows x 32 Columns Top View Signal Description A0 - A4 Address Inputs DQ0 - DQ3 Data In/Out E Chip Enable G Hardware Store RECALL B Hardware Recall B Column I/O Column Decoder Software Detect A0 - A5 Ground VCAP Store/ Recall Control Power Supply Voltage VSS Power Con trol Store Busy VCCX RECALL Write Enable STORE VCCX VCAP Output Enable W DQ1 Input Buffers DQ0 Signal Name VCCX VSS VCAP STORE Row Decoder F F F F F F F Description Capacitor DQ2 DQ3 STORE RECALL A0 A1 A2 A3 A4 E W August 29, 1997 Zentrum Mikroelektronik Dresden GmbH Grenzstraße 28 · D-01109 D-01109 Dresden · P. O. B. 80 01 34 · D-01101 D-01101 Dresden · Germany Phone: +49 351 8822 306 · Fax: +49 351 8822 337 · Email: sales@zmdh.de · http://www.zmd.de