U631H0604 M3015 D-01109 D-01101 - Datasheet Archive

 

Advanced Information SoftStore 64 x 4 nvSRAM Features F F F High-performance CMOS nonvolatile static RAM 64 x 4 bits 25 and 45 ns

 

U631H0604 U631H0604 Advanced Information SoftStore 64 x 4 nvSRAM Features F F F High-performance CMOS nonvolatile static RAM 64 x 4 bits 25 and 45 ns Access Times 12 and 25 ns Output Enable Times ICC = 10 mA at 200 ns Cycle Time Unlimited Read and Write to SRAM Software STORE Initiation (STORE Cycle Time < 4 ms) Automatic STORE Timing 105 STORE cycles to EEPROM 10 year data retention in EEPROM Automatic RECALL on Power Up Software RECALL Initiation (RECALL Cycle Time < 10 µs) Unlimited RECALL cycles from EEPROM Single 5 V ± 10 % Operation Operating temperature ranges 0 to 70 °C -40 to 85 °C CECC 90000 Quality Standard ESD characterization according MIL STD 883C M3015 M3015.7-HBM Package: SOP14 (150 mil) The U631H0604 U631H0604 has two separate modes of operation: SRAM mode and nonvolatile mode. In SRAM mode, the memory operates as an ordinary static RAM. In nonvolatile operation, data is transferred in parallel from SRAM to EEPROM or from EEPROM to SRAM. In this mode SRAM functions are disabled. The U631H0604 U631H0604 is a fast static RAM (25 and 45 ns), with a nonvolatile electrically erasable PROM (EEPROM) element incorporated in each static memory cell. The SRAM can be read and written an unlimited number of times, while independent nonvolatile data resides in EEPROM. Data transfers from the SRAM to the EEPROM (the STORE operation), or from the EEPROM to the SRAM (the RECALL operation) are initiated through software sequences. Pin Configuration A4 A3 A2 A1 A0 E VSS 1 2 3 4 5 6 7 14 13 12 SOP 11 10 9 8 The U631H0604 U631H0604 combines the high performance and ease of use of a fast SRAM with nonvolatile data integrity. Once a STORE cycle is initiated, further input or output are disabled until the cycle is completed. Because a sequence of addresses is used for STORE initiation, it is important that no other read or write accesses intervene in the sequence or the sequence will be aborted. Internally, RECALL is a two step procedure. First, the SRAM data is cleared and second, the nonvolatile information is transferred into the SRAM cells. The RECALL operation in no way alters the data in the EEPROM cells. The nonvolatile data can be recalled an unlimited number of times. Logic Block Diagram VCC A5 DQ3 DQ2 DQ1 DQ0 W EEPROM Array STORE A5 Row Decoder F F F F F F F F F F F F F F Description SRAM Array RECALL VCC VSS 2 Rows x 32 Columns Store/ Recall Control Top View DQ0 VCC Software Detect A0 - A5 Input Buffers Column I/O Signal Name Signal Description DQ1 A0 - A4 Address Inputs DQ2 DQ0 - DQ3 Data In/Out E Chip Enable W VCC Write Enable Power Supply Voltage E VSS Ground W Column Decoder DQ3 A0 A1 A2 A3 A4 August 29, 1997 Zentrum Mikroelektronik Dresden GmbH Grenzstraße 28 · D-01109 D-01109 Dresden · P. O. B. 80 01 34 · D-01101 D-01101 Dresden · Germany Phone: +49 351 8822 306 · Fax: +49 351 8822 337 · Email: sales@zmd.de · http://www.zmd.de