NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
| Catalog Datasheet Results | Type | Document Tags |
| Abstract: SN74LVC2G07 SN74LVC2G07 B MGPIO1 MGPIO2 MGPIO3 U506B D1 IN1 ADG821 ADG821 +3.3V R513 2K 3 3 R505 10K S1 4 R503 10K 5 R504 10K +5V 7 .1uF U502 4 .1uF U506A GND ... | Original |
7 pages, |
U-507 transistor D400 u400 transistor c114 tr d400 TPS3307-18 u504 TC R509 U300 U506 TI-401 D206 U200B U202A datasheet abstract |
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| Abstract: 14-Bit, 150 MSPS, 1.8 V Analog-to-Digital Converter AD9254 AD9254 Preliminary Technical Data FEATURES 1.8 V analog supply operation 1.8 V to 3.3 V output supply SNR = 71.7 dBc (72.7 dBFS) to 70 MHz input SFDR = 83 dBc to 70 MHz input Low power: 430 mW @ 150 MSPS Differential input with 650 MHz bandwidth On-chip voltage reference and sample-and-hold amplifier DNL = ± 0.5 LSB Flexible analog input: 1 V p-p to 2 V p-p range Offset binary, Gray code, or twos complement data format Clock du ... | Original |
40 pages, |
AD9246 AD9254 AD9254BCPZ-150 AN-742 AN-827 AN-835 AD9233 l504 transistor C535 r519 J503 LC1210 C539 R579 C532 transistor AD9254 abstract |
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| Abstract: R529 14-Bit, 80 MSPS/105 MSPS/105 MSPS/125 MSPS/125 MSPS, 1.8 V Analog-to-Digital Converter AD9246 AD9246 FEATURES FUNCTIONAL BLOCK DIAGRAM AVDD DRVDD AD9246 AD9246 VIN+ VIN 8-STAGE 1 1/2-BIT PIPELINE MDAC1 SHA 8 4 A/D 3 A/D REFT REFB CORRECTION LOGIC OR 15 OUTPUT BUFFERS DCO D13 (MSB) VREF D0 (LSB) SENSE 0.5V REF SELECT AGND CLOCK DUTY CYCLE STABILIZER CLK+ CLK SCLK/DFS MODE SELECT PDWN SDIO/DCS CSB DRGND APPLICATIONS Ultrasoun ... | Original |
44 pages, |
u504 24 AD9246BCPZ-125 AD9246BCPZ-80 AN-835 C531 c531 diode C532 transistor AD9246 C551 AD9233 IMT-2000 LC1210 r565 u504 MSPS/105 MSPS/125 MSPS/105 abstract |
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| Abstract: 14-Bit, 150 MSPS, 1.8 V Analog-to-Digital Converter AD9254 AD9254 FEATURES FUNCTIONAL BLOCK DIAGRAM AVDD AD9254 AD9254 VIN+ VIN Macro, micro, and pico cell infrastructure GENERAL DESCRIPTION The AD9254 AD9254 is a monolithic, single 1.8 V supply, 14-bit, 150 MSPS analog-to-digital converter (ADC), featuring a high performance sample-and-hold amplifier (SHA) and on-chip voltage reference. The product uses a multistage differential pipeline architecture with output error correction logic to pro ... | Original |
40 pages, |
AD9233 c535 transistor ROHDE SCHWARZ SMHU C557 r530 OSC500 C551 C539 manual SMHU c516 transistor c537 A transistor C538 c531 diode transistor C546 AD9254 AD9254 abstract |
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| Abstract: Part Number Qty per Reel Reel Size uClamp 0506T 0506T.TCT U506T YW Working Voltage 5V ... | Original |
7 pages, |
SLP1313P6T 0506T 0506T abstract |
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| Abstract: K3638 8 DNI MCLR GP2 PIC12F629 PIC12F629 GP4 GP5 VDD U506 D R559 D505 261 Optional DNI , (U506) AD9233 AD9233 RC0603 RC0603 64. Rev. A | Page 35 of 44 DUTDRVDDIN GND 5 P5 6 P6 , EVQ-PLDA15 EVQ-PLDA15 AD9233 AD9233 62 63 64 65 66 U506 IC 8SOIC 8 / Microchip ... | Original |
44 pages, |
IMT-2000 R579 l507 r574 OSC500 r559 R582 RCA74204 R547 R517 850dBc TSW-140-08-G-T-RA SMDC110F-2 cp c531 ADCJP508 MSPS/105 MSPS/125 MSPS/105 abstract |
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| Abstract: p6p20e SW4002 EDP XC167 XC167 CPU Module Manual This document contains information on the XC167 XC167 module for the RS EDP system Version v4.0, 10/06/2010 EDP-CM-XC167 EDP-CM-XC167 Manual Contents 1. EDP-CM-XC167 EDP-CM-XC167 CPU Module 3 2. Get The Latest Versions 3 3. Module Features 4 4. 4.1 4.2 4.3 4.4 4.5 XC167 XC167 To EDP Baseboard Connector Pin Mapping 5 MCU Pin Mapping . 5 Resources used by MCU Module . ... | Original |
29 pages, |
B300 X300 B301 SAF-XC167CI-32F40F B302 NX8045GBS das jtag over usb mini wiggler XC167 EDP-CM-XC167 XC167 abstract |
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| Abstract: GATE4 L511 TBD C520 4700pF L_433SQ 433SQ 12V_FILTER 4 U506 R42 10 NCP5355 NCP5355 6 VS BST TG 5 , U502 U504 U505 U506 IC, SMT, SO8, NCP5355 NCP5355 ON Semiconductor NCP5355 NCP5355 4 http://onsemi.com ... | Original |
18 pages, |
NTD6 schematic atx 160 W dc input atx schematic BGA775 MiniFit-JR 24 c531 DIODE C536 L510 mosfet lga775 schematic C577 C532 diode c535 transistor 60N02R 85n02 NCP5318DEMO NCP5318 NCP5318DEMO abstract |
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| Abstract: U-506 Step-Down Switching Current Regulation Using the bq2003 Fast-Charge IC Thermal packaging requirements are often the practical limits in electronic design. Basic thermal management or component thermal stress/reliability issues can affect an otherwise successful product. The use of switching power-conversion techniques results in dramatically less heat being generated in the product. Introduction This application note describes the use of the bq2003 Fast-Charge IC as the modulator in a ... | Original |
17 pages, |
Keystone RL0703-5744-103-S1 philips thermistor 2322 640 1N4148 1N749 1N755 1N758 1N964A 1N966A 1N967A 2N7000 U506 REGULATOR 0-220V GFS MAGNETICS U-506 U-506 abstract |
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| Abstract: CobraNetTM EV-2 Digital Audio Networking Processor CobraNet TM EV-2 Development System Manual ©Copyright 2005 Cirrus Logic, Inc. http://www.cirrus.com SEP 2005 EV-2MAN21 EV-2MAN21 CobraNetTM EV-2 Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find the one nearest to you go to www.cirrus.com IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this d ... | Original |
44 pages, |
diode b514 U601D transistor b331 XCS10XLVQ100-4 74HC165 b514 transistor motorola U310 A 42 B331 transistor datasheet CR710 u320 motorola B511 transistor U501D B331 transistor datasheet datasheet abstract |
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| Abstract | Saved from | Date Saved | File Size | Type | Download |
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| Schematic netlist from : layout 14-Jun-97 18:04 - Net Name | Reference designator-Pin number - ADC_SYNC | U46-3 U46-3 U46-3 U46-3 U46-4 U46-4 U46-4 U46-4 U55-3 U55-3 U55-3 U55-3 U55-4 U55-4 U55-4 U55-4 AD[0] | R21-2 R21-2 R21-2 R21-2 TP86-1 TP86-1 TP86-1 TP86-1 U46-25 U46-25 U46-25 U46-25 U55-23 U55-23 U55-23 U55-23 AD[1] | TP81-1 TP81-1 TP81-1 TP81-1 U46-24 U46-24 U46-24 U46-24 U55-22 U55-22 U55-22 U55-22 AD[2] | TP85-1 TP85-1 TP85-1 TP85-1 U46-23 U46-23 U46-23 U46-23 U55-21 U55-21 U55-21 U55-21 AD[3] www.datasheetarchive.com/files/metcomp/ds/sa/sa-1100/brutus/scematic/netlist.txt |
Metcomp | 23/06/1997 | 80.35 Kb | TXT | netlist.txt |
| LCANET, 5 PROG, "", "", "carol ppr 1995/06/01 14:52:16 Created" PROG, XNFPREP, "", "beta-5.2.0a,'1995/06/01 14:51:51'" PROG, Synopsys, "", "v3.3a,'Created from barrel.db'" PROG, XNFMERGE, "", "beta-5.2.0c,'Created from 13384.xnf: Thu Jun 1 14:51:24 1995: Options: d p a'" PROG, "", "", "carol ppr 1995/06/01 14:52:25 PICPREP" PROG, "", "", "carol ppr 1995/06/01 14:52:25 PPR picprep" PROG, "", "", "carol ppr 1995/06/01 14:52:26 XNF and CST constraints merged." PROG, "", "", "carol ppr 1995/06/01 1 www.datasheetarchive.com/files/xilinx/bbs/swhlp/synopsys/verilog/barrel/barrel.map |
Xilinx | 01/06/1995 | 41.54 Kb | MAP | barrel.map |
| LCANET, 6 PROG, XNFMERGE, beta-5.2.0c, "Created from 13384.xnf: Thu Jun 1 14:51:24 1995: Options: d p a" PART, 4005APC84-5 4005APC84-5 4005APC84-5 4005APC84-5 HIERG, 1, obuf_s, U281, / , 0 HIERG, 2, obuf_s, U280, / , 0 HIERG, 3, obuf_s, U279, / , 0 HIERG, 4, obuf_s, U278, / www.datasheetarchive.com/files/xilinx/bbs/swhlp/synopsys/verilog/barrel/barrel.xnf |
Xilinx | 01/06/1995 | 45.34 Kb | XNF | barrel.xnf |
| LCANET, 6 PROG, XNFMERGE, beta-5.2.0c, "Created from 13384.xnf: Thu Jun 1 14:51:24 1995: Options: d p a" PROG, Synopsys, v3.3a, "Created from barrel.db" PROG, XNFPREP, beta-5.2.0a, "1995/06/01 14:51:51" PART, 4005APC84-5 4005APC84-5 4005APC84-5 4005APC84-5 USER, OLDLCANET, 5 SYM, U282_map, HMAP, MAP=PUC, LIBVER=2.0.0 PIN, I1, I, n622 PIN, I2, I, n621 PIN, O, I, n896 END SYM, U286_map, FMAP, MAP=PUC, LIBVER=2.0.0 PIN, I1, I, n554 PIN, I2, I, n553 PIN, O, I, n622 PIN, I3, I, SEL2 PIN, I4, I, SEL2 END SYM, U290_map, FMAP, MAP= www.datasheetarchive.com/files/xilinx/bbs/swhlp/synopsys/verilog/barrel/barrel.xtf |
Xilinx | 01/06/1995 | 37.4 Kb | XTF | barrel.xtf |
| LCANET, 6 PROG, XNFMERGE, beta-5.2.0c, "Created from 13384.xnf: Thu Jun 1 14:51:24 1995: Options: d p a" PART, 4005APC84-5 4005APC84-5 4005APC84-5 4005APC84-5 HIERG, 1, obuf_s, U281, / , 0 HIERG, 2, obuf_s, U280, / , 0 HIERG, 3, obuf_s, U279, / , 0 HIERG, 4, obuf_s, U278, / www.datasheetarchive.com/files/xilinx/bbs/swhlp/synopsys/verilog/barrel/barrel.xff |
Xilinx | 01/06/1995 | 45.34 Kb | XFF | barrel.xff |
| LCANET,5 PROG,Synopsys,v3.3a,"Created from barrel.db" PART,4005APC84-5 4005APC84-5 4005APC84-5 4005APC84-5 SYM,U246,IBUF,SCHNM=IBUF,LIBVER=2.0.0 PIN,O,O,SEL2, PIN,I,I,S, END SYM,U247,IBUF,SCHNM=IBUF,LIBVER=2.0.0 PIN,O,O,SEL2, PIN,I,I,S, END SYM,U248,IBUF,SCHNM=IBUF,LIBVER=2.0.0 PIN,O,O,SEL1, PIN,I,I,S, END SYM,U249,IBUF,SCHNM=IBUF,LIBVER=2.0.0 PIN,O,O,SEL1, PIN,I,I,S, END SYM,U250,IBUF,SCHNM=IBUF,LIBVER=2.0.0 PIN,O,O,n411, PIN,I,I,A_P, END SYM,U251,IBUF,SCHNM=IBUF,LIBVER=2.0.0 PIN,O,O,n412, P www.datasheetarchive.com/files/xilinx/bbs/swhlp/synopsys/verilog/barrel/barrel.sxn |
Xilinx | 01/06/1995 | 39.53 Kb | SXN | barrel.sxn |
| LCANET, 5 PROG, "", "", "carol ppr 1995/05/30 17:44:50 Created" PROG, XNFPREP, "", "beta-5.2.0a,'1995/05/30 17:44:34'" PROG, Synopsys, "", "v3.3a-slot4a,'Created from barrel.db'" PROG, XNFMERGE, "", "beta-5.2.0c,'Created from 3011.xnf: Tue May 30 17:44:14 1995: Options: d p a'" PROG, "", "", "carol ppr 1995/05/30 17:44:59 PICPREP" PROG, "", "", "carol ppr 1995/05/30 17:44:59 PPR picprep" PROG, "", "", "carol ppr 1995/05/30 17:44:59 XNF and CST constraints merged." PROG, "", "", "carol ppr 1995/0 www.datasheetarchive.com/files/xilinx/bbs/swhlp/synopsys/vhdl/barrel/barrel.map |
Xilinx | 30/05/1995 | 40.54 Kb | MAP | barrel.map |
| LCANET, 6 PROG, XNFMERGE, beta-5.2.0c, "Created from 3011.xnf: Tue May 30 17:44:14 1995: Options: d p a" PART, 4005APC84-5 4005APC84-5 4005APC84-5 4005APC84-5 HIERG, 1, obuf_s, U268, / , 0 HIERG, 2, obuf_s, U267, / , 0 HIERG, 3, obuf_s, U266, / , 0 HIERG, 4, obuf_s, U265, / www.datasheetarchive.com/files/xilinx/bbs/swhlp/synopsys/vhdl/barrel/barrel.xnf |
Xilinx | 30/05/1995 | 44.37 Kb | XNF | barrel.xnf |
| LCANET, 6 PROG, XNFMERGE, beta-5.2.0c, "Created from 3011.xnf: Tue May 30 17:44:14 1995: Options: d p a" PROG, Synopsys, v3.3a-slot4a, "Created from barrel.db" PROG, XNFPREP, beta-5.2.0a, "1995/05/30 17:44:34" PART, 4005APC84-5 4005APC84-5 4005APC84-5 4005APC84-5 USER, OLDLCANET, 5 SYM, U269_map, HMAP, MAP=PUC, LIBVER=2.0.0 PIN, I1, I, n470 PIN, I2, I, n469 PIN, O, I, n744 END SYM, U273_map, FMAP, MAP=PUC, LIBVER=2.0.0 PIN, I1, I, n402 PIN, I2, I, n401 PIN, I3, I, n256 PIN, I4, I, n255 PIN, O, I, n470 END SYM, U277_map, FMAP, MAP= www.datasheetarchive.com/files/xilinx/bbs/swhlp/synopsys/vhdl/barrel/barrel.xtf |
Xilinx | 30/05/1995 | 36.4 Kb | XTF | barrel.xtf |
| LCANET, 6 PROG, XNFMERGE, beta-5.2.0c, "Created from 3011.xnf: Tue May 30 17:44:14 1995: Options: d p a" PART, 4005APC84-5 4005APC84-5 4005APC84-5 4005APC84-5 HIERG, 1, obuf_s, U268, / , 0 HIERG, 2, obuf_s, U267, / , 0 HIERG, 3, obuf_s, U266, / , 0 HIERG, 4, obuf_s, U265, / www.datasheetarchive.com/files/xilinx/bbs/swhlp/synopsys/vhdl/barrel/barrel.xff |
Xilinx | 30/05/1995 | 44.37 Kb | XFF | barrel.xff |