U3745BM U2745B 4663B LL2012 F33NJ F82NJ F27NJ B3555 F47NJ B3551 F22NJ F39NJ - Datasheet Archive

 

· Supply Voltage 4.5V to 5.5V · Operating Temperature Range ­40°C to +85°C · Minimal External

 

Features · Supply Voltage 4.5V to 5.5V · Operating Temperature Range ­40°C to +85°C · Minimal External Circuitry Requirements, No RF Components on the PC Board Except · · · · · · · · · · · Matching to the Receiver Antenna High Sensitivity, Especially at Low Data Rates Sensitivity Reduction Possible Even While Receiving Fully Integrated VCO Low Power Consumption Due to Configurable Self Polling with a Programmable Time Frame Check Single-ended RF Input for Easy Matching to /4 Antenna or Printed Antenna on PCB Low-cost Solution Due to High Integration Level ESD Protection According to MIL-STD 883 (4 KV HBM) Except Pin POUT (2 KV HBM) High Image Frequency Suppression Due to 1 MHz IF in Conjunction with a SAW Frontend Filter. Up to 40 dB is Thereby Achievable with Newer SAWs Programmable Output Port for Sensitivity Selection or for Controlling External Periphery Communication to the Microcontroller Possible via a Single, Bi-directional Data Line Power Management (Polling) is also Possible by Means of a Separate Pin via the Microcontroller UHF ASK/FSK Receiver U3745BM U3745BM 1. Description The U3745BM U3745BM is a multi-chip PLL receiver device supplied in an SO20 package. It has been specially developed for the demands of RF low-cost data transmission systems with low data rates from 1 kBaud to 10 kBaud in Manchester or Bi-phase code. The receiver is well suited to operate with Atmel's PLL RF transmitter U2745B U2745B. It can be used in the frequency receiving range of f0 = 310 MHz to 440 MHz for ASK data transmission. All the statements made below refer to 433.92 MHz and 315 MHz applications. The main applications of the U3745BM U3745BM are in the areas of outside temperature metering, socket control, garage door opener, consumption metering, light/fan or aircondition control, jalousies, wireless keyboard and various other consumer market applications. Rev. 4663B 4663B­RKE­05/05 Figure 1-1. System Block Diagram UHF ASK/FSK Remote control receiver UHF ASK/FSK Remote control transmitter 1 Li cell U2745B U2745B Encoder ATARx9x U3745BM U3745BM 1.3 µC PLL Antenna Antenna Keys XTO IF Amp. VCO PLL Power amp. Figure 1-2. Data Interf. Demod LNA XTO VCO Block Diagram VS ASK Demodulator and data filter CDEM RSSI AVCC 50 k DEMOD_OUT DATA Limiter out IF Amp Sensitivity reduction Polling circuit and control logic AGND POUT MODE 4th Order DGND TEST FE CLK DVCC Standby logic LPF 3 MHz MIXVCC LFGND LNAGND LFVCC IF Amp LPF 3 MHz VCO XTO XTO f LNA_IN LF LNA ÷ 64 2 U3745BM U3745BM 4663B 4663B­RKE­05/05 U3745BM U3745BM 2. Pin Configuration Figure 2-1. Pinning SO20 NC ASK CDEM AVCC AGND DGND MIXVCC LNAGND LNA_IN NC Table 2-1. 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 DATA ENABLE TEST POUT MODE DVCC XTO LFGND LF LFVCC Pin Description Pin Symbol Function 1 NC Not connected 2 ASK ASK high 3 CDEM Lower cut-off frequency data filter 4 AVCC Analog power supply 5 AGND Analog ground 6 DGND Digital ground 7 MIXVCC Power supply mixer 8 LNAGND High-frequency ground LNA and mixer 9 LNA_IN 10 NC 11 LFVCC 12 LF 13 LFGND 14 XTO RF input Not connected Power supply VCO Loop filter Ground VCO Crystal oscillator 15 DVCC Digital power supply 16 MODE Selecting 433.92 MHz/315 MHz. Low: 4.90625 MHz (USA), High: 6.76438 (Europe) 17 POUT Programmable output port 18 TEST Test pin, during operation at GND 19 ENABLE 20 DATA Enables the polling mode. Low: polling mode off (sleep mode). High: polling mode on (active mode) Data output/configuration input 3 4663B 4663B­RKE­05/05 3. RF Front End The RF front end of the receiver is a heterodyne configuration that converts the input signal into a 1-MHz IF signal. According to the block diagram, the front end consists of an LNA (low noise amplifier), LO (local oscillator), a mixer and RF amplifier. The LO generates the carrier frequency for the mixer via a PLL synthesizer. The XTO (crystal oscillator) generates the reference frequency fXTO. The VCO (voltage-controlled oscillator) generates the drive voltage frequency fLO for the mixer. fLO is dependent on the voltage at pin LF. fLO is divided by a factor of 64. The divided frequency is compared to fXTO by the phase frequency detector. The current output of the phase frequency detector is connected to a passive loop filter and thereby generates the control voltage VLF for the VCO. By means of that configuration, VLF is controlled in a way that fLO/64 is equal to fXTO. If fLO is determined, fXTO can be calculated using the following formula: f LO f XTO = -64 The XTO is a one-pin oscillator that operates at the series resonance of the quartz crystal. According to Figure 3-1, the crystal should be connected to GND via a capacitor CL. The value of that capacitor is recommended by the crystal supplier. The value of CL should be optimized for the individual board layout to achieve the exact value of fXTO and hereby of fLO. When designing the system in terms of receiving bandwidth, the accuracy of the crystal and XTO must be considered. Figure 3-1. PLL Peripherals VS DVCC CL XTO LFGND R1 = 820 C9 = 4.7 nF C10 = 1 nF LF LFVCC VS R1 C10 C9 The passive loop filter connected to Pin LF is designed for a loop bandwidth of BLoop = 100 kHz. This value for BLoop exhibits the best possible noise performance of the LO. Figure 3-1 shows the appropriate loop filter components to achieve the desired loop bandwidth. If the filter components are changed for any reason, please note that the maximum capacitive load at pin LF is limited. If the capacitive load is exceeded, a bit check may no longer be possible since fLO cannot settle in time before the bit check starts to evaluate the incoming data stream. Therefore, self polling also does not work in that case. fLO is determined by the RF input frequency fRF and the IF frequency fIF using the following formula: f LO = f RF ­ f IF 4 U3745BM U3745BM 4663B 4663B­RKE­05/05 U3745BM U3745BM To determine fLO, the construction of the IF filter must be considered at this point. The nominal IF frequency is fIF = 1 MHz. To achieve a good accuracy of the filter's corner frequencies, the filter is tuned by the crystal frequency fXTO. This means that there is a fixed relation between fIF and fLO that depends on the logic level at pin mode. This is described by the following formulas: f LO MODE = 0 (USA) f IF = -314 f LO MODE = 0 (Europe) f IF = -432.92 The relation is designed to achieve the nominal IF frequency of fIF = 1 MHz for most applications. For applications where f RF = 315 MHz, the MODE must be set to `0'. In the case of fRF = 433.92 MHz, the MODE must be set to `1'. For other RF frequencies, fIF is not equal to 1 MHz. fIF is then dependent on the logical level at pin MODE and on fRF. Table 3-1 summarizes the different conditions. The RF input either from an antenna or from a generator must be transformed to the RF input pin LNA_IN. The input impedance of that pin is provided in the electrical parameters. The parasitic board inductances and capacitances also influence the input matching. The RF receiver U3745BM U3745BM exhibits its highest sensitivity at the best signal-to-noise ratio in the LNA. Hence, noise matching is the best choice for designing the transformation network. A good practice when designing the network is to start with power matching. From that starting point, the values of the components can be varied to some extent to achieve the best sensitivity. If a SAW is implemented into the input network, a mirror frequency suppression of PRef = 40 dB can be achieved. There are SAWs available that exhibit a notch at f = 2 MHz. These SAWs work best for an intermediate frequency of IF = 1 MHz. The selectivity of the receiver is also improved by using a SAW. In typical automotive applications, a SAW is used. Figure 3-2 on page 6 shows a typical input matching network for f RF = 315 MHz and fRF = 433.92 MHz using a SAW. Figure 3-3 on page 6 illustrates an input matching to 50 without a SAW. The input matching networks shown in Figure 3-3 on page 6 are the reference networks for the parameters given in the section "Electrical Characteristics" on page 22. Table 3-1. Calculation of LO and IF Frequency Conditions Local Oscillator Frequency Intermediate Frequency fRF = 315 MHz, MODE = 0 fLO = 314 MHz fIF = 1 MHz fRF = 433.92 MHz, MODE = 1 fLO = 432.92 MHz fIF = 1 MHz 300 MHz < fRF < 365 MHz, MODE = 0 f RF f LO = -11 + -314 f LO f IF = -314 365 MHz < fRF < 450 MHz, MODE = 1 f RF f LO = -1 1 + -432.92 f LO f IF = -432.92 5 4663B 4663B­RKE­05/05 Figure 3-2. Input Matching Network with SAW Filter 8 8 LNAGND LNAGND U3745BM U3745BM U3745BM U3745BM 9 C3 L 22p 25n C3 LNA_IN 8.2p 100p L2 TOKO LL2012 LL2012 F33NJ F33NJ RFIN L3 27n C2 33n 1 2 IN_GND OUT 5 Figure 3-3. L3 47n L2 TOKO LL2012 LL2012 F82NJ F82NJ RFIN 6 OUT_GND 3, 4 22p 100p CASE_GND 8.2p C17 fRF = 315 MHz TOKO LL2012 LL2012 F27NJ F27NJ B3555 B3555 IN C16 C17 fRF = 433.92 MHz LNA_IN 25n 47p C16 9 L 82n C2 1 2 IN IN_GND 10p 7, 8 TOKO LL2012 LL2012 F47NJ F47NJ B3551 B3551 OUT OUT_GND CASE_GND 5 6 3, 4 7, 8 Input Matching Network without SAW Filter fRF = 315 MHz fRF = 433.92 MHz 8 8 LNAGND U3745BM U3745BM U3745BM U3745BM 9 9 15p 25n LNAGND 25n 33p LNA_IN LNA_IN RFIN RFIN 3.3p 100p 22n TOKO LL2012 LL2012 F22NJ F22NJ 3.3p 39n 100p TOKO LL2012 LL2012 F39NJ F39NJ Please note that for all coupling conditions (see Figure 3-2 and Figure 3-3), the bond wire inductivity of the LNA ground is compensated. C3 forms a series resonance circuit together with the bond wire. L = 25 nH is a feed inductor to establish a DC path. Its value is not critical but must be large enough not to detune the series resonance circuit. For cost reduction, this inductor can be easily printed on the PCB. This configuration improves the sensitivity of the receiver by about 1 dB to 2 dB. 6 U3745BM U3745BM 4663B 4663B­RKE­05/05 U3745BM U3745BM 4. Analog Signal Processing 4.1 IF Amplifier The signals coming from the RF front end are filtered by the fully integrated 4th-order IF filter. The IF center frequency is fIF = 1 MHz for applications where fRF = 315 MHz or fRF = 433.92 MHz is used. For other RF input frequencies, refer to Table 3-1 on page 5 to determine the center frequency. The receiver U3745BM U3745BM employs an IF bandwidth of BIF = 600 kHz. This IC can be used together with the U2745B U2745B. SAW transmitters exhibit much higher transmit frequency tolerances compared to PLL transmitters. Generally, it is necessary to use BIF = 600 kHz together with such transmitters. 4.2 RSSI Amplifier The subsequent RSSI amplifier enhances the output signal of the IF amplifier before it is fed into the demodulator. The dynamic range of this amplifier is RRSSI = 60 dB. If the RSSI amplifier is operated within its linear range, the best S/N ratio is maintained in ASK mode. If the dynamic range is exceeded by the transmitter signal, the S/N ratio is defined by the ratio of the maximum RSSI output voltage and the RSSI output voltage due to a disturber. The dynamic range of the RSSI amplifier is exceeded if the RF input signal is about 60 dB higher compared to the RF input signal at full sensitivity. Since different RF input networks may exhibit slightly different values for the LNA gain, the sensitivity values given in the electrical characteristics refer to a specific input matching. This matching is illustrated in Figure 3-3 on page 6 and exhibits the best possible sensitivity. 4.3 Demodulator and Data Filter The signal coming from the RSSI amplifier is converted into the raw data signal by the ASK demodulator. In ASK mode, an automatic threshold control circuit (ATC) is employed to set the detection reference voltage to a value where a good signal-to-noise ratio is achieved. This circuit also implies the effective suppression of any kind of in-band noise signals or competing transmitters. If the S/N ratio exceeds 10 dB, the data signal can be detected properly. The output signal of the demodulator is filtered by the data filter before it is fed into the digital signal processing circuit. The data filter improves the S/N ratio as its bandpass can be adopted to the characteristics of the data signal. The data filter consists of a 1st-order high-pass and a 1st-order low-pass filter. The high-pass filter cut-off frequency is defined by an external capacitor connected to pin CDEM. The cut-off frequency of the high-pass filter is defined by the following formula: 1 f cu_DF = -2 × × 30 k × CDEM In self-polling mode, the data filter must settle very rapidly to achieve a low current consumption. Therefore, CDEM cannot be increased to very high values if self polling is used. On the other hand, CDEM must be large enough to meet the data filter requirements according to the data signal. Recommended values for CDEM are given in the section "Electrical Characteristics" on page 22. 7 4663B 4663B­RKE­05/05 The cut-off frequency of the low-pass filter is defined by the selected baud rate range (BR_Range). BR_Range is defined in the OPMODE register (refer to section "Configuration of the Receiver" on page 17). BR_Range must be set in accordance to the used baud rate. The U3745BM U3745BM is designed to operate with data coding where the DC level of the data signal is 50%. This is valid for Manchester and Bi-phase coding. If other modulation schemes are used, the DC level should always remain within the range of VDC_min = 33% and VDC_max = 66%. The sensitivity may be reduced by up to 1.5 dB in that condition. Each BR_Range is also defined by a minimum and a maximum edge-to-edge time (tee_sig). These limits are defined in the section "Electrical Characteristics" on page 22. They should not be exceeded to maintain full sensitivity of the receiver. 4.4 Receiving Characteristics The RF receiver U3745BM U3745BM can be operated with and without a SAW front end filter. The selectivity with and without a SAW front-end filter is illustrated in Figure 4-1. This example relates to ASK mode of the U3745BM U3745BM. Note that the mirror frequency is reduced by 40 dB. The plots are printed relatively to the maximum sensitivity. If a SAW filter is used, an insertion loss of about 4 dB must be considered. When designing the system in terms of receiving bandwidth, the LO deviation must be considered as it also determines the IF center frequency. The total LO deviation is calculated to be the sum of the deviation of the crystal and the XTO deviation of the U3745BM U3745BM. Low-cost crystals are specified to be within ±100 ppm. The XTO deviation of the U3745BM U3745BM is an additional deviation due to the XTO circuit. This deviation is specified to be ±50 ppm. If a crystal of ±100 ppm is used, the total deviation is ±150 ppm in that case. Note that the receiving bandwidth and the IF-filter bandwidth are equivalent in ASK mode. Figure 4-1. Receiving Frequency Response 0.0 -10.0 dP (dB) -20.0 without SAW -30.0 -40.0 -50.0 -60.0 -70.0 -80.0 with SAW -90.0 -100.0 -6.0 -5.0 -4.0 -3.0 -2.0 -1.0 0.0 1.0 2.0 3.0 4.0 5.0 6.0 df (MHz) 8 U3745BM U3745BM 4663B 4663B­RKE­05/05 U3745BM U3745BM 5. Polling Circuit and Control Logic The receiver is designed to consume less than 1 mA while being sensitive to signals from a corresponding transmitter. This is achieved via the polling circuit. This circuit enables the signal path periodically for a short time. During this time the bit check logic verifies the presence of a valid transmitter signal. Only if a valid signal is detected the receiver remains active and transfers the data to the connected microcontroller. If there is no valid signal present, the receiver is in sleep mode most of the time resulting in low current consumption. This condition is called polling mode. A connected microcontroller is disabled during that time. All relevant parameters of the polling logic can be configured by the connected microcontroller. This flexibility enables the user to meet the specifications in terms of current consumption, system response time, data rate etc. Regarding the number of connection wires to the microcontroller, the receiver is very flexible. It can be either operated by a single bi-directional line to save ports to the connected microcontroller, or it can be operated by up to three uni-directional ports. 5.1 Basic Clock Cycle of the Digital Circuitry The complete timing of the digital circuitry and the analog filtering is derived from one clock. According to Figure 5-1, this clock cycle TClk is derived from the crystal oscillator (XTO) in combination with a divider. The division factor is controlled by the logical state at pin MODE. According to section "RF Front End" on page 4, the frequency of the crystal oscillator (fXTO) is defined by the RF input signal (fRFin) which also defines the operating frequency of the local oscillator (fLO). Figure 5-1. Generation of the Basic Clock Cycle TClk MODE Divider :14/:10 fXTO 16 L : USA (:10) H: Europe (:14) DVCC 15 XTO XTO 14 Pin MODE can now be set in accordance with the desired clock cycle TClk. TClk controls the following application-relevant parameters: · Timing of the polling circuit including bit check · Timing of analog and digital signal processing · Timing of register programming · Frequency of the reset marker · F filter center frequency (fIF0) 9 4663B 4663B­RKE­05/05 Most applications are dominated by two transmission frequencies: fSend = 315 MHz is mainly used in the USA, fSend = 433.92 MHz in Europe. In order to ease the usage of all TClk-dependent parameters, the electrical characteristics display three conditions for each parameter. · USA Applications (fXTO = 4.90625 MHz, MODE = L, TClk = 2.0383 µs) · Europe Applications (fXTO = 6.76438 MHz, MODE = H, TClk = 2.0697 µs) · Other applications (TClk is dependent on fXTO and on the logical state of pin MODE. The electrical characteristic is given as a function of TClk). The clock cycle of some function blocks depends on the selected baud rate range (BR_Range) which is defined in the OPMODE register. This clock cycle TXClk is defined by the following formulas for further reference: TXClk = 8 × TClk TXClk = 4 × TClk BR_Range2: TXClk = 2 × TClk BR_Range3: 5.2 BR_Range0: BR_Range1: BR_Range = TXClk = 1 × TClk Polling Mode According to Figure 3-2 on page 6, the receiver stays in polling mode in a continuous cycle of three different modes. In sleep mode, the signal processing circuitry is disabled for the time period TSleep while consuming low current of IS = ISoff. During the start-up period, TStartup, all signal processing circuits are enabled and settled. In the following bit check mode, the incoming data stream is analyzed bit by bit contra a valid transmitter signal. If no valid signal is present, the receiver is set back to sleep mode after the period TBitcheck. This period varies check by check as it is a statistical process. An average value for TBitcheck is given in the section "Electrical Characteristics" on page 22. During TStartup and TBitcheck the current consumption is IS = ISon. The average current consumption in polling mode is dependent on the duty cycle of the active mode and can be calculated as: I Soff × T Sleep + I Son × ( T Startup + T Bitcheck ) I Spoll = -T Sleep + T Startup + T Bitcheck During TSleep and TStartup, the receiver is not sensitive to a transmitter signal. To guarantee the reception of a transmitted command, the transmitter must start the telegram with an adequate preburst. The required length of the preburst is dependent on the polling parameters TSleep, TStartup, TBitcheck and the startup time of a connected microcontroller (TStart,µC). TBitcheck thus depends on the actual bit rate and the number of bits (NBitcheck) to be tested. The following formula indicates how to calculate the preburst length. TPreburst TSleep + TStartup + TBitcheck + TStart_µC 5.2.1 Sleep Mode The length of period TSleep is defined by the 5-bit word Sleep of the OPMODE register, the extension factor XSleep, according to table 10, and the basic clock cycle TClk. It is calculated to be: T Sleep = Sleep × X Sleep × 1024 × T Clk 10 U3745BM U3745BM 4663B 4663B­RKE­05/05 U3745BM U3745BM In US and European applications, the maximum value of TSleep is about 60 ms if XSleep is set to 1. The time resolution is about 2 ms in that case. The sleep time can be extended to almost half a second by setting XSleep to 8. XSleep can be set to 8 by bit XSleepStd or by bit XSleepTemp resulting in a different mode of action as described below: XSleepStd = 1 implies the standard extension factor. The sleep time is always extended. XSleepTemp = 1 implies the temporary extension factor. The extended sleep time is used as long as every bit check is OK. If the bit check fails once, this bit is set back to 0 automatically resulting in a regular sleep time. This functionality can be used to save current in presence of a modulated disturber similar to an expected transmitter signal. The connected microcontroller is rarely activated in that condition. If the disturber disappears, the receiver switches back to regular polling and is again sensitive to appropriate transmitter signals. According to Table 5-6 on page 18, the highest register value of Sleep sets the receiver to a permanent sleep condition. The receiver remains in that condition until another value for Sleep is programmed into the OPMODE register. This function is desirable where several devices share a single data line. Figure 5-2. Polling Mode Flow Chart Sleep Mode: All circuits for signal processing are disabled. Only XTO and polling logic are enabled. IS = ISOFF TSleep = Sleep × XSleep × 1024 × TClk Bit-check Mode: The incomming data stream is analyzed. If the timing indicates a valid transmitter signal, the receiver is set to receiving mode. Otherwise it is set to Sleep mode. IS = ISON TBitcheck NO 5-bit word defined by Sleep0 to Sleep4 in OPMODE register XSleep: Extension factor defined by XSleepTemp according to Table 8 TClk: Basic clock cycle defined by fXTO and pin MODE TStartup: Is defined by the selected baud rate range and TClk. The baud-rate range is defined by Baud0 and Baud1 in the OPMODE register. TBit-check: Start-up Mode: The signal processing circuits are enabled. After the start-up time (TStartup) all circuits are in stable condition and ready to receive. IS = ISON TStartup Sleep: Depends on the result of the bit check. If the bit check is ok, TBit-check depends on the number of bits to be checked (NBit-checked) and on the utilized data rate. If the bit check fails, the average time period for that check depends on the selected baud-rate range and on TClk. The baud-rate range is defined by Baud0 and Baud1 in the OPMODE register. Bit check OK? YES Receiving Mode: The receiver is turned on permanently and passes the data stream to the connected microcontroller. It can be set to Sleep mode through an OFF command via pin DATA or ENABLE IS = ISON OFF command 11 4663B 4663B­RKE­05/05 Figure 5-3. Timing Diagram for a Completely Successful Bit Check (Number of Checked Bits: 3) Bit check ok Enable IC Bit check 1/2 Bit 1/2 Bit 1/2 Bit 1/2 Bit 1/2 Bit 1/2 Bit Dem_out DATA Polling mode 5.3 Receiving mode Bit Check Mode In bit check mode, the incoming data stream is examined to distinguish between a valid signal from a corresponding transmitter and signals due to noise. This is done by subsequent time frame checks where the distances between 2 signal edges are continuously compared to a programmable time window. The maximum count of this edge-to-edge test, before the receiver switches to receiving, mode is also programmable. 5.3.1 Configuring the Bit Check Assuming a modulation scheme that contains 2 edges per bit, two time frame checks are verifying one bit. This is valid for Manchester, Bi-phase and most other modulation schemes. The maximum count of bits to be checked can be set to 0, 3, 6 or 9 bits via the variable NBitcheck in the OPMODE register. This implies 0, 6, 12 and 18 edge-to-edge checks respectively. If NBitcheck is set to a higher value, the receiver is less likely to switch to the receiving mode due to noise. In the presence of a valid transmitter signal, the bit check takes less time if NBitcheck is set to a lower value. In polling mode, the bit check time is not dependent on NBitcheck. Figure 5-3 shows an example where 3 bits are tested successfully and the data signal is transferred to pin DATA. According to Figure 5-4, the time window for the bit check is defined by two separate time limits. If the edge-to-edge time tee is in between the lower bit check limit TLim_min and the upper bit check limit TLim_max, the check will be continued. If tee is smaller than TLim_min or tee exceeds TLim_max, the bit check will be terminated and the receiver switches to sleep mode. Figure 5-4. Valid Time Window for Bit Check 1/fSig Dem_out tee TLim_min TLim_max For best noise immunity it is recommended to use a low span between TLim_min and TLim_max. This is achieved using a fixed frequency at a 50% duty cycle for the transmitter preburst. A `11111.' or a `10101.' sequence in Manchester or Bi-phase is a good choice in this regard. A good compromise between receiver sensitivity and susceptibility to noise is a time window of ±25% regarding the expected edge-to-edge time tee. Using preburst patterns that contain various edge-to-edge time periods, the bit check limits must be programmed according to the required span. 12 U3745BM U3745BM 4663B 4663B­RKE­05/05 U3745BM U3745BM The bit check limits are determined by means of the formula below: TLim_min = Lim_min × TXClk TLim_max = (Lim_max ­ 1) × TXClk Lim_min and Lim_max are defined by a 5-bit word each within the LIMIT register. Using the above formulas, Lim_min and Lim_max can be determined according to the required TLim_min, TLim_max and TXClk. The time resolution when defining TLim_min and TLim_max is TXClk. The minimum edge-to-edge time tee (tDATA_L_min, tDATA_H_min) is defined according to the section "Receiving Mode". Due to this, the lower limit should be set to Lim_min 10. The maximum value of the upper limit is Lim_max = 63. Figure 5-5, Figure 5-6 and Figure 5-7 on page 14 illustrate the bit check for the default bit check limits Lim_min = 14 and Lim_max = 24. When the IC is enabled, the signal processing circuits are enabled during TStartup. The output of the demodulator (Dem_out) is undefined during that period. When the bit check becomes active, the bit check counter is clocked with the cycle TXClk. Figure 5-5 shows how the bit check proceeds if the bit-check counter value CV_Lim is within the limits defined by Lim_min and Lim_max at the occurrence of a signal edge. In Figure 5-7, the bit check fails as the value CV_lim is lower than the limit Lim_min. The bit check also fails if CV_Lim reaches Lim_max. This is illustrated in Figure 5-8 on page 15. Figure 5-5. Timing Diagram During Bit Check (Lim_min = 14, Lim_max = 24) Bit check ok Bit check ok Enable IC TStartup Bit check 1/2 Bit 1/2 Bit 1/2 Bit Dem_out Bit check Counter 0 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 9 10 111213 1415 161718 1 2 3 4 5 6 7 8 9 10 1112131415 1 2 3 4 TXClk Figure 5-6. Timing Diagram for Failed Bit Check (Condition: CV_Lim < Lim_min) Bit check failed (CV_Lim < Lim_min) (Lim_min = 14, Lim_max = 24) Enable IC Bit check 1/2 bit Dem_out Bit check Counter 0 Startup mode 1 2 3 4 5 6 1 2 3 4 5 6 7 8 9 10 1112 Bit check mode 0 Sleep mode 13 4663B 4663B­RKE­05/05 Figure 5-7. Timing Diagram for Failed Bit Check (condition: CV_Lim Lim_max) (Lim_min = 14, Lim_max = 24) Bit check failed (CV_Lim = Lim_max) Enable IC Bit check 1/2 bit Dem_out Bit check Counter 0 Startup mode 5.3.2 1 2 3 4 5 6 7 1 2 3 4 5 6 7 8 9 10 1112 13141516 171819 20 21222324 Bitcheck mode 0 Sleep mode Duration of the Bit Check If no transmitter signal is present during the bit check, the output of the demodulator delivers random signals. The bit check is a statistical process and TBitcheck varies for each check. Therefore, an average value for TBitcheck is given in the section "Electrical Characteristics" on page 22. TBitcheck depends on the selected baud rate range and on TClk. A higher baudrate range causes a lower value for TBitcheck resulting in lower current consumption in polling mode. In the presence of a valid transmitter signal, TBitcheck is dependant on the frequency of that signal, fSig and the count of the checked bits, NBitcheck. A higher value for NBitcheck thereby results in a longer period for TBitcheck requiring a higher value for the transmitter preburst TPreburst. 5.4 Receiving Mode If the bit check has been successful for all bits specified by NBitcheck, the receiver switches to receiving mode. According to Figure 5-4 on page 12, the internal data signal is switched to pin DATA in that case. A connected microcontroller can be woken up by the negative edge at pin DATA. The receiver stays in that condition until it is switched back to polling mode explicitly. 5.4.1 14 Digital Signal Processing The data from the demodulator (Dem_out) is digitally processed in different ways and as a result converted into the output signal data. This processing depends on the selected baud rate range (BR_Range). Figure 5-8 on page 15 illustrates how Dem_out is synchronized by the extended clock cycle TXClk. This clock is also used for the bit check counter. Data can change its state only after TXClk elapsed. The edge-to-edge time period tee of the Data signal as a result is always an integral multiple of TXClk. The minimum time period between two edges of the data signal is limited to tee TDATA_min. This implies an efficient suppression of spikes at the DATA output. At the same time, it limits the maximum frequency of edges at DATA. This eases the interrupt handling of a connected microcontroller. TDATA_min is to some extent affected by the preceding edge-to-edge time interval tee as illustrated in Figure 5-9 on page 15. If tee is in between the specified bit check limits, the following level is frozen for the time period TDATA_min = tmin1, in case of tee being outside that bit check limits TDATA_min = tmin2 is the relevant stable time period. The maximum time period for DATA to be low is limited to TDATA_L_max. This function ensures a finite response time during programming or switching off the receiver via pin DATA. TDATA_L_max is thereby longer than the maximum time period indicated by the transmitter data stream. Figure 5-10 on page 15 gives an example where Dem_out remains low after the receiver has switched to receiving mode. U3745BM U3745BM 4663B 4663B­RKE­05/05 U3745BM U3745BM Figure 5-8. Synchronization of the Demodulator Output TXClk Clock bit check counter Dem_out DATA Figure 5-9. tee Debouncing of the Demodulator Output Dem_out DATA Lim_min CV_Lim < Lim_max tmin1 tee CV_Lim < Lim_min or CV_Lim Lim_max tmin2 tee Figure 5-10. Steady L State Limited DATA Output Pattern after Transmission Enable IC Bit check Dem_out DATA Sleep mode Bit check mode Receiving mode tmin2 tDATA_L_max After the end of a data transmission, the receiver remains active and random noise pulses appear at pin DATA. The edge-to-edge time period tee of the majority of these noise pulses is equal to or slightly higher than TDATA_min. 5.4.2 Switching the Receiver Back to Sleep Mode The receiver can be set back to polling mode via pin DATA or via pin ENABLE. When using pin DATA, this pin must be pulled to Low for the period t1 by the connected microcontroller. Figure 5-11 on page 16 illustrates the timing of the OFF command (see also Figure 515 on page 21). The minimum value of t1 depends on the BR_Range. The maximum value for t1 is not limited but it is recommended not to exceed the specified value to prevent erasing the reset marker. This item is explained in more detail in the section "Configuration of the Receiver". Setting the receiver to sleep mode via DATA is achieved by programming bit 1 of the OPMODE register to 1. Only one synchronous pulse (t3) is issued. 15 4663B 4663B­RKE­05/05 The duration of the OFF command is determined by the sum of t1, t2 and t10. After the OFF command, the sleep time TSleep elapses. Note that the capacitive load at pin DATA is limited. The resulting time constant t together with an optional external pull-up resistor may not be exceeded to ensure proper operation. If the receiver is set to polling mode via pin ENABLE, an `L' pulse (TDoze) must be issued at that pin. Figure 5-12 illustrates the timing of that command. After the positive edge of this pulse, the sleep time TSleep elapses. The receiver remains in sleep mode as long as ENABLE is held to `L'. If the receiver is polled exclusively by a microcontroller, TSleep can be programmed to 0 to enable a instantaneous response time. This command is the faster option than via pin DATA at the cost of an additional connection to the microcontroller. Figure 5-11. Timing Diagram of the OFF Command Via Pin DATA t1 t2 t3 t5 t4 t10 t7 Out1 (microcontroller) DATA (U3745BM U3745BM) X X Serial bi-directional data line X X Bit 1 ("1") (Start bit) Receiver on TSleep Startup mode OFF Command Figure 5-12. Timing Diagram of the OFF Command Via Pin ENABLE TDoze TSleep toff ENABLE DATA (U3745BM U3745BM) X X Serial bi-directional data line X X Receiver on 16 Startup mode U3745BM U3745BM 4663B 4663B­RKE­05/05 U3745BM U3745BM 5.5 Configuration of the Receiver The U3745BM U3745BM receiver is configured via two 12-bit RAM registers called OPMODE and LIMIT. The registers can be programmed by means of the bi-directional DATA port. If the register contents have changed due to a voltage drop, this condition is indicated by a certain output pattern called reset marker (RM). The receiver must be reprogrammed in that case. After a power-on reset (POR), the registers are set to default mode. If the receiver is operated in default mode, there is no need to program the registers. Table 5-2 shows the structure of the registers. According to Table 5-1, bit 1 defines if the receiver is set back to polling mode via the OFF command, (see section "Receiving Mode") or if it is programmed. Bit 2 represents the register address. It selects the appropriate register to be programmed. Table 5-1. Effect of Bit 1 and Bit 2 in Programming the Registers Bit 1 Bit 2 1 x Action The receiver is set back to polling mode (OFF command) 0 1 The OPMODE register is programmed 0 0 The LIMIT register is programmed Table 5-3 on page 18 and the following illustrate the effect of the individual configuration words. The default configuration is highlighted for each word. BR_Range sets the appropriate baud rate range. At the same time it defines XLim. XLim is used to define the bit check limits TLim_min and TLim_max as shown in Table 5-3 on page 18. POUT can be used to control the sensitivity of the receiver. In that application, POUT is set to 1 to reduce the sensitivity. This implies that the receiver operates with full sensitivity after a POR. Table 5-2. Bit1 Bit2 Effect of the Configuration Words within the Registers Bit2 Bit4 Bit5 Bit6 Bit7 Bit8 Bit9 Bit10 Bit11 Bit12 Bit13 Bit14 OFF Command 1 OPMODE Register 0 1 0 1 BR_Range VPOUT NBitcheck Sleep XSleep Baud1 Baud0 BitChk1 BitChk0 POUT Sleep4 Sleep3 Sleep2 Sleep1 Sleep0 XSleep Std XSleep Temp 0 0 1 0 0 0 1 0 1 1 0 0 (Default) LIMIT Register 0 0 0 0 Lim_min Lim_max Lim_min5 Lim_min4 Lim_min3 Lim_min2 Lim_min1 Lim_min0 Lim_max5 Lim_max4 Lim_max3 Lim_max2 Lim_max1 Lim_max0 (Default) 0 0 1 1 1 0 0 1 1 0 0 0 17 4663B 4663B­RKE­05/05 Table 5-3. Effect of the Configuration Word BR_Range BR_Range Baud1 Baud0 0 0 BR_Range0 (application USA/Europe: BR_Range0 = 1.0 kBaud to 1.8 kBaud) (Default) XLim = 8 (Default) 0 1 BR_Range1 (application USA/Europe: BR_Range1 = 1.8 kBaud to 3.2 kBaud) XLim = 4 1 0 BR_Range2 (application USA/Europe: BR_Range2 = 3.2 kBaud to 5.6 kBaud) XLim = 2 1 1 BR_Range3 (Application USA/Europe: BR_Range3 = 5.6 kBaud to 10 kBaud) XLim = 1 Table 5-4. Baudrate Range/Extension Factor for Bit Check Limits (XLim) Effect of the Configuration Word NBitcheck NBitcheck BitChk1 Number of Bits to be Checked 0 0 0 0 1 3 1 0 6 (Default) 1 Table 5-5. BitChk0 1 9 Effect of the Configuration Bit VPOUT VPOUT Level of the Multi-purpose Output Port POUT POUT 0 1 Table 5-6. 0 (Default) 1 Effect of the Configuration Word Sleep Sleep Sleep4 Sleep3 Sleep2 Sleep1 Sleep0 Start Value for Sleep Counter (TSleep = Sleep × XSleep × 1024 × TClk) 0 0 0 0 0 0 (Receiver is continuously polling until a valid signal occurs) 0 0 0 1 1 (TSleep 2ms for XSleep = 1 in US-/European applications) 0 0 1 0 2 0 0 0 1 1 3 . . . . . . . . . . . . . . . . . . 0 1 0 1 1 11 (USA: TSleep = 22.96 ms, Europe: TSleep = 23.31 ms) (Default) . . . . . . . . . . . . . . . . . . 1 1 1 0 1 29 1 1 1 1 0 30 1 18 0 0 1 1 1 1 31 (Permanent sleep mode) U3745BM U3745BM 4663B 4663B­RKE­05/05 U3745BM U3745BM Table 5-7. Effect of the Configuration Word XSleep XSleep Extension Factor for Sleep Time (TSleep = Sleep × XSleep × 1024 × TClk) XSleepStd XSleepTemp 0 0 1 (Default) 0 1 8 (XSleep is reset to 1 if bit check fails once) 1 0 8 (XSleep is set permanently) 1 1 8 (XSleep is set permanently) Table 5-8. Effect of the Configuration Word Lim_min Lim_min Lower Limit Value for Bit Check Lim_min < 10 is not applicable (TLim_min = Lim_min × XLim × TClk) 0 0 1 0 1 0 10 0 0 1 0 1 1 11 0 0 1 1 0 0 12 0 0 1 1 0 1 13 0 0 1 1 1 0 14 (Default) (USA: TLim_min = 228 µs, Europe: TLim_min = 232 µs) . . . . . . . . . . . . . . . . . . 1 1 1 1 0 1 61 1 1 1 1 1 0 62 1 1 1 1 1 1 63 Table 5-9. Effect of the Configuration Word Lim_max Lim_max Upper Limit Value for Bit Check Lim_max < 12 is not applicable (TLim_max = (Lim_max ­ 1) × XLim × TClk) 0 0 1 1 0 0 12 0 0 1 1 0 1 13 0 0 1 1 1 0 14 . . . . . . . . . . . . . . . . . . 0 1 1 0 0 0 . . . . . . . . . . . . . . . . . . 1 1 1 1 0 1 61 1 1 1 1 1 0 62 1 1 1 1 1 1 63 24 (Default) (USA: TLim_max = 375 µs, Europe: TLim_max = 381 µs) 19 4663B 4663B­RKE­05/05 5.5.1 Conservation of the Register Information The U3745BM U3745BM has an integrated power-on reset and brown-out detection circuitry to provide a mechanism to preserve the RAM register information. According to Figure 5-13, a power-on reset (POR) is generated if the supply voltage VS drops below the threshold voltage VThReset. The default parameters are programmed into the configuration registers in that condition. Once V S exceeds V ThReset , the POR is canceled after the minimum reset period tRst. A POR is also generated when the supply voltage of the receiver is turned on. To indicate that condition, the receiver displays a reset marker (RM) at pin DATA after a reset. The RM is represented by the fixed frequency fRM at a 50% duty cycle. RM can be canceled via an `L' pulse t1 at pin DATA. The RM implies the following characteristics: · fRM is lower than the lowest feasible frequency of a data signal. By this means, RM cannot be misinterpreted by the connected microcontroller. · If the receiver is set back to polling mode via pin DATA, RM cannot be canceled by accident if t1 is applied according to the proposal in the section "Programming the Configuration Register" on page 21. By means of that mechanism, the receiver cannot lose its register information without communicating that condition via the reset marker RM. Figure 5-13. Generation of the Power-on Reset VS VThReset POR tRst DATA (U3745BM U3745BM) X 1/fRM Figure 5-14. Timing of the Register Programming t1 t2 t3 t9 t5 t4 TSleep t8 t6 t7 Out1 (microcontroller) DATA (U3745BM U3745BM) X X Serial bi-directional data line X X Bit 1 ("0") (Start bit) Receiver on 20 Bit 2 ("1") (Register select) Programming Frame Bit 13 ("0") (Poll8) Bit 14 ("1") (Poll8R) Startup mode U3745BM U3745BM 4663B 4663B­RKE­05/05 U3745BM U3745BM 5.5.2 Programming the Configuration Register The configuration registers are programmed serially via the bi-directional data line according to Figure 5-14 on page 20 and Figure 5-15. Figure 5-15. One-wire Connection to a Microcontroller U3745BM U3745BM Internal pull-up resistor Microcontroller Bi-directional data line DATA I/O Out 1 (microcontroller) DATA (U3745BM U3745BM) To start programming, the serial data line DATA is pulled to L for the time period t1 by the microcontroller. When DATA has been released, the receiver becomes the master device. When the programming delay period t2 has elapsed, it emits 14 subsequent synchronization pulses with the pulse length t3. After each of these pulses, a programming window occurs. The delay until the program window starts is determined by t4, the duration is defined by t5. Within the programming window, the individual bits are set. If the microcontroller pulls down pin DATA for the time period t7 during t5, the according bit is set to 0. If no programming pulse t7 is issued, this bit is set to 1. All 14 bits are subsequently programmed in this way. The time frame to program a bit is defined by t6. Bit 14 is followed by the equivalent time window t9. During this window, the equivalent acknowledge pulse t8 (E_Ack) occurs if the mode word just programmed is equivalent to the mode word that was already stored in that register. E_Ack should be used to verify that the mode word was correctly transferred to the register. The register must be programmed twice in that case. Programming of a register is possible both during sleep and active mode of the receiver. During programming, the LNA, LO, lowpass filter, IF-amplifier and the demodulator are disabled. The programming start pulse t1 initiates the programming of the configuration registers. If bit 1 is set to 1, it represents the OFF command to set the receiver back to polling mode at the same time. For the length of the programming start pulse t1, the following convention should be considered: · t1(min) < t1 < 1535 × TClk: [t1(min) is the minimum specified value for the relevant BR_Range] Programming (respectively OFF command) is initiated if the receiver is not in reset mode. If the receiver is in reset mode, programming (respectively Off command) is not initiated, and the reset marker RM is still present at pin DATA. This period is generally used to switch the receiver to polling mode. In a reset condition, RM is not canceled by accident. · t1 > 5632 × TClk Programming (respectively OFF command) is initiated in any case. RM is cancelled if present. This period is used if the connected microcontroller detected RM. If a configuration register is programmed, this time period for t1 can generally be used. Note that the capacitive load at pin DATA is limited. The resulting time constant t together with an optional external pull-up resistor may not be exceeded to ensure proper operation. 21 4663B 4663B­RKE­05/05 6. Absolute Maximum Ratings Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameters Max. Unit Supply voltage Symbol VS 6 V Power dissipation Ptot 450 mW Tj 150 °C Junction temperature Min. Storage temperature Tstg ­55 +125 °C Ambient temperature Tamb ­40 +85 °C 10 dBm Maximum input level, input matched to 50 Pin_max 7. Thermal Resistance Parameters Symbol Unit RthJA Junction ambient Value 100 K/W 8. Electrical Characteristics All parameters refer to GND, VS = 5V, Tamb = 25°C, f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified. The possible operating range refer to different circuit conditions: VS = 4.5V to 5.5V, Tamb = ­40°C to +85°C Parameters Test Conditions Symbol Min. Typ. Max. Unit Sleep mode (XTO and polling logic active) ISoff 190 350 µA IC active (startup-, bit check-, receiving mode) Pin DATA = H ISon 7.0 8.6 mA Third-order intercept point LNA/mixer/IF amplifier input matched according to Figure 3-3 on page 6 IIP3 ­28 LO spurious emission at RFIn Input matched according to Figure 3-3 on page 6, required according to I-ETS 300220 ISLORF ­73 Noise figure LNA and mixer (DSB) Input matching according to Figure 33 on page 6 NF 7 dB LNA_IN input impedance at 433.92 MHz at 315 MHz ZiLNA_IN 1.0 || 1.56 1.3 || 1.0 k || pF k || pF 1 dB compression point (LNA, mixer, IF amplifier) Input matched according to Figure 3-3 on page 6, referred to RFin IP1db ­40 dBm Maximum input level Input matched according to Figure 3-3 on page 6, BER 10-3, ASK mode Pin_max Current consumption LNA Mixer 22 dBm ­57 ­23 dBm dBm U3745BM U3745BM 4663B 4663B­RKE­05/05 U3745BM U3745BM 8. Electrical Characteristics (Continued) All parameters refer to GND, VS = 5V, Tamb = 25°C, f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified. The possible operating range refer to different circuit conditions: VS = 4.5V to 5.5V, Tamb = ­40°C to +85°C Parameters Test Conditions Symbol Min. fVCO Typ. 309 Max. Unit 439 MHz Local Oscillator Operating frequency range VCO Loop bandwidth of the PLL For best LO noise (design parameter) R1 = 820 C9 = 4.7 nF C10 = 1 nF BLoop Capacitive load at Pin LF The capacitive load at pin LF is limited if bit check is used. The limitation therefore also applies to self polling. CLF_tot XTO operating frequency kHz nF 6.764375 +50 ppm 4.90625 +50 ppm MHz RS 150 220 CXT0 XTO crystal frequency, appropriate load capacitance must be connected to XTAL 6.764375 MHz 10 6.5 pF ­113.5 dBm fXTO 4.90625 MHz Series resonance resistor of the crystal 100 fXTO = 6.764 MHz 4.906 MHz Static capacitance at Pin XT0 6.764375 ­50 ppm 4.90625 ­50 ppm 6.764375 4.90625 MHz Analog Signal Processing Input matched according to figure 6 ASK (level of carrier) BER 10-3, B = 600 kHz fin = 433.92 MHz/315 MHz T = 25° C, VS = 5V Input sensitivity ASK 600-kHz IF filter fIF = 1 MHz BR_Range0 PRef_ASK ­106 ­110 BR_Range1 ­104.5 ­108.5 ­112 dBm BR_Range2 ­104 ­108 ­111.5 dBm BR_Range3 ­102 ­106 ­109.5 dBm Sensitivity variation ASK for full operating range including IF filter compared to Tamb = 25° C, VS = 5V 600-kHz version fin = 433.92 MHz/315 MHz fIF = 0.81 MHz to 1.19 MHz fIF = 0.75 MHz to 1.25 MHz PASK = PRef_ASK + PRef S/N ratio to suppress inband noise signals ASK mode +3 +5 dB dB 1 f cu_DF = -2 × × 30k × CDEM SNRASK 11 dB RRSSI Dynamic range RSSI ampl. Lower cut-off frequency of the data filter PRef 60 dB fcu_DF 0.11 0.16 0.20 kHz CDEM = 33 nF 23 4663B 4663B­RKE­05/05 8. Electrical Characteristics (Continued) All parameters refer to GND, VS = 5V, Tamb = 25°C, f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified. The possible operating range refer to different circuit conditions: VS = 4.5V to 5.5V, Tamb = ­40°C to +85°C Parameters Test Conditions Recommended CDEM for best performance ASK mode BR_Range0 (Default) BR_Range1 BR_Range2 BR_Range3 BR_Range0 (Default) Maximum edge-to-edge time period of BR_Range1 the input data signal for full sensitivity BR_Range2 BR_Range3 BR_Range0 (Default) Minimum edge-to-edge time period of BR_Range1 the input data signal for full sensitivity BR_Range2 BR_Range3 Threshold voltage for reset Symbol Min. Typ. Max. 39 22 12 8.2 CDEM Unit nF nF nF nF tee_sig 1000 560 320 180 µs µs µs µs tee_sig 270 156 89 50 µs µs µs µs VThRESET 1.95 2.8 3.75 V 39 0.08 50 0.3 61 2.5 41 540 V k µs pF pF 0.3 V V Digital Ports Data output - Saturation voltage LOW - Internal pull-up resistor - Maximum time constant - Maximum capacitive load = CL (Rpup//RExt) without external pull-up resistor Rext = 5 k VOI RPup CL CL IPOUT = 1 mA IPOUT = ­1 mA VOl VOh ASK VIh 0.8 × VS ENABLE input - Low-level input voltage - High-level input voltage Idle mode Active mode VIl VIh 0.8 × VS MODE input - Low-level input voltage - High-level input voltage Division factor = 10 Division factor = 14 VIl VIh 0.8 × VS POUT output - Saturation voltage LOW - Saturation voltage HIGH ASK input - High-level input voltage TEST input - Low-level input voltage 24 Iol = 1 mA Test input must always be set to LOW VIl 0.08 VS ­ 0.3 V VS ­ 0.14 V V 0.2 × VS V V 0.2 × VS V V 0.2 × VS V U3745BM U3745BM 4663B 4663B­RKE­05/05 U3745BM U3745BM 9. Electrical Characteristics All parameters refer to GND, VS = 5V, Tamb = 25°C, f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified. The possible operating range refer to different circuit conditions: VS = 4.5V to 5.5V, Tamb = ­40°C to +85°C 6.76438-Mhz Osc. (Mode 1) Parameter Test Condition Symbol Min. Typ. Max. 4.90625-Mhz Osc. (Mode 0) Min. Typ. Max. Variable Oscillator Min. Typ. Max. Unit Basic Clock Cycle of the Digital Circuitry Basic clock cycle MODE = 0 (USA) MODE = 1 (Europe) Extended basic clock cycle BR_Range0 BR_Range1 BR_Range2 BR_Range3 2.0383 1/(fXTO/10) 1/(fXTO/14) µs µs TXClk 16.6 8.3 4.1 2.1 16.3 8.2 4.1 2.0 8 × TClk 4 × TClk 2 × TClk 1 × TClk µs µs µs µs TSleep Sleep × XSleep × 1024 × 2.0697 Sleep × XSleep × 1024 × 2.0383 Sleep × XSleep × 1024 × TClk ms 1855 1061 1061 663 1827 1045 1045 653 896.5 512.5 512.5 320.5 × TClk 0.45 0.24 0.14 0.14 0.47 0.26 0.16 0.15 TClk 2.0697 Polling Mode Sleep time Sleep and XSleep are defined in the OPMODE register BR_Range0 BR_Range1 BR_Range2 BR_Range3 Start-up time Time for Bit check TStartup Average bit check time while polling BR_Range0 BR_Range1 BR_Range2 BR_Range3 TBitcheck Bit check time for a valid input signal fSig NBitcheck = 0 NBitcheck = 3 NBitcheck = 6 NBitcheck = 9 TBitcheck 3/fSig 6/fSig 9/fSig 3.5/fSig 6.5/fSig 9.5/fSig 3/fSig 6/fSig 9/fSig µs µs µs µs ms ms ms ms 3.5/fSig 6.5/fSig 9.5/fSig TXClk 3.5/fSig 6.5/fSig 9.5/fSig ms ms ms ms Receiving Mode Intermediate frequency MODE=0 (USA) MODE=1 (Europe) fIF Baud rate range BR_Range0 BR_Range1 BR_Range2 BR_Range3 BR_Range Minimum time period between edges at Pin DATA (Figure 5-9 on page 15) BR_Range0 Maximum low period at DATA (Figure 5-10 on page 15) BR_Range0 BR_Range1 BR_Range2 BR_Range3 BR_Range1 BR_Range2 BR_Range3 TDATA_min tmin1 tmin2 tmin1 tmin2 tmin1 tmin2 tmin1 tmin2 TDATA_L_max fXTO × 64/314 fXTO × 64/432.92 1.0 1.0 1.8 3.2 5.6 10.0 1.0 1.8 3.2 5.6 1.8 3.2 5.6 10.0 1.0 1.8 3.2 5.6 BR_Range0 × BR_Range1 × BR_Range2 × BR_Range3 × 2 ms/TClk 2 ms/TClk 2 ms/TClk 2 ms/TClk MHz MHz kBaud kBaud kBaud kBaud 149 182 75 91 37.3 45.5 18.6 22.8 147 179 73 90 36.7 44.8 18.3 22.4 9 × TXClk 11 × TXCl 9 × TXClk 11 × TXClk 9 × TXClk 11 × TXClk 9 × TXClk 11 × TXClk µs µs µs µs µs µs µs µs 2169 1085 542 271 2136 1068 534 267 131 × 131 × 131 × 131 × µs µs µs µs TXClk TXClk TXClk TXClk 25 4663B 4663B­RKE­05/05 9. Electrical Characteristics All parameters refer to GND, VS = 5V, Tamb = 25°C, f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified. The possible operating range refer to different circuit conditions: VS = 4.5V to 5.5V, Tamb = ­40°C to +85°C 6.76438-Mhz Osc. (Mode 1) Parameter Test Condition Symbol Min. tDoze OFF command at Pin ENABLE (Figure 5-12 on page 16) Typ. Max. 3.1 4.90625-Mhz Osc. (Mode 0) Min. Typ. Max. Variable Oscillator Min. Typ. Max. 1.5 × TClk 3.05 Unit µs Configuration of the Receiver Frequency of the reset marker (Figure 5-13 on page 20) fRM 117.9 1 -4096 × T CLK 119.8 BR_Range0 Programming start pulse (Figure 5-11 on page 16, Figure 5-14 on page 20) 2188 3176 2155 3128 BR_Range1 1104 3176 1087 3128 561 3176 553 3128 290 3176 286 3128 BR_Range2 t1 BR_Range3 11656 11479 after POR Hz 1057 × TClk 533 × TClk 271 × TClk 140 × TClk 5632 × TClk 1535 × TClk 1535 × TClk 1535 × TClk 1535 × TClk 384.5 × TClk 385.5 × TClk µs Programming delay period (Figure 5-11 on page 16, Figure 5-14 on page 20) t2 Synchronization pulse (Figure 5-11 on page 16, Figure 5-14 on page 20) t3 265 261 128 × TClk µs Delay until the program window starts (Figure 5-11 on page 16, Figure 5-14 on page 20) t4 131 129 63.5 × TClk µs Programming window (Figure 5-11 on page 16, Figure 5-14 on page 20) t5 530 522 256 × TClk µs Time frame of a bit (Figure 5-14 on page 20) t6 1060 1044 512 × TClk µs 26 795 798 783 786 µs U3745BM U3745BM 4663B 4663B­RKE­05/05 U3745BM U3745BM 9. Electrical Characteristics All parameters refer to GND, VS = 5V, Tamb = 25°C, f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified. The possible operating range refer to different circuit conditions: VS = 4.5V to 5.5V, Tamb = ­40°C to +85°C 6.76438-Mhz Osc. (Mode 1) Parameter Test Condition Typ. 4.90625-Mhz Osc. (Mode 0) Max. Min. 529 Typ. 131 Variable Oscillator Symbol Min. Programming pulse (Figure 5-11 on page 16, Figure 514 on page 20) Max. Min. 521 Typ. 64 × TClk Max. Unit t7 133 256 × TClk µs Equivalent acknowledge pulse: E_Ack (Figure 5-14 on page 20) t8 265 261 128 × TClk µs Equivalent time window (Figure 5-14 on page 20) t9 534 526 258 × TClk µs OFF-bit programming window (Figure 5-11 on page 16) t10 930 916 449.5 × TClk µs 27 4663B 4663B­RKE­05/05 10. Ordering Information Extended Type Number Package Remarks U3745BM-P3FL U3745BM-P3FL SO20 Tube U3745BM-P3FLG3 U3745BM-P3FLG3 SO20 Taped and reeled 11. Package Information 9.15 8.65 Package SO20 Dimensions in mm 12.95 12.70 7.5 7.3 2.35 0.25 0.25 0.10 0.4 10.50 10.20 1.27 11.43 20 11 technical drawings according to DIN specifications 1 10 12. Revision History Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. Revision No. 4663B-RKE-05/05 4663B-RKE-05/05 28 History · Put datasheet in a new template · New heading rows at Table "Absolute Maximum Ratings" on page 22 added · Table "Ordering Information" on page 28 changed U3745BM U3745BM 4663B 4663B­RKE­05/05 Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 Microcontrollers 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3, France Tel: (33) 2-40-18-18-18 Fax: (33) 2-40-18-19-60 ASIC/ASSP/Smart Cards 1150 East Cheyenne Mtn. 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