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TURBO-DECO-XM-U3 Lattice Semiconductor Corporation IP CORE TURBO DECODER XP visit Digikey Buy
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TURBO-DECO-X2-UT3 Lattice Semiconductor Corporation SITE LICENSE TURBO DECODER XP2 visit Digikey Buy
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Turbo decoder Xilinx

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Turbo decoder Xilinx

Abstract: verilog code for floating point adder Package 3GPP Compliant Turbo Convolutional Decoder 3GPP Compliant Turbo Convolutional Encoder 3GPP Turbo Decoder Xilinx Xilinx Xilinx SysOnChip LogiCORE LogiCORE LogiCORE AllianceCORE Viterbi Decoder, Turbo , Encoder TURBO_DEC Turbo Decoder Viterbi Decoder SysOnChip TILAB TILAB Xilinx AllianceCORE , Support (Continued) Function 8b/10b Decoder Vendor Name Xilinx IP Type LogiCORE Key Features Industry std , Error correction, wireless, DVB, Satellite data link DVB-RCS Turbo Decoder iCODING AllianceCORE
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Turbo decoder Xilinx

Abstract: Turbo Decoder from Xilinx. For more information, visit the Turbo Decoder product page. Contact your local Xilinx , 3GPP LTE Turbo Decoder v2.0 XMP020 June 24, 2009 Product Brief Introduction General Description The Turbo Convolution Code (TCC) decoder core is used in conjunction with a TCC encoder to , data reliably over noisy data channels. The turbo decoder operates very well under low signal-tonoise , 3GPP LTE Turbo Decoder v2.0 Performance The performance of the core varies with FPGA family and
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Turbo decoder Xilinx Turbo Decoder lte turbo encoder xilinx lte TURBO decoder LTE Turbo decoder design of lte turbo encoder

Turbo decoder Xilinx

Abstract: CRC lte LTE UL Channel Decoder v2.0 XMP024 June 24, 2009 Product Brief Introduction The Xilinx® LTE UL Channel Decoder core provides designers with an LTE Uplink Channel Decoding block for the 3GPP , Identifier to ensure block synchronization. · Scalable performance of Turbo Decoder and Block Decoder , full license must be obtained from Xilinx. For more information, visit the LTE UL Channel Decoder , ) size according to the configuration parameters. · Decoding - Turbo decoding applied to UL-SCH
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CRC lte LTE uplink TB lte redundancy version automatic repeat request

turbo encoder circuit, VHDL code

Abstract: turbo codes matlab simulation program IEEE 802.16-Compatible Turbo Product Code Decoder v1.1 DS212 June 30, 2008 Product , Synthesis None Support Provided by Xilinx, Inc. Applications The TPC decoder core operates in , IEEE 802.16-Compatible Turbo Product Code Decoder v1.1 Pinout Figure 1 shows the top level , 30, 2008 Product Specification IEEE 802.16-Compatible Turbo Product Code Decoder v1.1 Table 1 , 802.16-Compatible Turbo Product Code Decoder v1.1 Table 2 lists the Hamming code generator polynomials
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turbo encoder circuit, VHDL code turbo codes matlab simulation program turbo codes matlab code 5 to 32 decoder using 38 decoder vhdl code hamming decoder vhdl code Comtech Aha 4501

spartan ucf file 6

Abstract: vhdl code for spartan 6 Xilinx. For more information, visit the IEEE 802.16e CTC Decoder Product Page. Contact your local Xilinx , IEEE 802.16e CTC Decoder v4.0 XMP004 December 2, 2009 Product Brief Introduction 88 Mbps , 802.16e CTC decoder core performs iterative decoding of channel data that has been encoded as described , decoder core is capable of achieving high throughput. The decoded data rate reaches up to 220 Mbps with , Xilinx Implementation Tools ISE 11.2 Verification ModelSim PE 6.2c Simulation ModelSim
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spartan ucf file 6 vhdl code for spartan 6 vhdl spartan 3a turbo codes using vhdl Puncturing vhdl Spartan 3E VHDL code

software defined radio

Abstract: turbo encoder simulink of the Turbo Decoder 7.4% of XC2V6000 2811 slices 4 Block RAMs tools. The Filter silicon. This , /dsp/. and a Turbo Codec. reduces power consumption. Turbo Decoder Turbo Decoder Viterbi Dec. Turbo Decoder Turbo Decoder Viterbi Dec. Viterbi Dec. Viterbi Dec. Fall/Winter 2001 Xcell Journal 83 , parallel architecture within Turbo Encoder the device. Flexibility One of the key aspects of an SDR , . Xilinx also offers a complete solution for general DSP development and has made significant advances to
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software defined radio turbo encoder simulink functions of multiplier and how it can be developed turbo fec viterbi

turbo encoder model simulink

Abstract: xilinx TURBO decoder Xilinx 3GPP Turbo Encoder and Decoder cores is incorporated into a System Generator design to provide , , logic gates, etc.) and custom blocks, such as the Xilinx Turbo encoder and decoder. Figure 2 shows that , Xilinx Turbo encoder or decoder data sheets for more details (provided within the ZIP file associated , Xilinx Turbo Encoder or Decoder is required, the design must be re-synthesized. This section describes , . Create the Xilinx Turbo encoder and decoder hardware design files. The encoder and decoder are brought
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XAPP948 ML402 turbo encoder model simulink xilinx TURBO decoder FER performance of the Turbo code matlab code turbo encoder design using xilinx vhdl code for siso shift register

vhdl code for DES algorithm

Abstract: XAPP921c Reed-Solomon Decoder 4 Reed-Solomon Encoder 4 Turbo Convolutional Code Decoder, CDMA2000/3GPP2 4 Turbo Convolutional Code Encoder, CDMA2000/3GPP2 4 UMTS/3GPP Turbo Convolutional Decoder , Design Tool and comes with an extensive library of Xilinx LogiCORE IP. Reed Solomon Decoder (MC-XIL-RSDEC) 4 Avnet Reed Solomon Encoder (MC-XIL-RSENC) 4 Avnet Turbo Decoder, 3GPP 4 SysOnChip, Inc. Turbo Decoder, 3GPP (S3000) 4 iCoding Technology, Inc. Turbo Decoder, DVB-RCS
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vhdl code for DES algorithm XAPP921c FLOATING POINT PROCESSOR TMSC6000 pulse compression radar fir filter matlab code LMS adaptive filter simulink model XILINX vhdl code REED SOLOMON encoder decoder

verilog code for 2-d discrete wavelet transform

Abstract: XAPP921c Interleaver / De-interleaver Reed-Solomon Decoder Reed-Solomon Encoder Turbo Convolutional Code Decoder, CDMA2000/3GPP2 Turbo Convolutional Code Encoder, CDMA2000/3GPP2 UMTS/3GPP Turbo Convolutional Decoder UMTS/3GPP Turbo Convolutional Encoder IEEE 802.16 TPC , Solomon Decoder (MC-XIL-RSDEC) Avnet Reed Solomon Encoder (MC-XIL-RSENC) Avnet Turbo Decoder, 3GPP SysOnChip, Inc. Turbo Decoder, 3GPP (S3000) iCoding Technology, Inc
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verilog code for 2-d discrete wavelet transform simulink universal MOTOR in matlab matched filter simulink simulink model for kalman filter using vhdl fpga based wireless jamming networks umts simulink

xilinx TURBO decoder

Abstract: DS275 The data into the DIN port of the Turbo Decoder core must be generated using the Xilinx TCC Encoder , 0 3GPP2 Turbo Decoder v1.0 DS275 April 28, 2005 0 Product Specification 0 Features , data storage · To be used with Xilinx CORE GeneratorTM system v7.1i The TCC decoder is used in , data channels. The turbo decoder core operates very well under low-signal to noise conditions and , Log MAP Turbo Decoder, describes this approach in greater detail. www.xilinx.com DS275 April 28
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Turbo Code LogiCORE IP License Terms XC2V500 XC2VP20 RSC11

vhdl code for ethernet mac spartan 3

Abstract: vhdl code for ethernet mac lite spartan 3 Decoder (IP only, no HW) LogiCORE Reed-Solomon Encoder (IP only , no HW) LogiCORE, Turbo Convolutional Decoder, CDMA2000/3GPP2 LogiCORE, Turbo Convolutional Encoder, CDMA2000/3GPP2 LogiCORE Turbo Product Code Decoder LogiCORE Turbo Product Code Encoder LogiCORE UART 16450 / 16550 (with OPB CoreConnect , Xilinx (Price List) 30 2004 . R Xilinx * ISE 6.2i ISE WebPack* - , ISE BaseX/MXE Dongle Bundle - ISE BaseX+MTI Xilinx Edition VHDL Simulator Dongle License
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vhdl code for ethernet mac spartan 3 vhdl code for ethernet mac lite spartan 3 rs232 VHDL xc9500 VHDL CODE FOR HDLC controller DO-DI-10GEMAC verilog code for fibre channel

80C31 instruction set

Abstract: xc2s200 pq208 Multiplexer Slice 3G FEC Package 3GPP Compliant Turbo Convolutional Decoder 3GPP Compliant Turbo Convolutional Encoder 3GPP Turbo Decoder 8b/10b Decoder 8b/10b Encoder ADPCM 1024 Channel ADPCM 16 Channel ADPCM 256 , Turbo Decoder Fast Ethernet (10/100 Mbps) MAC Evaluation Board Fast Ethernet (10/100 Mbps) Media Access , Encoder Reed-Solomon Decoder Vendor Name Xilinx Xilinx Xilinx Xilinx sysonchip Xilinx Xilinx Amphion , XF-HDLC Controller SPEEDROUTER Network Processor T1 Deframer T1/E1 Framer Turbo Decoder - 3GPP Turbo
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DO-DI-ADPCM32 DO-DI-ADPCM64 80C31 instruction set xc2s200 pq208 xilinx code for 8-bit serial adder dvb-RCS transmitter XC2S50 driver POS-PHY ATM format CC-201 CC-200 CRC10 CC-130

80C31 instruction set

Abstract: xilinx fifo generator 6.2 Communication & Networking 3G FEC Package 3GPP Compliant Turbo Convolutional Decoder 3GPP Compliant Turbo Convolutional Encoder 3GPP Turbo Decoder 8b/10b Decoder 8b/10b Encoder ADPCM 1024 Channel ADPCM 16 Channel ADPCM , Modulator Core DVB-RCS Turbo Decoder Fast Ethernet (10/100 Mbps) MAC Evaluation Board Fast Ethernet (10/100 , XC2V1000-4 XC4005XL-1 XC4010XL-9 XCV50-6 XC2V40 XCS30-4 Key Features Viterbi Decoder, Turbo Codec , Framer Turbo Decoder - 3GPP Turbo Encoder TURBO_DEC Turbo Decoder UTOPIA Level-2 PHY Side RX Interface
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xilinx fifo generator 6.2 application of 8259 microcontroller design BCD adder pal adder xilinx XC2S150 FG676 dvb-RCS modem CRC32 CC-131 DO-DI-FLX4C16 IMA-32

xilinx vhdl code for floating point square root

Abstract: multiplier accumulator MAC code verilog deep Communication & Networking 3G FEC Package 3GPP Compliant Turbo Convolutional Decoder 3GPP Compliant Turbo Convolutional Encoder Xilinx LogiCORE Viterbi Decoder, Turbo Codec, Convolutional Enc 80% 40 , correction, wireless Xilinx LogiCORE Xilinx LogiCORE 65% 60 XC2V250 3GPP Turbo , switches DVB-RCS Turbo Decoder Flexbus 4 Interface Core, 16-Channel (DO-DI-FLX4C16) Flexbus 4 Interface , Reed-Solomon Decoder Xilinx LogiCORE 40% 98 XC2V250 Std or custom coding, 312 bit symbol
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xilinx vhdl code for floating point square root multiplier accumulator MAC code verilog multi channel UART controller using VHDL vhdl code of 32bit floating point adder verilog code for floating point adder xilinx logicore fifo generator 6.2 XC2V1000 FG456-5

lte turbo encoder

Abstract: its 31567 data sheet Downlink Chip Rate" · "3GPP LTE Turbo Decoder" · "3GPP LTE Turbo Encoder" · "3GPP RACH Preamble Detector" · "3GPP Searcher" · "3GPP Turbo Convolutional Code Decoder" · "3GPP Turbo Convolutional Code Encoder" · "3GPP2 Turbo Convolutional Code Decoder" · "3GPP2 Turbo Convolutional Code Encoder" · "802.16E Convolutional Turbo Code (CTC) Decoder" · "802.16E Convolutional Turbo Code (CTC) Encoder" · , " · "Reed-Solomon Decoder" · "Reed-Solomon Encoder" · "Turbo Product Code (TPC) Decoder" · "Viterbi
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XTP025 its 31567 data sheet LDPC decoder ip core LDPC encoder decoder ip core 24604 dvb-s encoder design with fpga 64B/66B 1000BASE-X

LDPC decoder ip core

Abstract: 33258 Downlink Chip Rate" · "3GPP LTE MIMO Decoder" · "3GPP LTE MIMO Encoder" · "3GPP LTE Turbo Decoder" · , Convolutional Code Decoder" · "3GPP Turbo Convolutional Code Encoder" · "3GPP2 Turbo Convolutional Code Decoder" · "3GPP2 Turbo Convolutional Code Encoder" · "802.16E Convolutional Turbo Code (CTC) Decoder , Factor Reduction" · "Reed-Solomon Decoder" · "Reed-Solomon Encoder" · "Turbo Product Code (TPC , Release Date v2.0 33266 11.3 September 16, 2009 3GPP LTE Turbo Decoder Product Page
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33258 LDPC decoder timing 3GPP LTE MIMO Decoder LDPC encoder 223-28 30291 8B10B

DO-DI-AWGN

Abstract: matlab code for turbo product code Xilinx Additive White Gaussian Noise Core | Silicon Solutions | Design Resources | Services | Documentation | Home : Products & Services : Intellectual Property : Xilinx Turbo Product Code Xilinx , such as Reed-Solomon, Viterbi Decoder,Turbo Convolutional code or Turbo Product code are generated , customers Download the AWGN Xilinx Additive White Gaussian Noise Core q q q q q q q q q , synthesizable with Synplify Pro Incorporate Xilinx Smart-IP Technology for maximum and predictable performance
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DO-DI-AWGN matlab code for turbo product code xilinx silicon device xilinx vhdl code

RTL 8186

Abstract: vhdl code for block interleaver utilization estimate of the IEEE 802.16e CTC decoder core. These estimates are given by the Xilinx ISE , CTC decoder core using the Xilinx ISE 8.1.03i software (PRODUCTION 1.58 2006-02-24, STEPPING level 1). Table 11: IEEE 802.16 CTC Decoder Core Static Timing Results Xilinx FPGA Clock Speed (MHz , addition to the decoder core, the hardware test bench contains an LFSR-based data generator, the Xilinx , 0 IEEE 802.16e CTC Decoder Core DS137 (v2.3) July 11, 2006 0 Product Specification 0
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RTL 8186 vhdl code for block interleaver RTL 8190 32 bit adder vhdl code matlab code for half adder encoder 1387 16-2004/C

matlab codes for wcdma rake receiver

Abstract: 3G HSDPA circuits diagram efforts as a baseline to eventually merge the development efforts into © 2005 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, and other designated brands included herein are trademarks of Xilinx , for voice users encompasses the Viterbi decoder, deinterleaver, and rate matching. Symbol-rate processing for data additionally includes turbo encoding and decoding. Chip-rate processing involves the , requires significant parallel processing and, therefore, is ideally suited for Xilinx FPGA implementation
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matlab codes for wcdma rake receiver 3G HSDPA circuits diagram HSDPA matlab wcdma simulink mimo model simulink hsdpa matlab codes XAPP726

vhdl codes for Return to Zero encoder in fpga

Abstract: rsc Encoder Template The 3GPP2 Turbo Encoder core can be used in conjunction with the Xilinx 3GPP2 Turbo Decoder (available from the Xilinx CORE GeneratorTM system) to provide an extremely effective way of transmitting , Support General Description Provided by Xilinx, Inc @ www.xilinx.com The 3GPP2 Turbo Encoder core , 0 3GPP2 Turbo Encoder v2.0 DS604 April 2, 2007 0 Product Specification 0 Features , -3, Spartan-3E, Spartan-3A/3AN/3A DSP FPGAs Core Specifics · Implements the 3GPP2/CDMA-2000 Turbo
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vhdl codes for Return to Zero encoder in fpga rsc Encoder turbo-code vhdl code for CDMA convolution encoder with interleaver MULT18X18S
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