NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
| Part | Manufacturer | Description | Samples | Ordering |
| TNETA1585PCM | Texas Instruments | ATM traffic management scheduler 160-QFP 0 to 0 | 
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| TNETA1585PGF | Texas Instruments | ATM traffic management scheduler 176-LQFP 0 to 0 |
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| Catalog Datasheet Results | Type | Document Tags |
| Abstract: Preliminary Product Brief JUNE 2001 XeleratorTM T40 Traffic Manager 10-40 Gbps PROGRAMMABLE TRAFFIC MANAGER XeleratorTM T40 Traffic Manager Preliminary Product Brief JUNE 2001 Features , Traffic Manager Preliminary Product Brief JUNE 2001 First 40 Gbps Network Processor Family The , the XeleratorTM T40 Traffic Manager represent a unique offering on the market. The X40 and T40, both , Manager The XeleratorTM T40 is a highly integrated solution, enabling advanced traffic management at 40 ... | Original |
7 pages, |
T40 N ON T40 OC768 OC192 code t40 diode t40 Xelerated datasheet abstract |
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| Abstract: TME-2000 TME-2000 Brief ® INTEGRATED SWITCH AND TRAFFIC MANAGER SUMMARY OF BENEFITS FEATURES · , system integration · Traffic Manager · · · · · · · · · · · markets · Multicast , · 1517-pin FC-BGA · 10W 20-Gbps Traffic Manager on Line Card Line Card Switch Fabric SPI4 , Stand Alone Solutions with FE-1000 FE-1000 The TME-2000 TME-2000 is a pure flow Traffic Manager optimized for a wide , as a 20-Gbps traffic manager. The TME-2000 TME-2000 is also offered as part of a complete system solution ... | Original |
2 pages, |
TME-2000 QE-2000 TME-2000 abstract |
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| Abstract: TME-2000 TME-2000 ® INTEGRATED SWITCH AND TRAFFIC MANAGER SUMMARY OF BENEFITS FEATURES · Bandwidth , Standard interfaces (SPI-4.2 and PCI) for easy system · Traffic Manager · · · · · · · · · · · , · IP DSLAM/GE PON/VPNs · 1517-pin FC-BGA · 10W 20-Gbps Traffic Manager on Line Card Line , FE-1000 FE-1000 The TME-2000 TME-2000 is a Traffic Manager with integrated switching and processing, optimized for a , as either a 20-Gbps fabric interface, or a full-duplex 10-Gbps traffic manager. The TME-2000 TME-2000 is ... | Original |
2 pages, |
TME-2000 fe1000 FE-1000 qe-2000 TME-2000 abstract |
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| Abstract: Processor and Traffic Manager SRAM SRAM SRAM SRAM/ TCAM Applications · Switched Ethernet , GE(GMII) MACs Integrated Traffic Manager · Stream Based Traffic Management · Hardware and Software , Manager Block Diagram 32 64 TCAM I/F(XSC) 32 SRAM XMI (SPU) XSC I/F Traffic , On-Chip debugger : Debug on any hardware system Integrated Traffic Manager · Based on nP3400 , /24/2003 4.4Gbps Integrated Network Processor and Traffic Manager System Diagrams SRAM TCAM ... | Original |
4 pages, |
NP3454 nP3450 MPLS tcam PB3454 PB3454 abstract |
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| Abstract: nP3450 Advanced Product Brief 4.4Gbps Integrated Network Processor and Traffic Manager , FE(SMII) MACs · Integrated GE(TBI/GMII) MACs Integrated Traffic Manager · Stream Based Traffic , ) XSC I/F Traffic Manager And Switch Fabric nPcores 2 Cores @ 400 MHz MACs Switch Interface , Integrated Traffic Manager · Based on nP3400 Per-Stream Queuing Technology AMCC Confidential nP3450 Advanced Product Brief 4.4Gbps Integrated Network Processor and Traffic Manager PB3450 PB3450 / V0.3 / 04/24 ... | Original |
4 pages, |
PB3450 nP3450 TCAM nP3400 PB3450 abstract |
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| Abstract: of Service With Customizable Traffic Managers Altera's Solution Altera's traffic manager provides the benefits of: Future-proofing your traffic manager with the inherent flexibility , functions Scaling to adapt the solution across multiple platforms or cards Altera Traffic Manager Overview Altera has a working 10-Gbps traffic manager solution targeting Stratix® II FPGAs. (See Figure 1 for a schematic.) The inherent programmability of the FPGA allows the traffic manager to be adapted ... | Original |
7 pages, |
Memory Access Scheduler datasheet abstract |
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| Abstract: 4x2488 S/UNI 9953 IP Processor Traffic Manager Traffic Manager IP Processor S/UNI , Ethernet LAN Line Card SFI-4 XSBI Integrated Optics S/UNI 9953 L2/L3 Processor Traffic Manager APS Port (Protect Mate) TT1 Multi-Gbit/s to Terabit Switch Fabric XSBI Traffic Manager L2/L3 Processor 200/300 MSA Optics S/UNI 1x10GE 10 Gigabit Ethernet XAUI Based LAN , Traffic Manager XAUI Traffic Manager L2/L3 Processor S/UNI 1x10GE-X XENPAK Optics 1 X ... | Original |
2 pages, |
PM3392 P802 64b/66b encoder PM3392 abstract |
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| Abstract: 9953 IP Processor Traffic Manager Traffic Manager IP Processor S/UNI 10xGE 10x , Line Card SFI-4 XSBI Integrated Optics S/UNI 9953 L2/L3 Processor Traffic Manager APS Port (Protect Mate) TT1 Multi-Gbit/s to Terabit Switch Fabric XSBI Traffic Manager , Integrated Optics S/UNI 9953 200/300 MSA Optics S/UNI 1x10GE L2/L3 Processor Traffic Manager XAUI Traffic Manager L2/L3 Processor S/UNI 1x10GE-XP XENPAK Optics 1 X OC-192 OC-192 ... | Original |
2 pages, |
XAUI PM3393 PM3393 abstract |
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| Abstract: DROP Traffic Manager (SONET/SDH Level). 11 ADD Traffic Manager , . 13 DROP Traffic Manager (Tributary Level) . 14 ADD Traffic Manager (Tributary Level) . 16 DISCLAIMER , PRELIMINARY ISSUE 1 In the transmit direction, the ADD Traffic Manager transfers the PPP data from the , aligned AC1J1V1 and APL inputs to the SPTX. In the receive direction, the DROP Traffic Manager transfers ... | Original |
21 pages, |
PMC-960725 PM5362 PM5344 PM5343 PM5312 hdlc datasheet abstract |
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| Abstract: gluelessly to AMCC 's nPX5400, nPX5410, nPX5418, and nPX5500 Switch Fabric / Traffic Manager platforms and to , for a Login Account to request access. Products Framer/Mapper nPC1140 nPC1110 Traffic Manager ... | Original |
1 pages, |
GPIF-200 OC-12 GPIF-200 abstract |
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| Abstract | Saved from | Date Saved | File Size | Type | Download |
| Over 1.1 million files (1986-2013): html articles, reference designs, gerber files, chemical content, spice models, programs, code, pricing, images, circuits, parametric data, RoHS data, cross references, pcns, military data, and more. Please note that due to their age, these files do not always format correctly in modern browsers. Disclaimer. |
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| immediately downstream, the logic generates port-specific backpressure to the ingress traffic manager over traffic manager. Figure 4F indicates that the architecture also supports the communication of flow backpressure to the ingress traffic manager with priority-specific information per port. The egress -specific backpressure to all ingress traffic managers. Egress from the priority queues is controlled by the interface, enabling the egress traffic manager to assert priority-based flow control on the scheduling www.datasheetarchive.com/files/xilinx/files/xcell journal articles/xcell_49/xc_mesh49.htm |
Xilinx | 26/04/2004 | 22.44 Kb | HTM | xc_mesh49.htm |
| - - Module : itm_fc.vhd Last Update: - - Project : Mesh Fabric Reference Design - - Description : Ingress Traffic Manager flow control interface. - - Company : Xilinx, Inc. - - Disclaimer : XILINX IS PROVIDING THIS DESIGN, CODE, OR - INFORMATION "AS IS" SOLELY FOR USE www.datasheetarchive.com/download/66124278-995866ZC/mfrd_source_code.zip (itm_fc.vhd) |
Xilinx | 11/11/2004 | 958.87 Kb | ZIP | mfrd_source_code.zip |
| - - Module : itm_if.vhd Last Update: - - Project : Mesh Fabric Reference Design - - Description : Ingress Traffic Manager interface - - Company : Xilinx, Inc. - - Disclaimer : XILINX IS PROVIDING THIS DESIGN, CODE, OR - INFORMATION "AS IS" SOLELY FOR USE www.datasheetarchive.com/download/66124278-995866ZC/mfrd_source_code.zip (itm_if.vhd) |
Xilinx | 11/11/2004 | 958.87 Kb | ZIP | mfrd_source_code.zip |
| - - Description : Interface to the Egress Traffic Manager downstream - FPGA. This approach should yield the same affect for traffic shaping, but only over 10s to 100s number of cells since the FIFO is a single channel. - This means, at the start of a traffic burst, lower ); end generate; - retiming buffer for local loopback traffic raw_retime_d www.datasheetarchive.com/download/66124278-995866ZC/mfrd_source_code.zip (etm_if.vhd) |
Xilinx | 11/11/2004 | 958.87 Kb | ZIP | mfrd_source_code.zip |
| - - Module : itm_fifo_per_pair.vhd Last Update: - - Project : Mesh Fabric Reference Design - - Description : Ingress Traffic Manager FIFO, which gets instantiated - one instance for every pair of SERDES on a side. - - Company : Xilinx, Inc. - - Disclaimer : XILINX IS PROVIDING THIS DESIGN, CODE, OR - INFORMATION "AS IS" SOLELY FOR USE www.datasheetarchive.com/download/66124278-995866ZC/mfrd_source_code.zip (itm_fifo_per_pair.vhd) |
Xilinx | 11/11/2004 | 958.87 Kb | ZIP | mfrd_source_code.zip |
| data transport portion of the WinSock 2 DLL is to serve as a sort of "traffic manager" between service and performing this automatic traffic routing function, the WinSock 2 DLL allows applications to the appropriate service provider. In addition to its major "traffic routing" service, the WinSock 2 -level traffic management that interconnects these transport protocols with applications. Applications in turn provide the policy of how these traffic streams and network-specific operations are used to accomplish the www.datasheetarchive.com/download/27770108-250121ZC/ws2docs.zip (WSSPI22.DOC) |
Intel | 20/06/1997 | 624.83 Kb | ZIP | ws2docs.zip |
| data transport portion of the WinSock 2 DLL is to serve as a sort of "traffic manager" between service and performing this automatic traffic routing function, the WinSock 2 DLL allows applications to the appropriate service provider. In addition to its major "traffic routing" service, the WinSock 2 -level traffic management that interconnects these transport protocols with applications. Applications in turn provide the policy of how these traffic streams and network-specific operations are used to accomplish the www.datasheetarchive.com/download/51670909-250124ZC/wsspi22.doc |
Intel | 20/06/1997 | 1096.5 Kb | DOC | wsspi22.doc |
| QA - Texas Instruments TMS320AV7000 TMS320AV7000 TMS320AV7000 TMS320AV7000 Traffic Interface Manager (TIM) Reduces System Cost by Backgrounder TMS320AV7000 TMS320AV7000 TMS320AV7000 TMS320AV7000 Traffic Interface Manager (TIM) Reduces System Cost by Achieving Highest Level of Texas Instruments TMS320AV7000 TMS320AV7000 TMS320AV7000 TMS320AV7000 Traffic Interface Manager (TIM) Reduces System Cost by Achieving Highest Traffic Interface Manager Through the development of the Traffic Interface Manager (TIM) in the TMS name implies, the TIM controls the traffic around each of these AV7000 AV7000 AV7000 AV7000 cores by monitoring their peak www.datasheetarchive.com/files/texas-instruments/sc/docs/news/1996/96065a.htm |
Texas Instruments | 08/01/1997 | 8.82 Kb | HTM | 96065a.htm |
| Manager, North American Distribution 267 kbaker@plxtech.com Banneck, Jim Manager, Asia Pacific Area Sales 243 jbanneck@plxtech.com Best, Simon Manager, European Area Sales sbest@plxtech.com Easley, Mark VP @plxtech.com Le, Bryan Manager, Technical Support 242 ble@plxtech.com Miller, Jeff Manager, Western Area Sales 204 jmiller@plxtech.com Parker www.datasheetarchive.com/files/scantec/plx/sales/sales_hq.htm |
Scantec | 22/05/1998 | 11.41 Kb | HTM | sales_hq.htm |
| Forum UNI 3.1 compliant device Enables traffic flow control in ATM switches Protects the network -performance ATM switching and security products, National's device enables effective traffic control in ATM networks by "policing" cell traffic at the input ports of switches. GTE Network Systems, headquartered in regulating the inbound traffic to an ATM switch. It ensures that a given customer connection doesn't violate its negotiated traffic contract by using more resources than it is entitled to and will also prevent www.datasheetarchive.com/files/national/docs/wcd00038/wcd03866.htm |
National | 03/04/1998 | 6.03 Kb | HTM | wcd03866.htm |