E123MUX TXC-03361 E12/E23 TXC-03361-MB O-151 E12TCKO3 E12TD3 E12TCKI3 E1TCK12 - Datasheet Archive

 

E1/E2/E3 MUX/DEMUX TXC-03361 DATA SHEET FEATURES DESCRIPTION · E1 (2048 kbit/s) multiplexer/demultiplexer for ITU-T

 

E123MUX E123MUX Device E1/E2/E3 MUX/DEMUX TXC-03361 TXC-03361 DATA SHEET FEATURES DESCRIPTION · E1 (2048 kbit/s) multiplexer/demultiplexer for ITU-T Recommendations: G.742 (8448 kbit/s E2 frame format) G.751 (34368 kbit/s E3 frame format) The E123MUX E123MUX is a CMOS VLSI device that provides the E13 functions needed to multiplex and demultiplex 16 independent E1 signals to and from an E3 signal that conforms to the ITU-T G.751 Recommendation. The E1 and E3 signal interfaces can be either dual unipolar (rail) or NRZ. Digital phase-locked loop circuits are provided for the received E1 signals, but they may be bypassed. · Multiplexer/demultiplexer converts: 16 E1s to/from 1 E3 (E13 skip mux), or 16 E1s to/from 4 E2s, or 4 E2s to/from 1 E3 (E12/E23 E12/E23 split mux) The E123MUX E123MUX can also be configured to operate as an E12 or E23 multiplexer and demultiplexer. Sixteen E1 signals can be multiplexed and demultiplexed to and from four E2 signals that conform to the ITU-T G.742 Recommendation. Alternatively, four E2 signals can multiplexed and demultiplexed to and from one E3 signal. The E2 signal interfaces are NRZ only. The E123MUX E123MUX uses memory locations for setting control bits and reporting status information. The status bits have maskable interrupt control bits. · Counters for bipolar violations, frame errors and loss of frame conditions · E1 digital phase-locked loop circuits with bypass option · Test features: PRBS generator and analyzer for E1 channels Local/Remote Loopbacks for E1, E2 or E3 channels Corrupt frame generation for E2 and E3 frames · E2 and E3 bit error rate indications APPLICATIONS · E1 and E3 line side interfaces are selectable as positive and negative rail or NRZ with external loss of signal indication on negative input pin. · Single-board E13 multiplexer · Microprocessor input/output bus provides multiplexed, Intel or Motorola interfaces · DCS and EDSX systems · Compact add/drop multiplexer · CSU/DSU equipment · Test access port for boundary scan · Single +5 volt, ±5 % power supply · 208-pin plastic quad flat package +5V LINE SIDE E3 Clock & Data E2 Clock & Data (x 4 channels) Receive Transmit Receive Transmit TERMINAL SIDE 3 E123MUX E123MUX 3 3 3 E1/E2/E3 MUX/DEMUX 2 2 2 TXC-03361 TXC-03361 24 4 Test Microprocessor Interface Access Port selection and I/O bus Receive E1 Clock & Data Transmit (x 16 channels) 2 Receive E2 Clock & Data (x 4 channels) Transmit 5 Control and clock inputs Copyright 1999 TranSwitch Corporation and ATL E123MUX E123MUX is a trademark of TranSwitch Corporation TranSwitch and TXC are registered trademarks of TranSwitch Corporation TranSwitch Corporation · 3 Enterprise Drive · Shelton, Connecticut 06484 Tel: 203-929-8810 · Fax: 203-926-9453 · www.transwitch.com Document Number: TXC-03361-MB TXC-03361-MB Ed. 5, September 1999 · USA E123MUX E123MUX TXC-03361 TXC-03361 DATA SHEET TABLE OF CONTENTS Section Page Block Diagram . 3 Block Diagram Description . 4 Pin Diagram . 6 Pin Descriptions . 7 Absolute Maximum Ratings and Environmental Limitations . 16 Thermal Characteristics . 16 Power Requirements . 16 Input, Output and I/O Parameters . 17 Timing Characteristics . 19 Operation . 36-44 Test Access Port . 36 Initialization Sequence . 38 Sample Configurations . 42 Alarm and Interrupt Indications . 44 Throughput Delays . 44 Memory Map . 45 Memory Map Descriptions . 51 Package Information . 77 Ordering Information . 78 Related Products . 78 Standards Documentation Sources . 79 List of Data Sheet Changes . 81 Documentation Update Registration Form* . 85 * Please note that TranSwitch provides documentation for all of its products. Customers who are using a TranSwitch Product, or planning to do so, should register with the TranSwitch Marketing Department to receive relevant updated and supplemental documentation as it is issued. They should also contact the Applications Engineering Department to ensure that they are provided with the latest available information about the product, especially before undertaking development of new designs incorporating the product. LIST OF FIGURES Figure 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. Page E123MUX E123MUX TXC-03361 TXC-03361 Block Diagram . 3 E123MUX E123MUX TXC-03361 TXC-03361 Pin Diagram . 6 E1 Transmit Input Interface Timing . 19 E12 Transmit Output Interface Timing . 20 E23 Transmit Input Interface Timing . 21 E3 Transmit Output Interface Timing . 22 E3 Receive Input Interface Timing . 23 E23 Receive Output Interface Timing . 24 E12 Receive Input Interface Timing . 25 E1 Receive Output Interface Timing - PLL Enabled . 26 E1 Receive Output Interface Timing - PLL Bypassed . 27 External Clocks Interface Timing . 28 Boundary Scan Timing . 29 Multiplex Mode - Microprocessor Read Cycle Timing . 30 Multiplex Mode - Microprocessor Write Cycle Timing . 31 Intel Mode - Microprocessor Read Cycle Timing . 32 Intel Mode - Microprocessor Write Cycle Timing . 33 Motorola Mode - Microprocessor Read Cycle Timing . 34 Motorola Mode - Microprocessor Write Cycle Timing . 35 Boundary Scan Schematic . 37 E123MUX E123MUX TXC-03361 TXC-03361 208-pin Plastic Quad Flat Package . 77 -2- TXC-03361-MB TXC-03361-MB Ed. 5, September 1999 E123MUX E123MUX TXC-03361 TXC-03361 DATA SHEET BLOCK DIAGRAM E12TCKIm (8448 kHz) Clock E1 to E2 Multiplexer (Four) Ch 1 Ch 1 E1 E1 Mux E1TDPn/E1TNRZn E1 Mux E2 Mux E2 Mux FIFO Ch 2 HDB3, LOS Ch 3 E1TCKn E2 Data and Clock E12 E3TDP/E3TNRZ Ch 2 Ch 3 E12TDm/ E23TDm E12TCKOm/ E23TCKm (m = 1-4) Internal Clock E2 Ch 1 FIFO I/O Block Mux Ch 4 (n = 1 - 16) Ch 1 Ch 1 I/O E1TDNn/E1LOSn E2 to E3 Multiplexer Ch 1 E3 Mux I/O HDB3 E23 Mux E3TDN E3TCKO E3TCKI Ch 4 Internal Clock Frame Pattern Alarm Bit National Bit AIS GEN Frame Pattern Alarm Bit National Bit AIS GEN E2AISC 3 Transmit Mux 2-4 Alarms, Control, Overhead Bits Microprocessor Block Microprocessor Interface Receive E2 to E1 Demultiplexer (Four) Ch 1 E3 to E2 Demultiplexer Ch 1 Ch 1 Ch 1 E2 E2 Demux FIFO E1 E1RDPn/E1RNRZn E1RDNn E1 Demux I/O HDB3 E1 Demux FIFO E2 Ch 1 E2 Data and Clock Ch 2 Demux Ch 4 E1RCKn (n = 1 - 16) E12RDm/ E23RDm E12RCKm/ E23RCKm/ E23RGCm (m = 1-4) E32 Ch 3 HDB3 Demux Ch 4 DPLL Block E3RDP/E3RNRZ E3RDN/E3LOS E3RCKI Clock System Clock XCLK E3 Demux I/O HDB3 LOS Ch 2 Demux I/O E21 Ch 3 Ch 1 Clock Frame SYNC Alarm Bit National Bit AIS Detector Frame SYNC Alarm Bit National Bit AIS Detector Note: Test Access Port block and Microprocessor Interface lead details are not shown. Please refer to Pin Descriptions section. Figure 1. E123MUX E123MUX TXC-03361 TXC-03361 Block Diagram -3- TXC-03361-MB TXC-03361-MB Ed. 5, September 1999 DATA SHEET E123MUX E123MUX TXC-03361 TXC-03361 BLOCK DIAGRAM DESCRIPTION Figure 1 shows a simplified block diagram of the E123MUX E123MUX and its signal leads. In the transmit direction (multiplexer direction), the E123MUX E123MUX multiplexes 16 independent asynchronous E1 signals operating at 2048 kbit/s into four separate E2 signals operating at 8448 kbit/s. The E1 transmit signal inputs can be in either the dual rail unipolar HDB3 format (E1TDPn and E1TDNn) or in the NRZ format (E1TNRZn). The rail/NRZ interface selection is common to both the multiplexer and demultiplexer sections of the chip. The clock edge for clocking in the data is programmable for either clock (E1TCKn) edge. When the rail interface is selected, the E1 rail signal interface is monitored for loss of signal using the detect and recovery requirements specified in ITU-T Recommendation G.775. Loss of signal status information is provided along with a maskable interrupt. In addition, bipolar violations (BPVs) are counted in 16-bit counters provided for each of the E1 channels. When the NRZ interface is selected for an E1 channel, an external loss of signal indication from the external line interface unit can also be provided as an input to the E123MUX E123MUX on the lead designated as E1TDNn/E1LOSn, to provide status information and a maskable interrupt for the microprocessor. Four E1 framed or unframed asynchronous channels operating at 2048 kbit/s are multiplexed into one E2 signal, using the frame format specified in ITU-T recommendation G.742. The G.742 format consists of the 848 bits, starting with bit 1 in the frame alignment. The frame alignment pattern is defined as 1111010000. Bit 11 is defined as a remote alarm, and bit 12 is defined as a spare bit. The remaining bits carry tributary bits and justification control bits. The four E12 multiplexers are numbered 1 through 4. Microprocessor access is provided in the transmit direction in each of the four E1 frame formats for controlling the states of the remote alarm indication bit (bit 11) and the spare bit (bit 12). Continuous framing errors may also be inserted into each of four frame formats. The output of the four E12 multiplexers is connected internally to the E23 multiplexer section when the device is configured for E13 operation. The E2 multiplexed data and clock for the four E12 channels is not provided as an interface in this mode. However, an external 8448 kHz clock is required to be connected to the E12TCKIm input for clocking data out from the E12 multiplexer. The E23 section multiplexes each of the four E2 frames into a single E3 signal using the format specified in ITU-T recommendation G.751. The G.751 format consists of the 1536 bits, starting with bit 1 in the frame alignment. The frame alignment pattern is defined as 1111010000. Bit 11 is defined as a remote alarm, and bit 12 is defined as a spare bit. The remaining bits carry tributary bits and justification control bits. A 34368 kHz input clock (E3TCKI) is used to derive the output E3 clock (E3TCKO), which is used to clock out the E3 data. Microprocessor access is provided for controlling the states of the remote alarm indication bit (bit 11) and the spare bit (bit 12) in the E3 frame format. Continuous framing errors may also be inserted into the frame format. The output of the E23 multiplexer can be configured to be either a dual unipolar HDB3 signal or an NRZ signal. The control bit for selecting the HDB3 or NRZ format is common to the demultiplexer (receive direction). Data (E3TDP/E3TNRZ and E3TDN) is clocked out of the E123MUX E123MUX using the E3 clock (E3TCKO) signal, which is derived from the E3 input clock (E3TCKI). A control bit is provided for clocking out the data on either clock edge. In the receive direction (demultiplexed direction) from the E3 line, HDB3 or NRZ data (E3RDP/E3RNRZ and E3RDN/E3LOS) is clocked into the E123MUX E123MUX using the E3 clock (E3RCKI) signal. The clock edge employed can be programmed using the microprocessor. The E23 demultiplexer monitors the incoming signal for loss of signal using the requirements specified in ITU-T recommendation G.775. Bipolar violations are counted in a 16-bit counter. In addition, the E123MUX E123MUX detects frame alignment using the requirements specified in the G.751 recommendation, and monitors the line signal for AIS. Besides providing status bits for LOS, AIS, and LOF, both framing errors and loss of frame events are counted in 8-bit counters. The status bits have maskable interrupt control bits for enabling and disabling the interrupt for the microprocessor. The remote alarm bit (bit 11), and the national bit (bit 12) in the frame format are monitored for status. A threshold detector is provided for a bit error rate (BER) measurement. The E3 signal is demultiplexed into four E2 signals, which pass through 32-bit FIFOs at the output. When the device is configured as an E13 multiplexer/demultiplexer, the four E2 signals are connected internally to the four E12 demultiplexers. However, the four E23RGCm Clock outputs must be physically connected -4- TXC-03361-MB TXC-03361-MB Ed. 5, September 1999 DATA SHEET E123MUX E123MUX TXC-03361 TXC-03361 to E23RCKm clock inputs for proper operation in E13 mode. The E2 signals are available for monitoring using the data lead E23RDm and gapped clock lead. Each of the four E2 signals is monitored for frame alignment and AIS, which are provided with status bits and maskable interrupt control bits. The states of the remote alarm bit (bit 11) and national bit (bit 12) in each of the four E2 frames are provided as status bits with associated maskable interrupts. A threshold detector is provided for a bit error rate (BER) measurement. Each of the E12s demultiplexes the E2 frame into four E1 signals. The data is written into 32-bit FIFOs using the internal gapped clock. Each E1 channel has an internal digital phase-locked loop circuit (DPLL). The receive gapped clock is connected to the digital phase-locked loop circuit as the reference frequency, along with the 34368 kHz external system clock (XCLK). The output of the DPLL is used to clock the data from the E1 receive FIFO, and is also provided as an output (E1RCKn). The E1 DPLLs require approximately 1 second of settling time after they are enabled to ensure proper operation of E1 FIFOs. Under microprocessor control, either clock edge may be used to clock out the data (E1RDPn/ E1RNRZn and E1RDNn). The E123MUX E123MUX can also be configured into hybrid configurations. That is, the device can be configured to provide four E12 multiplexers and demultiplexers (16 E1 channels to/from four E2 channels), and one E23 multiplexer and demultiplexer (four E2 channels to/from one E3 channel). In this configuration, the format of the data from the four multiplexers and demultiplexers at the E2 level is NRZ only. In the multiplex direction, the data (E12TDm) from the four sections is clocked out by the E2 clocks (E12TCKOm). The NRZ data input (E23TDn) to the E23 multiplexer is clocked in by the E2 clocks (E23TCKm). The clock edges used for clocking in and out data from the E23 section are programmable. In the demultiplex direction, four E23 gapped output clocks are provided on leads E23RGCm. E2 data (E23RDm) is clocked out of the internal FIFO by the receive input clock (E23RCKm). It is assumed that external DPLLs will be used in this configuration to provide a symmetrical clock, and that the outputs of the DPLLs are connected to the E23RCKm leads for E2 operation. The receive data input to the four E12 demultiplexers consists of data (E12RDm) and clock (E12RCKm). If an E23 demultiplexer is connected to the E12 demultiplexer to provide E3 to E1 demultiplexing, the E23 receive gapped clock lead (E23RGCm) is connected to the E23 receive input clock (E23RCKm) and the E12 receive input clock (E12RCKm). The E23 data leads (E23RDm) are connected to the E12 receive data leads (E12RDm). The clock edges used for clocking data into and out of the E12 sections are programmable. The E123MUX E123MUX provides a number of testing features, including an E1 PRBS generator and analyzer. The PRBS sequence is a 215-1 polynomial, and the sequence corresponds to the sequence specified in the ITU-T O-151 O-151 recommendation. The E1 transmit channel to be used for inserting the PRBS pattern is programmable. The E1 receive channel to be analyzed is also programmable, and is independent of the channel selected in the transmit direction. Only one channel at a time is programmable for PRBS testing in each direction. The E123MUX E123MUX also supports individual E1 remote loopbacks, E2 local and remote loopbacks, and E3 local and remote loopbacks. Remote loopback enables the receive clock and data leads to be looped back as transmit clock and data in the upstream direction. For device testing, both boundary scan and an option to force all bidirectional outputs to a high impedance state for board testing are provided. The microprocessor interface supports a multiplexed 8-bit address/data bus, an Intel-compatible split bus or a Motorola-compatible split bus. The split bus has 8 address bits and 8 data bits. Interrupt capability is also provided, with the ability to mask an active alarm status from causing an interrupt. -5- TXC-03361-MB TXC-03361-MB Ed. 5, September 1999 E123MUX E123MUX TXC-03361 TXC-03361 DATA SHEET 105 110 115 120 125 130 135 140 145 150 160 100 165 95 170 90 175 85 E123MUX E123MUX 180 TXC-03361 TXC-03361 80 Pin Diagram 185 75 (Top View) 190 70 195 65 200 60 205 50 45 40 35 30 25 20 15 10 RD- (RD- / RD/WR-) WR- (WR- / DS-) TDO TRSTCK TDI TMS TESTDATA TESTCK A0 A1 A2 A3 A4 A5 A6 A7 VDD GND GND A/D0 (D0) A/D1 (D1) A/D2 (D2) A/D3 (D3) A/D4 (D4) A/D5 (D5) A/D6 (D6) A/D7 (D7) GND GND VDD VDD XCLK SEL- (SEL-) RESETTESTHIGHZMP1 MP0 INT (INT/IRQ-) VDD GND E12TCKO3 E12TCKO3 E12TD3 E12TD3 E12TCKI3 E12TCKI3 E1TCK12 E1TCK12 E1TDN12 E1TDN12 E1TDP12 E1TDP12 E1TCK11 E1TCK11 E1TDN11 E1TDN11 E1TDP11 E1TDP11 E1TCK10 E1TCK10 E1TDP1 E1TDN1 E1TCK1 E1TDP2 E1TDN2 E1TCK2 E1TDP3 E1TDN3 E1TCK3 E1TDP4 E1TDN4 E1TCK4 GND VDD E12TCKI1 E12TCKI1 E12TD1 E12TD1 E12TCKO1 E12TCKO1 E23TD1 E23TD1 E23TCK1 E23TCK1 E23TD2 E23TD2 E23TCK2 E23TCK2 E23TD3 E23TD3 E23TCK3 E23TCK3 E23TD4 E23TD4 E23TCK4 E23TCK4 GND VDD E3TDP/E3TNRZ E3TDN E3TCKI E3TCKO GND E1TDP5 E1TDN5 E1TCK5 E1TDP6 E1TDN6 E1TCK6 E1TDP7 E1TDN7 E1TCK7 E1TDP8 E1TDN8 E1TCK8 E12TCKI2 E12TCKI2 E12TD2 E12TD2 E12TCKO2 E12TCKO2 E1TDP9 E1TDN9 E1TCK9 E1TDP10 E1TDP10 E1TDN10 E1TDN10 5 55 1 E12RD1 E12RD1 E12RCK1 E12RCK1 E1RDP9 E1RDN9 E1RCK9 E1RDP10 E1RDP10 E1RDN10 E1RDN10 E1RCK10 E1RCK10 E1RDP11 E1RDP11 E1RDN11 E1RDN11 E1RCK11 E1RCK11 E1RDP12 E1RDP12 E1RDN12 E1RDN12 E1RCK12 E1RCK12 E12RD3 E12RD3 E12RCK3 E12RCK3 GND VDD E1RDP13 E1RDP13 E1RDN13 E1RDN13 E1RCK13 E1RCK13 E1RDP14 E1RDP14 E1RDN14 E1RDN14 E1RCK14 E1RCK14 VDD VDD GND GND E1RDP15 E1RDP15 E1RDN15 E1RDN15 E1RCK15 E1RCK15 E1RDP16 E1RDP16 E1RDN16 E1RDN16 E1RCK16 E1RCK16 E12RD4 E12RD4 E12RCK4 E12RCK4 GND E1TDP13 E1TDP13 E1TDN13 E1TDN13 E1TCK13 E1TCK13 E1TDP14 E1TDP14 E1TDN14 E1TDN14 E1TCK14 E1TCK14 E1TDP15 E1TDP15 E1TDN15 E1TDN15 E1TCK15 E1TCK15 E1TDP16 E1TDP16 E1TDN16 E1TDN16 E1TCK16 E1TCK16 E12TCKI4 E12TCKI4 E12TD4 E12TD4 E12TCKO4 E12TCKO4 155 E1RCK4 E1RDN4 E1RDP4 E1RCK3 E1RDN3 E1RDP3 E1RCK2 E1RDN2 E1RDP2 E1RCK1 E1RDN1 E1RDP1 E2AISC GND GND E3RDN/E3LOS E3RDP/E3RNRZ E3RCKI GND GND VDD VDD E23RGC4 E23RGC4 E23RCK4 E23RCK4 E23RD4 E23RD4 E23RGC3 E23RGC3 E23RCK3 E23RCK3 E23RD3 E23RD3 E23RGC2 E23RGC2 E23RCK2 E23RCK2 E23RD2 E23RD2 E23RGC1 E23RGC1 E23RCK1 E23RCK1 E23RD1 E23RD1 GND VDD E12RCK2 E12RCK2 E12RD2 E12RD2 E1RCK8 E1RDN8 E1RDP8 E1RCK7 E1RDN7 E1RDP7 E1RCK6 E1RDN6 E1RDP6 E1RCK5 E1RDN5 E1RDP5 RDY (RDY/DTACK-) ALE PIN DIAGRAM Notes: 1. An X(Y/Z) format is used for symbol names of microprocessor interface signal pins to identify pin functions in the Multiplexed Address/Data [X] and (Intel [Y] / Motorola [Z]) modes of operation, where these functions are different. 2. Active low (inverted) signals are indicated by '-' at end of symbol (e.g., RESET- is equivalent to RESET). 3. Some pin symbols have been abbreviated due to space limitations (see Pin Descriptions section for complete symbols). Figure 2. E123MUX E123MUX TXC-03361 TXC-03361 Pin Diagram -6- TXC-03361-MB TXC-03361-MB Ed. 5, September 1999 E123MUX E123MUX TXC-03361 TXC-03361 DATA SHEET PIN DESCRIPTIONS POWER SUPPLY AND GROUND Symbol Pin No. I/O/P* Type Name/Function VDD 14, 27, 64, 73, 74, 87, 121, 135, 136, 174, 181, 182 P VDD: +5 volt supply voltage, ± 5%. GND 13, 26, 32, 63, 75, 76, 85, 86, 122, 137, 138, 142, 143, 173, 183, 184, 193 P Ground: 0 volts reference *Note: I = Input; O = Output; P = Power; T = Tri-state; D = Open Drain Tri-state E1 RECEIVE AND TRANSMIT INTERFACES Symbol Pin No. I/O/P Type * Name/Function E1RDPn/ E1RNRZn (n = 1 - 16) n=4 -> 145 148 151 154 107 110 113 116 159 162 165 168 175 178 185 188 O CMOS 2 mA Receive Positive Rail/NRZ Output, E1 Channels 1 - 16: These pins are used for output of the receive positive rail HDB3 signal, or the receive NRZ signal, for E1 channels 1 through 16. Dual rail unipolar or NRZ mode may be selected for each channel independently, by setting 16 control bits. Pin 145 represents the output signal for E1 channel 1, while pin 188 represents channel 16. The positive rail or NRZ signals for all 16 ports are clocked out of the E123MUX E123MUX on rising edges of the receive clocks E1RCKn when control bit RE1CS is a 1, and on falling edges of the clocks when the control bit is set to 0. 146 149 152 155 108 111 114 117 160 163 166 169 176 179 186 189 O CMOS 2 mA Receive Negative Rail Output, E1 Channels 1 - 16: These pins are used for the receive negative rail HDB3 signal outputs for E1 channels 1 through 16. Pin 146 represents the negative rail signal for E1 channel 1, while pin 189 represents channel 16. The negative rail signals for all 16 ports are clocked out of the E123MUX E123MUX on rising edges of the receive clocks E1RCKn when control bit RE1CS is a 1, and on falling edges of the clocks when this control bit is set to 0. This pin is disabled when the NRZ mode is selected for a channel. n=8 -> n=12 -> n=16 -> E1RDNn (n = 1 - 16) n=4 -> n=8 -> n=12 -> n=16 -> *See Input, Output and I/O Parameters section below for Type definitions. -7- TXC-03361-MB TXC-03361-MB Ed. 5, September 1999 E123MUX E123MUX TXC-03361 TXC-03361 DATA SHEET Symbol Pin No. I/O/P Type * Name/Function E1RCKn (n = 1 - 16) 147 150 153 156 109 112 115 118 161 164 167 170 177 180 187 190 O CMOS 2 mA Receive Output Clock, E1 Channels 1 - 16: These pins provide receive output clocks for E1 channels 1 through 16. These clocks are derived from internal DPLLs using the system clock (XCLK) and the internal E1 receive gapped clock. When control bit BPPLLm is a 1 (m = 1 to 4, for n = 1-4, 5-8, 9-12 and 13-16), the DPLL is bypassed and the output is the receive gapped clock. Pin 147 represents channel 1, while pin 190 represents channel 16. 1 4 7 10 33 36 39 42 48 51 54 57 194 197 200 203 I TTL Transmit Positive Rail/NRZ Input, E1 Channels 1 - 16: These pins are used for the transmit positive rail HDB3 signal inputs, or the transmit NRZ signal inputs, for E1 channels 1 through 16. Dual rail unipolar or NRZ mode may be selected for each channel independently by setting 16 control bits. Pin 1 represents the input signal for E1 channel 1, while pin 203 represents channel 16. The positive rail or NRZ signal input for channel n is clocked into the E123MUX E123MUX on rising edges of the transmit clock E1TCKn when control bit TE1CS is a 0, and on falling edges of this clock when this control bit is set to 1. 2 5 8 11 34 37 40 43 49 52 55 58 195 198 201 204 I TTL Transmit Negative Rail Input or Loss of Signal Input, E1 Channels 1 - 16: In the dual rail unipolar operating mode, these pins are used for the transmit negative rail HDB3 signal inputs for E1 channels 1 through 16. Pin 2 represents the input negative rail signal for E1 channel 1, while pin 204 represents channel 16. The negative rail signal for channel n is clocked into the E123MUX E123MUX on rising edges of the transmit clock E1TCKn when control bit TE1CS is a 0, and on falling edges of this clock when this control bit is set to 1. n=4 -> n=8 -> n=12 -> n=16 -> E1TDPn/ E1TNRZn (n = 1 - 16) n=4 -> n=8 -> n=12 -> n=16 -> E1TDNn/ E1LOSn (n = 1 - 16) n=4 -> n=8 -> n=12 -> n=16 -> When the NRZ operating mode is selected for a channel, this pin may be used as the input for an external E1 loss of signal (LOS) indication from an external line interface unit. E1LOSn is active low. Any of these pins that are not used for LOS inputs must be held high. -8- TXC-03361-MB TXC-03361-MB Ed. 5, September 1999 E123MUX E123MUX TXC-03361 TXC-03361 DATA SHEET Symbol Pin No. I/O/P Type * Name/Function E1TCKn (n = 1 - 16) 3 6 9 12 35 38 41 44 50 53 56 59 196 199 202 205 I CMOS Transmit Input Clock, E1 Channels 1 - 16: These pins provide the transmit input clocks for E1 channels 1 through 16. Pin 3 represents channel 1, while pin 205 represents channel 16. The clock frequency must be 2048 kHz ± 50 ppm and the duty cycle must be (50 ± 10) %. n=4 -> n=8 -> n=12 -> n=16 -> E2 RECEIVE AND TRANSMIT INTERFACES (E12 MULTIPLEXERS/DEMULTIPLEXERS 1-4) Symbol Pin No. I/O/P Type Name/Function E12RDm (m = 1 - 4) 157 119 171 191 I TTL Receive E12 Data: These four pins are used for the receive E2 NRZ data input signals when the E123MUX E123MUX is configured as a separate E12 multiplexer/demultiplexer. Pin 157 corresponds to the E12 multiplexer/demultiplexer number 1, which is associated with E1 channels 1 - 4. In the E13 mode of operation these pins are connected internally to the corresponding E23RDm output pins. E12RCKm (m = 1 - 4) 158 120 172 192 I CMOS Receive E12 Clock: These four pins are used to clock in the receive E2 NRZ data signals. Pin 158 corresponds to the E12 multiplexer/demultiplexer number 1. Receive data is clocked into the E123MUX E123MUX on rising edges of this clock. In the E13 mode of operation these pins are connected internally to the corresponding E23RGCm output pins. E12TDm (m = 1 - 4) 16 46 61 207 O CMOS 2 mA Transmit E12 Data: These four pins are used to output the transmit E2 NRZ data signal when the E123MUX E123MUX is configured as a separate E12 multiplexer/demultiplexer. Pin 16 corresponds to the E12 multiplexer number 1, which is associated with E1 channels 1 - 4. In the E13 mode of operation these pins are connected internally to the corresponding E23TDm pins. E12TCKIm (m = 1 - 4) 15 45 60 206 I CMOS Transmit E12 Clock Input: These four pins are used to provide input clocks for clocking out the transmit E2 NRZ data output signals E12TDm and clock signal E12TCKOm. Pin 15 corresponds to the E12 multiplexer/ demultiplexer number 1. Please note that an 8448 kHz clock with a ± 30 ppm tolerance and a duty cycle of (50 ± 10) % must be connected to these pins for proper E12 to E23 operation. -9- TXC-03361-MB TXC-03361-MB Ed. 5, September 1999 E123MUX E123MUX TXC-03361 TXC-03361 DATA SHEET Symbol Pin No. I/O/P Type Name/Function E12TCKOm (m = 1 - 4) 17 47 62 208 O CMOS 2 mA Transmit E12 Clock Output: These four pins are used to provide output clocks for clocking out the transmit E2 NRZ data output signals (E12TDm). Pin 17 corresponds to the E12 multiplexer/demultiplexer number 1. Transmit data is clocked out of the E12 on rising edges of this clock in E13 mode. In E12 skip mux mode this is programmable by control bit T12CSm. In the E13 mode of operation the E12TCKOm signals are connected internally to the corresponding E23TCKm signals. E2 RECEIVE AND TRANSMIT INTERFACES (E23 MULTIPLEXER/DEMULTIPLEXER) Symbol Pin No. I/O/P Type Name/Function E23RDm (m = 1 - 4) 123 126 129 132 O CMOS 2 mA Receive E23 Data: These four pins are used to output the receive E2 NRZ data signals when the E123MUX E123MUX is configured as a separate E23 multiplexer/demultiplexer. Pin 123 corresponds to the E23 demultiplexer E2 output channel number 1. E23RGCm (m = 1 - 4) 125 128 131 134 O CMOS 2 mA Receive Gapped E23 Clock: These four pins provide the receive gapped clock outputs for the E23 demultiplexer when the E123MUX E123MUX is configured for E23 operation. These clocks are the write clocks of an internal FIFO. These clocks may be connected to an external digital PLL if the E123MUX E123MUX is used in hybrid configurations (E12 and E23 sections). The dejittered clock from the digital PLL is connected to the E23RCKm input clocks. This clock is derived from the received E3 34368 kHz clock. Pin 125 represents the output gapped clock for E2 channel 1. Please note that, for E13 operation, the E23RGCm output receive gapped clock leads must be connected to the corresponding E23RCKm input clock leads. E23RCKm (m = 1 - 4) 124 127 130 133 I CMOS Receive Input Clock: These four pins provide the input clocks for clocking out the receive data from the E23 demultiplexer when the E123MUX E123MUX is configured for E23 operation. The receive data is clocked out of an internal FIFO. For hybrid configurations these clocks may be connected to digital PLLs. The NRZ signal for channel m is clocked out of the E23 on rising edges of the E23RCKm clocks when control bit R23CSm is a 1, and on falling edges of this clock when the control bit is set to 0. Pin 124 represents the input clock for E2 channel 1. Please note that, for E13 operation, the E23RCKm input clock leads must be connected to the corresponding E23RGCm output receive gapped clock leads. - 10 - TXC-03361-MB TXC-03361-MB Ed. 5, September 1999 E123MUX E123MUX TXC-03361 TXC-03361 DATA SHEET Symbol Pin No. I/O/P Type Name/Function E23TDm (m = 1 - 4) 18 20 22 24 I TTL Transmit E2 Data: These four pins are used for the transmit E2 NRZ data input signals when the E123MUX E123MUX is configured as an E23 multiplexer/demultiplexer. Pin 18 corresponds to the E23 multiplexer/demultiplexer E2 input channel number 1. When in E13 skip mux mode these input pins are ignored by the internal logic. For E13 operation these unused pins should be attached to a common pull-up resistor. E23TCKm (m = 1 - 4) 19 21 23 25 I CMOS Transmit E2 Clock: These four pins are used to provide input clocks for clocking in the transmit E2 NRZ data input signals when the E123MUX E123MUX is configured for E23 operation. Pin 19 represents the input clock for E23 multiplexer/ demultiplexer E2 input channel number 1. Transmit data is clocked into the E123MUX E123MUX on rising edges of this clock when control bit T23CSm is a 0, and on falling edges of this clock when the control bit is set to 1 for each E23 multiplexer. When in E13 Mode, these input pins are ignored and the clocking is done by internal logic. For E13 Mode, these pins should be attached to a common pull-up resistor. When in E23 Mode, the input clock frequency must be 8448 kHz with ± 30 ppm accuracy and a duty cycle of (50 ± 10) %. E3 RECEIVE AND TRANSMIT INTERFACES Symbol Pin No. I/O/P Type Name/Function E3RDP/ E3RNRZ 140 I TTL Receive E3 Positive Rail/NRZ Input: This pin is used for the receive E3 positive rail HDB3 signal input, or the receive E3 NRZ signal input. E3RDN/ E3LOS 141 I TTL Receive E3 Negative Rail Input/E3 LOS Input: In dual rail unipolar mode, this pin is used for the receive E3 negative rail HDB3 signal input. When the NRZ operating mode is selected, this pin may be used as the input for an active low external E3 loss of signal (LOS) indication from an external line interface unit. If this pin is not used for LOS it must be tied high. E3RCKI 139 I CMOS Receive E3 Clock In: The E3 positive and negative rail signals or the E3 NRZ signal are clocked into the E123MUX E123MUX on rising edges of this clock input signal when control bit RE3CS is a 0, and on falling edges when this control bit is a 1. E3TDP/ E3TNRZ 28 O CMOS 2 mA Transmit E3 Positive Rail/NRZ Output: This pin is used for the transmit E3 positive rail HDB3 signal output, or the transmit NRZ signal output. E3TDN 29 O CMOS 2 mA Transmit E3 Negative Rail Output: This pin is used for the transmit E3 negative rail HDB3 signal output. This lead is disabled when the NRZ mode is selected. - 11 - TXC-03361-MB TXC-03361-MB Ed. 5, September 1999 E123MUX E123MUX TXC-03361 TXC-03361 DATA SHEET Symbol Pin No. I/O/P Type Name/Function E3TCKO 31 O CMOS 2 mA Transmit E3 Clock Output: The E3 positive and negative rail signals or the E3 NRZ signal are clocked out of the E123MUX E123MUX on rising edges of this clock when control bit TE3CS is a 1, and on falling edges when this control bit is a 0. E3TCKO is derived from E3TCKI. E3TCKI 30 I CMOS Transmit E3 Clock Input: This input clock frequency must be 34368 kHz ± 20 ppm and the duty cycle must be (50 ± 5) %. EXTERNAL CLOCK INPUTS Symbol Pin No. I/O/P Type Name/Function XCLK 72 I CMOS External Clock: A 34368 kHz clock with ± 20 ppm accuracy and a duty cycle of (50 ± 5) % must be connected to this pin. It is used by the E123MUX E123MUX as a reference for the internal E1 digital PLLs. E2AISC 144 I CMOS E2 AIS External Clock: An 8448 kHz clock with ± 30 ppm accuracy and a duty cycle of (50 ± 10) % must be connected to this pin. It is used by the E123MUX E123MUX for E2 AIS generation during fault conditions. This clock may also be connected to the Transmit E12 Clock Input pins (E12TCKIm). Note: This clock is required for the proper operation of the microprocessor interface. Name/Function CONTROL LEADS Symbol Pin No. I/O/P Type HIGHZ 68 I TTL High Impedance Enable: A low forces all E123MUX E123MUX output and bidirectional leads (except TDO) to a high impedance state for board level testing. For normal operation this pin must be held high. TEST 69 I TTL TranSwitch Test Mode: For normal operation this pin must be held high. RESET 70 I TTL Reset: An active low on this lead resets the internal state machines, counters and control registers to their default states. The reset signal should be held low for a minimum of 150 nanoseconds. It should be applied after power becomes stable. - 12 - TXC-03361-MB TXC-03361-MB Ed. 5, September 1999 E123MUX E123MUX TXC-03361 TXC-03361 DATA SHEET TEST ACCESS PORT FOR BOUNDARY SCAN Symbol Pin No. I/O/P Type Name/Function TCK 100 I TTL Test Clock: This is the input clock for boundary scan testing. The TDI and TMS states are clocked into the E123MUX E123MUX on rising edges of this clock. TDI 99 I TTLp Test Data Input: Serial data input for boundary scan test messages. This lead has an internal pull-up resistor. TDO 102 O(T) CMOS 4 mA TMS 98 I TTLp Test Boundary Mode Select: This input signal is used to control test operations. This lead has an internal pull-up resistor. TRS 101 I TTLp Test Boundary Scan Reset: This pin must be either held low or asserted low, then high (pulsed low) for a minimum of 500 ns to asynchronously reset the Test Access Port (TAP) controller. Failure to perform this reset may cause the TAP controller to take over control of the output pins. See Test Access Port Section for details. This lead has an internal pull-up resistor. Symbol Pin No. I/O/P Type Name/Function TESTCK 96 O CMOS 2 mA Test Scan Clock: Provided for TranSwitch testing purposes only. TESTDATA 97 O CMOS 2 mA Test Scan Data: Provided for TranSwitch testing purposes only. Test Boundary Data Output: Serial data output whose information is clocked out on falling edges of TCK. TEST PINS MICROPROCESSOR SELECTION Symbol Pin No. I/O/P Type Name/Function MP0 MP1 66 67 I TTL Microprocessor Selection Control Bits: The type of microprocessor interface bus is selected according to the states given in the table below: MP0 Low Low High High - 13 - MP1 Low High Low High Selection Motorola-compatible bus I/O Reserved. Do not use. Intel-compatible bus I/O Multiplexed bus I/O TXC-03361-MB TXC-03361-MB Ed. 5, September 1999 E123MUX E123MUX TXC-03361 TXC-03361 DATA SHEET MICROPROCESSOR INTERFACE - MULTIPLEXED BUS Symbol Pin No. I/O/P Type Name/Function A/D(7-0) 77 - 84 I/O TTL 4 mA Address/Data Bus: Address input leads and bidirectional data leads used for selecting the address and transferring data between the E123MUX E123MUX and the microprocessor. High is logic one. A/D0 (pin 84) is the least significant bit. ALE 105 I TTL Address Latch Enable: An active high signal generated by the microprocessor. It is used for holding an address stable during a read/write cycle when in multiplexed microprocessor mode. This pin should be held high in Motorola/ Intel modes. SEL 71 I TTL Select: A low enables data transfers between the microprocessor and the E123MUX E123MUX during a read/write cycle. RD 104 I TTL Read: An active low signal generated by the microprocessor for reading the E123MUX E123MUX memory map locations. WR 103 I TTL Write: An active low signal generated by the microprocessor for writing to the E123MUX E123MUX memory map locations. RDY 106 O(T) CMOS 4 mA Ready: A high is an acknowledgment from the addressed memory location that the transfer can be completed. A low indicates that the transfer cannot be completed and that microprocessor wait states must be generated. This lead is tri-stated when not driven high or low. INT 65 O(D) CMOS 2 mA Interrupt: A high on this output pin signals an interrupt request to the microprocessor when an alarm occurs while the interrupt mask bit for that alarm is disabled (set to 0). This pin is open drain and requires a 4.7 kilohm pull-up resistor for proper operation. - 14 - TXC-03361-MB TXC-03361-MB Ed. 5, September 1999 E123MUX E123MUX TXC-03361 TXC-03361 DATA SHEET MICROPROCESSOR INTERFACE - SPLIT BUS Symbol Pin No. I/O/P Type Name/Function A(7-0) 88 - 95 I TTL Address Bus (Intel/Motorola Interfaces): These are address line inputs that are used for accessing a memory location for a read/write cycle. High is logic one. A0 (pin 95) is the least significant bit. D(7-0) 77 - 84 I/O TTL 4 mA Data Bus (Intel/Motorola Interfaces): These are bidirectional data lines used for transferring data between the memory and the microprocessor. High is logic one. D0 (pin 84) is the least significant bit. SEL 71 I TTL Select (Intel/Motorola Interfaces): A low enables data transfers between the microprocessor and the E123MUX E123MUX during a read/write cycle. RD / RD/WR 104 I TTL Read (Intel Interface) or Read/Write (Motorola): Intel Interface - An active low signal generated by the microprocessor for reading the E123MUX E123MUX memory map locations. Motorola Interface - An active high signal is generated by the microprocessor for reading the E123MUX E123MUX memory map locations. An active low signal is used to write to E123MUX E123MUX memory map locations. WR/DS 103 I TTL Write (Intel Interface) or Data Select (Motorola): Intel Interface - An active low signal generated by the microprocessor for writing to the E123MUX E123MUX memory map locations. Motorola Interface - An active low signal generated by the microprocessor to select the data to be read or written. Connect to the DS signal at the microprocessor. RDY/ DTACK 106 O(T) CMOS 4 mA Ready (Intel Interface) or Data Transfer Acknowledge (Motorola Interface): Intel Interface - A high is an acknowledgment from the addressed memory map location that the transfer can be completed. A low indicates that the E123MUX E123MUX cannot complete the transfer cycle and that microprocessor wait states must be generated. Motorola Interface - During a read bus cycle, a low signal indicates that the information on the data bus is valid. During a write bus cycle, a low signal acknowledges the acceptance of data. This lead is tri-stated when it is not driven high or low. INT/IRQ 65 O(D) CMOS 2 mA Interrupt (Intel Interface) or Interrupt Request (Motorola Interface): Intel Interface - A high on this output pin signals an interrupt to the microprocessor when an alarm occurs while the interrupt mask bit for that alarm is disabled (set to 0). Motorola Interface - A low on this output pin signals an interrupt request to the microprocessor when an alarm occurs while the interrupt mask bit for that alarm is disabled (set to 0). This pin is open drain tri-state and requires a 4.7 kilohm pull-up resistor for proper operation in both Intel and Motorola Modes. - 15 - TXC-03361-MB TXC-03361-MB Ed. 5, September 1999 E123MUX E123MUX TXC-03361 TXC-03361 DATA SHEET ABSOLUTE MAXIMUM RATINGS AND ENVIRONMENTAL LIMITATIONS Parameter Symbol Min Max Unit Conditions Supply voltage VDD -0.3 +7.0 V Note 1 DC input voltage VIN -0.5 VDD + 0.5 V Note 1 Storage temperature range TS -55 150 o C Note 1 85 o C 0 ft/min linear airflow Cxs Note 1 Level per EIA/JEDEC JESD22-A112-A JESD22-A112-A Ambient operating temperature TA Component Temperature x Time TI Moisture Exposure Level ME 5 Relative Humidity, during assembly RH 30 60 % Note 2 Relative Humidity, in-circuit RH 0 100 % non-condensing ±2000 V per MIL-STD-833D MIL-STD-833D Method 3015.7 ESD Classification -40 o 270 x 5 ESD Notes: 1. Conditions exceeding the Min or Max values may cause permanent failure. Exposure to conditions near the Min or Max values for extended periods may impair device reliability. 2. Pre-assembly storage in non-drypack conditions is not recommended. Please refer to the instructions on the "CAUTION" label on the drypack bag in which devices are supplied. THERMAL CHARACTERISTICS Parameter Min Thermal resistance junction to ambient Typ Max Unit oC/W 26.0 Test Conditions 0 ft/min linear airflow POWER REQUIREMENTS Parameter Min Typ Max Unit 4.75 5.0 5.25 V IDD 285 mA PDD 1500 mW VDD - 16 - Test Conditions Inputs switching TXC-03361-MB TXC-03361-MB Ed. 5, September 1999 E123MUX E123MUX TXC-03361 TXC-03361 DATA SHEET INPUT, OUTPUT AND I/O PARAMETERS Input Parameters For TTL Parameter Min Typ Max Test Conditions V 2.0 VIH Unit 4.75