TXC-02050 TXC-02050-MB 1N914 1N4148 IN4148 IN914 WB-1010 ACT11034

6-, 8-, 34-Mbit/s Line Interface TXC-02050 DATA SHEET FEATURES DESCRIPTION · 6312/8448/34368 kbit/s line interface The

MRT Device 6-, 8-, 34-Mbit/s Line Interface TXC-02050 TXC-02050 DATA SHEET FEATURES DESCRIPTION · 6312/8448/34368 kbit/s line interface The TranSwitch Multi-rate Receive/Transmit (MRT) device is a CMOS VLSI device that provides the functions needed for terminating two CCITT line rates, 8448 and 34368 kbit/s, and a 6312 kbit/s rate which is specified in the Japanese NTT Technical Reference for High Speed Digital Leased Circuits. For 8448 and 34368 kbit/s operation, the MRT provides an optional HDB3 codec. · AGC and equalizer · Line quality monitor (10-6 error rate) · Receive loss of signal and transmit loss of clock alarms The MRT is equipped with a receive equalizer circuit and AGC. The MRT also provides a rail or NRZ interface, HDB3 error rate monitor, alarm detection, and AIS generators. Testing capability is provided by transmit and receive loopbacks. · Optional HDB3 encoder/decoder · Two loopbacks: -Receive to transmit (digital) -Transmit to receive (analog) · Optional transmit and receive AIS generators · Rail or NRZ terminal side I/O APPLICATIONS · Meets CCITT Recommendation G.703 · Digital cross-connect equipment · Remote terminals · Terminal interface for multiplexers/demultiplexers · Switching systems · CSU/DSU LINE SIDE +5V TERMINAL SIDE 6,8,34 Mbit/s receive bipolar data Clock & data MRT -6 10 error rate indication Error rate clock reference 6-,8-,34-Mbit/s Line Interface Clock & data NRZ or P N rail , Operating rate reference frequency 6,8,34 Mbit/s transmit bipolar data Equalization and rate control LOS/LOC AIS control Patents Pending Copyright 1994 TranSwitch Corporation TXC and TranSwitch are registered trademarks of TranSwitch Corporation TranSwitch Corporation · 3 Enterprise Drive · Shelton, Connecticut 06484 Tel: 203-929-8810 · Fax: 203-926-9453 · www.transwitch.com Document Number: TXC-02050-MB TXC-02050-MB Ed 3, April 1994 · USA MRT BLOCK DIAGRAM LINE SIDE EQB1 EQB0 LOW VAGC GNDA AGFIL TERMINAL SIDE RXLOS VCOC PLLC PNENB RXDIS + + DI1 DI2 Equalization Network AGC Clock Recovery RXAIS RP/RD RN - HDB3 - clk Decoder clk CLKO CLKO DCK LBKTX I/O Circuits CV Error Detector TPO HDB3 Encoder + TNO TP/TD - Output Driver TN clk VDD GND DCK LBKRX BERCK CV LQLTY CLKI TXAIS TXLOC Figure 1. MRT Block Diagram BLOCK DIAGRAM DESCRIPTION On the Line Side, a symmetrical bipolar signal is applied to the input signal pin (DI1), which requires an external 75 termination. DI2 is a DC reference voltage output which serves as an AC ground. Equalization for various lengths of cable having a f characteristic is compensated by the two EQB0 and EQB1 signal leads. The Equalization Network Block is connected to an AGC Block which has approximately a 20 dB dynamic range. The AGC has separate voltage and ground leads for noise immunity, and uses an external capacitor as part of an AGC filter. The AGC output is connected to the Clock Recovery Block. The Clock Recovery Block contains a phase-locked loop and supporting logic to generate a clock signal from the line signal. The signal lead LOW selects the appropriate circuit in the Clock Recovery Block for the operating frequency and provides input attenuation for the receive line signal. The line signal is monitored for loss of signal, with an alarm indication provided on the RXLOS signal lead. The Clock Recovery Block requires an external reference clock at the operating frequency (DCK). The reference clock is also used for generating and sending a receive Alarm Indication Signal (AIS). The generation and sending of AIS for recovered data is controlled by the RXAIS signal lead. The output of the Clock Recovery Block is connected to the HDB3 Decoder Block or the Output Circuits Block. When the decoder is enabled, indications of coding violation errors, other than the normal HDB3 zero substitution codes, are provided as pulses on the signal lead labeled CV. An external clock (BERCK) is used to generate a 10-second sampling window for detecting a 10-6 or greater error rate. The line quality indication is provided on the signal lead labeled LQLTY. -2- TXC-02050-MB TXC-02050-MB Ed. 3, April 1994 MRT Two Terminal Side interfaces are provided, a positive and negative rail (RP and RN) or NRZ (RD) interface. The selection is determined by the state placed on the signal lead labeled PNENB. When a low is applied to the signal lead, the HDB3 Decoder and HDB3 Encoder Blocks are bypassed, and the terminal side I/O is a positive and negative rail interface. When a high is applied to the signal lead, an NRZ interface is provided. Data is clocked out of the MRT on negative edges of the clock signal (CLKO). Receive data and the clock signals are disabled, and forced to a high impedance state by placing a low on the receive disable lead (RXDIS). For a receive positive and negative rail interface, an inverted clock (CLKO) is also provided. The terminal side interface for the transmitter can either be positive and negative rail (TP and TN) or NRZ (TD) data depending on the state of the common control lead PNENB. Data is clocked into the MRT on positive transitions of the clock signal (CLKI). The input clock is monitored for the loss of clock. When the input clock remains high or low, TXLOC will be set low. The MRT also provides the capability to generate and insert AIS (all ones signal), independent of the transmit data. A low placed on the TXAIS lead enables the transmit AIS generator. Two loopbacks are provided, transmit loopback and receive loopback. Transmit loopback connects the data path from the transmitter output driver stage to the clock recovery, and disables the external receiver input. Transmit loopback is activated by placing a low on the LBKTX signal lead. Receive loopback connects the receive data path to the transmit output circuits and disables the transmit input. Receive loopback is activated by placing a low on the LBKRX signal lead. For 6 Mbps operation, the MRT should be operated in the P and N rail mode, bypassing the HDB3 Decoder/ Encoder. TP/TD 40 TN VDD TXAIS 42 44 GND 8 38 CLKI 10 36 VCOC PNENB GND GND TXLOC 2 RXAIS BERCK 4 GND 6 LQLTY PIN DIAGRAM VDD DCK VDD RN MRT PIN DIAGRAM (Top View) 12 RP/RD CLKO 34 32 14 GND GNDA 28 EQB1 26 LOW LBKTX 24 LBKRX VAGC 22 AGFIL 20 RXDIS RXLOS 18 CV DI2 DI1 EQB0 30 16 VDD PLLC TPO TNO CLKO GND GND VDD GND Figure 2. MRT Pin Diagram With Names and Numbers -3- TXC-02050-MB TXC-02050-MB Ed. 3, April 1994 MRT PIN DESCRIPTIONS Power Supply and Ground Symbol Pin No. I/O/P* Type Name/Function VDD 10,18,35, 37,42 P VDD: 5-volt supply, ± 5%. GND 1,6,11,16,32, 36,39,44 P Ground: 0 volts reference. VAGC 23 P AGC VDD: Isolate from VDD using 1N914 1N914 or 1N4148 1N4148 diode. GNDA 31 P AGC Ground: 0 volts reference. *Note: I = Input; O = Output; P = Power Line Side I/O Symbol Pin No. I/O/P Type Name/Function DI1 29 I Analog Data In 1: HDB3 or B8ZS encoded bipolar receive data input. DI2 30 O Analog Data In 2: DC Voltage Reference for Data Input DI1. The MRT uses an internally generated voltage reference as an AC ground for the received data input. An external 0.1 µF capacitor, in parallel with a 10 µF/6.3 V tantalum capacitor, is connected between this pin and ground. No other connection should be made to this pin. TNO 33 O TTL24mA Transmit Negative Out: Line transmit negative; output is an active low. TPO 34 O TTL24mA Transmit Positive Out: Line transmit positive; output is an active low. Symbol Pin No. I/O/P Type Name/Function RN 12 O TTL4mA Receive Negative: When PNENB is low, the HDB3 codec is bypassed and N-rail (RN) data is provided on this pin. When PNENB is high, the output is forced to a high impedance state. RP/RD 13 O TTL4mA Receive Positive/Receive Data: When PNENB is low, the HDB3 codec is bypassed and P-Rail (RP) data is provided on this pin. When PNENB is high, NRZ data (RD) is provided. CLKO 14 O CMOS8mA Terminal Side I/O Clock Out Inverted: Receive inverted clock output. Positive and negative rail receive data is clocked out on the rising edge. Disabled in the NRZ mode. -4- TXC-02050-MB TXC-02050-MB Ed. 3, April 1994 MRT Symbol Pin No. I/O/P Type Name/Function CLKO 15 O CMOS8mA Clock Out: Receive clock output. Receive positive and negative rail and NRZ data is clocked out on the falling edge. CLKI 38 I TTLr Clock In: Transmit clock input for P and N rail and NRZ data. Transmit data is clocked into the MRT on the rising edge. This clock must have a frequency of ± 20 ppm for the 34368 kbit/s operation and ± 30 ppm for the 6312/8448 kbit/s operation (ref: CCITT recommendation G.703). The duty cycle requirement for this clock signal is 50% ± 5%, measured at the 1.4V TTL threshold level. TP/TD 40 I TTL Transmit Positive/Transmit Data: When PNENB is low, the HDB3 codec is bypassed and transmit P-rail (TP) data is applied to this pin. When PNENB is high, NRZ transmit data (TD) is applied. TN 41 I TTL Transmit Negative: When PNENB is low, the HDB3 codec is bypassed and transmit N-Rail (TN) is applied to this pin. When PNENB is high, this input is disabled. Alarm Signal Outputs Symbol Pin No. I/O/P Type Name/Function TXLOC 2 O TTL2mA Transmit Loss Of Clock: Active low output. A transmit loss of clock alarm occurs when the transmit clock input (CKLI) is stuck high or low for 20-32 clock cycles. Recovery occurs on the first input clock transition. LQLTY 5 O TTL2mA Line Quality: This signal represents a gross estimate of the line quality which is determined by counting coding violations for 34 (8) Mbit/s operation. If the line error rate exceeds a 10-6 threshold during a 10 (40) second interval, LQLTY goes active high. LQLTY is active low when coding violations do not exceed the 10-6 threshold in a 10 (40) second interval. The output on this pin is only valid when the appropriate clock signal is applied to BERCK. It should be disregarded in the P and N mode of operation. CV 19 O TTL2mA Coding Violation: Active high output. A coding violation pulse occurs when an HDB3 coding violation is detected in the received line data input. A coding violation is not part of the HDB3 zero-substitution code. A coding violation occurs because of noise or other impairments affecting the line signal. The output of this pin should be disregarded in the P and N mode. RXLOS 20 O TTL2mA Receive Loss Of Signal: Active low output. A receive loss of signal occurs when the input data is zero for 20-32 clock cycles. Recovery occurs when the receive signal returns. -5- TXC-02050-MB TXC-02050-MB Ed. 3, April 1994 MRT MRT Control Leads Symbol Pin No. I/O/P Type Name/Function RXAIS 3 I CMOSr Receive Alarm Indication Signal: When RXAIS is low, the MRT generates AIS (all ones signal) for the terminal side receive output data. The line side receive data path is disabled. The reference clock (DCK) provides the clock source required for generating AIS. BERCK 4 I TTLr Bit Error Rate Clock: This clock establishes the time base for estimating the coding violation error rate. For 34 Mbit/s operation the clock frequency must be 6 kHz, and for 8 Mbit/s operation the clock frequency must be 1.5 kHz. This pin should be left open for P and N mode operation. PNENB 8 I CMOSr P And N Enable: When PNENB is low, the P and N rail interface is enabled, and the HDB3 codec is bypassed. When PNENB is high, the terminal side I/O data is NRZ and the HDB3 codec is enabled. This pin must be held low for 6 Mbit/s operation. DCK 9 I TTL Reference Clock: Operating frequency reference clock. For receive signal clock recovery, ± 200 ppm frequency accuracy is adequate. If the transmit and receive AIS features are used, the frequency accuracy must be ± 20 ppm for 34368 kbit/s and ± 30 ppm for 8448 and 6312 kbit/s operation. The duty cycle requirement for this clock signal is 50% ± 5% as measured at the 1.4V TTL threshold level. RXDIS 21 I CMOSr Receive Disable: When RXDIS is low, the receive side of the MRT is disabled and the RN, RP/RD, CLKO and CLKO output leads are forced to a high impedance state. LBKRX 24 I CMOSr Loopback Receive: When LBKRX is low, the MRT loops back receive data as transmit data. The receive data is also sent to the terminal side, but the transmit data input on the terminal side is disabled. (Note 1) LBKTX 25 I CMOSr Loopback Transmit: When LBKTX is low, the MRT loops back transmit data as receive data. The transmit data is sent on the line side, but the receive data input on the line side is disabled. (Note 1) LOW 26 I CMOSr Low Frequency: When LOW is low, the MRT enables equalization and input attenuator settings for 6312 or 8448 kbit/s operation. This lead also controls the clock recovery high/low frequency range circuit. Note 1: Setting LBKTX and LBKRX low simultaneously will cause invalid outputs at the receive terminal and transmit line ports. -6- TXC-02050-MB TXC-02050-MB Ed. 3, April 1994 MRT Symbol Pin No. I/O/P Type Name/Function EQB1 EQB0 27 28 I I CMOSr Equalizer Bit 1: MSB of equalizer setting. Equalizer Bit 0: LSB of equalizer setting. Equalization is as follows for 34 Mbit/s operation: EQB1 EQB0 CABLE EQUALIZATION f * 1 1 0dB< cable