TVP5158 SLES243B TVP5157 TVP5156 TVP5158/TVP5157 TVP5154A TVP5150AM1 TVP5146M2 - Datasheet Archive

 

Four-Channel NTSC/PAL Video Decoders With Independent Scalers, Noise Reduction, Auto Contrast, and Flexible Output Formatter for

 

TVP5158 TVP5158 Four-Channel NTSC/PAL Video Decoders With Independent Scalers, Noise Reduction, Auto Contrast, and Flexible Output Formatter for Security and Other Multi-Channel Video Applications Data Manual PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Literature Number: SLES243B SLES243B July 2009 ­ Revised September 2009 TVP5158 TVP5158, TVP5157 TVP5157, TVP5156 TVP5156 SLES243B SLES243B ­ JULY 2009 ­ REVISED SEPTEMBER 2009 www.ti.com Contents 1 2 3 2 . 9 1.1 Features . 9 1.2 Applications . 10 1.3 Related Products . 10 1.4 Description . 10 1.5 ORDERING INFORMATION . 11 Terminal Assignments . 12 2.1 Functional Block Diagram . 12 Functional Description . 16 3.1 Video Analog Processing and A/D Converters . 16 3.1.1 Analog Video Input . 16 3.1.2 Analog Video Input Clamping . 17 3.1.3 Analog Audio Input Clamping . 17 3.1.4 A/D Converter . 17 3.2 Digital Video Processing . 17 3.2.1 2x Decimation Filter . 17 3.2.2 Automatic Gain Control . 17 3.2.3 Composite Processor . 17 3.2.3.1 Color Low-Pass Filter . 18 3.2.3.2 Y/C Separation . 19 3.2.4 Luminance Processing . 20 3.3 AVID Cropping . 21 3.4 Embedded Syncs . 21 3.5 Scaler . 22 3.6 Noise Reduction . 22 3.7 Auto Contrast . 22 3.8 Output Formatter . 23 3.8.1 Non-Interleaved Mode . 23 3.8.2 Pixel-Interleaved Mode . 23 3.8.2.1 2-Ch Pixel-Interleaved Mode . 24 3.8.2.2 4-Ch Pixel-Interleaved Mode . 24 3.8.2.3 Metadata Insertion for Non-Interleave Mode and Pixel-Interleaved Mode . 24 3.8.3 Line-Interleaved Mode Support (TVP5158 TVP5158 only) . 25 3.8.3.1 2-Ch Line-Interleaved Mode . 26 3.8.3.2 4-Ch Line-Interleaved Mode . 26 3.8.3.3 Video Cascade Mode . 26 3.8.3.4 Metadata Insertion for Line-Interleaved Mode . 29 3.9 Audio Sub-System (TVP5157 TVP5157 and TVP5158 TVP5158 Only) . 31 3.9.1 Features . 31 3.9.2 Audio Sub-System Functional Diagram . 32 3.9.3 Audio Cascade Connection . 33 3.10 I2C Host Interface . 34 3.10.1 I2C Write Operation . 36 3.10.2 I2C Read Operation . 36 3.11 Clock Circuits . 37 Introduction Contents Copyright © 2009, Texas Instruments Incorporated TVP5158 TVP5158, TVP5157 TVP5157, TVP5156 TVP5156 www.ti.com . . 4.1 Overview . 4.2 Register Definitions . Electrical Specifications . 5.1 Absolute Maximum Ratings . 5.2 Recommended Operating Conditions . 5.3 Reference Clock Specifications . 5.4 Electrical Characteristics . 5.5 DC Electrical Characteristics . 5.6 Video A/D Converters Electrical Characteristics . 5.7 Audio A/D Converters Electrical Characteristics . 5.8 Video Output Clock and Data Timing . 5.8.1 Video Input Clock and Data Timing . 5.9 I2C Host Port Timing . 5.9.1 I2S Port Timing . 5.10 Miscellaneous Timings . 5.11 Thermal Specification . Application Information . 6.1 4-Ch D1 Applications . 6.2 8-Ch CIF Applications . 6.3 16-Ch CIF Applications . 6.4 Application Circuit Examples . 6.5 Designing with PowerPAD Devices . Revison History . 3.12 4 5 6 7 SLES243B SLES243B ­ JULY 2009 ­ REVISED SEPTEMBER 2009 Reset Mode Internal Control Registers Copyright © 2009, Texas Instruments Incorporated Contents 38 39 39 42 83 83 83 84 84 84 85 85 86 86 87 88 88 88 89 89 89 90 91 92 93 3 TVP5158 TVP5158, TVP5157 TVP5157, TVP5156 TVP5156 SLES243B SLES243B ­ JULY 2009 ­ REVISED SEPTEMBER 2009 www.ti.com List of Figures 2-1 Functional Block Diagram . 13 3-1 Video Analog Processing and ADC Block Diagram . 16 3-2 Anti-Aliasing Filter Frequency Response 3-3 Composite Processor Block Diagram. 18 3-4 Color Low-Pass Filter Frequency Response 3-5 Color Low-Pass Filter with Filter Characteristics, NTSC/PAL ITU-R BT.601 Sampling. 19 3-6 Chroma Trap Filter Frequency Response, NTSC ITU-R BT.601 Sampling . 20 3-7 Chroma Trap Filter Frequency Response, PAL ITU-R BT.601 Sampling . 20 3-8 Luminance Edge-Enhancer Peaking Block Diagram . 21 3-9 Peaking Filter Response, NTSC/PAL ITU-R BT.601 Sampling . 21 3-10 2-Ch Pixel-Interleaved Mode Timing Diagram. 24 3-11 4-Ch Pixel-Interleaved Mode Timing Diagram. 24 3-12 Cascade Connection for 16-Ch CIF Recoding and Multi-Ch CIF Preview 3-13 Cascade Connection for 16-Ch CIF Recoding and Multi-Ch Half-D1 Preview . 28 3-14 Cascade Connection for 16-Ch CIF Recoding and 2-Ch D1/Multi-Ch CIF Preview . 29 3-15 Start Code in 8-Bit BT.656 Interface . 29 3-16 Start Code in 16-Bit YCbCr 4:2:2 Interface . 29 3-17 Audio Sub-System Functional Diagram . 33 3-18 Audio Cascade Connection . 33 3-19 Clock and Crystal Connectivity . 38 . . . 17 19 28 3-20 Reset Timing . 38 5-1 Video Output Clock and Data Timing . 86 5-2 I2C Host Port Timing . 87 6-1 4-Ch D1 Application (Single BT.656 Interface) . 89 6-2 4-Ch D1 Application (16-Bit YCbCr 4:2:2 Interface) . 89 6-3 8-Ch CIF Real Time Encoding and Multi-Ch D1 Preview Application . 90 6-4 8-Ch CIF Real Time Encoding and Multi-Ch D1 Preview Application . 90 6-5 Video Input Connectivity. 92 6-6 Audio Input Connectivity. 92 4 List of Figures Copyright © 2009, Texas Instruments Incorporated TVP5158 TVP5158, TVP5157 TVP5157, TVP5156 TVP5156 www.ti.com SLES243B SLES243B ­ JULY 2009 ­ REVISED SEPTEMBER 2009 List of Tables . . EAV and SAV Sequence . Standard Video Resolutions . Video Resolutions Converted by the Scaler . Summary of Line Frequencies, Data Rates and Pixel Counts for Different Standards . Output Ports Configuration for Non-Interleave Mode . Output Ports Configuration for Pixel-Interleaved Mode . VDET Statues Insertion in SAV/EAV Codes . Channel ID Insertion in Horizontal Blanking Code . Channel ID Insertion in SAV/EAV Code Sequence . Line-Interleaved Modes. TVP5158 TVP5158 Video Cascade Modes . Bit Assignment of 4-Byte Start Code for Active Video Line. Bit Field Definition of 4-Byte Start Code for Active Video Line . Bit Assignment of 4-Byte Start Code for the Dummy Line . Serial Audio Output Channel Assignment. I2C Terminal Description . I2C Host Interface Device Addresses . Reset Mode . Reset Sequence . Registers Summary . Status 1 . Status 2 . Color Subcarrier Phase Status . ROM Version . Chip ID MSB . Chip ID LSB . Video Standard Status . Video Standard Select . CVBS Autoswitch Mask . Auto Contrast Mode . Luminance Brightness . Luminance Contrast . Chrominance Saturation . Chrominance Hue . Color Killer . Luminance Processing Control 1 . Luminance Processing Control 2 . Power Control . Chrominance Processing Control 1 . Chrominance Processing Control 2 . AGC Gain Status . Back-End AGC Status . Status Request . AFE Gain Control . 1-1 Device Options 10 2-1 TERMINAL FUNCTIONS 14 3-1 3-2 3-3 3-4 3-5 3-6 3-7 3-8 3-9 3-10 3-11 3-12 3-13 3-14 3-15 3-16 3-17 3-18 3-19 4-1 4-2 4-3 4-4 4-5 4-6 4-7 4-8 4-9 4-10 4-11 4-12 4-13 4-14 4-15 4-16 4-17 4-18 4-19 4-20 4-21 4-22 4-23 4-24 4-25 Copyright © 2009, Texas Instruments Incorporated List of Tables 21 22 22 23 23 23 25 25 25 26 27 29 30 31 34 35 35 38 38 39 42 43 43 43 44 44 44 45 45 45 46 46 46 46 47 47 48 49 50 50 51 51 51 51 5 TVP5158 TVP5158, TVP5157 TVP5157, TVP5156 TVP5156 SLES243B SLES243B ­ JULY 2009 ­ REVISED SEPTEMBER 2009 www.ti.com . . AGC Increment Speed . AGC Increment Delay . AGC Decrement Speed . AGC Decrement Delay . AGC White Peak Processing . Back-End AGC Control . AFE Fine Gain . AVID Start Pixel . AVID Pixel Width . Noise Reduction Max Noise . Noise Reduction Control . Noise Reduction Noise Filter Beta . Operation Mode Control . Color PLL Speed Control . Sync Height Low Threshold . Sync Height High Threshold . Clear Lost Lock Detect . VSYNC Filter Shift . 656 Version/F-bit Control . F-Bit and V-Bit Decode Control . F-Bit and V-Bit Control . Output Timing Delay . Auto Contrast User Table Index . Blue Screen Y Control . Blue Screen Cb Control . Blue Screen Cr Control . Blue Screen LSB Control . Noise Measurement . Weak Signal High Threshold . Weak Signal Low Threshold . Noise Reduction Y/U/V T0 . Vertical Line Count Status . Output Formatter Control 1 . Output Formatter Control 2 . Embedded Sync Offset Control 1 . Embedded Sync Offset Control 2 . AVD Output Control 1 . AVD Output Control 2 . OFM Mode Control . OFM Channel Select 1 . OFM Channel Select 2 . OFM Channel Select 3 . OFM Super-Frame Size . OFM H-Blank Duration . Misc OFM Control . Audio Sample Rate Control . 4-26 Luma ALC Freeze Upper Threshold 52 4-27 Chroma ALC Freeze Upper Threshold 52 4-28 4-29 4-30 4-31 4-32 4-33 4-34 4-35 4-36 4-37 4-38 4-39 4-40 4-41 4-42 4-43 4-44 4-45 4-46 4-47 4-48 4-49 4-50 4-51 4-52 4-53 4-54 4-55 4-56 4-57 4-58 4-59 4-60 4-61 4-62 4-63 4-64 4-65 4-66 4-67 4-68 4-69 4-70 4-71 4-72 4-73 6 List of Tables 52 52 53 53 54 55 55 56 56 56 57 57 58 58 58 59 59 59 59 60 61 61 62 62 62 62 63 63 63 63 64 64 64 65 65 65 66 67 68 69 70 70 71 71 72 72 Copyright © 2009, Texas Instruments Incorporated TVP5158 TVP5158, TVP5157 TVP5157, TVP5156 TVP5156 www.ti.com 4-74 4-75 4-76 4-77 4-78 4-79 4-80 4-81 4-82 4-83 4-84 4-85 4-86 7-1 SLES243B SLES243B ­ JULY 2009 ­ REVISED SEPTEMBER 2009 . . Audio Mode Control . Audio Mixer Select . Audio Mute Control . Analog Mixing Ratio Control 1 . Analog Mixing Ratio Control 2 . Audio Cascade Mode Control . Interrupt Status . Interrupt Mask . Interrupt Clear . Decoder Write Enable . Decoder Read Enable . Revison History . Analog Audio Gain Control 1 73 Analog Audio Gain Control 2 74 Copyright © 2009, Texas Instruments Incorporated List of Tables 75 76 77 77 78 78 79 80 81 81 82 93 7 TVP5158 TVP5158, TVP5157 TVP5157, TVP5156 TVP5156 SLES243B SLES243B ­ JULY 2009 ­ REVISED SEPTEMBER 2009 8 List of Tables www.ti.com Copyright © 2009, Texas Instruments Incorporated TVP5158 TVP5158, TVP5157 TVP5157, TVP5156 TVP5156 www.ti.com SLES243B SLES243B ­ JULY 2009 ­ REVISED SEPTEMBER 2009 Four-Channel NTSC/PAL Video Decoders Check for Samples: TVP5158 TVP5158 TVP5157 TVP5157 TVP5156 TVP5156 1 Introduction 1.1 Features 1234 · Common Device Features (TVP5156 TVP5156, TVP5157 TVP5157, TVP5158 TVP5158) ­ Four separate video decoder channels having the following features for each channel · Accepts NTSC (J, M, 4.43) and PAL (B, D, G, H, I, M, N, Nc, 60) video data · Composite video inputs, Pseudo-differential video inputs to improved noise immunity · High-speed 10-bit ADC · Fully differential CMOS analog preprocessing channels with clamping · Integrated Anti-Aliasing filter · 2D 5-line (5H) adaptive comb filter · Noise reduction and auto contrast · Robust automatic video standard detection (NTSC/PAL) and switching · Programmable hue, saturation, sharpness, brightness and contrast · Luma-peaking processing · Patented architecture for locking to weak, noisy, or unstable signals ­ Four independent scalers support horizontal and/or vertical 2:1 downscaling ­ Channel multiplexing capabilities with metadata insertion · Pixel-interleaved mode supports up to four-channel D1 multiplexed 8-bit output at 108 MHz · Supports concurrent NTSC and PAL inputs ­ Support crystal interface with on-chip oscillator and single clock input mode ­ Single 27-MHz clock input or crystal for all standards and all channels ­ Internal phase-locked loop (PLL) for line-locked clock (separate for each channel) and sampling ­ Standard programmable video output format · ITU-R BT.656, 8-bit 4:2:2 with embedded syncs · YCbCr 16-bit 4:2:2 with embedded syncs ­ MacrovisionTM copy protection detection ­ 3.3-V compatible I/O ­ 128-pin TQFP package ­ Available in commercial (0°C to 70°C) temperature range · Additional TVP5158/TVP5157 TVP5158/TVP5157 Specific Features ­ Integrated four-channel audio ADC with audio sample rate of 8 kHz or 16 kHz ­ Support Master and Slave mode I2S Output ­ Support audio cascade connection · Additional TVP5158 TVP5158 Specific Features ­ Enhanced channel multiplexing capability ­ Line-interleaved mode ­ Four-channel D1 multiplexed output at 8 bit at 108 MHz ­ Video cascade connection for 8-Ch CIF, 8-Ch Half-D1, and 8-Ch CIF + 1-Ch D1 outputs ­ Also available in Industrial (-40°C to 85°C) temperature range 1 2 3 4 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. DaVinci, PowerPAD are trademarks of Texas Instruments. Macrovision is a trademark of Macrovision Corporation. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2009, Texas Instruments Incorporated TVP5158 TVP5158, TVP5157 TVP5157, TVP5156 TVP5156 SLES243B SLES243B ­ JULY 2009 ­ REVISED SEPTEMBER 2009 1.2 Applications · · · · 1.3 Security/surveillance digital video recorders/servers and PCI products Automotive infotainment video hub Large format video wall displays Game systems Related Products · · · · 1.4 www.ti.com TVP5154A TVP5154A TVP5150AM1 TVP5150AM1 TVP5146M2 TVP5146M2 TVP5147M1 TVP5147M1 Description The TVP5158 TVP5158, TVP5157 TVP5157, and TVP5156 TVP5156 devices are 4-channel, high-quality NTSC/PAL video decoder that digitizes and decodes all popular base-band analog video formats into digital video output. Each channel of this decoder includes 10-bit 27-MSPS 27-MSPS A/D converter (ADC). Preceding each ADC in the device, the corresponding analog channel contains an analog circuit that clamps the input to a reference voltage and applies the gain. Composite input signal is sampled at 2x the ITU-R BT.601 clock frequency, line-locked alignment, and is then decimated to the 1x pixel rate. CVBS decoding uses five-line adaptive comb filtering for both the luma and chroma data paths to reduce both cross-luma and cross-chroma artifacts. A chroma trap filter is also available. On CVBS inputs, the user can control video characteristics such as contrast, brightness, saturation, and hue via an I2C host port interface. Furthermore, luma peaking (sharpness) with programmable gain is included. All 4 channels are independently controllable. These decoders share a single clock input for all channels and for all supported standards. TVP5158 TVP5158 provides a glueless audio and video interface to TI DaVinciTM video processors. Video output ports support 8-bit ITU-R BT.656 and 16-bit 4:2:2 YCbCr with embedded synchronization. TVP5158 TVP5158 supports multiplexed pixel-interleaved and line-interleaved mode video outputs with metadata insertion. TVP5158 TVP5158 and TVP5157 TVP5157 integrate 4-Ch audio ADCs to reduce the BOM cost for surveillance market. Multiple TVP5158 TVP5158 devices can be cascade connected to support up to 8-Ch Video or 16-Ch audio processing. Noise reduction and auto contrast functions improve the video quality under low light condition which is very critical for surveillance products. The TVP5158 TVP5158, TVP5157 TVP5157, and TVP5156 TVP5156 can be programmed by using a single I2C serial interface. I2C commands can be sent to one or more decoder cores simultaneously, reducing the amount of I2C activity necessary to configure each core. This is especially useful for fast downloading modified firmware to the decoder cores. TVP5158 TVP5158, TVP5157 TVP5157, and TVP5156 TVP5156 use 1.1-V, 1.8-V, and 3.3-V power supplies for the analog/digital core and I/O. These devices are available in a 128-pin TQFP package. Table 1-1. Device Options Device Name No Yes No TVP5158 TVP5158 Introduction Line-Interleaved Modes No TVP5157 TVP5157 10 4-Ch Audio ADC TVP5156 TVP5156 Yes Yes Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5158 TVP5158 TVP5157 TVP5157 TVP5156 TVP5156 TVP5158 TVP5158, TVP5157 TVP5157, TVP5156 TVP5156 www.ti.com 1.5 SLES243B SLES243B ­ JULY 2009 ­ REVISED SEPTEMBER 2009 ORDERING INFORMATION PACKAGED DEVICES TQFP 128-Pin PowerPADTM Package TA TVP5156PNP TVP5156PNP 0°C to 70°C TVP5157PNP TVP5157PNP TVP5158PNP TVP5158PNP -40°C to 85°C TVP5158IPNP TVP5158IPNP Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5158 TVP5158 TVP5157 TVP5157 TVP5156 TVP5156 Introduction 11 TVP5158 TVP5158, TVP5157 TVP5157, TVP5156 TVP5156 SLES243B SLES243B ­ JULY 2009 ­ REVISED SEPTEMBER 2009 2 Terminal Assignments 2.1 www.ti.com Functional Block Diagram VIN_1_P VIN_1_N VIN_2_P VIN_2_N 10-Bit ADC Y/C Separation Noise Reduction/ Auto Contrast Scaler DVO_A_[7:0] 10-Bit ADC Y/C Separation Noise Reduction/ Auto Contrast Scaler DVO_B_[7:0] Output Formattor VIN_3_P VIN_3_N VIN_4_P VIN_4_N 10-Bit ADC Y/C Separation Noise Reduction/ Auto Contrast Scaler 10-Bit ADC Y/C Separation Noise Reduction/ Auto Contrast Scaler ARM/Memory Registers DVO_C_[7:0] DVO_D_[7:0] Delay Match & Re-Sync I2C Host port Cascade Input I2C AIN_1 AIN_2 AIN_3 Audio ADC Decimation Filter & Mixer BCLK_R LRCLK_R I2S Encoder SD_R/SD_M SD_CO AIN_4 Audio Cascade Input Figure 2-1. Functional Block Diagram 12 Terminal Assignments Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5158 TVP5158 TVP5157 TVP5157 TVP5156 TVP5156 TVP5158 TVP5158, TVP5157 TVP5157, TVP5156 TVP5156 OSC_OUT VSSA XTAL_IN XTAL_REF XTAL_OUT VDDA_1_8 VDDA_1_1 VSSA VSSA VDDA_1_1 VDDA_1_8 VIN_1_P I2CA1 VSS 65 69 68 67 66 DVO_A_5 VDD_3_3 DVO_A_6 DVO_A_7 VDD_1_1 70 DVO_A_2 DVO_A_3 VSS DVO_A_4 74 73 72 71 I2CA0 VSS DVO_A_0 DVO_A_1 VDD_1_1 79 78 77 76 75 VDD_1_1 SD_CO VSS VDD_3_3 83 82 81 80 SD_M SD_R VSS LRCLK_R BCLK_R 88 87 86 85 84 97 98 99 100 64 63 62 61 101 102 103 104 60 59 58 57 105 106 107 108 56 55 54 53 TVP5158 TVP5158 VSSA VIN_2_P 109 110 111 112 VIN_2_N VDDA_1_8 VDDA_1_8 REXT_2K 113 114 115 116 VSSA VSSA VDDA_1_1 VDDA_1_8 117 118 119 120 44 43 42 41 VIN_3_P VIN_3_N 121 122 123 124 40 39 38 37 125 126 127 128 36 35 34 33 Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5158 TVP5158 TVP5157 TVP5157 TVP5156 TVP5156 VDD_1_1 DVO_B_0 DVO_B_1 VSS DVO_B_2 DVO_B_3 VDD_3_3 DVO_B_4 DVO_B_5 VSS DVO_B_6 DVO_B_7 VDD_1_1 OCLK_P OCLK_N/CLKIN VSS I2CA2 VSS DVO_C_0 DVO_C_1 VDD_1_1 DVO_C_2 DVO_C_3 VDD_3_3 DVO_C_4 DVO_C_5 VSS DVO_C_6 DVO_C_7 VDD_1_1 NC 32 VSS DVO_D_0 VDD_1_1 27 28 29 30 31 48 47 46 45 VSS DVO_D_3 DVO_D_2 VDD_3_3 DVO_D_1 24 25 26 23 DVO_D_7 DVO_D_6 VDD_1_1 DVO_D_5 DVO_D_4 18 19 20 21 22 BCLK_CI VDD_1_1 SD_CI VSS 14 15 16 17 VDD_1_1 VSS VDD_3_3 LRCLK_CI T5 VSS 9 10 11 12 13 T3 T4 SCL SDA VSS T1 VSS INTREQ RESETB 1 2 3 4 VSSA VSSA VIN_4_P VIN_4_N VDDA_1_8 VDAA_3_3 52 51 50 49 128-Pin TQFP Package T2 VSSA 5 6 7 8 VIN_1_N 92 91 90 89 96 95 94 93 AIN_3 AIN_4 VDDA_1_8 VSS SLES243B SLES243B ­ JULY 2009 ­ REVISED SEPTEMBER 2009 VSSA AIN_1 AIN_2 www.ti.com Terminal Assignments 13 TVP5158 TVP5158, TVP5157 TVP5157, TVP5156 TVP5156 SLES243B SLES243B ­ JULY 2009 ­ REVISED SEPTEMBER 2009 www.ti.com Table 2-1. TERMINAL FUNCTIONS TERMINAL NAME NO. I/O DESCRIPTION Analog Section VIN_1_P 108 I Analog video input for ADC channel 1. VIN_1_N 109 I Common-mode reference input for ADC channel 1. VIN_2_P 112 I Analog video input for ADC channel 2. VIN_2_N 113 I Common-mode reference input for ADC channel 2. VIN_3_P 121 I Analog video input for ADC channel 3. VIN_3_N 122 I Common-mode reference input for ADC channel 3. VIN_4_P 125 I Analog video input for ADC channel 4. VIN_4_N 126 I Common-mode reference input for ADC channels. REXT_2K 116 I External resistor for AFE bias generator. Connect external 1.8k resistor to ground. AIN_1 95 I Analog audio input for channel 1 (No Connect for TVP5156 TVP5156 Only) AIN_2 94 I Analog audio input for channel 2 (No Connect for TVP5156 TVP5156 Only) AIN_3 93 I Analog audio input for channel 3 (No Connect for TVP5156 TVP5156 Only) AIN_4 92 I Analog audio input for channel 4 (No Connect for TVP5156 TVP5156 Only) XTAL_IN 99 I External clock reference input. It may be connected to external oscillator with 1.8-V compatible clock signal or 27.0-MHz crystal oscillator. XTAL_REF 100 G Crystal reference. Connected to analog ground internally. XTAL_OUT 101 O External clock reference output. Not connected if XTAL_IN is driven by an external single-ended oscillator. VDDA_1_1 103, 106, 119 P 1.1V analog supply VDDA_1_8 91, 102, 107, 114, 115, 120, 127 P 1.8V analog supply Analog Power VDDA_3_3 128 P 3.3V analog supply for all 4 video channels 96, 98, 104, 105, 110, 111, 117, 118, 123, 124 G Analog ground VSS 1, 6, 12, 14, 20, 26, 33, 38, 47, 49, 55, 61, 65, 73, 79, 82, 87, 90 G Digital ground VDD_1_1 13, 18, 23, 32, 35, 44, 52, 64, 67, 76, 84 P Digital core supply. Connect to 1.1-V digital supply. VDD_3_3 15, 29, 41, 58, 70, 81 P Digital I/O supply. Connect to 3.3-V digital supply. INTREQ 2 O Interrupt request. Interrupt signal to host processor. RESETB 3 I Reset. An active low signal that controls the reset state. SCL 4 I/O I2C serial clock (open drain) SDA 5 I/O I2C serial data (open drain) OSC_OUT 97 O Buffered crystal oscillator output. 1.8-V compatible. OCLK_P 51 O Output data clock+. All 4 digital video output ports are synchronized to this clock. OCLK_N/CLKIN 50 I/O Output data clock- for 2-Ch time-multiplexed mode or data clock input for 8-Ch video cascade mode 68, 69, 71, 72, 74, 75, 77, 78 O Digital video output data bus. VSSA Digital Power Digital Section DVO_A_[7:0] 14 Terminal Assignments Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5158 TVP5158 TVP5157 TVP5157 TVP5156 TVP5156 TVP5158 TVP5158, TVP5157 TVP5157, TVP5156 TVP5156 www.ti.com SLES243B SLES243B ­ JULY 2009 ­ REVISED SEPTEMBER 2009 TERMINAL FUNCTIONS (continued) TERMINAL NAME NO. I/O DESCRIPTION DVO_B_[7:0] 53, 54, 56, 57, 59, 60, 62, 63 O Digital video output data bus. DVO_C_[7:0] 36, 37, 39, 40, 42, 43, 45, 46 I/O Digital video output data bus. In cascade mode, all pins operate as input from another TVP5158 TVP5158 device. DVO_D_[7:0] 21, 22, 24, 25, 27, 28, 30, 31 I/O Digital video output data bus. In cascade mode, all pins operate as input from another TVP5158 TVP5158 device. I2CA0 80 I I2C slave address bit 0 I2CA1 66 I I2C slave address bit 1 I2CA2 48 I I2C slave address bit 2 Digital Audio Section (Not supported on TVP5156 TVP5156) BCLK_R 85 I/O I2S bit clock for recording. Also known as I2S serial clock (SCK). Supports master and slave modes. LRCLK_R 86 I/O I2S left/right clock for recording. Also known as I2S word select (WS). Supports master and slave modes. SD_R 88 O I2S serial data output for recording. SD_M 89 O I2S serial data output for mixed audio or recording. SD_CO 83 O Audio serial data output for cascade mode LRCLK_CI 16 I I2S left/right clock input for cascade mode. Also known as I2S word select (WS). BCLK_CI 17 I I2S bit clock input for cascade mode. Also known as I2S serial clock (SCK). SD_CI 19 I Audio serial data input for cascade mode. 7, 8, 9, 10, 11, 34 NC No Connect Pins T1, T2, T3, T4, T5, NC For normal operation, no connect Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5158 TVP5158 TVP5157 TVP5157 TVP5156 TVP5156 Terminal Assignments 15 TVP5158 TVP5158, TVP5157 TVP5157, TVP5156 TVP5156 SLES243B SLES243B ­ JULY 2009 ­ REVISED SEPTEMBER 2009 www.ti.com 3 Functional Description 3.1 Video Analog Processing and A/D Converters Each video decoder accepts one composite video input and performs video clamping, anti-aliasing filtering, video amplification, A/D conversion, and gain and offset adjustments to center the digitized video signal. Figure 3-1 shows the video analog processing and ADC block diagram. Analog CVBS Input Anti-Aliasing Filter ADC Clamp Output to Digital Processing Reference & Bias Figure 3-1. Video Analog Processing and ADC Block Diagram 3.1.1 Analog Video Input Supports NTSC (J, M, 4.43) and PAL (B, D, G, H, I, M, N, Nc, 60) video standards. Each video decoder channel supports a composite video input with a pseudo-differential pin which improves the noise immunity and analog performance. Each video decoder input should be ac-coupled through a 0.1-F capacitor. The nominal parallel termination resistor before the input to the device is 75 . Each video decoder integrates an anti-aliasing filter to provide good stop-band rejection on the analog video input signal. Figure 3-2 shows the frequency response of the anti-aliasing filter. Frequency Response 5 0 -5 Gain(dB) -10 -15 -20 -25 -30 -35 - 5 10 15 20 25 Frequency (MHz) Figure 3-2. Anti-Aliasing Filter Frequency Response 16 Functional Description Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5158 TVP5158 TVP5157 TVP5157 TVP5156 TVP5156 TVP5158 TVP5158, TVP5157 TVP5157, TVP5156 TVP5156 www.ti.com 3.1.2 SLES243B SLES243B ­ JULY 2009 ­ REVISED SEPTEMBER 2009 Analog Video Input Clamping An internal clamping circuit provides dc restoration for all four analog composite video inputs. The dc restoration circuit (sync-tip clamp) restores sync-tip level of the ac-coupled composite video signal to a fixed dc level near the bottom of the A/D converter range. 3.1.3 Analog Audio Input Clamping An internal clamping circuit provides mid-level clamping of all four analog audio inputs to a dc level of approximately 0.625 V. 3.1.4 A/D Converter All ADCs have a resolution of 10 bits and can operate at 27 MSPS. Each A/D channel receives a clock from the on-chip phase-locked loop (PLL) at a frequency 27 MHz. All ADC reference voltages are generated internally. 3.2 Digital Video Processing Digital Video Processing block receives digitized video signals from the ADCs and performs composite processing and YCbCr signal enhancements. The digital data output can be programmed to two formats: ITU-R BT.656 8-bit 4:2:2 with embedded syncs or 16-bit 4:2:2 with embedded syncs. The circuit also detects pseudo-sync pulses, AGC pulses, and color striping in Macrovision-encoded copy-protected material. 3.2.1 2x Decimation Filter All input signals are over-sampled by a factor of 2 (by 27-MHz clock). The A/D outputs initially pass through decimation filters that reduce the data rate to 1x the pixel rate. The decimation filter is a half-band filter. Over-sampling and decimation filtering can effectively increase the overall signal-to-noise ratio by 3 dB. 3.2.2 Automatic Gain Control The automatic gain control (AGC) can be enabled and can adjust the signal amplitude controlled by 14-bit digital gain stage after the ADC. The AGC algorithms can use up to four amplitude references: sync height, color burst amplitude, composite peak, and luma peak. The specific amplitude references being used by the AGC algorithms can be controlled using the AGC white peak processing register located at sub-address 2Dh. The gain increment speed and gain increment delay can be controlled using the AGC increment speed register located at sub-address 29h and the AGC increment delay register located at sub-address 2Ah. The gain decrement speed and gain decrement delay can be controlled using the AGC decrement speed register located at sub-address 2Bh and the AGC decrement delay register located at sub-address 2Ch. 3.2.3 Composite Processor This Composite Processor circuit receives a digitized composite signal from the ADCs and performs sync and Y/C separation, chroma demodulation for PAL/NTSC, and YUV signal enhancements. The slice levels of the sync separator are adaptive. The slice levels continually adapt to changes in the back-porch and sync-tip levels. The 10-bit composite video is multiplied by the sub carrier signals in the quadrature demodulator to generate U and V color difference signals. The U and V signals are then sent to low-pass filters to achieve the desired bandwidth. An adaptive 5-line comb filter separates UV from Y based on the unique property of color phase shifts from line to line. The chroma is re-modulated through a quadrature modulator and subtracted from line-delayed composite video to generate luma. This form of Y/C Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5158 TVP5158 TVP5157 TVP5157 TVP5156 TVP5156 Functional Description 17 TVP5158 TVP5158, TVP5157 TVP5157, TVP5156 TVP5156 SLES243B SLES243B ­ JULY 2009 ­ REVISED SEPTEMBER 2009 www.ti.com separation is completely complementary, thus there is no loss of information. However, in some applications, it is desirable to limit the U/V bandwidth to avoid crosstalk. In that case, notch filters can be turned on. To accommodate some viewing preferences, a peaking filter is also available in the luma path. Contrast, brightness, sharpness, hue, and saturation controls are programmable through the I2C host port. Figure 3-3 shows the block diagram of Composite Processor. CVBS Line Delay Delay Peaking Y NTSC/PAL Remodulation Y Contrast Notch Notch Filter Brightness Saturation Filter Adjust Cr Color LPF 2 Cb Burst Accumulator (U) 5 Line Adaptive CVBS NTSC/PAL Demodulation Color LPF 2 Burst Accumulator (V) Comb Filter Notch Filter Delay Notch Filter Delay U V Figure 3-3. Composite Processor Block Diagram 3.2.3.1 Color Low-Pass Filter High filter bandwidth preserves sharp color transitions and produces crisp color boundaries. However, for nonstandard video sources that have asymmetrical U and V side bands, it is desirable to limit the filter bandwidth to avoid UV crosstalk. The color low-pass filter bandwidth is programmable to enable one of the three notch filters. Figure 3-4 and Figure 3-5 represent the frequency responses of the wideband color low-pass filters. 18 Functional Description Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5158 TVP5158 TVP5157 TVP5157 TVP5156 TVP5156 TVP5158 TVP5158, TVP5157 TVP5157, TVP5156 TVP5156 www.ti.com SLES243B SLES243B ­ JULY 2009 ­ REVISED SEPTEMBER 2009 Figure 3-4. Color Low-Pass Filter Frequency Response Figure 3-5. Color Low-Pass Filter with Filter Characteristics, NTSC/PAL ITU-R BT.601 Sampling 3.2.3.2 Y/C Separation Y/C separation can be done using adaptive 5-line (5-H delay) comb filters or a chroma trap filter. The comb filter can be selectively bypassed in the luma or chroma path. If the comb filter is bypassed in the luma path, then chroma trap filters are used which are shown in Figure 3-6 and Figure 3-7. The TI patented adaptive comb filter algorithm reduces artifacts such as hanging dots at color boundaries. It detects and properly handles false colors in high-frequency luminance images such as a multiburst pattern or circle pattern. Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5158 TVP5158 TVP5157 TVP5157 TVP5156 TVP5156 Functional Description 19 TVP5158 TVP5158, TVP5157 TVP5157, TVP5156 TVP5156 SLES243B SLES243B ­ JULY 2009 ­ REVISED SEPTEMBER 2009 www.ti.com Figure 3-6. Chroma Trap Filter Frequency Response, NTSC ITU-R BT.601 Sampling Figure 3-7. Chroma Trap Filter Frequency Response, PAL ITU-R BT.601 Sampling 3.2.4 Luminance Processing The digitized composite video signal passes through either a luminance comb filter or a chroma trap filter, either of which removes chrominance information from the composite signal to generate a luminance signal. The luminance signal is then fed into the input of a peaking circuit. Figure 3-8 shows the basic functions of the luminance data path. A peaking filter (edge enhancer) amplifies high-frequency components of the luminance signal. Figure 3-9 shows the characteristics of the peaking filter at four different gain settings that are user-programmable via the I2C interface. Gain IN Peak Detector Bandpass Filter x Peaking Filter Delay + OUT Figure 3-8. Luminance Edge-Enhancer Peaking Block Diagram 20 Functional Description Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5158 TVP5158 TVP5157 TVP5157 TVP5156 TVP5156 TVP5158 TVP5158, TVP5157 TVP5157, TVP5156 TVP5156 www.ti.com SLES243B SLES243B ­ JULY 2009 ­ REVISED SEPTEMBER 2009 Figure 3-9. Peaking Filter Response, NTSC/PAL ITU-R BT.601 Sampling 3.3 AVID Cropping AVID or active video cropping provides a means to decrease the amount of video data output. This is accomplished by horizontally blanking a number of AVID pulses and by vertically blanking a number of lines per frame. Horizontal cropping can be enabled/disabled using bit-6 of address B1h. When line cropping is enabled, active video will be reduced from 720 to 704 pixels for unscaled video and from 360 to 352 pixels for down-scaled video. When line cropping is enabled, the TVP5158 TVP5158 crops an equal amount from both the start and end of active video. Register 8Ch can be used to delay both the start and end of active video. It allows selecting which 704 pixels out of 720 are actually being used for active video when line cropping is enabled. 3.4 Embedded Syncs Standards with embedded syncs insert SAV and EAV codes into the data stream at the beginning and end of horizontal blanking. These codes contain the V and F bits which also define vertical timing. F and V change on EAV. Table 3-1 gives the format of the SAV and EAV codes. H equals 1 always indicates EAV. H equals 0 always indicates SAV. The alignment of V and F to the line and field counter varies depending on the standard. Please refer to ITU-R BT.656 for more information on embedded syncs. The P bits are protection bits: P3 = V xor H P2 = F xor H P1 = F xor V P0 = F xor V xor H Table 3-1. EAV and SAV Sequence 8-BIT DATA D7 (MSB) D6 D5 D4 D3 D2 D1 D0 Preamble 1 1 1 1 1 1 1 1 Preamble 0 0 0 0 0 0 0 0 Preamble 0 0 0 0 0 0 0 0 Status word 1 F V H P3 P2 P1 P0 Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5158 TVP5158 TVP5157 TVP5157 TVP5156 TVP5156 Functional Description 21 TVP5158 TVP5158, TVP5157 TVP5157, TVP5156 TVP5156 SLES243B SLES243B ­ JULY 2009 ­ REVISED SEPTEMBER 2009 3.5 www.ti.com Scaler Each video decoder has an independent horizontal and vertical scaler, which supports D1 to half-D1 or CIF conversion. Table 3-2 gives the details of video resolution including un-cropped and cropped. Table 3-3 shows the video resolutions converted by the scaler. Table 3-2. Standard Video Resolutions Uncropped Format Cropped NTSC PAL NTSC PAL D1 720 x 480 720 x 576 704 x 480 704 x 576 Half-D1 360 x 480 360 x 576 352 x 480 352 x 576 CIF 360 x 240 360 x 288 352 x 240 352 x 288 Table 3-3. Video Resolutions Converted by the Scaler Scaling Ratio D1 D1 to Half-D1 D1 to CIF 3.6 Format Horizontal Scaling Vertical Scaling Total Pixel Active Output Resolution NTSC 1:1 1:1 858 x 525 720 x 480 PAL 1:1 1:1 864 x 625 720 x 576 NTSC 2:1 1:1 429 x 525 360 x 480 PAL 2:1 1:1 432 x 625 360 x 576 NTSC 2:1 2:1 429 x 262 360 x 240 PAL 2:1 2:1 432 x 312 360 x 288 Noise Reduction A video sequence shot under low light condition, which is typical of video surveillance applications, can contain lots of noise. Human eyes are very sensitive to oscillating signals, the visual quality degenerates significantly even when the noise level is small. Each video decoder uses a TI proprietary spatial filter to reduce video noise. For each frame of image, the video noise filter (VNF) produces an estimate of the Y/U/V noise. Based on the noise estimates, the firmware adjusts the threshold for Y/U/V filtering. The filtered video shows improved video quality and lower compression bit-rate. The firmware can also utilize the Y/U/V noise estimates to make decisions to disable color if the video noise is determined to be too high. This "color killer" decision bit can be used to control another module that implements the color killing function. The Noise Reduction can be controlled using I2C registers from 50h to 5Fh. This module can also be set to bypass mode by I2C register 5Dh (Bit 0). 3.7 Auto Contrast The Auto Contrast (AC) module can adjust the picture brightness automatically or manually (user programmable) for better image quality. The goal of AC processing is to make the dark area brighter and high-light area dimmer. This makes it possible for the viewer to see details hidden in the shadows. It also prevents loss of details in the washed-out high light area. The AC processing is mostly for video surveillance applications. For each frame of image, the auto contrast module collects the statistics of its Y (luminance) values. The AC algorithm implemented in the firmware processes the statistics and generates a look-up table (LUT). This LUT is used to map each incoming pixel Y value to an output pixel Y value for the next frame of image. The LUT is updated during the blanking period between two frames. The Auto Contrast Mode can be controlled by using I2C registers 0Fh. This module can also be set to disable mode by I2C register 0Fh (Bit 1:0). 22 Functional Description Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5158 TVP5158 TVP5157 TVP5157 TVP5156 TVP5156 TVP5158 TVP5158, TVP5157 TVP5157, TVP5156 TVP5156 www.ti.com 3.8 SLES243B SLES243B ­ JULY 2009 ­ REVISED SEPTEMBER 2009 Output Formatter The output formatter is responsible for generating the output digital video stream. Table 3-4 provides a summary of line frequencies, data rates, and pixel counts for different input standards. TVP5158 TVP5158 supports non-interleaved output mode, pixel-interleaved output mode and line-interleaved output mode. The non-interleaved mode is similar to the TVP5154A TVP5154A device, except that a single fixed clock output is used. In the interleaved modes, the video output data from multiple decoder channels are multiplexed together and then output to a single 8-bit or 16-bit port. The video output data from selected channels can be interleaved on a pixel or line basis. Table 3-4. Summary of Line Frequencies, Data Rates and Pixel Counts for Different Standards STANDARDS (ITU-R BT.601) PIXELS PER LINE ACTIVE PIXELS PER LINE LINES PER FRAME COLOR SUB-CARRIER FREQUENCY (MHz) PIXEL FREQUENCY (MHz) HORIZONTAL LINE RATE (kHz) NTSC-J, M 858 720 525 13.5 3.579545 15.73426 NTSC-4.43 858 720 525 13.5 4.43361875 15.73426 PAL-M 858 720 525 13.5 3.57561149 15.73426 PAL-60 PAL-60 858 720 525 13.5 4.43361875 15.73426 PAL-B, D, G, H, I 864 720 625 13.5 4.43361875 15.625 PAL-N 864 720 625 13.5 4.43361875 15.625 PAL-Nc 864 720 625 13.5 3.58205625 15.625 3.8.1 Non-Interleaved Mode In the non-interleaved mode, the YCbCr digital output is programmed as 8-bit ITU-R BT.656 parallel interface standard. Depending on which output mode is selected, the output for each channel can be un-scaled data or scaled data. Also each video output port can be selected to output the video data from any 1 of 4 video decoders. Table 3-5 shows the detailed information about non-interleaved mode. Table 3-5. Output Ports Configuration for Non-Interleave Mode VIDEO OUTPUT FORMATS DATA CLOCK RATE (MHz) INTERFACE TYPE DVO_A DVO_B DVO_C DVO_D 1-Ch D1 Quad BT.656 Any 1 of 4 Ch Any 1 of 4 Ch Any 1 of 4 Ch Any 1 of 4 Ch 27 Quad BT.656 Any 1 of 4 Ch Any 1 of 4 Ch Any 1 of 4 Ch Any 1 of 4 Ch 1-Ch CIF 3.8.2 27 1-Ch Half-D1 27 Quad BT.656 Any 1 of 4 Ch Any 1 of 4 Ch Any 1 of 4 Ch Any 1 of 4 Ch Pixel-Interleaved Mode Each video decoder supports multiplexing two or four channels ITU-R BT.656 format data together on a pixel basis. The output from each video decoder channel is still ITU-R BT.656 format. After the processing in output formatter, two or four channels video data has been interleaved together by strictly one pixel from each channel. The pixel-interleaved mode is dedicated for the backend chip which has limited video input ports. Table 3-6 gives the output port configuration for pixel-interleaved mode. Table 3-6. Output Ports Configuration for Pixel-Interleaved Mode VIDEO OUTPUT FORMATS DATA CLOCK RATE (MHz) INTERFACE TYPE INTERLEAVE MODE DVO_A DVO_B DVO_C DVO_D 2-Ch D1 54 Dual BT.656 Pixel Based Any 2 of 4 Ch Any 2 of 4 Ch Hi-Z Hi-Z 4-Ch D1 108 Single BT.656 Pixel Based All 4 Ch Hi-Z Hi-Z Hi-Z 4-Ch Half-D1 54 Single BT.656 Pixel Based All 4 Ch Hi-Z Hi-Z Hi-Z 4-Ch CIF 54 Single BT.656 Pixel Based All 4 Ch Hi-Z Hi-Z Hi-Z Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5158 TVP5158 TVP5157 TVP5157 TVP5156 TVP5156 Functional Description 23 TVP5158 TVP5158, TVP5157 TVP5157, TVP5156 TVP5156 SLES243B SLES243B ­ JULY 2009 ­ REVISED SEPTEMBER 2009 3.8.2.1 www.ti.com 2-Ch Pixel-Interleaved Mode In 2-Ch pixel-interleaved mode, the video output data with D1 resolution from two video channels is multiplexed pixel by pixel at 54 MHz. The output ports DVO_A and DVO_B are used in this mode. The output clocks OCLK_P and OCLK_N are synchronized with each channel so that the backend chip can de-multiplexed each video channel data easily. The video output from each channel is compatible with ITU-R BT.656 format. Figure 3-10 shows the timing diagram for 2-Ch pixel-interleaved mode. CLK_P (27MHz) CLK_N (27MHz) CH1_D FF CH2_D 00 00 Cb20 DVO_A_ [7:0] FF Cb20 Y20 00 Y20 Cr20 00 Cb0 XY Cr20 Y0 Y21 XY Cb22 Y21 Cb0 Cb22 Cr0 Y22 Y0 Y22 Y1 Cr22 Cr0 Cr22 Cb2 Y2 Y23 Y1 Cb24 Y23 Cb2 Cb24 Cr2 Y24 Y2 Y24 Y3 Cr24 Cr2 Cr24 Y25 Y3 Y25 Figure 3-10. 2-Ch Pixel-Interleaved Mode Timing Diagram 3.8.2.2 4-Ch Pixel-Interleaved Mode In 4-Ch pixel-interleaved mode, the video output data with D1 resolution from four video channels is multiplexed pixel by pixel at 108 MHz. The output DVO_A is used in this mode. The output clock OCLK_P is synchronized with all four channels data. Each channel video data is compatible with ITU-R BT.656 format. Figure 3-11 shows the timing diagram for 4-Ch pixel-interleaved mode. CLK (108MHz) CH1_D FF CH2_D Cb20 CH3_D Y 20 Cr92 FF Cb20 Cr50 Cr92 Y 20 Y51 Cb0 Y93 Y52 Cr20 Cb52 Cb94 Y22 Y53 Cr52 Y94 Cb94 00 Y0 Cb22 Y21 Cb52 Y93 00 XY Cr20 Y51 Cr50 CH4_D DVO_A_ [7:0] 00 00 XY Y21 Y52 Cr94 Y94 Cb0 Cb22 Cr52 Cr94 Y95 Y0 Y22 Y53 Y95 Figure 3-11. 4-Ch Pixel-Interleaved Mode Timing Diagram In 4-Ch pixel-interleaved mode, TVP5158 TVP5158 also supports Half-D1 and CIF format data multiplexed at 54 MHz. The output DVO_A is used in this mode. The output clock OCLK_P is synchronized with all four channels data. 3.8.2.3 Metadata Insertion for Non-Interleave Mode and Pixel-Interleaved Mode In non-interleaved mode and pixel-interleaved mode, the video detection status (VDET) has also been inserted in MSB of SAV/EAV control byte. Table 3-7 shows VDET status insertion in SAV/EAV codes. 24 Functional Description Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5158 TVP5158 TVP5157 TVP5157 TVP5156 TVP5156 TVP5158 TVP5158, TVP5157 TVP5157, TVP5156 TVP5156 www.ti.com SLES243B SLES243B ­ JULY 2009 ­ REVISED SEPTEMBER 2009 Table 3-7. VDET Statues Insertion in SAV/EAV Codes CONDITION FVH VALUE SAV/EAV CODE SEQUENCE 4th FIELD V TIME H TIME F V H 1st 2nd 3rd 1 Active SAV 0 0 0 FFh 00h 00h 80h 00h 1 Active EAV 0 0 1 FFh 00h 00h 9Dh 1Dh 1 Blank SAV 0 1 0 FFh 00h 00h ABh 2Bh 1 Blank EAV 0 1 1 FFh 00h 00h B6h 36h 2 Active SAV 1 0 0 FFh 00h 00h C7h 47h 2 Active EAV 1 0 1 FFh 00h 00h DAh 5Ah 2 Blank SAV 1 1 0 FFh 00h 00h ECh 6Ch 2 Blank EAV 1 1 1 FFh 00h 00h F1h 71h VDET = 1 VDET = 0 In the pixel-interleaved mode, Channel ID is inserted in the horizontal blanking code as Table 3-8. The backend chip can easily identify the video data from which video decoder channel by inserted Channel ID. Table 3-8. Channel ID Insertion in Horizontal Blanking Code H BLANKING CODE WITH CHANNEL ID CHANNEL Y Cb Cr Ch1 10h 80h 80h Ch2 11h 81h 81h Ch3 12h 82h 82h Ch4 13h 83h 83h In the pixel-interleaved mode, Channel ID can also be inserted in 4 LSBs of SAV/EAV control byte replacing protection bits as Table 3-9. Table 3-9. Channel ID Insertion in SAV/EAV Code Sequence CONDITION FVH VALUE SAV/EAV CODE SEQUENCE 4th FIELD V TIME H TIME F V H 1st 2nd 3rd Ch1 Ch2 Ch3 Ch4 1 Active SAV 0 0 0 FFh 00h 00h 80h 81h 82h 83h 1 Active EAV 0 0 1 FFh 00h 00h 90h 91h 92h 93h 1 Blank SAV 0 1 0 FFh 00h 00h A0h A1h A2h A3h 1 Blank EAV 0 1 1 FFh 00h 00h B0h B1h B2h B3h 2 Active SAV 1 0 0 FFh 00h 00h C0h C1h C2h C3h 2 Active EAV 1 0 1 FFh 00h 00h D0h D1h D2h D3h 2 Blank SAV 1 1 0 FFh 00h 00h E0h E1h E2h E3h 2 Blank EAV 1 1 1 FFh 00h 00h F0h F1h F2h F3h 3.8.3 Line-Interleaved Mode Support (TVP5158 TVP5158 only) TVP5158 TVP5158 supports line-interleaved modes to multiplex 2 or 4 video channels outputs together line by line. Compared to pixel-interleaved mode, the line-interleaved mode significantly reduces the code complexity and MIPS consumption of the backend DSP. TVP5158 TVP5158 supports 2-Ch and 4-Ch line-interleaved modes. Each mode supports different resolutions including D1, Half-D1 and CIF. Table 3-10 includes all line-interleaved modes supported by a single TVP5158 TVP5158 device. Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5158 TVP5158 TVP5157 TVP5157 TVP5156 TVP5156 Functional Description 25 TVP5158 TVP5158, TVP5157 TVP5157, TVP5156 TVP5156 SLES243B SLES243B ­ JULY 2009 ­ REVISED SEPTEMBER 2009 www.ti.com Table 3-10. Line-Interleaved Modes VIDEO OUTPUT FORMATS DATA CLOCK RATE INTERFACE TYPE (MHz) INTERLEAVE MODE DVO_A DVO_B DVO_C DVO_D 2-Ch D1 54 Dual BT.656 Line Based Any 2 of 4 Ch Any 2 of 4 Ch Hi-Z Hi-Z 4-Ch D1 108 Single BT.656 Line Based All 4 Ch Hi-Z Hi-Z Hi-Z 4-Ch Half-D1 54 Single BT.656 Line Based All 4 Ch Hi-Z Hi-Z Hi-Z 4-Ch CIF 27 Single BT.656 Line Based All 4 Ch Hi-Z Hi-Z Hi-Z All 4 Ch (C data) Hi-Z Hi-Z 4-Ch D1 54 16-bit BT.601 Line Based All 4 Ch (Y data) 4-Ch Half-D1 27 16-bit BT.601 Line Based All 4 Ch (Y data) All 4 Ch (C data) Hi-Z Hi-Z 4-Ch CIF + 1-Ch D1 54 Single BT.656 Line Based All 4 Ch CIF + Any 1 of 4 D1 Hi-Z Hi-Z Hi-Z 4-Ch Half-D1 + 1-Ch D1 108 Single BT.656 Line Based All 4 Ch Half-D1 + Any 1 of 4 D1 Hi-Z Hi-Z Hi-Z 3.8.3.1 2-Ch Line-Interleaved Mode TVP5158 TVP5158 supports 2-Ch line-interleaved mode at 54 MHz. The video output data with D1 resolution from any two video channels is multiplexed together on a line basis. The output ports DVO_A and DVO_B are used in this mode. The output clock OCLK_P is synchronized with both output ports. 3.8.3.2 4-Ch Line-Interleaved Mode In 4-Ch line-interleaved mode, the video output data from all 4 channels is multiplexed together on a line basis. The output resolution of video data can be D1, Half-D1 or CIF. For D1 and Half-D1 output resolutions, the video output port can be configured to support 8-bit BT.656 or 16-Bit YCbCr 4:2:2 data with embedded sync. Port DVO_A is used for 8-bit output. Ports DVO_A and DVO_B are used for 16-Bit output. The output clock OCLK_P is synchronized with all four output ports. TVP5158 TVP5158 supports multiplexing 4-Ch CIF and 1-Ch D1 data together and then output through DVO_A at 54 MHz. 1-Ch D1 can be from any one of 4 video channels. In typical surveillance applications, CIF resolution is used for recording and D1 resolution is used for video preview. TVP5158 TVP5158 also supports multiplexing 4-Ch Half-D1 and 1-Ch D1 data together and then output through DVO_A at 108 MHz. The backend chip can use Half-D1 to generate CIF format by dropped one field. Pleas note that the line-interleaved mode does NOT strictly output one line from each decoder channel sequentially. The order of multiplexed the video line data is based on the availability of video output data from each decoder channel. Therefore, it is possible to output two consecutive lines from the same decoder channel or to skip one decoder channel output. 3.8.3.3 Video Cascade Mode Two TVP5158 TVP5158 devices can be cascade connected and work as single 8-Ch video decoder. In cascade mode, the port DVO_C and DVO_D of master TVP5158 TVP5158 (first stage) can be configured as the video input interface. The DVO_A and DVO_B of master TVP5158 TVP5158 are configured as the output interface for two devices. This mode is dedicated for the backend chip with extremely limited input ports. Table 3-11 includes all cascade modes in TVP5158 TVP5158. For the modes of 4-Ch CIF + 1 - Ch D1 at 54 MHz and 8-Ch CIF + 1 - Ch D1 at 108 MHz modes, the D1 line is broken into two equal-length half lines and then multiplex with other CIF lines. Therefore, all video data is actually multiplexed by CIF line length. Additionally, in these two modes, both the scaled and un-scaled data streams must use the same line cropping setting. The cropping setting can be controlled by I2C register B1h (Bit 6). 26 Functional Description Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5158 TVP5158 TVP5157 TVP5157 TVP5156 TVP5156 TVP5158 TVP5158, TVP5157 TVP5157, TVP5156 TVP5156 www.ti.com SLES243B SLES243B ­ JULY 2009 ­ REVISED SEPTEMBER 2009 Table 3-11. TVP5158 TVP5158 Video Cascade Modes VIDEO OUTPUT FORMATS CASCADE STAGE DATA CLOCK RATE (MHz) INTERFACE TYPE INTERLEAVE MODE DVO_A DVO_B DVO_C DVO_D 1st Stage 54 Single BT.656 Line Based All 8 Ch CIF Hi-Z Hi-Z 4-Ch CIF Input 2nd Stage 27 Single BT.656 Line Based All 4 Ch CIF Hi-Z Hi-Z Hi-Z 1st Stage 108 Single BT.656 Line Based All 8 Ch Half-D1 Hi-Z Hi-Z 4-Ch Half-D1 Input 2nd Stage 54 Single BT.656 Line Based All 4 Ch Half-D1 Hi-Z Hi-Z Hi-Z 1st Stage 108 Single BT.656 Line Based All 8 Ch CIF + Any 1 of 8 D1 Hi-Z 1-Ch D1 Input 4-Ch CIF Input 2nd Stage 27/27 Dual BT.656 Line Based All 4 Ch CIF Any 1 of 4 Ch D1 Hi-Z Hi-Z 8-Ch CIF 8-Ch Half-D1 8-Ch CIF + 1-Ch D1 Typical applications with cascade mode show on next several pages. Figure 3-12 shows the Cascade Connection for 16-Ch CIF Recoding and Multi-Ch CIF Preview. Figure 3-13 shows the Cascade Connection for 16-Ch CIF Recoding and Multi-Ch Half-D1 Preview. Figure 3-14 shows the Cascade Connection for 16-Ch CIF Recoding and 2-Ch D1/Multi-Ch CIF Preview. DVO_A_[7:0] OCLK_P VIN_1 VIN_2 TVP5158 TVP5158 VIN_3 8-C h CIF 8Bit@54MH z VPIF_A DVO_D_[7:0] OCLKN/CLKIN VIN_4 I2 C VIN_1 VIN_2 VIN_3 TVP5158 TVP5158 VIN_4 VIN_1 VIN_2 H.264 DVO_A_[7:0] OCLK_P DVO_A_[7:0] OCLK_P TVP5158 TVP5158 4-C h CIF 8Bit@ 27MHz 8-C h CIF 16 -Ch CIF Recording DM6467 DM6467 DaVinci HD VPIF_B 8Bit@54MH z VIN_3 DVO _D_[7:0] OCLKN/CLKIN VIN_4 Multi-Ch CIF Preview I2 C VIN_1 VIN_2 VIN_3 DVO_A_[7:0] OCLK_P TVP5158 TVP5158 VIN_4 4-C h CIF 8Bit@ 27MHz Figure 3-12. Cascade Connection for 16-Ch CIF Recoding and Multi-Ch CIF Preview Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5158 TVP5158 TVP5157 TVP5157 TVP5156 TVP5156 Functional Description 27 TVP5158 TVP5158, TVP5157 TVP5157, TVP5156 TVP5156 SLES243B SLES243B ­ JULY 2009 ­ REVISED SEPTEMBER 2009 www.ti.com DVO_A_[7:0] OCLK_P VIN_1 VIN_2 TVP5158 TVP5158 VIN_3 8-Ch Half-D1 8Bit@108 MHz VPIF _A DVO_D_[7:0] OCLKN/CLKIN VIN_4 I2C H.264 VIN_1 DVO_A_[7:0] OCLK_P VIN_2 4-Ch H alf-D1 8Bit@ 54MHz TVP5158 TVP5158 VIN_3 VIN_4 VIN_1 VIN_2 TVP5158 TVP5158 VIN_3 16 -Ch CIF R ecording DVO_A_[7:0] OCLK_P DM6467 DM6467 DaVinci HD 8-Ch Half-D1 8Bit@ 108MHz VPIF _B Multi-Ch H alf-D1 Preview DVO_D_[7:0] OCLKN/CLKIN VIN_4 I2C VIN_1 VIN_2 VIN_3 DVO_A_[7:0] OCLK_P TVP5158 TVP5158 VIN_4 4-Ch H alf-D1 8Bit@ 54MHz Figure 3-13. Cascade Connection for 16-Ch CIF Recoding and Multi-Ch Half-D1 Preview VIN_1 VIN_2 VIN_3 VIN_4 DVO_A_[7:0] OCLK_P TVP5158 TVP5158 8-Ch CIF + 1 -Ch D 1 VPIF_A 8Bit@108MHz DVO _C_[7:0] DVO_D_[7:0] OCLKN/CLKIN I2C VIN_1 VIN_2 VIN_3 DVO_A_[7:0] OCLK_P 4-C h CIF 8 Bit@ 27 MHz DVO_B _[7:0] TVP5158 TVP5158 H.264 1-Ch D1 8Bit@27MH z 16 -C h CIF Recording VIN_4 VIN_1 VIN_2 VIN_3 VIN_4 DM6467 DM6467 DaVinci HD DVO_A_[7:0] OCLK_P TVP5158 TVP5158 8-C h C IF + 1 -C h D 1 2 -Ch D1/Multi-Ch CIF Preview VPIF_B 8Bit@108MHz DVO _C_[7:0] DVO_D_[7:0] OCLKN/CLKIN I2C VIN_1 VIN_2 VIN_3 DVO_A_[7:0] OCLK_P 4 -C h CIF 8 Bit@ 27 MHz DVO_B _[7:0] TVP 5158 1 -Ch D1 8Bit@27MH z VIN_4 Figure 3-14. Cascade Connection for 16-Ch CIF Recoding and 2-Ch D1/Multi-Ch CIF Preview 28 Functional Description Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5158 TVP5158 TVP5157 TVP5157 TVP5156 TVP5156 TVP5158 TVP5158, TVP5157 TVP5157, TVP5156 TVP5156 www.ti.com 3.8.3.4 SLES243B SLES243B ­ JULY 2009 ­ REVISED SEPTEMBER 2009 Metadata Insertion for Line-Interleaved Mode In the line-interleaved mode, the video data is rearranged on a line-by-line basis. There can be no guaranteed output line order since all analog video inputs are not synchronized. In order to be compatible with general backend BT.656 decoder, the video data is encapsulated on TVP5158 TVP5158 output so that all input data is preserved and output data is understandable to a BT.656 decoder. To prevent confusion over image line count and vertical blanking appearing haphazardly, SAV/EAV codes will have FID and V data stripped and replaced with FID=V=0. Since vertical blanking in the input is being masked out, artificial vertical sync will be inserted every encapsulated frame (a.k.a. super frame). Thus to the unaware BT.656 decoder, the stream will appear to be progressive data with 2 lines of vertical blanking. 4-Byte Start Code (SC3:SC0) is inserted immediately after SAV code for encapsulated frame. Figure 3-15 and Figure 3-16 show the start code details. Horizontal Active Period SAV FFh 00h P0 00h P1 P2 P3 P4 P5 P6 P7 Horizontal Blanking Interval Channel Data EAV XYh SC3 SC3 SC2 SC2 SC1 SC1 SC0 SC0 Cb Y Cr SAV for encapsulated frame FFh 00h HBI 00h XYh Y EAV for encapsulated frame Start Code Figure 3-15. Start Code in 8-Bit BT.656 Interface Horizontal Active Period SAV FFh 00h 00h P0 00h 00h P2 P3 Channel Data EAV XYh SC3 SC2 SC1 SC0 Y FFh P1 Horizontal Blanking Interval Y Y FFh SAV for encapsulated frame Cr 00h 00h XYh FFh 00h 00h XYh Y XYh SC3 SC2 SC1 SC0 Cb HBI Cb Cr EAV for encapsulated frame Start Code Figure 3-16. Start Code in 16-Bit YCbCr 4:2:2 Interface Table 3-12 and Table 3-13 show the bit assignment and field definition of 4-Byte start code for Active Video Line. Table 3-12. Bit Assignment of 4-Byte Start Code for Active Video Line BYTE 7 6 5 SC[3] 1 RSVD RSVD SC[2] 0 BOL EOL SC[1] ~LD_ID[6] SC[0] 1 4 3 2 RSVD 1 VCS_ID VDET 0 CH_ID[1:0] RSVD LN_ID[8:7] LN_ID[6:0] F V H P3 Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5158 TVP5158 TVP5157 TVP5157 TVP5156 TVP5156 P2 P1 P0 Functional Description 29 TVP5158 TVP5158, TVP5157 TVP5157, TVP5156 TVP5156 SLES243B SLES243B ­ JULY 2009 ­ REVISED SEPTEMBER 2009 www.ti.com Table 3-13. Bit Field Definition of 4-Byte Start Code for Active Video Line BIT NAME FUNCTION 31 1 30 RSVD Reserved. Must be set to 1. Reserved. 29 RSVD Reserved. [28:27] RSVD Reserved (to support up to 32 video channels) Video cascade stage ID. Set to 0 for normal operation. In cascade mode, the back-end device (e.g., TMS320DM6467 TMS320DM6467) interfaces to the first stage. 26 VCS_ID 0: First stage (channels 1 to 4) 1: Second stage (channels 5 to 8) 2-bit Channel ID. Video decoder channel number. 00: Channel 1 [25:24] CH_ID[1:0] 01: Channel 2 10: Channel 3 11: Channel 4 23 0 22 BOL Reserved. Must be set to 0. Active-high beginning of line flag. Used in split-line mode which may be required for hybrid formats (e.g. 1-Ch D1 + 8-Ch CIF). Set high when the current encapsulated line of channel data includes the beginning of a video line. 0: BOL not included (2nd half of split line) 1: BOL included (1st half of split line or full line) Active-high end of line flag. Used in split-line mode which may be required for hybrid formats (e.g. 1-Ch D1 + 8-Ch CIF). Set high when the current line of channel data includes the end of a video line. 21 EOL 0: EOL not included (1st half of split line) 1: EOL included (2nd half of split line or full line) Active-high video detection status 20 VDET 0: Video not detected [19:18] RSVD [17:16] LN_ID[8:7] Two MSBs of 9-bit Line ID, active video line number. Line counter resets to 000h at beginning of active video (i.e., resets once per field). During the vertical blanking interval, the line counter may either continue counting or hold the terminal count determined at the end of active video. 15 ~LN_ID[6] Reserved. Must be set to the complement of bit 14 (LN_ID[6]). [14:8] LN_ID[6:0] Seven LSBs of 9-bit Line ID, active video line number. Line counter resets to 000h at beginning of active video (i.e., resets once per field). During the vertical blanking interval, the line counter may either continue counting or hold the terminal count determined at the end of active video. 7 1 6 F 1: Video detected Reserved. Reserved. Must be set to 1. F-bit 0: First field of frame 1: Second field of frame V-bit 5 V 0: when not in vertical blanking 1: during vertical blanking H-bit. Always set to 0. 4 H 0: SAV 3 P3 P3 = V XOR H, Protection bits used for error detection/correction 2 P2 P2 = F XOR H, Protection bits used for error detection/correction 1 P1 P1 = F XOR V, Protection bits used for error detection/correction 0 P0 P0 = F XOR V XOR H, Protection bits used for error detection/correction 1: EAV (never used) 30 Functional Description Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5158 TVP5158 TVP5157 TVP5157 TVP5156 TVP5156 TVP5158 TVP5158, TVP5157 TVP5157, TVP5156 TVP5156 www.ti.com SLES243B SLES243B ­ JULY 2009 ­ REVISED SEPTEMBER 2009 NOTE For line-interleaved output mode, if none of video decoder channels has the data ready at a given time, TVP5158 TVP5158 outputs the dummy line until any one of video decoder channels is ready to output a line. The backend chip needs to keep only the active video line and ignore the dummy line. The start code of the dummy line is different with active video line. Table 3-14 shows the bit assignment and field definition of 4-Byte start code for the Dummy Line. Table 3-14. Bit Assignment of 4-Byte Start Code for the Dummy Line BYTE 7 6 5 4 3 2 1 0 SC[3] 0 0 0 0 0 0 0 1 SC[2] 0 0 0 0 0 0 0 1 SC[1] 0 0 0 0 0 0 0 1 SC[0] 0 0 0 0 0 0 0 1 NOTE The Dummy Line can be easily distinguished from active video line by simply looking at the MSB of byte SC[0]. 3.9 Audio Sub-System (TVP5157 TVP5157 and TVP5158 TVP5158 Only) The audio sub-system integrates 4-Ch audio analog-to-digital converters, digital processing and I2S encoder. TVP5158 TVP5158 audio sub-system supports 4-Ch mono analog audio input and standard/multiple I2S output. TVP5158 TVP5158 also supports audio cascade connection up to four devices cascade connected for 16-Ch audio input. 3.9.1 Features · · · · · · · · · Four mono analog audio input channels ­ Requires external passive attenuator to support 2.828-Vpp analog audio input Programmable Gain Amplifier (PGA) ­ Gain range: -12 ~ 0 dB, Gain Step: 1.5 dB Integrated Anti-Aliasing Filter (AAF) 10-Bit Analog-to-Digital Converter Integrates Audio High-pass filter to eliminate low frequency hum Digital serial audio interface ­ 16-Bit Linear PCM, 8-Bit A-Law and 8-Bit -Law Data ­ I2S or DSP Format ­ Master and Slave mode operation ­ Up to 16 slots TDM output ­ 64 fs or 256 fs system clock Sampling Rate : 16 kHz , 8 kHz Audio Cascade connection ­ Up to 4 cascaded devices ­ I2S format ­ 256 fs system clock Audio Mixing Output ­ Audio ADC has one register to set mix ratio ­ The Mixing output pin SD_M can also be used for recording. Combined with the recording output pin SD_R, two I2S bit-streams can be output simultaneously. Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5158 TVP5158 TVP5157 TVP5157 TVP5156 TVP5156 Functional Description 31 TVP5158 TVP5158, TVP5157 TVP5157, TVP5156 TVP5156 SLES243B SLES243B ­ JULY 2009 ­ REVISED SEPTEMBER 2009 3.9.2 www.ti.com Audio Sub-System Functional Diagram Figure 3-17. Audio Sub-System Functional Diagram 32 Functional Description Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5158 TVP5158 TVP5157 TVP5157 TVP5156 TVP5156 TVP5158 TVP5158, TVP5157 TVP5157, TVP5156 TVP5156 www.ti.com 3.9.3 SLES243B SLES243B ­ JULY 2009 ­ REVISED SEPTEMBER 2009 Audio Cascade Connection A IN_1 S D_CO BCLK_R A IN_2 LRCLK_R A IN_3 SD_R A IN_4 XTAL_IN X TAL TVP5158 TVP5158 First Stage Record Output (A IN_1-AN_16) Mix Output SD_M XTAL_OUT B CLK_CI OS C_OUT LRC LK_CI A IN_5 SD_CI A IN_7 TVP5158 TVP5158 Second Stage A IN_8 XTAL_IN OS C_OUT A IN_9 BC LK_R BCLK_R LRCLK_R SD_R S D_CO A IN_6 LRCLK_R SD_R SD_M SD_M B CLK_CI SD_CI LRC LK_CI AIN_11 TVP5158 TVP5158 Third Stage XTAL_IN OS C_OUT AIN_13 BC LK_R BCLK_R LRCLK_R SD_R S D_CO AIN_10 AIN_12 LRCLK_R SD_R SD_M SD_M Record Output (A IN_9-AN_16) BC LK_CI SD_CI LRCLK_CI AIN_15 TVP5158 TVP5158 Last Stage BC LK_R BCLK_R LRCLK_R SD _R S D_CO AIN_14 AIN_16 Record Output (A IN_5-AN_16) LRCLK_R SD_R SD _M SD_M Record Output (A IN_13-AN 13-AN_16) XTAL_IN OS C_OUT SD_CI Figure 3-18. Audio Cascade Connection TVP5158 TVP5158 supports up to 4 devices cascaded together for audio cascade connection. The I2S output of master TVP5158 TVP5158 (1st stage) combines all audio channel data from cascaded TVP5158 TVP5158 devices. Key Features of Audio Cascade Connection · 16-Bit linear PCM data · I2S format · Bit Clock: 256 fs · All cascade inputs are always in slave mode · Second to fourth stage serial audio outputs are always in master mode · First stage serial audio output can be in either master or slave mode · Common clock source for all cascaded devices is required The Serial Audio Output Channel Assignment shown on Table 3-15. Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5158 TVP5158 TVP5157 TVP5157 TVP5156 TVP5156 Functional Description 33 TVP5158 TVP5158, TVP5157 TVP5157, TVP5156 TVP5156 SLES243B SLES243B ­ JULY 2009 ­ REVISED SEPTEMBER 2009 www.ti.com Table 3-15. Serial Audio Output Channel Assignment I2S LRCLK_R Left tdm_ch tdm_out_pin Slot 1 SD_R Slot 2 Slot 3 Slot 4 Slot 5 LRCLK_R Right Slot 6 Slot 7 Slot 8 AIN_1 Slot 9 Slot 10 Slot 11 Slot 12 Slot 13 Slot 14 Slot 15 Slot 16 AIN_2 0 SD_M 0 (2 channel) SD_R AIN_1 SD_M AIN_2 SD_R AIN_1 1 AIN_3 AIN_2 AIN_4 0 SD_M 1 (4 channel) SD_R AIN_1 SD_M AIN_3 AIN_2 SD_R AIN_1 AIN_3 1 AIN_4 AIN_5 AIN_7 AIN_2 AIN_4 AIN_6 AIN_8 AIN_8 AIN_10 AIN_12 AIN_8 AIN_10 AIN_12 AIN_14 AIN_16 0 SD_M 2 (8 channel) SD_R AIN_1 AIN_5 AIN_2 AIN_6 SD_M AIN_3 AIN_7 AIN_4 AIN_8 SD_R AIN_1 AIN_3 AIN_2 AIN_4 AIN_6 1 AIN_5 AIN_7 AIN_9 AIN_11 0 SD_M 3 (12 channel) SD_R AIN_1 AIN_5 AIN_9 AIN_2 AIN_6 AIN_10 SD_M AIN_3 AIN_7 AIN_11 AIN_4 AIN_8 AIN_12 SD_R AIN_1 AIN_3 AIN_5 AIN_7 AIN_2 AIN_4 AIN_6 1 AIN_9 AIN_11 AIN_13 AIN_15 0 SD_M 4 (16 channel) SD_R AIN_1 AIN_5 AIN_9 AIN_13 AIN_2 AIN_6 AIN_10 AIN_14 SD_M AIN_3 AIN_7 AIN_11 AIN_15 AIN_4 AIN_8 AIN_12 AIN_16 Slot 1 Slot 2 Slot 9 Slot 10 Slot 11 Slot 12 Slot 13 Slot 14 Slot 15 Slot 16 SD_R AIN_1 AIN_2 1 DSP Format tdm_ch tdm_out_pin Slot 3 Slot 4 AIN_2 Slot 5 Slot 6 Slot 7 Slot 8 AIN_4 AIN_2 AIN_4 AIN_6 AIN_8 AIN_2 AIN_4 AIN_6 AIN_8 AIN_10 AIN_12 AIN_2 AIN_4 AIN_6 0 SD_M 0 (2 channel) SD_R AIN_1 SD_M AIN_2 SD_R AIN_1 AIN_3 1 0 SD_M 1 (4 channel) SD_R AIN_1 AIN_2 SD_M AIN_3 AIN_4 SD_R AIN_1 AIN_3 AIN_5 AIN_7 1 0 SD_M 2 (8 channel) SD_R AIN_1 AIN_5 AIN_2 AIN_6 SD_M AIN_3 AIN_7 AIN_4 AIN_8 SD_R AIN_1 AIN_3 AIN_5 AIN_7 AIN_9 AIN_11 1 0 SD_M 3 (12 channel) SD_R AIN_1 AIN_5 AIN_9 AIN_2 AIN_6 AIN_10 SD_M AIN_3 AIN_7 AIN_11 AIN_4 AIN_8 AIN_12 SD_R AIN_1 AIN_3 AIN_5 AIN_7 AIN_9 AIN_11 AIN_13 AIN_15 SD_R AIN_1 AIN_5 AIN_9 AIN_13 AIN_2 AIN_6 AIN_10 AIN_14 SD_M AIN_3 AIN_7 AIN_11 AIN_15 AIN_4 AIN_8 AIN_12 AIN_16 1 AIN_8 AIN_10 AIN_12 AIN_14 AIN_16 0 SD_M 4 (16 channel) 1 3.10 I2C Host Interface The I2C standard consists of two signals, serial input/output data line (SDA) and input/output clock line (SCL), which carry information between the devices connected to the bus. The input pins I2CA0, I2CA1 and I2CA2 are used to select the slave address to which the device responds. Although the I2C system can be multi-mastered, the TVP5158 TVP5158 decoder functions as a slave device only. 34 Functional Description Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5158 TVP5158 TVP5157 TVP5157 TVP5156 TVP5156 TVP5158 TVP5158, TVP5157 TVP5157, TVP5156 TVP5156 www.ti.com SLES243B SLES243B ­ JULY 2009 ­ REVISED SEPTEMBER 2009 Both SDA and SCL must be connected to IOVDD via pullup resistors. When the bus is free, both lines are high. The slave address select terminals (I2CA0, I2CA1 and I2CA2) enable the use of up to eight devices on the same I2C bus. At the trailing edge of reset, the status of the I2CA0, I2CA1 and I2CA2 lines are sampled to determine the device address used. Table 3-16 summarizes the terminal functions of the I2C host interface. Table 3-17 shows the device address selection options. Table 3-16. I2C Terminal Description SIGNAL TYPE DESCRIPTION I2CA0 I Slave address selection I2CA1 I Slave address selection I2CA2 I Slave address selection SCL I/O (open drain) Input/output clock line SDA I/O (open drain) Input/output data line Table 3-17. I2C Host Interface Device Addresses A6 A5 A4 A3 A2(I2CA2) A1(I2CA1) A0 (I2CA0) R/W HEX 1 0 1 1 0 0 0 1/0 B1/B0 1 0 1 1 0 0 1 1/0 B3/B2 1 0 1 1 0 1 0 1/0 B5/B4 1 0 1 1 0 1 1 1/0 B7/B6 1 0 1 1 1 0 0 1/0 B9/B8 1 0 1 1 1 0 1 1/0 BB/BA 1 0 1 1 1 1 0 1/0 BD/BC 1 0 1 1 1 1 1 1/0 BF/BE Data transfer rate on the bus is up to 400 Kbit/s. The number of devices connected to the bus is dependent on the bus capacitance limit of 400 pF. The data on the SDA line must be stable during the high period of the SCL except for start and stop conditions. The high or low state of the data line can only change with the clock signal on the SCL line being low. A high-to-low transition on the SDA line while the SCL is high indicates an I2C start condition. A low-to-high transition on the SDA line while the SCL is high indicates an I2C stop condition. Every byte placed on the SDA must be 8 bits long. The number of bytes which can be transferred is unrestricted. Each byte must be followed by an acknowledge bit. The acknowledge-related clock pulse is generated by the I2C master. To simplify programming of each of the 4 decoder channels a single I2C write transaction can be transmitted to any one or more of the 4 cores in parallel. This reduces the time required to download firmware or to configure the device when all channels are to be configured in the same manner. It also enables the addresses for all registers to be common across all decoders. I2C sub-address FEh contains 4 bits with each bit corresponding to one of the decoder cores. If a decoder write enable bit is set, then I2C write transactions will be sent to the corresponding decoder core. For multi-byte I2C write transactions there are options to auto-increment the sub-address or to auto-increment through the selected decoders or both. I2C sub-address FFh contains 4 bits with each bit corresponding to one of the decoder cores. If a decoder read enable bit is set, then I2C read transactions will be sent to the corresponding decoder core. If more than one decoder is enabled for reads then the lowest numbered decoder that is enabled will respond to the read transaction. For multi-byte I2C read transactions there are options to auto-increment the sub-address or to auto-increment through the selected decoders or both. Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5158 TVP5158 TVP5157 TVP5157 TVP5156 TVP5156 Functional Description 35 TVP5158 TVP5158, TVP5157 TVP5157, TVP5156 TVP5156 SLES243B SLES243B ­ JULY 2009 ­ REVISED SEPTEMBER 2009 www.ti.com 3.10.1 I2C Write Operation Data transfers occur utilizing the following formats. An I2C master initiates a write operation to the decoder by generating a start condition (S) followed by the decoder I2C address (as shown below), in MSB first bit order, followed by a 0 to indicate a write cycle. After receiving an acknowledge from the decoder, the master presents the sub-address of the register, or the first of a block of registers it wants to write, followed by one or more bytes of data, MSB first. The decoder acknowledges each byte after completion of each transfer. The I2C master terminates the write operation by generating a stop condition (P). Step 1 0 2 I C Start (master) S Step 2 7 6 5 4 3 2 1 0 I2C General address (master) 1 0 1 1 1 0 X 0 Step 3 9 I2C Acknowledge (slave) A Step 4 7 I2C Write register address (master) 6 5 4 3 2 1 0 Addr Addr Addr Addr Addr Addr Addr Addr Step 5 9 I2C Acknowledge (slave) A Step 6 (1) 7 6 5 4 3 2 1 0 Data Data Data Data Data Data Data Data 2 I C Write data (master) Step 7 (1) 9 I2C Acknowledge (slave) A Step 8 (1) 0 I2C Stop (master) P Repeat steps 6 and 7 until all data have been written. 3.10.2 I2C Read Operation The read operation consists of two phases. The first phase is the address phase. In this phase, an I2C master initiates a write operation to the decoder by generating a start condition (S) followed by the decoder slave address, in MSB first bit order, followed by a 0 to indicate a write cycle. After receiving acknowledge from the decoder, the master presents the sub-address of the register or the first of a block of registers it wants to read. After the cycle is acknowledged, the master has the option of generating a stop condition or not. In the data phase, an I2C master initiates a read operation to the decoder by generating a start condition followed by the decoder I2C slave address (as shown below for a read operation), in MSB first bit order, followed by a 1 to indicate a read cycle. After an acknowledge from the decoder, the I2C master receives one or more bytes of data from the decoder. The I2C master acknowledges the transfer at the end of each byte. After the last data byte has been transferred from the decoder, the master generates a not acknowledge followed by a stop. 36 Functional Description Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5158 TVP5158 TVP5157 TVP5157 TVP5156 TVP5156 TVP5158 TVP5158, TVP5157 TVP5157, TVP5156 TVP5156 www.ti.com SLES243B SLES243B ­ JULY 2009 ­ REVISED SEPTEMBER 2009 Read Phase 1 Step 1 0 2 I C Start (master) S Step 2 7 6 5 4 3 2 1 0 I2C General address (master) 1 0 1 1 X X X 0 Step 3 9 I2C Acknowledge (slave) A Step 4 7 6 5 4 3 2 1 0 Addr Addr Addr Addr Addr Addr Addr Addr 2 I C Read register address (master) Step 5 9 I2C Acknowledge (slave) A Step 6 (1) (1) 0 I2C Stop (master) P Step 6 is optional. Read Phase 2 Step 7 0 2 I C Start (master) S Step 8 7 6 5 4 3 2 1 0 I2C General address (master) 1 0 1 1 X X X 1 Step 9 9 I2C Acknowledge (slave) A Step 10 (1) 7 6 5 4 3 2 1 0 Data Data Data Data Data Data Data Data 2 I C Read data (slave) Step 11 (1) 9 I2C Not Acknowledge (master) A Step 12 (1) 0 I2C Stop (master) P Repeat steps 10 and 11 for all bytes read. Master does not acknowledge the last read data received. 3.11 Clock Circuits An analog clock multiplier PLL is used to generate a system clock from an external 27-MHz crystal (fundamental resonant frequency) or external clock reference input. A crystal can be connected across terminals 99 (XTAL_IN) and 101 (XTAL_OUT), or a 1.8-V external clock input can be connected to terminal 99. Four horizontal PLLs generate the line-locked sample clock for each video decoder core from the system clock. Four color PLLs generate the color subcarrier frequency for each video decoder core from the corresponding line-locked clock. Four vertical PLLs generate the field/frame sync for each video decoder core. A frequency synthesizer generates the 32.768-MHz audio oversampling clock for each analog audio input from the system clock. Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5158 TVP5158 TVP5157 TVP5157 TVP5156 TVP5156 Functional Description 37 TVP5158 TVP5158, TVP5157 TVP5157, TVP5156 TVP5156 SLES243B SLES243B ­ JULY 2009 ­ REVISED SEPTEMBER 2009 www.ti.com 27-MHz Crystal 0W VSSA 27-MHz CLK Output to other TVP5158 TVP5158 XTAL_IN pin 27-MHz CLK Output to other TVP5158 TVP5158 XTAL_IN pin Figure 3-19. Clock and Crystal Connectivity 3.12 Reset Mode Terminals 3 (RESETB) is active low signal to hold the decoder into reset. Table 3-18 shows the configuration of reset mode. Table 3-19 describes the status of the decoder signals during and immediately after reset. Figure 3-20 shows the reset timing. After power-up, the device will be in an unknown state until properly reset. An active low reset, Reset B, of greater than or equal to 20 ms is required following active and stable supply ramp-up. To avoid potential I2C issues, keep SCL and SDA inactive (high) for at least 260 s after reset goes high. There are no power sequencing requirements except that all power supplies should become active and stable within 500 ms of each other. Table 3-18. Reset Mode RESETB CONFIGURATION 0 Resets the decoder 1 Normal operation Table 3-19. Reset Sequence SIGNAL NAME DURING RESET RESET COMPLETED DVO_A_[7:0], DVO_B_[7:0], DVO_C_[7:0], DVO_D_[7:0], OCLK_P, OCLK_N, INTREQ, I2CA[2:0], BCLK_R, LRCLK_R, SD_R, SD_M, SD_CO Input High-impedance RESETB, SDA, SCL, LRCLK_CI, BCLK_CI, SD_CI, XTAL_IN Input Input XTAL_OUT, OSC_OUT Output Output 20ms (min) Normal operation RESETB (Terminal 3) Reset 260us (min) Invalid I2C Cycle Valid Figure 3-20. Reset Timing 38 Functional Description Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5158 TVP5158 TVP5157 TVP5157 TVP5156 TVP5156 TVP5158 TVP5158, TVP5157 TVP5157, TVP5156 TVP5156 www.ti.com SLES243B SLES243B ­ JULY 2009 ­ REVISED SEPTEMBER 2009 4 Internal Control Registers 4.1 Overview The decoder is initialized and controlled by a set of internal registers which set all device operating parameters. Communication between the external controller and the decoder is through I2C. Table 4-1 shows the summary of these registers. The reserved registers must not be written. Reserved bits in the defined registers must be written with 0s, unless otherwise noted. The detailed programming information of each register is described in the following sections. I2C register FEh controls which of the four decoders will receive I2C commands. I2C register FFh controls which decoder core responds to I2C reads. Note, for a read operation it is necessary to perform a write first in order to set the desired sub-address for reading. Compared to previous video decoder, TVP5154A TVP5154A, the TVP5156 TVP5156, TVP5157 TVP5157, and TVP5158 TVP5158 add decoder auto increment and address auto