NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
| Catalog Datasheet Results | Type | Document Tags |
| Abstract: SMFLDL SMFLDL TTL-130 TTL-130 TTL-140 TTL-140 TTL-150 TTL-150 TTL-160 TTL-160 TTL-170 TTL-170 TTL-180 TTL-190 TTL-190 TTL-200 TTL-200 TTL-210 TTL-210 TTL-220 TTL-220 TTL-230 TTL-230 ... | OCR Scan |
1 pages, |
TTL 21 TTL-60 TTL-210 ttl-140 -TTL-440 TTL-490 TTL-120 TTL-150 TTL240 TTL-75 TTL-160 TTL-190 TTL-390 datasheet abstract |
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| Abstract: TTL153 TTL153 TTL154q TTL157 TTL157 TTL161 TTL161 TTL163 TTL163 TTL164q TTL166q TTL169 TTL169 TTL171q TTL174q TTL180 TTL194q ... | Original |
14 pages, |
7400 QUAD Nor 7400 TTL datasheet 7400-series TTL CI 7400 7400series 7400 datasheet nand gate TTL 7400 7400 datasheet 2-input nand gate 16 bit ripple adder 7400 TTL half adder using x-OR and NAND gate bcd subtractor BCD adder and subtractor datasheet abstract |
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| Abstract: Drive ESCONTM With HOTLinkTM Introduction The IBM® ESCONTM (Enterprise System CONnection) interface is presently experiencing rapid growth. Originally designed as a replacement for the older block-mux channel, it is also finding use as a high-performance system interface. This once IBM-proprietary interface is presently being processed to become an ANSI standard interface (known as SBCON) for computer to peripheral interconnect. This application note contains an overview of ESCON operatio ... | Original |
28 pages, |
vhdl code for 8 bit odd parity checker CY7B933 CY7B923 rxq6 datasheet abstract |
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| Abstract: Drive ESCONTM With HOTLinkTM Introduction The IBM® ESCONTM (Enterprise System CONnection) interface is presently experiencing rapid growth. Originally designed as a replacement for the older block-mux channel, it is also finding use as a high-performance system interface. This once IBM-proprietary interface is presently being processed to become an ANSI standard interface (known as SBCON) for computer to peripheral interconnect. This application note contains an overview of ESCON operatio ... | Original |
28 pages, |
schematic XOR Gates rxq2 CY7B933 CY7B923 vhdl code for phase frequency detector rxq6 rxq5 schematic of TTL XOR Gates datasheet abstract |
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| Abstract: receive parity generate r3: TTL180 PORT MAP ( r_mux(0), r_mux(1), r_mux(2), r_mux(3), r_mux(4), r_mux(5 ... | Original |
27 pages, |
k286 CY7B933 CY7B923 AN1274 CY7B923/CY7B933 AN1274 abstract |
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| Abstract: TTL157 TTL157 TTL161 TTL161 TTL163 TTL163 TTL164q TTL166q TTL169 TTL169 TTL171q TTL174q TTL180 TTL194q TTL240q TTL244q ... | Original |
56 pages, |
74171 encoder 74174 74194 shift register pin configuration of d flip flip 7474 7474 j-k flip flop 74138 full subtractor circuit using nor gates TTL 74139 7400 QUAD Nor 74594 vhdl code for 8-bit BCD adder data sheet 74139 datasheet abstract |
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| Abstract: TTL154q TTL157 TTL157 TTL161 TTL161 TTL163 TTL163 TTL164q TTL166q TTL169 TTL169 TTL171q TTL174q TTL180 TTL194q TTL240q ... | Original |
60 pages, |
TTL 7474 74139 Dual 2 to 4 line decoder d-latch by using D flip-flop 7474 8 shift register by using D flip-flop 74823 FULL ADDER schematic of TTL XOR Gates 7474 shift register CI 74139 TTL 7400 full subtractor circuit using nor gates vhdl code for 74194 datasheet abstract |
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| Abstract: Drive ESCONt With HOTLinkt Introduction The IBM® ESCON erals as shown in Figure 1. These bus and tag cables t (Enterprise System CONnec tion) interface is presently experiencing rapid growth. Originally designed as a replacement for the older blockmux channel, it is also finding use as a highperformance system interface. This once IBMproprietary interface is presently being pro cessed to become an ANSI standard interface (known as SBCON) for computer to peripheral in terco ... | Original |
33 pages, |
CY7B933 CY7B923 vhdl code for 8-bit crc-8 PASIC 380 vhdl code CRC-8 datasheet abstract |
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| Abstract: fax id: 5119 Drive ESCONTM With HOTLinkTM Introduction The IBM® ESCONTM (Enterprise System CONnection) interface is presently experiencing rapid growth. Originally designed as a replacement for the older block-mux channel, it is also finding use as a high-performance system interface. This once IBM-proprietary interface is presently being processed to become an ANSI standard interface (known as SBCON) for computer to peripheral interconnect. This application note contains an overview of ... | Original |
28 pages, |
XOR GATES IC schematic XOR Gates IC of XOR GATE CY7B933 CY7B923 CRC-16 vhdl code CRC schematic of TTL XOR Gates datasheet abstract |
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| Abstract: QuickToolsTM User's Guide with SpDETM Reference January 1996 Copyright Information Copyright © 1991, 1992, 1993, 1994, 1995 QuickLogic Corporation. All rights reserved. The information contained in this manual and the accompanying software program are protected by copyright; all rights are reserved by QuickLogic Corporation. QuickLogic Corporation reserves the right to make periodic modifications of this product without obligation to notify any person or entity of such revision ... | Original |
185 pages, |
QL12X16B PQ208 QL8X12B PF100 PF144 16 bit ripple adder 74194 shift register grid tie inverters circuit diagrams vhdl code for 74194 pASIC 1 Family PL84 datasheet abstract |
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| Abstract: 7c198: 10/25/89 Revision: February 29, 1996 CY7C198 CY7C198 Features D D D Logic Block Diagram Pin Configurations CerDIP Top View LCC Top View A7 A 12 A 14 NC 4 3 2 1 32 31 30 A 13 D The CY7C198 CY7C198 is a highperformance CMOS static RAM organized as 32,768 words by8bits.Easymemoryexpansionis provided by an active LOW chip enable (CE)andactiveLOWoutputenable(OE) and threestate drivers. This device has an automatic powerdown feature, reducing the p ... | Original |
9 pages, |
CY7C198 C1983 C198 C1983 16 C1984 datasheet abstract |
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| Abstract: 7c198: 10/25/89 Revision: February 29, 1996 CY7C198 CY7C198 Features D D D Logic Block Diagram Pin Configurations CerDIP Top View LCC Top View A7 A 12 A 14 NC 4 3 2 1 32 31 30 A 13 D The CY7C198 CY7C198 is a highperformance CMOS static RAM organized as 32,768 words by8bits.Easymemoryexpansionis provided by an active LOW chip enable (CE)andactiveLOWoutputenable(OE) and threestate drivers. This device has an automatic powerdown feature, reducing the p ... | Original |
9 pages, |
CY7C198 C1986 C1984 C198 7C19825 datasheet abstract |
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| Abstract: T R I Q U I N T S E M I C O N D U C T O R, I N C . The TQ8214 TQ8214 is a SONET/SDH OC48 MUX that time-division multiplexes a 16-bit or 8-bit parallel data bus to a serial 2.48832 Gb/s NRZ data stream for transmission through a communications channel. Without any additional amplification, the 2.48832 Gb/s output stage can drive either a directly modulated laser or an optical external modulator. Outputs may also be configured to provide standard ECL/PECL levels with excel ... | Original |
23 pages, |
TQ8214 TD10 OC48 NTD10 CK311 optical external modulator datasheet abstract |
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| Abstract: 11C9ofl1C91^ 650 MHz PRESCALERS 11C00 11C00 SERIES GENERAL DESCRIPTION -The 11C90 11C90 and 11C91 11C91 are high speed prescalers designed specifically for communication and instrumentation applications. All discussions and examples in this data sheet are applicable to the 11C91 11C91 as well as the 11C90 11C90. The 11C90 11C90 will divide by 10 or 11 and the 11C91 11C91 divides by 5 or6, both overafrequency range from dc to typically 650 MHz. The division ratio is controlled by the mode control. The divide by 10 or 11 capability al ... | OCR Scan |
11 pages, |
11C91 fairchild ECL divide 5 prescaler preset variable resistor BK 4367 ecl prescaler la 4290 11C90 fairchild 11c90 11C00 11C00 abstract |
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| Abstract: T R I Q U I N T S E M I C O N D U C T O R, I N C . TQ8213 TQ8213 The TQ8213 TQ8213 operates in two different time-division multiplexing modes, making it extremely flexible for use in telecom and datacom applications. The serial 2.48832 Gb/s data stream can be generated from either a 16-bit wide 155.52 MHz data stream or a 32-bit wide 77.76 MHz data stream. Data integrity may be ensured through a byte-wise parity check, which occurs in parallel with the incoming data stream. ... | Original |
23 pages, |
TQ8213 OC48 CK311 76mb datasheet abstract |
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| Abstract: tu« 1WI pASIC rM 1 FAMILY ViaLink™ Technology Very High Speed CMOS FPGAs PRELIMINARY DA TA May 1991 FAMILY HIGHLIGHTS .migration path to 20.000 gates pASIC 1 Family 5 QuicicLogic Very High Speed - ViaLink™ Metal-to-metal programmable-via antifuse technology, ensures count«- speeds over 100 MHz, and logic cell delays of under 5 ns. High Usable Density - Up to 4,000 "gate array" gates, equivalent to 12,000 EPLD or LCA Gates. Technology migration path to 20,000 gates and above. Low Powe ... | OCR Scan |
32 pages, |
TTL153 TTL08 TTL138 pASIC 1 Family TTL154 TTL240 Military Plastic pASIC 3 Family TTL49 7400 family TTL QL16X24 ttl273 marking code JRW TTL06 2-input OR gate 7400 family datasheet abstract |
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| Abstract | Saved from | Date Saved | File Size | Type | Download |
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| A 5 r mgc_component 6958500cb7be.02.94.82.a0.05.00.00.00 1 2 0 0 V v 1 1 6958500cb85a.02.94.82.a0.05.00.00.00 F c 0 "TTL180" O 1 tar:compress:www.datasheetarchive.com/files/quicklogic/thirdp/mentor/mentor.tz!/mentor.!/./ttl/ttl180.mgc_component.attr |
QuickLogic | 26/02/1997 | 6387.15 Kb | TZ | mentor.tz |
| A 5 r Eddm_part 6958500f4d3c.02.94.82.a0.05.00.00.00 1 2 2 0 V v 1 1 69585037feef.02.94.82.a0.05.00.00.00 F f 1 "part.part_1" O 1 P "eddm_stream_to_use" "eddm_propl_dstream" R csduv 0 "$QLOGIC/TTL/TTL180/1" 1 mgc_symbol 6958500eaf21.02.94.82.a0.05.00.00.00 6958500eaea2.02.94.82.a0.05.00.00.00 R csduv 1 "$QLOGIC/TTL/TTL180/schematic" 1 mgc_schematic 69585012d71c.02.94.82.a0.05.00.00.00 69585012d696.02.94.82.a0.05.00.00.00 tar:compress:www.datasheetarchive.com/files/quicklogic/thirdp/mentor/mentor.tz!/mentor.!/./ttl/ttl180/part.eddm_part.attr |
QuickLogic | 26/02/1997 | 6387.15 Kb | TZ | mentor.tz |
| A 5 r mgc_symbol 6958500eaea2.02.94.82.a0.05.00.00.00 1 2 1 0 V v 1 1 6958500eaf21.02.94.82.a0.05.00.00.00 F f 1 "1.smbl_1" O 1 R csduv 0 "$QLOGIC/TTL/TTL180/part" 1 Eddm_part 6958500f4dbd.02.94.82.a0.05.00.00.00 6958500f4d3c.02.94.82.a0.05.00.00.00 tar:compress:www.datasheetarchive.com/files/quicklogic/thirdp/mentor/mentor.tz!/mentor.!/./ttl/ttl180/1.mgc_symbol.attr |
QuickLogic | 26/02/1997 | 6387.15 Kb | TZ | mentor.tz |
| A 5 r mgc_schematic 69585012d696.02.94.82.a0.05.00.00.00 1 2 1 0 V v 1 1 709bf46170bc.02.c0.01.01.16.00.00.00 F c 0 "schematic" O 1 R cspuv 0 "$ " 1 mgc_sheet 709bf460d499.02.c0.01.01.16.00.00.00 69585014ac04.02.94.82.a0.05.00.00.00 tar:compress:www.datasheetarchive.com/files/quicklogic/thirdp/mentor/mentor.tz!/mentor.!/./ttl/ttl180/schematic.mgc_schematic.attr |
QuickLogic | 26/02/1997 | 6387.15 Kb | TZ | mentor.tz |
| A 5 r Mgc_file 00000c9c0000.00.00.00.00.00.00.00.00 1 1 0 0 V v 1 1 752a580dff6d.02.c0.01.01.16.00.00.00 F f 0 "schem_id" O 1 tar:compress:www.datasheetarchive.com/files/quicklogic/thirdp/mentor/mentor.tz!/mentor.!/./ttl/ttl180/schematic/schem_id.mgc_file.attr |
QuickLogic | 26/02/1997 | 6387.15 Kb | TZ | mentor.tz |
| A 5 r mgc_sheet 69585014ac04.02.94.82.a0.05.00.00.00 1 2 21 0 V v 1 2 709bf460d499.02.c0.01.01.16.00.00.00 F f 1 "sheet1.ssht_1" F f 1 "sheet1.sgfx_1" O 1 P "eddm_stream_to_use" "eddm_propl_dstream" R csduv 0 "$QLOGIC/TTL/TTL180/schematic" 1 mgc_schematic 69585012d71c.02.94.82.a0.05.00.00.00 69585012d696.02.94.82.a0.05.00.00.00 R csduv 1 "$QLOGIC/AND/AND2I0/part" 1 Eddm_part 6958844a3880.02.94.82.a0.05.00.00.00 6958843ff485.02.94.82.a0.05.00.00.00 P "eddm_refer_state" "eddm_refer_floating" R csduv 2 "$QLOGIC tar:compress:www.datasheetarchive.com/files/quicklogic/thirdp/mentor/mentor.tz!/mentor.!/./ttl/ttl180/schematic/sheet1.mgc_sheet.attr |
QuickLogic | 26/02/1997 | 6387.15 Kb | TZ | mentor.tz |
| /////////////////////////////////////////////////////// // // // schematic.ample // // // // Library Menu for QUICK LOGIC Design Architect // // // // copyright(c) QUICK LOGIC // /////////////////////////////////////////////////////// // 1994 December, ver 1.00 Created by Atul tar:compress:www.datasheetarchive.com/files/quicklogic/thirdp/mentor/mentor.tz!/mentor.!/./userware/en_na/des_arch/schematic.ample |
QuickLogic | 26/02/1997 | 6387.15 Kb | TZ | mentor.tz |
| /////////////////////////////////////////////////////// // // // schematic.ample // // // // Library Menu for QUICK LOGIC Design Architect // // // // copyright(c) QUICK LOGIC // /////////////////////////////////////////////////////// // 1994 December, ver 1.00 Created by Atul tar:compress:www.datasheetarchive.com/files/quicklogic/thirdp/mentor/mentor.tz!/mentor.!/./userware/en_na/des_arch/schematic.ample~ |
QuickLogic | 26/02/1997 | 6387.15 Kb | TZ | mentor.tz |